1 /* 2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/prefetch.h> 34 #include <linux/ip.h> 35 #include <linux/ipv6.h> 36 #include <linux/tcp.h> 37 #include <linux/bpf_trace.h> 38 #include <net/busy_poll.h> 39 #include "en.h" 40 #include "en_tc.h" 41 #include "eswitch.h" 42 #include "en_rep.h" 43 #include "ipoib/ipoib.h" 44 #include "en_accel/ipsec_rxtx.h" 45 #include "lib/clock.h" 46 47 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config) 48 { 49 return config->rx_filter == HWTSTAMP_FILTER_ALL; 50 } 51 52 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc, 53 void *data) 54 { 55 u32 ci = cqcc & cq->wq.sz_m1; 56 57 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64)); 58 } 59 60 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq, 61 struct mlx5e_cq *cq, u32 cqcc) 62 { 63 mlx5e_read_cqe_slot(cq, cqcc, &cq->title); 64 cq->decmprs_left = be32_to_cpu(cq->title.byte_cnt); 65 cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter); 66 rq->stats.cqe_compress_blks++; 67 } 68 69 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc) 70 { 71 mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr); 72 cq->mini_arr_idx = 0; 73 } 74 75 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n) 76 { 77 u8 op_own = (cqcc >> cq->wq.log_sz) & 1; 78 u32 wq_sz = 1 << cq->wq.log_sz; 79 u32 ci = cqcc & cq->wq.sz_m1; 80 u32 ci_top = min_t(u32, wq_sz, ci + n); 81 82 for (; ci < ci_top; ci++, n--) { 83 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci); 84 85 cqe->op_own = op_own; 86 } 87 88 if (unlikely(ci == wq_sz)) { 89 op_own = !op_own; 90 for (ci = 0; ci < n; ci++) { 91 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci); 92 93 cqe->op_own = op_own; 94 } 95 } 96 } 97 98 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq, 99 struct mlx5e_cq *cq, u32 cqcc) 100 { 101 cq->title.byte_cnt = cq->mini_arr[cq->mini_arr_idx].byte_cnt; 102 cq->title.check_sum = cq->mini_arr[cq->mini_arr_idx].checksum; 103 cq->title.op_own &= 0xf0; 104 cq->title.op_own |= 0x01 & (cqcc >> cq->wq.log_sz); 105 cq->title.wqe_counter = cpu_to_be16(cq->decmprs_wqe_counter); 106 107 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) 108 cq->decmprs_wqe_counter += 109 mpwrq_get_cqe_consumed_strides(&cq->title); 110 else 111 cq->decmprs_wqe_counter = 112 (cq->decmprs_wqe_counter + 1) & rq->wq.sz_m1; 113 } 114 115 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq, 116 struct mlx5e_cq *cq, u32 cqcc) 117 { 118 mlx5e_decompress_cqe(rq, cq, cqcc); 119 cq->title.rss_hash_type = 0; 120 cq->title.rss_hash_result = 0; 121 } 122 123 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq, 124 struct mlx5e_cq *cq, 125 int update_owner_only, 126 int budget_rem) 127 { 128 u32 cqcc = cq->wq.cc + update_owner_only; 129 u32 cqe_count; 130 u32 i; 131 132 cqe_count = min_t(u32, cq->decmprs_left, budget_rem); 133 134 for (i = update_owner_only; i < cqe_count; 135 i++, cq->mini_arr_idx++, cqcc++) { 136 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE) 137 mlx5e_read_mini_arr_slot(cq, cqcc); 138 139 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc); 140 rq->handle_rx_cqe(rq, &cq->title); 141 } 142 mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc); 143 cq->wq.cc = cqcc; 144 cq->decmprs_left -= cqe_count; 145 rq->stats.cqe_compress_pkts += cqe_count; 146 147 return cqe_count; 148 } 149 150 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq, 151 struct mlx5e_cq *cq, 152 int budget_rem) 153 { 154 mlx5e_read_title_slot(rq, cq, cq->wq.cc); 155 mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1); 156 mlx5e_decompress_cqe(rq, cq, cq->wq.cc); 157 rq->handle_rx_cqe(rq, &cq->title); 158 cq->mini_arr_idx++; 159 160 return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1; 161 } 162 163 #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT) 164 165 static inline bool mlx5e_page_is_reserved(struct page *page) 166 { 167 return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id(); 168 } 169 170 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq, 171 struct mlx5e_dma_info *dma_info) 172 { 173 struct mlx5e_page_cache *cache = &rq->page_cache; 174 u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1); 175 176 if (tail_next == cache->head) { 177 rq->stats.cache_full++; 178 return false; 179 } 180 181 if (unlikely(mlx5e_page_is_reserved(dma_info->page))) { 182 rq->stats.cache_waive++; 183 return false; 184 } 185 186 cache->page_cache[cache->tail] = *dma_info; 187 cache->tail = tail_next; 188 return true; 189 } 190 191 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq, 192 struct mlx5e_dma_info *dma_info) 193 { 194 struct mlx5e_page_cache *cache = &rq->page_cache; 195 196 if (unlikely(cache->head == cache->tail)) { 197 rq->stats.cache_empty++; 198 return false; 199 } 200 201 if (page_ref_count(cache->page_cache[cache->head].page) != 1) { 202 rq->stats.cache_busy++; 203 return false; 204 } 205 206 *dma_info = cache->page_cache[cache->head]; 207 cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1); 208 rq->stats.cache_reuse++; 209 210 dma_sync_single_for_device(rq->pdev, dma_info->addr, 211 RQ_PAGE_SIZE(rq), 212 DMA_FROM_DEVICE); 213 return true; 214 } 215 216 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq, 217 struct mlx5e_dma_info *dma_info) 218 { 219 struct page *page; 220 221 if (mlx5e_rx_cache_get(rq, dma_info)) 222 return 0; 223 224 page = dev_alloc_pages(rq->buff.page_order); 225 if (unlikely(!page)) 226 return -ENOMEM; 227 228 dma_info->addr = dma_map_page(rq->pdev, page, 0, 229 RQ_PAGE_SIZE(rq), rq->buff.map_dir); 230 if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) { 231 put_page(page); 232 return -ENOMEM; 233 } 234 dma_info->page = page; 235 236 return 0; 237 } 238 239 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info, 240 bool recycle) 241 { 242 if (likely(recycle) && mlx5e_rx_cache_put(rq, dma_info)) 243 return; 244 245 dma_unmap_page(rq->pdev, dma_info->addr, RQ_PAGE_SIZE(rq), 246 rq->buff.map_dir); 247 put_page(dma_info->page); 248 } 249 250 static inline bool mlx5e_page_reuse(struct mlx5e_rq *rq, 251 struct mlx5e_wqe_frag_info *wi) 252 { 253 return rq->wqe.page_reuse && wi->di.page && 254 (wi->offset + rq->wqe.frag_sz <= RQ_PAGE_SIZE(rq)) && 255 !mlx5e_page_is_reserved(wi->di.page); 256 } 257 258 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix) 259 { 260 struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix]; 261 262 /* check if page exists, hence can be reused */ 263 if (!wi->di.page) { 264 if (unlikely(mlx5e_page_alloc_mapped(rq, &wi->di))) 265 return -ENOMEM; 266 wi->offset = 0; 267 } 268 269 wqe->data.addr = cpu_to_be64(wi->di.addr + wi->offset + rq->buff.headroom); 270 return 0; 271 } 272 273 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq, 274 struct mlx5e_wqe_frag_info *wi) 275 { 276 mlx5e_page_release(rq, &wi->di, true); 277 wi->di.page = NULL; 278 } 279 280 static inline void mlx5e_free_rx_wqe_reuse(struct mlx5e_rq *rq, 281 struct mlx5e_wqe_frag_info *wi) 282 { 283 if (mlx5e_page_reuse(rq, wi)) { 284 rq->stats.page_reuse++; 285 return; 286 } 287 288 mlx5e_free_rx_wqe(rq, wi); 289 } 290 291 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix) 292 { 293 struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix]; 294 295 if (wi->di.page) 296 mlx5e_free_rx_wqe(rq, wi); 297 } 298 299 static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq) 300 { 301 return rq->mpwqe.num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER; 302 } 303 304 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq, 305 struct sk_buff *skb, 306 struct mlx5e_mpw_info *wi, 307 u32 page_idx, u32 frag_offset, 308 u32 len) 309 { 310 unsigned int truesize = ALIGN(len, BIT(rq->mpwqe.log_stride_sz)); 311 312 dma_sync_single_for_cpu(rq->pdev, 313 wi->umr.dma_info[page_idx].addr + frag_offset, 314 len, DMA_FROM_DEVICE); 315 wi->skbs_frags[page_idx]++; 316 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 317 wi->umr.dma_info[page_idx].page, frag_offset, 318 len, truesize); 319 } 320 321 static inline void 322 mlx5e_copy_skb_header_mpwqe(struct device *pdev, 323 struct sk_buff *skb, 324 struct mlx5e_mpw_info *wi, 325 u32 page_idx, u32 offset, 326 u32 headlen) 327 { 328 u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset); 329 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx]; 330 unsigned int len; 331 332 /* Aligning len to sizeof(long) optimizes memcpy performance */ 333 len = ALIGN(headlen_pg, sizeof(long)); 334 dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len, 335 DMA_FROM_DEVICE); 336 skb_copy_to_linear_data_offset(skb, 0, 337 page_address(dma_info->page) + offset, 338 len); 339 if (unlikely(offset + headlen > PAGE_SIZE)) { 340 dma_info++; 341 headlen_pg = len; 342 len = ALIGN(headlen - headlen_pg, sizeof(long)); 343 dma_sync_single_for_cpu(pdev, dma_info->addr, len, 344 DMA_FROM_DEVICE); 345 skb_copy_to_linear_data_offset(skb, headlen_pg, 346 page_address(dma_info->page), 347 len); 348 } 349 } 350 351 static inline void mlx5e_post_umr_wqe(struct mlx5e_rq *rq, u16 ix) 352 { 353 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 354 struct mlx5e_icosq *sq = &rq->channel->icosq; 355 struct mlx5_wq_cyc *wq = &sq->wq; 356 struct mlx5e_umr_wqe *wqe; 357 u8 num_wqebbs = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_BB); 358 u16 pi; 359 360 /* fill sq edge with nops to avoid wqe wrap around */ 361 while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) { 362 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP; 363 mlx5e_post_nop(wq, sq->sqn, &sq->pc); 364 } 365 366 wqe = mlx5_wq_cyc_get_wqe(wq, pi); 367 memcpy(wqe, &wi->umr.wqe, sizeof(*wqe)); 368 wqe->ctrl.opmod_idx_opcode = 369 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) | 370 MLX5_OPCODE_UMR); 371 372 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR; 373 sq->pc += num_wqebbs; 374 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &wqe->ctrl); 375 } 376 377 static int mlx5e_alloc_rx_umr_mpwqe(struct mlx5e_rq *rq, 378 u16 ix) 379 { 380 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 381 int pg_strides = mlx5e_mpwqe_strides_per_page(rq); 382 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0]; 383 int err; 384 int i; 385 386 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) { 387 err = mlx5e_page_alloc_mapped(rq, dma_info); 388 if (unlikely(err)) 389 goto err_unmap; 390 wi->umr.mtt[i] = cpu_to_be64(dma_info->addr | MLX5_EN_WR); 391 page_ref_add(dma_info->page, pg_strides); 392 } 393 394 memset(wi->skbs_frags, 0, sizeof(*wi->skbs_frags) * MLX5_MPWRQ_PAGES_PER_WQE); 395 wi->consumed_strides = 0; 396 397 return 0; 398 399 err_unmap: 400 while (--i >= 0) { 401 dma_info--; 402 page_ref_sub(dma_info->page, pg_strides); 403 mlx5e_page_release(rq, dma_info, true); 404 } 405 406 return err; 407 } 408 409 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi) 410 { 411 int pg_strides = mlx5e_mpwqe_strides_per_page(rq); 412 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0]; 413 int i; 414 415 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) { 416 page_ref_sub(dma_info->page, pg_strides - wi->skbs_frags[i]); 417 mlx5e_page_release(rq, dma_info, true); 418 } 419 } 420 421 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq) 422 { 423 struct mlx5_wq_ll *wq = &rq->wq; 424 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); 425 426 rq->mpwqe.umr_in_progress = false; 427 428 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); 429 430 /* ensure wqes are visible to device before updating doorbell record */ 431 dma_wmb(); 432 433 mlx5_wq_ll_update_db_record(wq); 434 } 435 436 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) 437 { 438 int err; 439 440 err = mlx5e_alloc_rx_umr_mpwqe(rq, ix); 441 if (unlikely(err)) { 442 rq->stats.buff_alloc_err++; 443 return err; 444 } 445 rq->mpwqe.umr_in_progress = true; 446 mlx5e_post_umr_wqe(rq, ix); 447 return 0; 448 } 449 450 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) 451 { 452 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 453 454 mlx5e_free_rx_mpwqe(rq, wi); 455 } 456 457 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq) 458 { 459 struct mlx5_wq_ll *wq = &rq->wq; 460 int err; 461 462 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED))) 463 return false; 464 465 if (mlx5_wq_ll_is_full(wq)) 466 return false; 467 468 do { 469 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); 470 471 err = mlx5e_alloc_rx_wqe(rq, wqe, wq->head); 472 if (unlikely(err)) { 473 rq->stats.buff_alloc_err++; 474 break; 475 } 476 477 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); 478 } while (!mlx5_wq_ll_is_full(wq)); 479 480 /* ensure wqes are visible to device before updating doorbell record */ 481 dma_wmb(); 482 483 mlx5_wq_ll_update_db_record(wq); 484 485 return !!err; 486 } 487 488 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq, 489 struct mlx5e_icosq *sq, 490 struct mlx5e_rq *rq, 491 struct mlx5_cqe64 *cqe) 492 { 493 struct mlx5_wq_cyc *wq = &sq->wq; 494 u16 ci = be16_to_cpu(cqe->wqe_counter) & wq->sz_m1; 495 struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci]; 496 497 mlx5_cqwq_pop(&cq->wq); 498 499 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) { 500 WARN_ONCE(true, "mlx5e: Bad OP in ICOSQ CQE: 0x%x\n", 501 cqe->op_own); 502 return; 503 } 504 505 if (likely(icowi->opcode == MLX5_OPCODE_UMR)) { 506 mlx5e_post_rx_mpwqe(rq); 507 return; 508 } 509 510 if (unlikely(icowi->opcode != MLX5_OPCODE_NOP)) 511 WARN_ONCE(true, 512 "mlx5e: Bad OPCODE in ICOSQ WQE info: 0x%x\n", 513 icowi->opcode); 514 } 515 516 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq) 517 { 518 struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq); 519 struct mlx5_cqe64 *cqe; 520 521 if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED))) 522 return; 523 524 cqe = mlx5_cqwq_get_cqe(&cq->wq); 525 if (likely(!cqe)) 526 return; 527 528 /* by design, there's only a single cqe */ 529 mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe); 530 531 mlx5_cqwq_update_db_record(&cq->wq); 532 } 533 534 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq) 535 { 536 struct mlx5_wq_ll *wq = &rq->wq; 537 538 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED))) 539 return false; 540 541 mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq); 542 543 if (mlx5_wq_ll_is_full(wq)) 544 return false; 545 546 if (!rq->mpwqe.umr_in_progress) 547 mlx5e_alloc_rx_mpwqe(rq, wq->head); 548 549 return true; 550 } 551 552 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe, 553 u32 cqe_bcnt) 554 { 555 struct ethhdr *eth = (struct ethhdr *)(skb->data); 556 struct tcphdr *tcp; 557 int network_depth = 0; 558 __be16 proto; 559 u16 tot_len; 560 void *ip_p; 561 562 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe); 563 u8 tcp_ack = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) || 564 (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA); 565 566 skb->mac_len = ETH_HLEN; 567 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth); 568 569 tot_len = cqe_bcnt - network_depth; 570 ip_p = skb->data + network_depth; 571 572 if (proto == htons(ETH_P_IP)) { 573 struct iphdr *ipv4 = ip_p; 574 575 tcp = ip_p + sizeof(struct iphdr); 576 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 577 578 ipv4->ttl = cqe->lro_min_ttl; 579 ipv4->tot_len = cpu_to_be16(tot_len); 580 ipv4->check = 0; 581 ipv4->check = ip_fast_csum((unsigned char *)ipv4, 582 ipv4->ihl); 583 } else { 584 struct ipv6hdr *ipv6 = ip_p; 585 586 tcp = ip_p + sizeof(struct ipv6hdr); 587 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 588 589 ipv6->hop_limit = cqe->lro_min_ttl; 590 ipv6->payload_len = cpu_to_be16(tot_len - 591 sizeof(struct ipv6hdr)); 592 } 593 594 tcp->psh = get_cqe_lro_tcppsh(cqe); 595 596 if (tcp_ack) { 597 tcp->ack = 1; 598 tcp->ack_seq = cqe->lro_ack_seq_num; 599 tcp->window = cqe->lro_tcp_win; 600 } 601 } 602 603 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe, 604 struct sk_buff *skb) 605 { 606 u8 cht = cqe->rss_hash_type; 607 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 : 608 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 : 609 PKT_HASH_TYPE_NONE; 610 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht); 611 } 612 613 static inline bool is_first_ethertype_ip(struct sk_buff *skb) 614 { 615 __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto; 616 617 return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6)); 618 } 619 620 static inline void mlx5e_handle_csum(struct net_device *netdev, 621 struct mlx5_cqe64 *cqe, 622 struct mlx5e_rq *rq, 623 struct sk_buff *skb, 624 bool lro) 625 { 626 if (unlikely(!(netdev->features & NETIF_F_RXCSUM))) 627 goto csum_none; 628 629 if (lro) { 630 skb->ip_summed = CHECKSUM_UNNECESSARY; 631 rq->stats.csum_unnecessary++; 632 return; 633 } 634 635 if (is_first_ethertype_ip(skb)) { 636 skb->ip_summed = CHECKSUM_COMPLETE; 637 skb->csum = csum_unfold((__force __sum16)cqe->check_sum); 638 rq->stats.csum_complete++; 639 return; 640 } 641 642 if (likely((cqe->hds_ip_ext & CQE_L3_OK) && 643 (cqe->hds_ip_ext & CQE_L4_OK))) { 644 skb->ip_summed = CHECKSUM_UNNECESSARY; 645 if (cqe_is_tunneled(cqe)) { 646 skb->csum_level = 1; 647 skb->encapsulation = 1; 648 rq->stats.csum_unnecessary_inner++; 649 return; 650 } 651 rq->stats.csum_unnecessary++; 652 return; 653 } 654 csum_none: 655 skb->ip_summed = CHECKSUM_NONE; 656 rq->stats.csum_none++; 657 } 658 659 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe, 660 u32 cqe_bcnt, 661 struct mlx5e_rq *rq, 662 struct sk_buff *skb) 663 { 664 struct net_device *netdev = rq->netdev; 665 int lro_num_seg; 666 667 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24; 668 if (lro_num_seg > 1) { 669 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt); 670 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg); 671 /* Subtract one since we already counted this as one 672 * "regular" packet in mlx5e_complete_rx_cqe() 673 */ 674 rq->stats.packets += lro_num_seg - 1; 675 rq->stats.lro_packets++; 676 rq->stats.lro_bytes += cqe_bcnt; 677 } 678 679 if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp))) 680 skb_hwtstamps(skb)->hwtstamp = 681 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe)); 682 683 skb_record_rx_queue(skb, rq->ix); 684 685 if (likely(netdev->features & NETIF_F_RXHASH)) 686 mlx5e_skb_set_hash(cqe, skb); 687 688 if (cqe_has_vlan(cqe)) 689 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 690 be16_to_cpu(cqe->vlan_info)); 691 692 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK; 693 694 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg); 695 skb->protocol = eth_type_trans(skb, netdev); 696 } 697 698 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq, 699 struct mlx5_cqe64 *cqe, 700 u32 cqe_bcnt, 701 struct sk_buff *skb) 702 { 703 rq->stats.packets++; 704 rq->stats.bytes += cqe_bcnt; 705 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb); 706 } 707 708 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq) 709 { 710 struct mlx5_wq_cyc *wq = &sq->wq; 711 struct mlx5e_tx_wqe *wqe; 712 u16 pi = (sq->pc - 1) & wq->sz_m1; /* last pi */ 713 714 wqe = mlx5_wq_cyc_get_wqe(wq, pi); 715 716 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &wqe->ctrl); 717 } 718 719 static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq, 720 struct mlx5e_dma_info *di, 721 const struct xdp_buff *xdp) 722 { 723 struct mlx5e_xdpsq *sq = &rq->xdpsq; 724 struct mlx5_wq_cyc *wq = &sq->wq; 725 u16 pi = sq->pc & wq->sz_m1; 726 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi); 727 728 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; 729 struct mlx5_wqe_eth_seg *eseg = &wqe->eth; 730 struct mlx5_wqe_data_seg *dseg; 731 732 ptrdiff_t data_offset = xdp->data - xdp->data_hard_start; 733 dma_addr_t dma_addr = di->addr + data_offset; 734 unsigned int dma_len = xdp->data_end - xdp->data; 735 736 prefetchw(wqe); 737 738 if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE || 739 MLX5E_SW2HW_MTU(rq->channel->priv, rq->netdev->mtu) < dma_len)) { 740 rq->stats.xdp_drop++; 741 return false; 742 } 743 744 if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1))) { 745 if (sq->db.doorbell) { 746 /* SQ is full, ring doorbell */ 747 mlx5e_xmit_xdp_doorbell(sq); 748 sq->db.doorbell = false; 749 } 750 rq->stats.xdp_tx_full++; 751 return false; 752 } 753 754 dma_sync_single_for_device(sq->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE); 755 756 cseg->fm_ce_se = 0; 757 758 dseg = (struct mlx5_wqe_data_seg *)eseg + 1; 759 760 /* copy the inline part if required */ 761 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) { 762 memcpy(eseg->inline_hdr.start, xdp->data, MLX5E_XDP_MIN_INLINE); 763 eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE); 764 dma_len -= MLX5E_XDP_MIN_INLINE; 765 dma_addr += MLX5E_XDP_MIN_INLINE; 766 dseg++; 767 } 768 769 /* write the dma part */ 770 dseg->addr = cpu_to_be64(dma_addr); 771 dseg->byte_count = cpu_to_be32(dma_len); 772 773 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND); 774 775 /* move page to reference to sq responsibility, 776 * and mark so it's not put back in page-cache. 777 */ 778 rq->wqe.xdp_xmit = true; 779 sq->db.di[pi] = *di; 780 sq->pc++; 781 782 sq->db.doorbell = true; 783 784 rq->stats.xdp_tx++; 785 return true; 786 } 787 788 /* returns true if packet was consumed by xdp */ 789 static inline int mlx5e_xdp_handle(struct mlx5e_rq *rq, 790 struct mlx5e_dma_info *di, 791 void *va, u16 *rx_headroom, u32 *len) 792 { 793 const struct bpf_prog *prog = READ_ONCE(rq->xdp_prog); 794 struct xdp_buff xdp; 795 u32 act; 796 797 if (!prog) 798 return false; 799 800 xdp.data = va + *rx_headroom; 801 xdp_set_data_meta_invalid(&xdp); 802 xdp.data_end = xdp.data + *len; 803 xdp.data_hard_start = va; 804 805 act = bpf_prog_run_xdp(prog, &xdp); 806 switch (act) { 807 case XDP_PASS: 808 *rx_headroom = xdp.data - xdp.data_hard_start; 809 *len = xdp.data_end - xdp.data; 810 return false; 811 case XDP_TX: 812 if (unlikely(!mlx5e_xmit_xdp_frame(rq, di, &xdp))) 813 trace_xdp_exception(rq->netdev, prog, act); 814 return true; 815 default: 816 bpf_warn_invalid_xdp_action(act); 817 case XDP_ABORTED: 818 trace_xdp_exception(rq->netdev, prog, act); 819 case XDP_DROP: 820 rq->stats.xdp_drop++; 821 return true; 822 } 823 } 824 825 static inline 826 struct sk_buff *skb_from_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, 827 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt) 828 { 829 struct mlx5e_dma_info *di = &wi->di; 830 u16 rx_headroom = rq->buff.headroom; 831 struct sk_buff *skb; 832 void *va, *data; 833 bool consumed; 834 u32 frag_size; 835 836 va = page_address(di->page) + wi->offset; 837 data = va + rx_headroom; 838 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt); 839 840 dma_sync_single_range_for_cpu(rq->pdev, 841 di->addr + wi->offset, 842 0, frag_size, 843 DMA_FROM_DEVICE); 844 prefetch(data); 845 wi->offset += frag_size; 846 847 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { 848 rq->stats.wqe_err++; 849 return NULL; 850 } 851 852 rcu_read_lock(); 853 consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt); 854 rcu_read_unlock(); 855 if (consumed) 856 return NULL; /* page/packet was consumed by XDP */ 857 858 skb = build_skb(va, frag_size); 859 if (unlikely(!skb)) { 860 rq->stats.buff_alloc_err++; 861 return NULL; 862 } 863 864 /* queue up for recycling/reuse */ 865 page_ref_inc(di->page); 866 867 skb_reserve(skb, rx_headroom); 868 skb_put(skb, cqe_bcnt); 869 870 return skb; 871 } 872 873 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 874 { 875 struct mlx5e_wqe_frag_info *wi; 876 struct mlx5e_rx_wqe *wqe; 877 __be16 wqe_counter_be; 878 struct sk_buff *skb; 879 u16 wqe_counter; 880 u32 cqe_bcnt; 881 882 wqe_counter_be = cqe->wqe_counter; 883 wqe_counter = be16_to_cpu(wqe_counter_be); 884 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 885 wi = &rq->wqe.frag_info[wqe_counter]; 886 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 887 888 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 889 if (!skb) { 890 /* probably for XDP */ 891 if (rq->wqe.xdp_xmit) { 892 wi->di.page = NULL; 893 rq->wqe.xdp_xmit = false; 894 /* do not return page to cache, it will be returned on XDP_TX completion */ 895 goto wq_ll_pop; 896 } 897 /* probably an XDP_DROP, save the page-reuse checks */ 898 mlx5e_free_rx_wqe(rq, wi); 899 goto wq_ll_pop; 900 } 901 902 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 903 napi_gro_receive(rq->cq.napi, skb); 904 905 mlx5e_free_rx_wqe_reuse(rq, wi); 906 wq_ll_pop: 907 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 908 &wqe->next.next_wqe_index); 909 } 910 911 #ifdef CONFIG_MLX5_ESWITCH 912 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 913 { 914 struct net_device *netdev = rq->netdev; 915 struct mlx5e_priv *priv = netdev_priv(netdev); 916 struct mlx5e_rep_priv *rpriv = priv->ppriv; 917 struct mlx5_eswitch_rep *rep = rpriv->rep; 918 struct mlx5e_wqe_frag_info *wi; 919 struct mlx5e_rx_wqe *wqe; 920 struct sk_buff *skb; 921 __be16 wqe_counter_be; 922 u16 wqe_counter; 923 u32 cqe_bcnt; 924 925 wqe_counter_be = cqe->wqe_counter; 926 wqe_counter = be16_to_cpu(wqe_counter_be); 927 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 928 wi = &rq->wqe.frag_info[wqe_counter]; 929 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 930 931 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 932 if (!skb) { 933 if (rq->wqe.xdp_xmit) { 934 wi->di.page = NULL; 935 rq->wqe.xdp_xmit = false; 936 /* do not return page to cache, it will be returned on XDP_TX completion */ 937 goto wq_ll_pop; 938 } 939 /* probably an XDP_DROP, save the page-reuse checks */ 940 mlx5e_free_rx_wqe(rq, wi); 941 goto wq_ll_pop; 942 } 943 944 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 945 946 if (rep->vlan && skb_vlan_tag_present(skb)) 947 skb_vlan_pop(skb); 948 949 napi_gro_receive(rq->cq.napi, skb); 950 951 mlx5e_free_rx_wqe_reuse(rq, wi); 952 wq_ll_pop: 953 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 954 &wqe->next.next_wqe_index); 955 } 956 #endif 957 958 static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq, 959 struct mlx5_cqe64 *cqe, 960 struct mlx5e_mpw_info *wi, 961 u32 cqe_bcnt, 962 struct sk_buff *skb) 963 { 964 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe); 965 u32 wqe_offset = stride_ix << rq->mpwqe.log_stride_sz; 966 u32 head_offset = wqe_offset & (PAGE_SIZE - 1); 967 u32 page_idx = wqe_offset >> PAGE_SHIFT; 968 u32 head_page_idx = page_idx; 969 u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt); 970 u32 frag_offset = head_offset + headlen; 971 u16 byte_cnt = cqe_bcnt - headlen; 972 973 if (unlikely(frag_offset >= PAGE_SIZE)) { 974 page_idx++; 975 frag_offset -= PAGE_SIZE; 976 } 977 978 while (byte_cnt) { 979 u32 pg_consumed_bytes = 980 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt); 981 982 mlx5e_add_skb_frag_mpwqe(rq, skb, wi, page_idx, frag_offset, 983 pg_consumed_bytes); 984 byte_cnt -= pg_consumed_bytes; 985 frag_offset = 0; 986 page_idx++; 987 } 988 /* copy header */ 989 mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, wi, head_page_idx, 990 head_offset, headlen); 991 /* skb linear part was allocated with headlen and aligned to long */ 992 skb->tail += headlen; 993 skb->len += headlen; 994 } 995 996 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 997 { 998 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe); 999 u16 wqe_id = be16_to_cpu(cqe->wqe_id); 1000 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id]; 1001 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id); 1002 struct sk_buff *skb; 1003 u16 cqe_bcnt; 1004 1005 wi->consumed_strides += cstrides; 1006 1007 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { 1008 rq->stats.wqe_err++; 1009 goto mpwrq_cqe_out; 1010 } 1011 1012 if (unlikely(mpwrq_is_filler_cqe(cqe))) { 1013 rq->stats.mpwqe_filler++; 1014 goto mpwrq_cqe_out; 1015 } 1016 1017 skb = napi_alloc_skb(rq->cq.napi, 1018 ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, 1019 sizeof(long))); 1020 if (unlikely(!skb)) { 1021 rq->stats.buff_alloc_err++; 1022 goto mpwrq_cqe_out; 1023 } 1024 1025 prefetchw(skb->data); 1026 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe); 1027 1028 mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb); 1029 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1030 napi_gro_receive(rq->cq.napi, skb); 1031 1032 mpwrq_cqe_out: 1033 if (likely(wi->consumed_strides < rq->mpwqe.num_strides)) 1034 return; 1035 1036 mlx5e_free_rx_mpwqe(rq, wi); 1037 mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index); 1038 } 1039 1040 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget) 1041 { 1042 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq); 1043 struct mlx5e_xdpsq *xdpsq; 1044 struct mlx5_cqe64 *cqe; 1045 int work_done = 0; 1046 1047 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED))) 1048 return 0; 1049 1050 if (cq->decmprs_left) 1051 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget); 1052 1053 cqe = mlx5_cqwq_get_cqe(&cq->wq); 1054 if (!cqe) 1055 return 0; 1056 1057 xdpsq = &rq->xdpsq; 1058 1059 do { 1060 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) { 1061 work_done += 1062 mlx5e_decompress_cqes_start(rq, cq, 1063 budget - work_done); 1064 continue; 1065 } 1066 1067 mlx5_cqwq_pop(&cq->wq); 1068 1069 rq->handle_rx_cqe(rq, cqe); 1070 } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq))); 1071 1072 if (xdpsq->db.doorbell) { 1073 mlx5e_xmit_xdp_doorbell(xdpsq); 1074 xdpsq->db.doorbell = false; 1075 } 1076 1077 mlx5_cqwq_update_db_record(&cq->wq); 1078 1079 /* ensure cq space is freed before enabling more cqes */ 1080 wmb(); 1081 1082 return work_done; 1083 } 1084 1085 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq) 1086 { 1087 struct mlx5e_xdpsq *sq; 1088 struct mlx5_cqe64 *cqe; 1089 struct mlx5e_rq *rq; 1090 u16 sqcc; 1091 int i; 1092 1093 sq = container_of(cq, struct mlx5e_xdpsq, cq); 1094 1095 if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED))) 1096 return false; 1097 1098 cqe = mlx5_cqwq_get_cqe(&cq->wq); 1099 if (!cqe) 1100 return false; 1101 1102 rq = container_of(sq, struct mlx5e_rq, xdpsq); 1103 1104 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(), 1105 * otherwise a cq overrun may occur 1106 */ 1107 sqcc = sq->cc; 1108 1109 i = 0; 1110 do { 1111 u16 wqe_counter; 1112 bool last_wqe; 1113 1114 mlx5_cqwq_pop(&cq->wq); 1115 1116 wqe_counter = be16_to_cpu(cqe->wqe_counter); 1117 1118 do { 1119 struct mlx5e_dma_info *di; 1120 u16 ci; 1121 1122 last_wqe = (sqcc == wqe_counter); 1123 1124 ci = sqcc & sq->wq.sz_m1; 1125 di = &sq->db.di[ci]; 1126 1127 sqcc++; 1128 /* Recycle RX page */ 1129 mlx5e_page_release(rq, di, true); 1130 } while (!last_wqe); 1131 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq))); 1132 1133 mlx5_cqwq_update_db_record(&cq->wq); 1134 1135 /* ensure cq space is freed before enabling more cqes */ 1136 wmb(); 1137 1138 sq->cc = sqcc; 1139 return (i == MLX5E_TX_CQ_POLL_BUDGET); 1140 } 1141 1142 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq) 1143 { 1144 struct mlx5e_rq *rq = container_of(sq, struct mlx5e_rq, xdpsq); 1145 struct mlx5e_dma_info *di; 1146 u16 ci; 1147 1148 while (sq->cc != sq->pc) { 1149 ci = sq->cc & sq->wq.sz_m1; 1150 di = &sq->db.di[ci]; 1151 sq->cc++; 1152 1153 mlx5e_page_release(rq, di, false); 1154 } 1155 } 1156 1157 #ifdef CONFIG_MLX5_CORE_IPOIB 1158 1159 #define MLX5_IB_GRH_DGID_OFFSET 24 1160 #define MLX5_GID_SIZE 16 1161 1162 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq, 1163 struct mlx5_cqe64 *cqe, 1164 u32 cqe_bcnt, 1165 struct sk_buff *skb) 1166 { 1167 struct net_device *netdev; 1168 char *pseudo_header; 1169 u32 qpn; 1170 u8 *dgid; 1171 u8 g; 1172 1173 qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff; 1174 netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn); 1175 1176 /* No mapping present, cannot process SKB. This might happen if a child 1177 * interface is going down while having unprocessed CQEs on parent RQ 1178 */ 1179 if (unlikely(!netdev)) { 1180 /* TODO: add drop counters support */ 1181 skb->dev = NULL; 1182 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn); 1183 return; 1184 } 1185 1186 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3; 1187 dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET; 1188 if ((!g) || dgid[0] != 0xff) 1189 skb->pkt_type = PACKET_HOST; 1190 else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0) 1191 skb->pkt_type = PACKET_BROADCAST; 1192 else 1193 skb->pkt_type = PACKET_MULTICAST; 1194 1195 /* TODO: IB/ipoib: Allow mcast packets from other VFs 1196 * 68996a6e760e5c74654723eeb57bf65628ae87f4 1197 */ 1198 1199 skb_pull(skb, MLX5_IB_GRH_BYTES); 1200 1201 skb->protocol = *((__be16 *)(skb->data)); 1202 1203 skb->ip_summed = CHECKSUM_COMPLETE; 1204 skb->csum = csum_unfold((__force __sum16)cqe->check_sum); 1205 1206 if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp))) 1207 skb_hwtstamps(skb)->hwtstamp = 1208 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe)); 1209 1210 skb_record_rx_queue(skb, rq->ix); 1211 1212 if (likely(netdev->features & NETIF_F_RXHASH)) 1213 mlx5e_skb_set_hash(cqe, skb); 1214 1215 /* 20 bytes of ipoib header and 4 for encap existing */ 1216 pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN); 1217 memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN); 1218 skb_reset_mac_header(skb); 1219 skb_pull(skb, MLX5_IPOIB_HARD_LEN); 1220 1221 skb->dev = netdev; 1222 1223 rq->stats.csum_complete++; 1224 rq->stats.packets++; 1225 rq->stats.bytes += cqe_bcnt; 1226 } 1227 1228 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1229 { 1230 struct mlx5e_wqe_frag_info *wi; 1231 struct mlx5e_rx_wqe *wqe; 1232 __be16 wqe_counter_be; 1233 struct sk_buff *skb; 1234 u16 wqe_counter; 1235 u32 cqe_bcnt; 1236 1237 wqe_counter_be = cqe->wqe_counter; 1238 wqe_counter = be16_to_cpu(wqe_counter_be); 1239 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 1240 wi = &rq->wqe.frag_info[wqe_counter]; 1241 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 1242 1243 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 1244 if (!skb) 1245 goto wq_free_wqe; 1246 1247 mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1248 if (unlikely(!skb->dev)) { 1249 dev_kfree_skb_any(skb); 1250 goto wq_free_wqe; 1251 } 1252 napi_gro_receive(rq->cq.napi, skb); 1253 1254 wq_free_wqe: 1255 mlx5e_free_rx_wqe_reuse(rq, wi); 1256 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 1257 &wqe->next.next_wqe_index); 1258 } 1259 1260 #endif /* CONFIG_MLX5_CORE_IPOIB */ 1261 1262 #ifdef CONFIG_MLX5_EN_IPSEC 1263 1264 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1265 { 1266 struct mlx5e_wqe_frag_info *wi; 1267 struct mlx5e_rx_wqe *wqe; 1268 __be16 wqe_counter_be; 1269 struct sk_buff *skb; 1270 u16 wqe_counter; 1271 u32 cqe_bcnt; 1272 1273 wqe_counter_be = cqe->wqe_counter; 1274 wqe_counter = be16_to_cpu(wqe_counter_be); 1275 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 1276 wi = &rq->wqe.frag_info[wqe_counter]; 1277 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 1278 1279 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 1280 if (unlikely(!skb)) { 1281 /* a DROP, save the page-reuse checks */ 1282 mlx5e_free_rx_wqe(rq, wi); 1283 goto wq_ll_pop; 1284 } 1285 skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb); 1286 if (unlikely(!skb)) { 1287 mlx5e_free_rx_wqe(rq, wi); 1288 goto wq_ll_pop; 1289 } 1290 1291 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1292 napi_gro_receive(rq->cq.napi, skb); 1293 1294 mlx5e_free_rx_wqe_reuse(rq, wi); 1295 wq_ll_pop: 1296 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 1297 &wqe->next.next_wqe_index); 1298 } 1299 1300 #endif /* CONFIG_MLX5_EN_IPSEC */ 1301