1 /* 2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/ip.h> 34 #include <linux/ipv6.h> 35 #include <linux/tcp.h> 36 #include <net/busy_poll.h> 37 #include "en.h" 38 #include "en_tc.h" 39 40 static inline bool mlx5e_rx_hw_stamp(struct mlx5e_tstamp *tstamp) 41 { 42 return tstamp->hwtstamp_config.rx_filter == HWTSTAMP_FILTER_ALL; 43 } 44 45 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc, 46 void *data) 47 { 48 u32 ci = cqcc & cq->wq.sz_m1; 49 50 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64)); 51 } 52 53 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq, 54 struct mlx5e_cq *cq, u32 cqcc) 55 { 56 mlx5e_read_cqe_slot(cq, cqcc, &cq->title); 57 cq->decmprs_left = be32_to_cpu(cq->title.byte_cnt); 58 cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter); 59 rq->stats.cqe_compress_blks++; 60 } 61 62 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc) 63 { 64 mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr); 65 cq->mini_arr_idx = 0; 66 } 67 68 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n) 69 { 70 u8 op_own = (cqcc >> cq->wq.log_sz) & 1; 71 u32 wq_sz = 1 << cq->wq.log_sz; 72 u32 ci = cqcc & cq->wq.sz_m1; 73 u32 ci_top = min_t(u32, wq_sz, ci + n); 74 75 for (; ci < ci_top; ci++, n--) { 76 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci); 77 78 cqe->op_own = op_own; 79 } 80 81 if (unlikely(ci == wq_sz)) { 82 op_own = !op_own; 83 for (ci = 0; ci < n; ci++) { 84 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci); 85 86 cqe->op_own = op_own; 87 } 88 } 89 } 90 91 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq, 92 struct mlx5e_cq *cq, u32 cqcc) 93 { 94 u16 wqe_cnt_step; 95 96 cq->title.byte_cnt = cq->mini_arr[cq->mini_arr_idx].byte_cnt; 97 cq->title.check_sum = cq->mini_arr[cq->mini_arr_idx].checksum; 98 cq->title.op_own &= 0xf0; 99 cq->title.op_own |= 0x01 & (cqcc >> cq->wq.log_sz); 100 cq->title.wqe_counter = cpu_to_be16(cq->decmprs_wqe_counter); 101 102 wqe_cnt_step = 103 rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ? 104 mpwrq_get_cqe_consumed_strides(&cq->title) : 1; 105 cq->decmprs_wqe_counter = 106 (cq->decmprs_wqe_counter + wqe_cnt_step) & rq->wq.sz_m1; 107 } 108 109 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq, 110 struct mlx5e_cq *cq, u32 cqcc) 111 { 112 mlx5e_decompress_cqe(rq, cq, cqcc); 113 cq->title.rss_hash_type = 0; 114 cq->title.rss_hash_result = 0; 115 } 116 117 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq, 118 struct mlx5e_cq *cq, 119 int update_owner_only, 120 int budget_rem) 121 { 122 u32 cqcc = cq->wq.cc + update_owner_only; 123 u32 cqe_count; 124 u32 i; 125 126 cqe_count = min_t(u32, cq->decmprs_left, budget_rem); 127 128 for (i = update_owner_only; i < cqe_count; 129 i++, cq->mini_arr_idx++, cqcc++) { 130 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE) 131 mlx5e_read_mini_arr_slot(cq, cqcc); 132 133 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc); 134 rq->handle_rx_cqe(rq, &cq->title); 135 } 136 mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc); 137 cq->wq.cc = cqcc; 138 cq->decmprs_left -= cqe_count; 139 rq->stats.cqe_compress_pkts += cqe_count; 140 141 return cqe_count; 142 } 143 144 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq, 145 struct mlx5e_cq *cq, 146 int budget_rem) 147 { 148 mlx5e_read_title_slot(rq, cq, cq->wq.cc); 149 mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1); 150 mlx5e_decompress_cqe(rq, cq, cq->wq.cc); 151 rq->handle_rx_cqe(rq, &cq->title); 152 cq->mini_arr_idx++; 153 154 return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1; 155 } 156 157 void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val) 158 { 159 bool was_opened; 160 161 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression)) 162 return; 163 164 mutex_lock(&priv->state_lock); 165 166 if (priv->params.rx_cqe_compress == val) 167 goto unlock; 168 169 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 170 if (was_opened) 171 mlx5e_close_locked(priv->netdev); 172 173 priv->params.rx_cqe_compress = val; 174 175 if (was_opened) 176 mlx5e_open_locked(priv->netdev); 177 178 unlock: 179 mutex_unlock(&priv->state_lock); 180 } 181 182 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix) 183 { 184 struct sk_buff *skb; 185 dma_addr_t dma_addr; 186 187 skb = napi_alloc_skb(rq->cq.napi, rq->wqe_sz); 188 if (unlikely(!skb)) 189 return -ENOMEM; 190 191 dma_addr = dma_map_single(rq->pdev, 192 /* hw start padding */ 193 skb->data, 194 /* hw end padding */ 195 rq->wqe_sz, 196 DMA_FROM_DEVICE); 197 198 if (unlikely(dma_mapping_error(rq->pdev, dma_addr))) 199 goto err_free_skb; 200 201 *((dma_addr_t *)skb->cb) = dma_addr; 202 wqe->data.addr = cpu_to_be64(dma_addr); 203 204 rq->skb[ix] = skb; 205 206 return 0; 207 208 err_free_skb: 209 dev_kfree_skb(skb); 210 211 return -ENOMEM; 212 } 213 214 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix) 215 { 216 struct sk_buff *skb = rq->skb[ix]; 217 218 if (skb) { 219 rq->skb[ix] = NULL; 220 dma_unmap_single(rq->pdev, 221 *((dma_addr_t *)skb->cb), 222 rq->wqe_sz, 223 DMA_FROM_DEVICE); 224 dev_kfree_skb(skb); 225 } 226 } 227 228 static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq) 229 { 230 return rq->mpwqe_num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER; 231 } 232 233 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq, 234 struct sk_buff *skb, 235 struct mlx5e_mpw_info *wi, 236 u32 page_idx, u32 frag_offset, 237 u32 len) 238 { 239 unsigned int truesize = ALIGN(len, rq->mpwqe_stride_sz); 240 241 dma_sync_single_for_cpu(rq->pdev, 242 wi->umr.dma_info[page_idx].addr + frag_offset, 243 len, DMA_FROM_DEVICE); 244 wi->skbs_frags[page_idx]++; 245 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 246 wi->umr.dma_info[page_idx].page, frag_offset, 247 len, truesize); 248 } 249 250 static inline void 251 mlx5e_copy_skb_header_mpwqe(struct device *pdev, 252 struct sk_buff *skb, 253 struct mlx5e_mpw_info *wi, 254 u32 page_idx, u32 offset, 255 u32 headlen) 256 { 257 u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset); 258 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx]; 259 unsigned int len; 260 261 /* Aligning len to sizeof(long) optimizes memcpy performance */ 262 len = ALIGN(headlen_pg, sizeof(long)); 263 dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len, 264 DMA_FROM_DEVICE); 265 skb_copy_to_linear_data_offset(skb, 0, 266 page_address(dma_info->page) + offset, 267 len); 268 if (unlikely(offset + headlen > PAGE_SIZE)) { 269 dma_info++; 270 headlen_pg = len; 271 len = ALIGN(headlen - headlen_pg, sizeof(long)); 272 dma_sync_single_for_cpu(pdev, dma_info->addr, len, 273 DMA_FROM_DEVICE); 274 skb_copy_to_linear_data_offset(skb, headlen_pg, 275 page_address(dma_info->page), 276 len); 277 } 278 } 279 280 static inline void mlx5e_post_umr_wqe(struct mlx5e_rq *rq, u16 ix) 281 { 282 struct mlx5e_mpw_info *wi = &rq->wqe_info[ix]; 283 struct mlx5e_sq *sq = &rq->channel->icosq; 284 struct mlx5_wq_cyc *wq = &sq->wq; 285 struct mlx5e_umr_wqe *wqe; 286 u8 num_wqebbs = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_BB); 287 u16 pi; 288 289 /* fill sq edge with nops to avoid wqe wrap around */ 290 while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) { 291 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_NOP; 292 sq->ico_wqe_info[pi].num_wqebbs = 1; 293 mlx5e_send_nop(sq, true); 294 } 295 296 wqe = mlx5_wq_cyc_get_wqe(wq, pi); 297 memcpy(wqe, &wi->umr.wqe, sizeof(*wqe)); 298 wqe->ctrl.opmod_idx_opcode = 299 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) | 300 MLX5_OPCODE_UMR); 301 302 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_UMR; 303 sq->ico_wqe_info[pi].num_wqebbs = num_wqebbs; 304 sq->pc += num_wqebbs; 305 mlx5e_tx_notify_hw(sq, &wqe->ctrl, 0); 306 } 307 308 static inline int mlx5e_alloc_and_map_page(struct mlx5e_rq *rq, 309 struct mlx5e_mpw_info *wi, 310 int i) 311 { 312 struct page *page = dev_alloc_page(); 313 if (unlikely(!page)) 314 return -ENOMEM; 315 316 wi->umr.dma_info[i].page = page; 317 wi->umr.dma_info[i].addr = dma_map_page(rq->pdev, page, 0, PAGE_SIZE, 318 PCI_DMA_FROMDEVICE); 319 if (unlikely(dma_mapping_error(rq->pdev, wi->umr.dma_info[i].addr))) { 320 put_page(page); 321 return -ENOMEM; 322 } 323 wi->umr.mtt[i] = cpu_to_be64(wi->umr.dma_info[i].addr | MLX5_EN_WR); 324 325 return 0; 326 } 327 328 static int mlx5e_alloc_rx_umr_mpwqe(struct mlx5e_rq *rq, 329 struct mlx5e_rx_wqe *wqe, 330 u16 ix) 331 { 332 struct mlx5e_mpw_info *wi = &rq->wqe_info[ix]; 333 u64 dma_offset = (u64)mlx5e_get_wqe_mtt_offset(rq, ix) << PAGE_SHIFT; 334 int pg_strides = mlx5e_mpwqe_strides_per_page(rq); 335 int err; 336 int i; 337 338 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) { 339 err = mlx5e_alloc_and_map_page(rq, wi, i); 340 if (unlikely(err)) 341 goto err_unmap; 342 page_ref_add(wi->umr.dma_info[i].page, pg_strides); 343 wi->skbs_frags[i] = 0; 344 } 345 346 wi->consumed_strides = 0; 347 wqe->data.addr = cpu_to_be64(dma_offset); 348 349 return 0; 350 351 err_unmap: 352 while (--i >= 0) { 353 dma_unmap_page(rq->pdev, wi->umr.dma_info[i].addr, PAGE_SIZE, 354 PCI_DMA_FROMDEVICE); 355 page_ref_sub(wi->umr.dma_info[i].page, pg_strides); 356 put_page(wi->umr.dma_info[i].page); 357 } 358 359 return err; 360 } 361 362 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi) 363 { 364 int pg_strides = mlx5e_mpwqe_strides_per_page(rq); 365 int i; 366 367 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) { 368 dma_unmap_page(rq->pdev, wi->umr.dma_info[i].addr, PAGE_SIZE, 369 PCI_DMA_FROMDEVICE); 370 page_ref_sub(wi->umr.dma_info[i].page, 371 pg_strides - wi->skbs_frags[i]); 372 put_page(wi->umr.dma_info[i].page); 373 } 374 } 375 376 void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq) 377 { 378 struct mlx5_wq_ll *wq = &rq->wq; 379 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); 380 381 clear_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state); 382 383 if (unlikely(test_bit(MLX5E_RQ_STATE_FLUSH, &rq->state))) { 384 mlx5e_free_rx_mpwqe(rq, &rq->wqe_info[wq->head]); 385 return; 386 } 387 388 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); 389 390 /* ensure wqes are visible to device before updating doorbell record */ 391 dma_wmb(); 392 393 mlx5_wq_ll_update_db_record(wq); 394 } 395 396 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix) 397 { 398 int err; 399 400 err = mlx5e_alloc_rx_umr_mpwqe(rq, wqe, ix); 401 if (unlikely(err)) 402 return err; 403 set_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state); 404 mlx5e_post_umr_wqe(rq, ix); 405 return -EBUSY; 406 } 407 408 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) 409 { 410 struct mlx5e_mpw_info *wi = &rq->wqe_info[ix]; 411 412 mlx5e_free_rx_mpwqe(rq, wi); 413 } 414 415 #define RQ_CANNOT_POST(rq) \ 416 (test_bit(MLX5E_RQ_STATE_FLUSH, &rq->state) || \ 417 test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state)) 418 419 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq) 420 { 421 struct mlx5_wq_ll *wq = &rq->wq; 422 423 if (unlikely(RQ_CANNOT_POST(rq))) 424 return false; 425 426 while (!mlx5_wq_ll_is_full(wq)) { 427 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); 428 int err; 429 430 err = rq->alloc_wqe(rq, wqe, wq->head); 431 if (err == -EBUSY) 432 return true; 433 if (unlikely(err)) { 434 rq->stats.buff_alloc_err++; 435 break; 436 } 437 438 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); 439 } 440 441 /* ensure wqes are visible to device before updating doorbell record */ 442 dma_wmb(); 443 444 mlx5_wq_ll_update_db_record(wq); 445 446 return !mlx5_wq_ll_is_full(wq); 447 } 448 449 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe, 450 u32 cqe_bcnt) 451 { 452 struct ethhdr *eth = (struct ethhdr *)(skb->data); 453 struct iphdr *ipv4; 454 struct ipv6hdr *ipv6; 455 struct tcphdr *tcp; 456 int network_depth = 0; 457 __be16 proto; 458 u16 tot_len; 459 460 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe); 461 int tcp_ack = ((CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA == l4_hdr_type) || 462 (CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA == l4_hdr_type)); 463 464 skb->mac_len = ETH_HLEN; 465 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth); 466 467 ipv4 = (struct iphdr *)(skb->data + network_depth); 468 ipv6 = (struct ipv6hdr *)(skb->data + network_depth); 469 tot_len = cqe_bcnt - network_depth; 470 471 if (proto == htons(ETH_P_IP)) { 472 tcp = (struct tcphdr *)(skb->data + network_depth + 473 sizeof(struct iphdr)); 474 ipv6 = NULL; 475 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 476 } else { 477 tcp = (struct tcphdr *)(skb->data + network_depth + 478 sizeof(struct ipv6hdr)); 479 ipv4 = NULL; 480 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 481 } 482 483 if (get_cqe_lro_tcppsh(cqe)) 484 tcp->psh = 1; 485 486 if (tcp_ack) { 487 tcp->ack = 1; 488 tcp->ack_seq = cqe->lro_ack_seq_num; 489 tcp->window = cqe->lro_tcp_win; 490 } 491 492 if (ipv4) { 493 ipv4->ttl = cqe->lro_min_ttl; 494 ipv4->tot_len = cpu_to_be16(tot_len); 495 ipv4->check = 0; 496 ipv4->check = ip_fast_csum((unsigned char *)ipv4, 497 ipv4->ihl); 498 } else { 499 ipv6->hop_limit = cqe->lro_min_ttl; 500 ipv6->payload_len = cpu_to_be16(tot_len - 501 sizeof(struct ipv6hdr)); 502 } 503 } 504 505 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe, 506 struct sk_buff *skb) 507 { 508 u8 cht = cqe->rss_hash_type; 509 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 : 510 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 : 511 PKT_HASH_TYPE_NONE; 512 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht); 513 } 514 515 static inline bool is_first_ethertype_ip(struct sk_buff *skb) 516 { 517 __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto; 518 519 return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6)); 520 } 521 522 static inline void mlx5e_handle_csum(struct net_device *netdev, 523 struct mlx5_cqe64 *cqe, 524 struct mlx5e_rq *rq, 525 struct sk_buff *skb, 526 bool lro) 527 { 528 if (unlikely(!(netdev->features & NETIF_F_RXCSUM))) 529 goto csum_none; 530 531 if (lro) { 532 skb->ip_summed = CHECKSUM_UNNECESSARY; 533 return; 534 } 535 536 if (is_first_ethertype_ip(skb)) { 537 skb->ip_summed = CHECKSUM_COMPLETE; 538 skb->csum = csum_unfold((__force __sum16)cqe->check_sum); 539 rq->stats.csum_complete++; 540 return; 541 } 542 543 if (likely((cqe->hds_ip_ext & CQE_L3_OK) && 544 (cqe->hds_ip_ext & CQE_L4_OK))) { 545 skb->ip_summed = CHECKSUM_UNNECESSARY; 546 if (cqe_is_tunneled(cqe)) { 547 skb->csum_level = 1; 548 skb->encapsulation = 1; 549 rq->stats.csum_unnecessary_inner++; 550 } 551 return; 552 } 553 csum_none: 554 skb->ip_summed = CHECKSUM_NONE; 555 rq->stats.csum_none++; 556 } 557 558 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe, 559 u32 cqe_bcnt, 560 struct mlx5e_rq *rq, 561 struct sk_buff *skb) 562 { 563 struct net_device *netdev = rq->netdev; 564 struct mlx5e_tstamp *tstamp = rq->tstamp; 565 int lro_num_seg; 566 567 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24; 568 if (lro_num_seg > 1) { 569 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt); 570 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg); 571 rq->stats.lro_packets++; 572 rq->stats.lro_bytes += cqe_bcnt; 573 } 574 575 if (unlikely(mlx5e_rx_hw_stamp(tstamp))) 576 mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb)); 577 578 skb_record_rx_queue(skb, rq->ix); 579 580 if (likely(netdev->features & NETIF_F_RXHASH)) 581 mlx5e_skb_set_hash(cqe, skb); 582 583 if (cqe_has_vlan(cqe)) 584 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 585 be16_to_cpu(cqe->vlan_info)); 586 587 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK; 588 589 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg); 590 skb->protocol = eth_type_trans(skb, netdev); 591 } 592 593 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq, 594 struct mlx5_cqe64 *cqe, 595 u32 cqe_bcnt, 596 struct sk_buff *skb) 597 { 598 rq->stats.packets++; 599 rq->stats.bytes += cqe_bcnt; 600 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb); 601 napi_gro_receive(rq->cq.napi, skb); 602 } 603 604 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 605 { 606 struct mlx5e_rx_wqe *wqe; 607 struct sk_buff *skb; 608 __be16 wqe_counter_be; 609 u16 wqe_counter; 610 u32 cqe_bcnt; 611 612 wqe_counter_be = cqe->wqe_counter; 613 wqe_counter = be16_to_cpu(wqe_counter_be); 614 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 615 skb = rq->skb[wqe_counter]; 616 prefetch(skb->data); 617 rq->skb[wqe_counter] = NULL; 618 619 dma_unmap_single(rq->pdev, 620 *((dma_addr_t *)skb->cb), 621 rq->wqe_sz, 622 DMA_FROM_DEVICE); 623 624 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { 625 rq->stats.wqe_err++; 626 dev_kfree_skb(skb); 627 goto wq_ll_pop; 628 } 629 630 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 631 skb_put(skb, cqe_bcnt); 632 633 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 634 635 wq_ll_pop: 636 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 637 &wqe->next.next_wqe_index); 638 } 639 640 static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq, 641 struct mlx5_cqe64 *cqe, 642 struct mlx5e_mpw_info *wi, 643 u32 cqe_bcnt, 644 struct sk_buff *skb) 645 { 646 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe); 647 u32 wqe_offset = stride_ix * rq->mpwqe_stride_sz; 648 u32 head_offset = wqe_offset & (PAGE_SIZE - 1); 649 u32 page_idx = wqe_offset >> PAGE_SHIFT; 650 u32 head_page_idx = page_idx; 651 u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt); 652 u32 frag_offset = head_offset + headlen; 653 u16 byte_cnt = cqe_bcnt - headlen; 654 655 if (unlikely(frag_offset >= PAGE_SIZE)) { 656 page_idx++; 657 frag_offset -= PAGE_SIZE; 658 } 659 660 while (byte_cnt) { 661 u32 pg_consumed_bytes = 662 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt); 663 664 mlx5e_add_skb_frag_mpwqe(rq, skb, wi, page_idx, frag_offset, 665 pg_consumed_bytes); 666 byte_cnt -= pg_consumed_bytes; 667 frag_offset = 0; 668 page_idx++; 669 } 670 /* copy header */ 671 mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, wi, head_page_idx, 672 head_offset, headlen); 673 /* skb linear part was allocated with headlen and aligned to long */ 674 skb->tail += headlen; 675 skb->len += headlen; 676 } 677 678 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 679 { 680 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe); 681 u16 wqe_id = be16_to_cpu(cqe->wqe_id); 682 struct mlx5e_mpw_info *wi = &rq->wqe_info[wqe_id]; 683 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id); 684 struct sk_buff *skb; 685 u16 cqe_bcnt; 686 687 wi->consumed_strides += cstrides; 688 689 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { 690 rq->stats.wqe_err++; 691 goto mpwrq_cqe_out; 692 } 693 694 if (unlikely(mpwrq_is_filler_cqe(cqe))) { 695 rq->stats.mpwqe_filler++; 696 goto mpwrq_cqe_out; 697 } 698 699 skb = napi_alloc_skb(rq->cq.napi, 700 ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, 701 sizeof(long))); 702 if (unlikely(!skb)) { 703 rq->stats.buff_alloc_err++; 704 goto mpwrq_cqe_out; 705 } 706 707 prefetch(skb->data); 708 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe); 709 710 mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb); 711 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 712 713 mpwrq_cqe_out: 714 if (likely(wi->consumed_strides < rq->mpwqe_num_strides)) 715 return; 716 717 mlx5e_free_rx_mpwqe(rq, wi); 718 mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index); 719 } 720 721 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget) 722 { 723 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq); 724 int work_done = 0; 725 726 if (unlikely(test_bit(MLX5E_RQ_STATE_FLUSH, &rq->state))) 727 return 0; 728 729 if (cq->decmprs_left) 730 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget); 731 732 for (; work_done < budget; work_done++) { 733 struct mlx5_cqe64 *cqe = mlx5e_get_cqe(cq); 734 735 if (!cqe) 736 break; 737 738 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) { 739 work_done += 740 mlx5e_decompress_cqes_start(rq, cq, 741 budget - work_done); 742 continue; 743 } 744 745 mlx5_cqwq_pop(&cq->wq); 746 747 rq->handle_rx_cqe(rq, cqe); 748 } 749 750 mlx5_cqwq_update_db_record(&cq->wq); 751 752 /* ensure cq space is freed before enabling more cqes */ 753 wmb(); 754 755 return work_done; 756 } 757