1 /* 2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/prefetch.h> 34 #include <linux/ip.h> 35 #include <linux/ipv6.h> 36 #include <linux/tcp.h> 37 #include <linux/bpf_trace.h> 38 #include <net/busy_poll.h> 39 #include "en.h" 40 #include "en_tc.h" 41 #include "eswitch.h" 42 #include "en_rep.h" 43 #include "ipoib/ipoib.h" 44 #include "en_accel/ipsec_rxtx.h" 45 46 static inline bool mlx5e_rx_hw_stamp(struct mlx5e_tstamp *tstamp) 47 { 48 return tstamp->hwtstamp_config.rx_filter == HWTSTAMP_FILTER_ALL; 49 } 50 51 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc, 52 void *data) 53 { 54 u32 ci = cqcc & cq->wq.sz_m1; 55 56 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64)); 57 } 58 59 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq, 60 struct mlx5e_cq *cq, u32 cqcc) 61 { 62 mlx5e_read_cqe_slot(cq, cqcc, &cq->title); 63 cq->decmprs_left = be32_to_cpu(cq->title.byte_cnt); 64 cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter); 65 rq->stats.cqe_compress_blks++; 66 } 67 68 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc) 69 { 70 mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr); 71 cq->mini_arr_idx = 0; 72 } 73 74 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n) 75 { 76 u8 op_own = (cqcc >> cq->wq.log_sz) & 1; 77 u32 wq_sz = 1 << cq->wq.log_sz; 78 u32 ci = cqcc & cq->wq.sz_m1; 79 u32 ci_top = min_t(u32, wq_sz, ci + n); 80 81 for (; ci < ci_top; ci++, n--) { 82 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci); 83 84 cqe->op_own = op_own; 85 } 86 87 if (unlikely(ci == wq_sz)) { 88 op_own = !op_own; 89 for (ci = 0; ci < n; ci++) { 90 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci); 91 92 cqe->op_own = op_own; 93 } 94 } 95 } 96 97 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq, 98 struct mlx5e_cq *cq, u32 cqcc) 99 { 100 cq->title.byte_cnt = cq->mini_arr[cq->mini_arr_idx].byte_cnt; 101 cq->title.check_sum = cq->mini_arr[cq->mini_arr_idx].checksum; 102 cq->title.op_own &= 0xf0; 103 cq->title.op_own |= 0x01 & (cqcc >> cq->wq.log_sz); 104 cq->title.wqe_counter = cpu_to_be16(cq->decmprs_wqe_counter); 105 106 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) 107 cq->decmprs_wqe_counter += 108 mpwrq_get_cqe_consumed_strides(&cq->title); 109 else 110 cq->decmprs_wqe_counter = 111 (cq->decmprs_wqe_counter + 1) & rq->wq.sz_m1; 112 } 113 114 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq, 115 struct mlx5e_cq *cq, u32 cqcc) 116 { 117 mlx5e_decompress_cqe(rq, cq, cqcc); 118 cq->title.rss_hash_type = 0; 119 cq->title.rss_hash_result = 0; 120 } 121 122 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq, 123 struct mlx5e_cq *cq, 124 int update_owner_only, 125 int budget_rem) 126 { 127 u32 cqcc = cq->wq.cc + update_owner_only; 128 u32 cqe_count; 129 u32 i; 130 131 cqe_count = min_t(u32, cq->decmprs_left, budget_rem); 132 133 for (i = update_owner_only; i < cqe_count; 134 i++, cq->mini_arr_idx++, cqcc++) { 135 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE) 136 mlx5e_read_mini_arr_slot(cq, cqcc); 137 138 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc); 139 rq->handle_rx_cqe(rq, &cq->title); 140 } 141 mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc); 142 cq->wq.cc = cqcc; 143 cq->decmprs_left -= cqe_count; 144 rq->stats.cqe_compress_pkts += cqe_count; 145 146 return cqe_count; 147 } 148 149 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq, 150 struct mlx5e_cq *cq, 151 int budget_rem) 152 { 153 mlx5e_read_title_slot(rq, cq, cq->wq.cc); 154 mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1); 155 mlx5e_decompress_cqe(rq, cq, cq->wq.cc); 156 rq->handle_rx_cqe(rq, &cq->title); 157 cq->mini_arr_idx++; 158 159 return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1; 160 } 161 162 #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT) 163 164 static inline bool mlx5e_page_is_reserved(struct page *page) 165 { 166 return page_is_pfmemalloc(page) || page_to_nid(page) != numa_node_id(); 167 } 168 169 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq, 170 struct mlx5e_dma_info *dma_info) 171 { 172 struct mlx5e_page_cache *cache = &rq->page_cache; 173 u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1); 174 175 if (tail_next == cache->head) { 176 rq->stats.cache_full++; 177 return false; 178 } 179 180 if (unlikely(page_is_pfmemalloc(dma_info->page))) 181 return false; 182 183 cache->page_cache[cache->tail] = *dma_info; 184 cache->tail = tail_next; 185 return true; 186 } 187 188 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq, 189 struct mlx5e_dma_info *dma_info) 190 { 191 struct mlx5e_page_cache *cache = &rq->page_cache; 192 193 if (unlikely(cache->head == cache->tail)) { 194 rq->stats.cache_empty++; 195 return false; 196 } 197 198 if (page_ref_count(cache->page_cache[cache->head].page) != 1) { 199 rq->stats.cache_busy++; 200 return false; 201 } 202 203 *dma_info = cache->page_cache[cache->head]; 204 cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1); 205 rq->stats.cache_reuse++; 206 207 dma_sync_single_for_device(rq->pdev, dma_info->addr, 208 RQ_PAGE_SIZE(rq), 209 DMA_FROM_DEVICE); 210 return true; 211 } 212 213 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq, 214 struct mlx5e_dma_info *dma_info) 215 { 216 struct page *page; 217 218 if (mlx5e_rx_cache_get(rq, dma_info)) 219 return 0; 220 221 page = dev_alloc_pages(rq->buff.page_order); 222 if (unlikely(!page)) 223 return -ENOMEM; 224 225 dma_info->addr = dma_map_page(rq->pdev, page, 0, 226 RQ_PAGE_SIZE(rq), rq->buff.map_dir); 227 if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) { 228 put_page(page); 229 return -ENOMEM; 230 } 231 dma_info->page = page; 232 233 return 0; 234 } 235 236 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info, 237 bool recycle) 238 { 239 if (likely(recycle) && mlx5e_rx_cache_put(rq, dma_info)) 240 return; 241 242 dma_unmap_page(rq->pdev, dma_info->addr, RQ_PAGE_SIZE(rq), 243 rq->buff.map_dir); 244 put_page(dma_info->page); 245 } 246 247 static inline bool mlx5e_page_reuse(struct mlx5e_rq *rq, 248 struct mlx5e_wqe_frag_info *wi) 249 { 250 return rq->wqe.page_reuse && wi->di.page && 251 (wi->offset + rq->wqe.frag_sz <= RQ_PAGE_SIZE(rq)) && 252 !mlx5e_page_is_reserved(wi->di.page); 253 } 254 255 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix) 256 { 257 struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix]; 258 259 /* check if page exists, hence can be reused */ 260 if (!wi->di.page) { 261 if (unlikely(mlx5e_page_alloc_mapped(rq, &wi->di))) 262 return -ENOMEM; 263 wi->offset = 0; 264 } 265 266 wqe->data.addr = cpu_to_be64(wi->di.addr + wi->offset + rq->buff.headroom); 267 return 0; 268 } 269 270 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq, 271 struct mlx5e_wqe_frag_info *wi) 272 { 273 mlx5e_page_release(rq, &wi->di, true); 274 wi->di.page = NULL; 275 } 276 277 static inline void mlx5e_free_rx_wqe_reuse(struct mlx5e_rq *rq, 278 struct mlx5e_wqe_frag_info *wi) 279 { 280 if (mlx5e_page_reuse(rq, wi)) { 281 rq->stats.page_reuse++; 282 return; 283 } 284 285 mlx5e_free_rx_wqe(rq, wi); 286 } 287 288 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix) 289 { 290 struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix]; 291 292 if (wi->di.page) 293 mlx5e_free_rx_wqe(rq, wi); 294 } 295 296 static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq) 297 { 298 return rq->mpwqe.num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER; 299 } 300 301 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq, 302 struct sk_buff *skb, 303 struct mlx5e_mpw_info *wi, 304 u32 page_idx, u32 frag_offset, 305 u32 len) 306 { 307 unsigned int truesize = ALIGN(len, BIT(rq->mpwqe.log_stride_sz)); 308 309 dma_sync_single_for_cpu(rq->pdev, 310 wi->umr.dma_info[page_idx].addr + frag_offset, 311 len, DMA_FROM_DEVICE); 312 wi->skbs_frags[page_idx]++; 313 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 314 wi->umr.dma_info[page_idx].page, frag_offset, 315 len, truesize); 316 } 317 318 static inline void 319 mlx5e_copy_skb_header_mpwqe(struct device *pdev, 320 struct sk_buff *skb, 321 struct mlx5e_mpw_info *wi, 322 u32 page_idx, u32 offset, 323 u32 headlen) 324 { 325 u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset); 326 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx]; 327 unsigned int len; 328 329 /* Aligning len to sizeof(long) optimizes memcpy performance */ 330 len = ALIGN(headlen_pg, sizeof(long)); 331 dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len, 332 DMA_FROM_DEVICE); 333 skb_copy_to_linear_data_offset(skb, 0, 334 page_address(dma_info->page) + offset, 335 len); 336 if (unlikely(offset + headlen > PAGE_SIZE)) { 337 dma_info++; 338 headlen_pg = len; 339 len = ALIGN(headlen - headlen_pg, sizeof(long)); 340 dma_sync_single_for_cpu(pdev, dma_info->addr, len, 341 DMA_FROM_DEVICE); 342 skb_copy_to_linear_data_offset(skb, headlen_pg, 343 page_address(dma_info->page), 344 len); 345 } 346 } 347 348 static inline void mlx5e_post_umr_wqe(struct mlx5e_rq *rq, u16 ix) 349 { 350 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 351 struct mlx5e_icosq *sq = &rq->channel->icosq; 352 struct mlx5_wq_cyc *wq = &sq->wq; 353 struct mlx5e_umr_wqe *wqe; 354 u8 num_wqebbs = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_BB); 355 u16 pi; 356 357 /* fill sq edge with nops to avoid wqe wrap around */ 358 while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) { 359 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP; 360 sq->db.ico_wqe[pi].num_wqebbs = 1; 361 mlx5e_post_nop(wq, sq->sqn, &sq->pc); 362 } 363 364 wqe = mlx5_wq_cyc_get_wqe(wq, pi); 365 memcpy(wqe, &wi->umr.wqe, sizeof(*wqe)); 366 wqe->ctrl.opmod_idx_opcode = 367 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) | 368 MLX5_OPCODE_UMR); 369 370 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR; 371 sq->db.ico_wqe[pi].num_wqebbs = num_wqebbs; 372 sq->pc += num_wqebbs; 373 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &wqe->ctrl); 374 } 375 376 static int mlx5e_alloc_rx_umr_mpwqe(struct mlx5e_rq *rq, 377 u16 ix) 378 { 379 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 380 int pg_strides = mlx5e_mpwqe_strides_per_page(rq); 381 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0]; 382 int err; 383 int i; 384 385 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) { 386 err = mlx5e_page_alloc_mapped(rq, dma_info); 387 if (unlikely(err)) 388 goto err_unmap; 389 wi->umr.mtt[i] = cpu_to_be64(dma_info->addr | MLX5_EN_WR); 390 page_ref_add(dma_info->page, pg_strides); 391 } 392 393 memset(wi->skbs_frags, 0, sizeof(*wi->skbs_frags) * MLX5_MPWRQ_PAGES_PER_WQE); 394 wi->consumed_strides = 0; 395 396 return 0; 397 398 err_unmap: 399 while (--i >= 0) { 400 dma_info--; 401 page_ref_sub(dma_info->page, pg_strides); 402 mlx5e_page_release(rq, dma_info, true); 403 } 404 405 return err; 406 } 407 408 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi) 409 { 410 int pg_strides = mlx5e_mpwqe_strides_per_page(rq); 411 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0]; 412 int i; 413 414 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) { 415 page_ref_sub(dma_info->page, pg_strides - wi->skbs_frags[i]); 416 mlx5e_page_release(rq, dma_info, true); 417 } 418 } 419 420 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq) 421 { 422 struct mlx5_wq_ll *wq = &rq->wq; 423 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); 424 425 rq->mpwqe.umr_in_progress = false; 426 427 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); 428 429 /* ensure wqes are visible to device before updating doorbell record */ 430 dma_wmb(); 431 432 mlx5_wq_ll_update_db_record(wq); 433 } 434 435 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) 436 { 437 int err; 438 439 err = mlx5e_alloc_rx_umr_mpwqe(rq, ix); 440 if (unlikely(err)) { 441 rq->stats.buff_alloc_err++; 442 return err; 443 } 444 rq->mpwqe.umr_in_progress = true; 445 mlx5e_post_umr_wqe(rq, ix); 446 return 0; 447 } 448 449 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) 450 { 451 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 452 453 mlx5e_free_rx_mpwqe(rq, wi); 454 } 455 456 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq) 457 { 458 struct mlx5_wq_ll *wq = &rq->wq; 459 int err; 460 461 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED))) 462 return false; 463 464 if (mlx5_wq_ll_is_full(wq)) 465 return false; 466 467 do { 468 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); 469 470 err = mlx5e_alloc_rx_wqe(rq, wqe, wq->head); 471 if (unlikely(err)) { 472 rq->stats.buff_alloc_err++; 473 break; 474 } 475 476 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); 477 } while (!mlx5_wq_ll_is_full(wq)); 478 479 /* ensure wqes are visible to device before updating doorbell record */ 480 dma_wmb(); 481 482 mlx5_wq_ll_update_db_record(wq); 483 484 return !!err; 485 } 486 487 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq, 488 struct mlx5e_icosq *sq, 489 struct mlx5e_rq *rq, 490 struct mlx5_cqe64 *cqe, 491 u16 *sqcc) 492 { 493 struct mlx5_wq_cyc *wq = &sq->wq; 494 u16 ci = be16_to_cpu(cqe->wqe_counter) & wq->sz_m1; 495 struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci]; 496 497 mlx5_cqwq_pop(&cq->wq); 498 *sqcc += icowi->num_wqebbs; 499 500 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) { 501 WARN_ONCE(true, "mlx5e: Bad OP in ICOSQ CQE: 0x%x\n", 502 cqe->op_own); 503 return; 504 } 505 506 if (likely(icowi->opcode == MLX5_OPCODE_UMR)) { 507 mlx5e_post_rx_mpwqe(rq); 508 return; 509 } 510 511 if (unlikely(icowi->opcode != MLX5_OPCODE_NOP)) 512 WARN_ONCE(true, 513 "mlx5e: Bad OPCODE in ICOSQ WQE info: 0x%x\n", 514 icowi->opcode); 515 } 516 517 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq) 518 { 519 struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq); 520 struct mlx5_cqe64 *cqe; 521 u16 sqcc; 522 523 if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED))) 524 return; 525 526 cqe = mlx5_cqwq_get_cqe(&cq->wq); 527 if (likely(!cqe)) 528 return; 529 530 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(), 531 * otherwise a cq overrun may occur 532 */ 533 sqcc = sq->cc; 534 535 /* by design, there's only a single cqe */ 536 mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe, &sqcc); 537 538 mlx5_cqwq_update_db_record(&cq->wq); 539 540 /* ensure cq space is freed before enabling more cqes */ 541 wmb(); 542 543 sq->cc = sqcc; 544 } 545 546 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq) 547 { 548 struct mlx5_wq_ll *wq = &rq->wq; 549 550 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED))) 551 return false; 552 553 mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq); 554 555 if (mlx5_wq_ll_is_full(wq)) 556 return false; 557 558 if (!rq->mpwqe.umr_in_progress) 559 mlx5e_alloc_rx_mpwqe(rq, wq->head); 560 561 return true; 562 } 563 564 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe, 565 u32 cqe_bcnt) 566 { 567 struct ethhdr *eth = (struct ethhdr *)(skb->data); 568 struct tcphdr *tcp; 569 int network_depth = 0; 570 __be16 proto; 571 u16 tot_len; 572 void *ip_p; 573 574 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe); 575 u8 tcp_ack = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) || 576 (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA); 577 578 skb->mac_len = ETH_HLEN; 579 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth); 580 581 tot_len = cqe_bcnt - network_depth; 582 ip_p = skb->data + network_depth; 583 584 if (proto == htons(ETH_P_IP)) { 585 struct iphdr *ipv4 = ip_p; 586 587 tcp = ip_p + sizeof(struct iphdr); 588 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 589 590 ipv4->ttl = cqe->lro_min_ttl; 591 ipv4->tot_len = cpu_to_be16(tot_len); 592 ipv4->check = 0; 593 ipv4->check = ip_fast_csum((unsigned char *)ipv4, 594 ipv4->ihl); 595 } else { 596 struct ipv6hdr *ipv6 = ip_p; 597 598 tcp = ip_p + sizeof(struct ipv6hdr); 599 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 600 601 ipv6->hop_limit = cqe->lro_min_ttl; 602 ipv6->payload_len = cpu_to_be16(tot_len - 603 sizeof(struct ipv6hdr)); 604 } 605 606 tcp->psh = get_cqe_lro_tcppsh(cqe); 607 608 if (tcp_ack) { 609 tcp->ack = 1; 610 tcp->ack_seq = cqe->lro_ack_seq_num; 611 tcp->window = cqe->lro_tcp_win; 612 } 613 } 614 615 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe, 616 struct sk_buff *skb) 617 { 618 u8 cht = cqe->rss_hash_type; 619 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 : 620 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 : 621 PKT_HASH_TYPE_NONE; 622 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht); 623 } 624 625 static inline bool is_first_ethertype_ip(struct sk_buff *skb) 626 { 627 __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto; 628 629 return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6)); 630 } 631 632 static inline void mlx5e_handle_csum(struct net_device *netdev, 633 struct mlx5_cqe64 *cqe, 634 struct mlx5e_rq *rq, 635 struct sk_buff *skb, 636 bool lro) 637 { 638 if (unlikely(!(netdev->features & NETIF_F_RXCSUM))) 639 goto csum_none; 640 641 if (lro) { 642 skb->ip_summed = CHECKSUM_UNNECESSARY; 643 return; 644 } 645 646 if (is_first_ethertype_ip(skb)) { 647 skb->ip_summed = CHECKSUM_COMPLETE; 648 skb->csum = csum_unfold((__force __sum16)cqe->check_sum); 649 rq->stats.csum_complete++; 650 return; 651 } 652 653 if (likely((cqe->hds_ip_ext & CQE_L3_OK) && 654 (cqe->hds_ip_ext & CQE_L4_OK))) { 655 skb->ip_summed = CHECKSUM_UNNECESSARY; 656 if (cqe_is_tunneled(cqe)) { 657 skb->csum_level = 1; 658 skb->encapsulation = 1; 659 rq->stats.csum_unnecessary_inner++; 660 } 661 return; 662 } 663 csum_none: 664 skb->ip_summed = CHECKSUM_NONE; 665 rq->stats.csum_none++; 666 } 667 668 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe, 669 u32 cqe_bcnt, 670 struct mlx5e_rq *rq, 671 struct sk_buff *skb) 672 { 673 struct net_device *netdev = rq->netdev; 674 struct mlx5e_tstamp *tstamp = rq->tstamp; 675 int lro_num_seg; 676 677 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24; 678 if (lro_num_seg > 1) { 679 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt); 680 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg); 681 /* Subtract one since we already counted this as one 682 * "regular" packet in mlx5e_complete_rx_cqe() 683 */ 684 rq->stats.packets += lro_num_seg - 1; 685 rq->stats.lro_packets++; 686 rq->stats.lro_bytes += cqe_bcnt; 687 } 688 689 if (unlikely(mlx5e_rx_hw_stamp(tstamp))) 690 mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb)); 691 692 skb_record_rx_queue(skb, rq->ix); 693 694 if (likely(netdev->features & NETIF_F_RXHASH)) 695 mlx5e_skb_set_hash(cqe, skb); 696 697 if (cqe_has_vlan(cqe)) 698 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 699 be16_to_cpu(cqe->vlan_info)); 700 701 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK; 702 703 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg); 704 skb->protocol = eth_type_trans(skb, netdev); 705 } 706 707 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq, 708 struct mlx5_cqe64 *cqe, 709 u32 cqe_bcnt, 710 struct sk_buff *skb) 711 { 712 rq->stats.packets++; 713 rq->stats.bytes += cqe_bcnt; 714 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb); 715 } 716 717 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq) 718 { 719 struct mlx5_wq_cyc *wq = &sq->wq; 720 struct mlx5e_tx_wqe *wqe; 721 u16 pi = (sq->pc - 1) & wq->sz_m1; /* last pi */ 722 723 wqe = mlx5_wq_cyc_get_wqe(wq, pi); 724 725 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &wqe->ctrl); 726 } 727 728 static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq, 729 struct mlx5e_dma_info *di, 730 const struct xdp_buff *xdp) 731 { 732 struct mlx5e_xdpsq *sq = &rq->xdpsq; 733 struct mlx5_wq_cyc *wq = &sq->wq; 734 u16 pi = sq->pc & wq->sz_m1; 735 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi); 736 737 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; 738 struct mlx5_wqe_eth_seg *eseg = &wqe->eth; 739 struct mlx5_wqe_data_seg *dseg; 740 741 ptrdiff_t data_offset = xdp->data - xdp->data_hard_start; 742 dma_addr_t dma_addr = di->addr + data_offset; 743 unsigned int dma_len = xdp->data_end - xdp->data; 744 745 prefetchw(wqe); 746 747 if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE || 748 MLX5E_SW2HW_MTU(rq->channel->priv, rq->netdev->mtu) < dma_len)) { 749 rq->stats.xdp_drop++; 750 return false; 751 } 752 753 if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1))) { 754 if (sq->db.doorbell) { 755 /* SQ is full, ring doorbell */ 756 mlx5e_xmit_xdp_doorbell(sq); 757 sq->db.doorbell = false; 758 } 759 rq->stats.xdp_tx_full++; 760 return false; 761 } 762 763 dma_sync_single_for_device(sq->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE); 764 765 cseg->fm_ce_se = 0; 766 767 dseg = (struct mlx5_wqe_data_seg *)eseg + 1; 768 769 /* copy the inline part if required */ 770 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) { 771 memcpy(eseg->inline_hdr.start, xdp->data, MLX5E_XDP_MIN_INLINE); 772 eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE); 773 dma_len -= MLX5E_XDP_MIN_INLINE; 774 dma_addr += MLX5E_XDP_MIN_INLINE; 775 dseg++; 776 } 777 778 /* write the dma part */ 779 dseg->addr = cpu_to_be64(dma_addr); 780 dseg->byte_count = cpu_to_be32(dma_len); 781 782 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND); 783 784 /* move page to reference to sq responsibility, 785 * and mark so it's not put back in page-cache. 786 */ 787 rq->wqe.xdp_xmit = true; 788 sq->db.di[pi] = *di; 789 sq->pc++; 790 791 sq->db.doorbell = true; 792 793 rq->stats.xdp_tx++; 794 return true; 795 } 796 797 /* returns true if packet was consumed by xdp */ 798 static inline int mlx5e_xdp_handle(struct mlx5e_rq *rq, 799 struct mlx5e_dma_info *di, 800 void *va, u16 *rx_headroom, u32 *len) 801 { 802 const struct bpf_prog *prog = READ_ONCE(rq->xdp_prog); 803 struct xdp_buff xdp; 804 u32 act; 805 806 if (!prog) 807 return false; 808 809 xdp.data = va + *rx_headroom; 810 xdp.data_end = xdp.data + *len; 811 xdp.data_hard_start = va; 812 813 act = bpf_prog_run_xdp(prog, &xdp); 814 switch (act) { 815 case XDP_PASS: 816 *rx_headroom = xdp.data - xdp.data_hard_start; 817 *len = xdp.data_end - xdp.data; 818 return false; 819 case XDP_TX: 820 if (unlikely(!mlx5e_xmit_xdp_frame(rq, di, &xdp))) 821 trace_xdp_exception(rq->netdev, prog, act); 822 return true; 823 default: 824 bpf_warn_invalid_xdp_action(act); 825 case XDP_ABORTED: 826 trace_xdp_exception(rq->netdev, prog, act); 827 case XDP_DROP: 828 rq->stats.xdp_drop++; 829 return true; 830 } 831 } 832 833 static inline 834 struct sk_buff *skb_from_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, 835 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt) 836 { 837 struct mlx5e_dma_info *di = &wi->di; 838 u16 rx_headroom = rq->buff.headroom; 839 struct sk_buff *skb; 840 void *va, *data; 841 bool consumed; 842 u32 frag_size; 843 844 va = page_address(di->page) + wi->offset; 845 data = va + rx_headroom; 846 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt); 847 848 dma_sync_single_range_for_cpu(rq->pdev, 849 di->addr + wi->offset, 850 0, frag_size, 851 DMA_FROM_DEVICE); 852 prefetch(data); 853 wi->offset += frag_size; 854 855 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { 856 rq->stats.wqe_err++; 857 return NULL; 858 } 859 860 rcu_read_lock(); 861 consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt); 862 rcu_read_unlock(); 863 if (consumed) 864 return NULL; /* page/packet was consumed by XDP */ 865 866 skb = build_skb(va, frag_size); 867 if (unlikely(!skb)) { 868 rq->stats.buff_alloc_err++; 869 return NULL; 870 } 871 872 /* queue up for recycling/reuse */ 873 page_ref_inc(di->page); 874 875 skb_reserve(skb, rx_headroom); 876 skb_put(skb, cqe_bcnt); 877 878 return skb; 879 } 880 881 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 882 { 883 struct mlx5e_wqe_frag_info *wi; 884 struct mlx5e_rx_wqe *wqe; 885 __be16 wqe_counter_be; 886 struct sk_buff *skb; 887 u16 wqe_counter; 888 u32 cqe_bcnt; 889 890 wqe_counter_be = cqe->wqe_counter; 891 wqe_counter = be16_to_cpu(wqe_counter_be); 892 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 893 wi = &rq->wqe.frag_info[wqe_counter]; 894 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 895 896 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 897 if (!skb) { 898 /* probably for XDP */ 899 if (rq->wqe.xdp_xmit) { 900 wi->di.page = NULL; 901 rq->wqe.xdp_xmit = false; 902 /* do not return page to cache, it will be returned on XDP_TX completion */ 903 goto wq_ll_pop; 904 } 905 /* probably an XDP_DROP, save the page-reuse checks */ 906 mlx5e_free_rx_wqe(rq, wi); 907 goto wq_ll_pop; 908 } 909 910 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 911 napi_gro_receive(rq->cq.napi, skb); 912 913 mlx5e_free_rx_wqe_reuse(rq, wi); 914 wq_ll_pop: 915 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 916 &wqe->next.next_wqe_index); 917 } 918 919 #ifdef CONFIG_MLX5_ESWITCH 920 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 921 { 922 struct net_device *netdev = rq->netdev; 923 struct mlx5e_priv *priv = netdev_priv(netdev); 924 struct mlx5e_rep_priv *rpriv = priv->ppriv; 925 struct mlx5_eswitch_rep *rep = rpriv->rep; 926 struct mlx5e_wqe_frag_info *wi; 927 struct mlx5e_rx_wqe *wqe; 928 struct sk_buff *skb; 929 __be16 wqe_counter_be; 930 u16 wqe_counter; 931 u32 cqe_bcnt; 932 933 wqe_counter_be = cqe->wqe_counter; 934 wqe_counter = be16_to_cpu(wqe_counter_be); 935 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 936 wi = &rq->wqe.frag_info[wqe_counter]; 937 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 938 939 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 940 if (!skb) { 941 if (rq->wqe.xdp_xmit) { 942 wi->di.page = NULL; 943 rq->wqe.xdp_xmit = false; 944 /* do not return page to cache, it will be returned on XDP_TX completion */ 945 goto wq_ll_pop; 946 } 947 /* probably an XDP_DROP, save the page-reuse checks */ 948 mlx5e_free_rx_wqe(rq, wi); 949 goto wq_ll_pop; 950 } 951 952 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 953 954 if (rep->vlan && skb_vlan_tag_present(skb)) 955 skb_vlan_pop(skb); 956 957 napi_gro_receive(rq->cq.napi, skb); 958 959 mlx5e_free_rx_wqe_reuse(rq, wi); 960 wq_ll_pop: 961 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 962 &wqe->next.next_wqe_index); 963 } 964 #endif 965 966 static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq, 967 struct mlx5_cqe64 *cqe, 968 struct mlx5e_mpw_info *wi, 969 u32 cqe_bcnt, 970 struct sk_buff *skb) 971 { 972 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe); 973 u32 wqe_offset = stride_ix << rq->mpwqe.log_stride_sz; 974 u32 head_offset = wqe_offset & (PAGE_SIZE - 1); 975 u32 page_idx = wqe_offset >> PAGE_SHIFT; 976 u32 head_page_idx = page_idx; 977 u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt); 978 u32 frag_offset = head_offset + headlen; 979 u16 byte_cnt = cqe_bcnt - headlen; 980 981 if (unlikely(frag_offset >= PAGE_SIZE)) { 982 page_idx++; 983 frag_offset -= PAGE_SIZE; 984 } 985 986 while (byte_cnt) { 987 u32 pg_consumed_bytes = 988 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt); 989 990 mlx5e_add_skb_frag_mpwqe(rq, skb, wi, page_idx, frag_offset, 991 pg_consumed_bytes); 992 byte_cnt -= pg_consumed_bytes; 993 frag_offset = 0; 994 page_idx++; 995 } 996 /* copy header */ 997 mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, wi, head_page_idx, 998 head_offset, headlen); 999 /* skb linear part was allocated with headlen and aligned to long */ 1000 skb->tail += headlen; 1001 skb->len += headlen; 1002 } 1003 1004 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1005 { 1006 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe); 1007 u16 wqe_id = be16_to_cpu(cqe->wqe_id); 1008 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id]; 1009 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id); 1010 struct sk_buff *skb; 1011 u16 cqe_bcnt; 1012 1013 wi->consumed_strides += cstrides; 1014 1015 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { 1016 rq->stats.wqe_err++; 1017 goto mpwrq_cqe_out; 1018 } 1019 1020 if (unlikely(mpwrq_is_filler_cqe(cqe))) { 1021 rq->stats.mpwqe_filler++; 1022 goto mpwrq_cqe_out; 1023 } 1024 1025 skb = napi_alloc_skb(rq->cq.napi, 1026 ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, 1027 sizeof(long))); 1028 if (unlikely(!skb)) { 1029 rq->stats.buff_alloc_err++; 1030 goto mpwrq_cqe_out; 1031 } 1032 1033 prefetchw(skb->data); 1034 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe); 1035 1036 mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb); 1037 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1038 napi_gro_receive(rq->cq.napi, skb); 1039 1040 mpwrq_cqe_out: 1041 if (likely(wi->consumed_strides < rq->mpwqe.num_strides)) 1042 return; 1043 1044 mlx5e_free_rx_mpwqe(rq, wi); 1045 mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index); 1046 } 1047 1048 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget) 1049 { 1050 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq); 1051 struct mlx5e_xdpsq *xdpsq; 1052 struct mlx5_cqe64 *cqe; 1053 int work_done = 0; 1054 1055 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED))) 1056 return 0; 1057 1058 if (cq->decmprs_left) 1059 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget); 1060 1061 cqe = mlx5_cqwq_get_cqe(&cq->wq); 1062 if (!cqe) 1063 return 0; 1064 1065 xdpsq = &rq->xdpsq; 1066 1067 do { 1068 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) { 1069 work_done += 1070 mlx5e_decompress_cqes_start(rq, cq, 1071 budget - work_done); 1072 continue; 1073 } 1074 1075 mlx5_cqwq_pop(&cq->wq); 1076 1077 rq->handle_rx_cqe(rq, cqe); 1078 } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq))); 1079 1080 if (xdpsq->db.doorbell) { 1081 mlx5e_xmit_xdp_doorbell(xdpsq); 1082 xdpsq->db.doorbell = false; 1083 } 1084 1085 mlx5_cqwq_update_db_record(&cq->wq); 1086 1087 /* ensure cq space is freed before enabling more cqes */ 1088 wmb(); 1089 1090 return work_done; 1091 } 1092 1093 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq) 1094 { 1095 struct mlx5e_xdpsq *sq; 1096 struct mlx5_cqe64 *cqe; 1097 struct mlx5e_rq *rq; 1098 u16 sqcc; 1099 int i; 1100 1101 sq = container_of(cq, struct mlx5e_xdpsq, cq); 1102 1103 if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED))) 1104 return false; 1105 1106 cqe = mlx5_cqwq_get_cqe(&cq->wq); 1107 if (!cqe) 1108 return false; 1109 1110 rq = container_of(sq, struct mlx5e_rq, xdpsq); 1111 1112 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(), 1113 * otherwise a cq overrun may occur 1114 */ 1115 sqcc = sq->cc; 1116 1117 i = 0; 1118 do { 1119 u16 wqe_counter; 1120 bool last_wqe; 1121 1122 mlx5_cqwq_pop(&cq->wq); 1123 1124 wqe_counter = be16_to_cpu(cqe->wqe_counter); 1125 1126 do { 1127 struct mlx5e_dma_info *di; 1128 u16 ci; 1129 1130 last_wqe = (sqcc == wqe_counter); 1131 1132 ci = sqcc & sq->wq.sz_m1; 1133 di = &sq->db.di[ci]; 1134 1135 sqcc++; 1136 /* Recycle RX page */ 1137 mlx5e_page_release(rq, di, true); 1138 } while (!last_wqe); 1139 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq))); 1140 1141 mlx5_cqwq_update_db_record(&cq->wq); 1142 1143 /* ensure cq space is freed before enabling more cqes */ 1144 wmb(); 1145 1146 sq->cc = sqcc; 1147 return (i == MLX5E_TX_CQ_POLL_BUDGET); 1148 } 1149 1150 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq) 1151 { 1152 struct mlx5e_rq *rq = container_of(sq, struct mlx5e_rq, xdpsq); 1153 struct mlx5e_dma_info *di; 1154 u16 ci; 1155 1156 while (sq->cc != sq->pc) { 1157 ci = sq->cc & sq->wq.sz_m1; 1158 di = &sq->db.di[ci]; 1159 sq->cc++; 1160 1161 mlx5e_page_release(rq, di, false); 1162 } 1163 } 1164 1165 #ifdef CONFIG_MLX5_CORE_IPOIB 1166 1167 #define MLX5_IB_GRH_DGID_OFFSET 24 1168 #define MLX5_GID_SIZE 16 1169 1170 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq, 1171 struct mlx5_cqe64 *cqe, 1172 u32 cqe_bcnt, 1173 struct sk_buff *skb) 1174 { 1175 struct net_device *netdev = rq->netdev; 1176 struct mlx5e_tstamp *tstamp = rq->tstamp; 1177 char *pseudo_header; 1178 u8 *dgid; 1179 u8 g; 1180 1181 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3; 1182 dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET; 1183 if ((!g) || dgid[0] != 0xff) 1184 skb->pkt_type = PACKET_HOST; 1185 else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0) 1186 skb->pkt_type = PACKET_BROADCAST; 1187 else 1188 skb->pkt_type = PACKET_MULTICAST; 1189 1190 /* TODO: IB/ipoib: Allow mcast packets from other VFs 1191 * 68996a6e760e5c74654723eeb57bf65628ae87f4 1192 */ 1193 1194 skb_pull(skb, MLX5_IB_GRH_BYTES); 1195 1196 skb->protocol = *((__be16 *)(skb->data)); 1197 1198 skb->ip_summed = CHECKSUM_COMPLETE; 1199 skb->csum = csum_unfold((__force __sum16)cqe->check_sum); 1200 1201 if (unlikely(mlx5e_rx_hw_stamp(tstamp))) 1202 mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb)); 1203 1204 skb_record_rx_queue(skb, rq->ix); 1205 1206 if (likely(netdev->features & NETIF_F_RXHASH)) 1207 mlx5e_skb_set_hash(cqe, skb); 1208 1209 /* 20 bytes of ipoib header and 4 for encap existing */ 1210 pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN); 1211 memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN); 1212 skb_reset_mac_header(skb); 1213 skb_pull(skb, MLX5_IPOIB_HARD_LEN); 1214 1215 skb->dev = netdev; 1216 1217 rq->stats.csum_complete++; 1218 rq->stats.packets++; 1219 rq->stats.bytes += cqe_bcnt; 1220 } 1221 1222 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1223 { 1224 struct mlx5e_wqe_frag_info *wi; 1225 struct mlx5e_rx_wqe *wqe; 1226 __be16 wqe_counter_be; 1227 struct sk_buff *skb; 1228 u16 wqe_counter; 1229 u32 cqe_bcnt; 1230 1231 wqe_counter_be = cqe->wqe_counter; 1232 wqe_counter = be16_to_cpu(wqe_counter_be); 1233 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 1234 wi = &rq->wqe.frag_info[wqe_counter]; 1235 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 1236 1237 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 1238 if (!skb) 1239 goto wq_free_wqe; 1240 1241 mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1242 napi_gro_receive(rq->cq.napi, skb); 1243 1244 wq_free_wqe: 1245 mlx5e_free_rx_wqe_reuse(rq, wi); 1246 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 1247 &wqe->next.next_wqe_index); 1248 } 1249 1250 #endif /* CONFIG_MLX5_CORE_IPOIB */ 1251 1252 #ifdef CONFIG_MLX5_EN_IPSEC 1253 1254 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1255 { 1256 struct mlx5e_wqe_frag_info *wi; 1257 struct mlx5e_rx_wqe *wqe; 1258 __be16 wqe_counter_be; 1259 struct sk_buff *skb; 1260 u16 wqe_counter; 1261 u32 cqe_bcnt; 1262 1263 wqe_counter_be = cqe->wqe_counter; 1264 wqe_counter = be16_to_cpu(wqe_counter_be); 1265 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 1266 wi = &rq->wqe.frag_info[wqe_counter]; 1267 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 1268 1269 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 1270 if (unlikely(!skb)) { 1271 /* a DROP, save the page-reuse checks */ 1272 mlx5e_free_rx_wqe(rq, wi); 1273 goto wq_ll_pop; 1274 } 1275 skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb); 1276 if (unlikely(!skb)) { 1277 mlx5e_free_rx_wqe(rq, wi); 1278 goto wq_ll_pop; 1279 } 1280 1281 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1282 napi_gro_receive(rq->cq.napi, skb); 1283 1284 mlx5e_free_rx_wqe_reuse(rq, wi); 1285 wq_ll_pop: 1286 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 1287 &wqe->next.next_wqe_index); 1288 } 1289 1290 #endif /* CONFIG_MLX5_EN_IPSEC */ 1291