1 /* 2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/ip.h> 34 #include <linux/ipv6.h> 35 #include <linux/tcp.h> 36 #include <linux/bitmap.h> 37 #include <linux/filter.h> 38 #include <net/ip6_checksum.h> 39 #include <net/page_pool.h> 40 #include <net/inet_ecn.h> 41 #include <net/gro.h> 42 #include <net/udp.h> 43 #include <net/tcp.h> 44 #include <net/xdp_sock_drv.h> 45 #include "en.h" 46 #include "en/txrx.h" 47 #include "en_tc.h" 48 #include "eswitch.h" 49 #include "en_rep.h" 50 #include "en/rep/tc.h" 51 #include "ipoib/ipoib.h" 52 #include "en_accel/ipsec.h" 53 #include "en_accel/macsec.h" 54 #include "en_accel/ipsec_rxtx.h" 55 #include "en_accel/ktls_txrx.h" 56 #include "en/xdp.h" 57 #include "en/xsk/rx.h" 58 #include "en/health.h" 59 #include "en/params.h" 60 #include "devlink.h" 61 #include "en/devlink.h" 62 63 static struct sk_buff * 64 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, 65 struct mlx5_cqe64 *cqe, u16 cqe_bcnt, u32 head_offset, 66 u32 page_idx); 67 static struct sk_buff * 68 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, 69 struct mlx5_cqe64 *cqe, u16 cqe_bcnt, u32 head_offset, 70 u32 page_idx); 71 static void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); 72 static void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); 73 static void mlx5e_handle_rx_cqe_mpwrq_shampo(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); 74 75 const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic = { 76 .handle_rx_cqe = mlx5e_handle_rx_cqe, 77 .handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq, 78 .handle_rx_cqe_mpwqe_shampo = mlx5e_handle_rx_cqe_mpwrq_shampo, 79 }; 80 81 static inline void mlx5e_read_cqe_slot(struct mlx5_cqwq *wq, 82 u32 cqcc, void *data) 83 { 84 u32 ci = mlx5_cqwq_ctr2ix(wq, cqcc); 85 86 memcpy(data, mlx5_cqwq_get_wqe(wq, ci), sizeof(struct mlx5_cqe64)); 87 } 88 89 static void mlx5e_read_enhanced_title_slot(struct mlx5e_rq *rq, 90 struct mlx5_cqe64 *cqe) 91 { 92 struct mlx5e_cq_decomp *cqd = &rq->cqd; 93 struct mlx5_cqe64 *title = &cqd->title; 94 95 memcpy(title, cqe, sizeof(struct mlx5_cqe64)); 96 97 if (likely(test_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &rq->state))) 98 return; 99 100 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) 101 cqd->wqe_counter = mpwrq_get_cqe_stride_index(title) + 102 mpwrq_get_cqe_consumed_strides(title); 103 else 104 cqd->wqe_counter = 105 mlx5_wq_cyc_ctr2ix(&rq->wqe.wq, be16_to_cpu(title->wqe_counter) + 1); 106 } 107 108 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq, 109 struct mlx5_cqwq *wq, 110 u32 cqcc) 111 { 112 struct mlx5e_cq_decomp *cqd = &rq->cqd; 113 struct mlx5_cqe64 *title = &cqd->title; 114 115 mlx5e_read_cqe_slot(wq, cqcc, title); 116 cqd->left = be32_to_cpu(title->byte_cnt); 117 cqd->wqe_counter = be16_to_cpu(title->wqe_counter); 118 rq->stats->cqe_compress_blks++; 119 } 120 121 static inline void mlx5e_read_mini_arr_slot(struct mlx5_cqwq *wq, 122 struct mlx5e_cq_decomp *cqd, 123 u32 cqcc) 124 { 125 mlx5e_read_cqe_slot(wq, cqcc, cqd->mini_arr); 126 cqd->mini_arr_idx = 0; 127 } 128 129 static inline void mlx5e_cqes_update_owner(struct mlx5_cqwq *wq, int n) 130 { 131 u32 cqcc = wq->cc; 132 u8 op_own = mlx5_cqwq_get_ctr_wrap_cnt(wq, cqcc) & 1; 133 u32 ci = mlx5_cqwq_ctr2ix(wq, cqcc); 134 u32 wq_sz = mlx5_cqwq_get_size(wq); 135 u32 ci_top = min_t(u32, wq_sz, ci + n); 136 137 for (; ci < ci_top; ci++, n--) { 138 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci); 139 140 cqe->op_own = op_own; 141 } 142 143 if (unlikely(ci == wq_sz)) { 144 op_own = !op_own; 145 for (ci = 0; ci < n; ci++) { 146 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci); 147 148 cqe->op_own = op_own; 149 } 150 } 151 } 152 153 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq, 154 struct mlx5_cqwq *wq, 155 u32 cqcc) 156 { 157 struct mlx5e_cq_decomp *cqd = &rq->cqd; 158 struct mlx5_mini_cqe8 *mini_cqe = &cqd->mini_arr[cqd->mini_arr_idx]; 159 struct mlx5_cqe64 *title = &cqd->title; 160 161 title->byte_cnt = mini_cqe->byte_cnt; 162 title->check_sum = mini_cqe->checksum; 163 title->op_own &= 0xf0; 164 title->op_own |= 0x01 & (cqcc >> wq->fbc.log_sz); 165 166 /* state bit set implies linked-list striding RQ wq type and 167 * HW stride index capability supported 168 */ 169 if (test_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &rq->state)) { 170 title->wqe_counter = mini_cqe->stridx; 171 return; 172 } 173 174 /* HW stride index capability not supported */ 175 title->wqe_counter = cpu_to_be16(cqd->wqe_counter); 176 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) 177 cqd->wqe_counter += mpwrq_get_cqe_consumed_strides(title); 178 else 179 cqd->wqe_counter = 180 mlx5_wq_cyc_ctr2ix(&rq->wqe.wq, cqd->wqe_counter + 1); 181 } 182 183 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq, 184 struct mlx5_cqwq *wq, 185 u32 cqcc) 186 { 187 struct mlx5e_cq_decomp *cqd = &rq->cqd; 188 189 mlx5e_decompress_cqe(rq, wq, cqcc); 190 cqd->title.rss_hash_type = 0; 191 cqd->title.rss_hash_result = 0; 192 } 193 194 static u32 mlx5e_decompress_enhanced_cqe(struct mlx5e_rq *rq, 195 struct mlx5_cqwq *wq, 196 struct mlx5_cqe64 *cqe, 197 int budget_rem) 198 { 199 struct mlx5e_cq_decomp *cqd = &rq->cqd; 200 u32 cqcc, left; 201 u32 i; 202 203 left = get_cqe_enhanced_num_mini_cqes(cqe); 204 /* Here we avoid breaking the cqe compression session in the middle 205 * in case budget is not sufficient to handle all of it. In this case 206 * we return work_done == budget_rem to give 'busy' napi indication. 207 */ 208 if (unlikely(left > budget_rem)) 209 return budget_rem; 210 211 cqcc = wq->cc; 212 cqd->mini_arr_idx = 0; 213 memcpy(cqd->mini_arr, cqe, sizeof(struct mlx5_cqe64)); 214 for (i = 0; i < left; i++, cqd->mini_arr_idx++, cqcc++) { 215 mlx5e_decompress_cqe_no_hash(rq, wq, cqcc); 216 INDIRECT_CALL_3(rq->handle_rx_cqe, mlx5e_handle_rx_cqe_mpwrq, 217 mlx5e_handle_rx_cqe, mlx5e_handle_rx_cqe_mpwrq_shampo, 218 rq, &cqd->title); 219 } 220 wq->cc = cqcc; 221 rq->stats->cqe_compress_pkts += left; 222 223 return left; 224 } 225 226 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq, 227 struct mlx5_cqwq *wq, 228 int update_owner_only, 229 int budget_rem) 230 { 231 struct mlx5e_cq_decomp *cqd = &rq->cqd; 232 u32 cqcc = wq->cc + update_owner_only; 233 u32 cqe_count; 234 u32 i; 235 236 cqe_count = min_t(u32, cqd->left, budget_rem); 237 238 for (i = update_owner_only; i < cqe_count; 239 i++, cqd->mini_arr_idx++, cqcc++) { 240 if (cqd->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE) 241 mlx5e_read_mini_arr_slot(wq, cqd, cqcc); 242 243 mlx5e_decompress_cqe_no_hash(rq, wq, cqcc); 244 INDIRECT_CALL_3(rq->handle_rx_cqe, mlx5e_handle_rx_cqe_mpwrq, 245 mlx5e_handle_rx_cqe_mpwrq_shampo, mlx5e_handle_rx_cqe, 246 rq, &cqd->title); 247 } 248 mlx5e_cqes_update_owner(wq, cqcc - wq->cc); 249 wq->cc = cqcc; 250 cqd->left -= cqe_count; 251 rq->stats->cqe_compress_pkts += cqe_count; 252 253 return cqe_count; 254 } 255 256 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq, 257 struct mlx5_cqwq *wq, 258 int budget_rem) 259 { 260 struct mlx5e_cq_decomp *cqd = &rq->cqd; 261 u32 cc = wq->cc; 262 263 mlx5e_read_title_slot(rq, wq, cc); 264 mlx5e_read_mini_arr_slot(wq, cqd, cc + 1); 265 mlx5e_decompress_cqe(rq, wq, cc); 266 INDIRECT_CALL_3(rq->handle_rx_cqe, mlx5e_handle_rx_cqe_mpwrq, 267 mlx5e_handle_rx_cqe_mpwrq_shampo, mlx5e_handle_rx_cqe, 268 rq, &cqd->title); 269 cqd->mini_arr_idx++; 270 271 return mlx5e_decompress_cqes_cont(rq, wq, 1, budget_rem); 272 } 273 274 #define MLX5E_PAGECNT_BIAS_MAX (PAGE_SIZE / 64) 275 276 static int mlx5e_page_alloc_fragmented(struct mlx5e_rq *rq, 277 struct mlx5e_frag_page *frag_page) 278 { 279 struct page *page; 280 281 page = page_pool_dev_alloc_pages(rq->page_pool); 282 if (unlikely(!page)) 283 return -ENOMEM; 284 285 page_pool_fragment_page(page, MLX5E_PAGECNT_BIAS_MAX); 286 287 *frag_page = (struct mlx5e_frag_page) { 288 .page = page, 289 .frags = 0, 290 }; 291 292 return 0; 293 } 294 295 static void mlx5e_page_release_fragmented(struct mlx5e_rq *rq, 296 struct mlx5e_frag_page *frag_page, 297 bool recycle) 298 { 299 u16 drain_count = MLX5E_PAGECNT_BIAS_MAX - frag_page->frags; 300 struct page *page = frag_page->page; 301 302 if (page_pool_defrag_page(page, drain_count) == 0) 303 page_pool_put_defragged_page(rq->page_pool, page, -1, recycle); 304 } 305 306 static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq, 307 struct mlx5e_wqe_frag_info *frag) 308 { 309 int err = 0; 310 311 if (!frag->offset) 312 /* On first frag (offset == 0), replenish page. 313 * Other frags that point to the same page (with a different 314 * offset) should just use the new one without replenishing again 315 * by themselves. 316 */ 317 err = mlx5e_page_alloc_fragmented(rq, frag->frag_page); 318 319 return err; 320 } 321 322 static inline void mlx5e_put_rx_frag(struct mlx5e_rq *rq, 323 struct mlx5e_wqe_frag_info *frag, 324 bool recycle) 325 { 326 if (frag->last_in_page) 327 mlx5e_page_release_fragmented(rq, frag->frag_page, recycle); 328 } 329 330 static inline struct mlx5e_wqe_frag_info *get_frag(struct mlx5e_rq *rq, u16 ix) 331 { 332 return &rq->wqe.frags[ix << rq->wqe.info.log_num_frags]; 333 } 334 335 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe_cyc *wqe, 336 u16 ix) 337 { 338 struct mlx5e_wqe_frag_info *frag = get_frag(rq, ix); 339 int err; 340 int i; 341 342 for (i = 0; i < rq->wqe.info.num_frags; i++, frag++) { 343 dma_addr_t addr; 344 u16 headroom; 345 346 err = mlx5e_get_rx_frag(rq, frag); 347 if (unlikely(err)) 348 goto free_frags; 349 350 headroom = i == 0 ? rq->buff.headroom : 0; 351 addr = page_pool_get_dma_addr(frag->frag_page->page); 352 wqe->data[i].addr = cpu_to_be64(addr + frag->offset + headroom); 353 } 354 355 return 0; 356 357 free_frags: 358 while (--i >= 0) 359 mlx5e_put_rx_frag(rq, --frag, true); 360 361 return err; 362 } 363 364 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq, 365 struct mlx5e_wqe_frag_info *wi, 366 bool recycle) 367 { 368 int i; 369 370 if (rq->xsk_pool) { 371 /* The `recycle` parameter is ignored, and the page is always 372 * put into the Reuse Ring, because there is no way to return 373 * the page to the userspace when the interface goes down. 374 */ 375 xsk_buff_free(*wi->xskp); 376 return; 377 } 378 379 for (i = 0; i < rq->wqe.info.num_frags; i++, wi++) 380 mlx5e_put_rx_frag(rq, wi, recycle); 381 } 382 383 static void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix) 384 { 385 struct mlx5e_wqe_frag_info *wi = get_frag(rq, ix); 386 387 mlx5e_free_rx_wqe(rq, wi, false); 388 } 389 390 static int mlx5e_alloc_rx_wqes(struct mlx5e_rq *rq, u16 ix, int wqe_bulk) 391 { 392 struct mlx5_wq_cyc *wq = &rq->wqe.wq; 393 int i; 394 395 for (i = 0; i < wqe_bulk; i++) { 396 int j = mlx5_wq_cyc_ctr2ix(wq, ix + i); 397 struct mlx5e_rx_wqe_cyc *wqe; 398 399 wqe = mlx5_wq_cyc_get_wqe(wq, j); 400 401 if (unlikely(mlx5e_alloc_rx_wqe(rq, wqe, j))) 402 break; 403 } 404 405 return i; 406 } 407 408 static inline void 409 mlx5e_add_skb_frag(struct mlx5e_rq *rq, struct sk_buff *skb, 410 struct page *page, u32 frag_offset, u32 len, 411 unsigned int truesize) 412 { 413 dma_addr_t addr = page_pool_get_dma_addr(page); 414 415 dma_sync_single_for_cpu(rq->pdev, addr + frag_offset, len, 416 rq->buff.map_dir); 417 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 418 page, frag_offset, len, truesize); 419 } 420 421 static inline void 422 mlx5e_copy_skb_header(struct mlx5e_rq *rq, struct sk_buff *skb, 423 struct page *page, dma_addr_t addr, 424 int offset_from, int dma_offset, u32 headlen) 425 { 426 const void *from = page_address(page) + offset_from; 427 /* Aligning len to sizeof(long) optimizes memcpy performance */ 428 unsigned int len = ALIGN(headlen, sizeof(long)); 429 430 dma_sync_single_for_cpu(rq->pdev, addr + dma_offset, len, 431 rq->buff.map_dir); 432 skb_copy_to_linear_data(skb, from, len); 433 } 434 435 static void 436 mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, bool recycle) 437 { 438 bool no_xdp_xmit; 439 int i; 440 441 /* A common case for AF_XDP. */ 442 if (bitmap_full(wi->xdp_xmit_bitmap, rq->mpwqe.pages_per_wqe)) 443 return; 444 445 no_xdp_xmit = bitmap_empty(wi->xdp_xmit_bitmap, rq->mpwqe.pages_per_wqe); 446 447 if (rq->xsk_pool) { 448 struct xdp_buff **xsk_buffs = wi->alloc_units.xsk_buffs; 449 450 /* The `recycle` parameter is ignored, and the page is always 451 * put into the Reuse Ring, because there is no way to return 452 * the page to the userspace when the interface goes down. 453 */ 454 for (i = 0; i < rq->mpwqe.pages_per_wqe; i++) 455 if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap)) 456 xsk_buff_free(xsk_buffs[i]); 457 } else { 458 for (i = 0; i < rq->mpwqe.pages_per_wqe; i++) { 459 if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap)) { 460 struct mlx5e_frag_page *frag_page; 461 462 frag_page = &wi->alloc_units.frag_pages[i]; 463 mlx5e_page_release_fragmented(rq, frag_page, recycle); 464 } 465 } 466 } 467 } 468 469 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq, u8 n) 470 { 471 struct mlx5_wq_ll *wq = &rq->mpwqe.wq; 472 473 do { 474 u16 next_wqe_index = mlx5_wq_ll_get_wqe_next_ix(wq, wq->head); 475 476 mlx5_wq_ll_push(wq, next_wqe_index); 477 } while (--n); 478 479 /* ensure wqes are visible to device before updating doorbell record */ 480 dma_wmb(); 481 482 mlx5_wq_ll_update_db_record(wq); 483 } 484 485 /* This function returns the size of the continuous free space inside a bitmap 486 * that starts from first and no longer than len including circular ones. 487 */ 488 static int bitmap_find_window(unsigned long *bitmap, int len, 489 int bitmap_size, int first) 490 { 491 int next_one, count; 492 493 next_one = find_next_bit(bitmap, bitmap_size, first); 494 if (next_one == bitmap_size) { 495 if (bitmap_size - first >= len) 496 return len; 497 next_one = find_next_bit(bitmap, bitmap_size, 0); 498 count = next_one + bitmap_size - first; 499 } else { 500 count = next_one - first; 501 } 502 503 return min(len, count); 504 } 505 506 static void build_klm_umr(struct mlx5e_icosq *sq, struct mlx5e_umr_wqe *umr_wqe, 507 __be32 key, u16 offset, u16 klm_len, u16 wqe_bbs) 508 { 509 memset(umr_wqe, 0, offsetof(struct mlx5e_umr_wqe, inline_klms)); 510 umr_wqe->ctrl.opmod_idx_opcode = 511 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) | 512 MLX5_OPCODE_UMR); 513 umr_wqe->ctrl.umr_mkey = key; 514 umr_wqe->ctrl.qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) 515 | MLX5E_KLM_UMR_DS_CNT(klm_len)); 516 umr_wqe->uctrl.flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE; 517 umr_wqe->uctrl.xlt_offset = cpu_to_be16(offset); 518 umr_wqe->uctrl.xlt_octowords = cpu_to_be16(klm_len); 519 umr_wqe->uctrl.mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 520 } 521 522 static int mlx5e_build_shampo_hd_umr(struct mlx5e_rq *rq, 523 struct mlx5e_icosq *sq, 524 u16 klm_entries, u16 index) 525 { 526 struct mlx5e_shampo_hd *shampo = rq->mpwqe.shampo; 527 u16 entries, pi, header_offset, err, wqe_bbs, new_entries; 528 u32 lkey = rq->mdev->mlx5e_res.hw_objs.mkey; 529 u16 page_index = shampo->curr_page_index; 530 struct mlx5e_frag_page *frag_page; 531 u64 addr = shampo->last_addr; 532 struct mlx5e_dma_info *dma_info; 533 struct mlx5e_umr_wqe *umr_wqe; 534 int headroom, i; 535 536 headroom = rq->buff.headroom; 537 new_entries = klm_entries - (shampo->pi & (MLX5_UMR_KLM_NUM_ENTRIES_ALIGNMENT - 1)); 538 entries = ALIGN(klm_entries, MLX5_UMR_KLM_NUM_ENTRIES_ALIGNMENT); 539 wqe_bbs = MLX5E_KLM_UMR_WQEBBS(entries); 540 pi = mlx5e_icosq_get_next_pi(sq, wqe_bbs); 541 umr_wqe = mlx5_wq_cyc_get_wqe(&sq->wq, pi); 542 build_klm_umr(sq, umr_wqe, shampo->key, index, entries, wqe_bbs); 543 544 frag_page = &shampo->pages[page_index]; 545 546 for (i = 0; i < entries; i++, index++) { 547 dma_info = &shampo->info[index]; 548 if (i >= klm_entries || (index < shampo->pi && shampo->pi - index < 549 MLX5_UMR_KLM_NUM_ENTRIES_ALIGNMENT)) 550 goto update_klm; 551 header_offset = (index & (MLX5E_SHAMPO_WQ_HEADER_PER_PAGE - 1)) << 552 MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE; 553 if (!(header_offset & (PAGE_SIZE - 1))) { 554 page_index = (page_index + 1) & (shampo->hd_per_wq - 1); 555 frag_page = &shampo->pages[page_index]; 556 557 err = mlx5e_page_alloc_fragmented(rq, frag_page); 558 if (unlikely(err)) 559 goto err_unmap; 560 561 addr = page_pool_get_dma_addr(frag_page->page); 562 563 dma_info->addr = addr; 564 dma_info->frag_page = frag_page; 565 } else { 566 dma_info->addr = addr + header_offset; 567 dma_info->frag_page = frag_page; 568 } 569 570 update_klm: 571 umr_wqe->inline_klms[i].bcount = 572 cpu_to_be32(MLX5E_RX_MAX_HEAD); 573 umr_wqe->inline_klms[i].key = cpu_to_be32(lkey); 574 umr_wqe->inline_klms[i].va = 575 cpu_to_be64(dma_info->addr + headroom); 576 } 577 578 sq->db.wqe_info[pi] = (struct mlx5e_icosq_wqe_info) { 579 .wqe_type = MLX5E_ICOSQ_WQE_SHAMPO_HD_UMR, 580 .num_wqebbs = wqe_bbs, 581 .shampo.len = new_entries, 582 }; 583 584 shampo->pi = (shampo->pi + new_entries) & (shampo->hd_per_wq - 1); 585 shampo->curr_page_index = page_index; 586 shampo->last_addr = addr; 587 sq->pc += wqe_bbs; 588 sq->doorbell_cseg = &umr_wqe->ctrl; 589 590 return 0; 591 592 err_unmap: 593 while (--i >= 0) { 594 dma_info = &shampo->info[--index]; 595 if (!(i & (MLX5E_SHAMPO_WQ_HEADER_PER_PAGE - 1))) { 596 dma_info->addr = ALIGN_DOWN(dma_info->addr, PAGE_SIZE); 597 mlx5e_page_release_fragmented(rq, dma_info->frag_page, true); 598 } 599 } 600 rq->stats->buff_alloc_err++; 601 return err; 602 } 603 604 static int mlx5e_alloc_rx_hd_mpwqe(struct mlx5e_rq *rq) 605 { 606 struct mlx5e_shampo_hd *shampo = rq->mpwqe.shampo; 607 u16 klm_entries, num_wqe, index, entries_before; 608 struct mlx5e_icosq *sq = rq->icosq; 609 int i, err, max_klm_entries, len; 610 611 max_klm_entries = MLX5E_MAX_KLM_PER_WQE(rq->mdev); 612 klm_entries = bitmap_find_window(shampo->bitmap, 613 shampo->hd_per_wqe, 614 shampo->hd_per_wq, shampo->pi); 615 if (!klm_entries) 616 return 0; 617 618 klm_entries += (shampo->pi & (MLX5_UMR_KLM_NUM_ENTRIES_ALIGNMENT - 1)); 619 index = ALIGN_DOWN(shampo->pi, MLX5_UMR_KLM_NUM_ENTRIES_ALIGNMENT); 620 entries_before = shampo->hd_per_wq - index; 621 622 if (unlikely(entries_before < klm_entries)) 623 num_wqe = DIV_ROUND_UP(entries_before, max_klm_entries) + 624 DIV_ROUND_UP(klm_entries - entries_before, max_klm_entries); 625 else 626 num_wqe = DIV_ROUND_UP(klm_entries, max_klm_entries); 627 628 for (i = 0; i < num_wqe; i++) { 629 len = (klm_entries > max_klm_entries) ? max_klm_entries : 630 klm_entries; 631 if (unlikely(index + len > shampo->hd_per_wq)) 632 len = shampo->hd_per_wq - index; 633 err = mlx5e_build_shampo_hd_umr(rq, sq, len, index); 634 if (unlikely(err)) 635 return err; 636 index = (index + len) & (rq->mpwqe.shampo->hd_per_wq - 1); 637 klm_entries -= len; 638 } 639 640 return 0; 641 } 642 643 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) 644 { 645 struct mlx5e_mpw_info *wi = mlx5e_get_mpw_info(rq, ix); 646 struct mlx5e_icosq *sq = rq->icosq; 647 struct mlx5e_frag_page *frag_page; 648 struct mlx5_wq_cyc *wq = &sq->wq; 649 struct mlx5e_umr_wqe *umr_wqe; 650 u32 offset; /* 17-bit value with MTT. */ 651 u16 pi; 652 int err; 653 int i; 654 655 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) { 656 err = mlx5e_alloc_rx_hd_mpwqe(rq); 657 if (unlikely(err)) 658 goto err; 659 } 660 661 pi = mlx5e_icosq_get_next_pi(sq, rq->mpwqe.umr_wqebbs); 662 umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi); 663 memcpy(umr_wqe, &rq->mpwqe.umr_wqe, sizeof(struct mlx5e_umr_wqe)); 664 665 frag_page = &wi->alloc_units.frag_pages[0]; 666 667 for (i = 0; i < rq->mpwqe.pages_per_wqe; i++, frag_page++) { 668 dma_addr_t addr; 669 670 err = mlx5e_page_alloc_fragmented(rq, frag_page); 671 if (unlikely(err)) 672 goto err_unmap; 673 addr = page_pool_get_dma_addr(frag_page->page); 674 umr_wqe->inline_mtts[i] = (struct mlx5_mtt) { 675 .ptag = cpu_to_be64(addr | MLX5_EN_WR), 676 }; 677 } 678 679 /* Pad if needed, in case the value set to ucseg->xlt_octowords 680 * in mlx5e_build_umr_wqe() needed alignment. 681 */ 682 if (rq->mpwqe.pages_per_wqe & (MLX5_UMR_MTT_NUM_ENTRIES_ALIGNMENT - 1)) { 683 int pad = ALIGN(rq->mpwqe.pages_per_wqe, MLX5_UMR_MTT_NUM_ENTRIES_ALIGNMENT) - 684 rq->mpwqe.pages_per_wqe; 685 686 memset(&umr_wqe->inline_mtts[rq->mpwqe.pages_per_wqe], 0, 687 sizeof(*umr_wqe->inline_mtts) * pad); 688 } 689 690 bitmap_zero(wi->xdp_xmit_bitmap, rq->mpwqe.pages_per_wqe); 691 wi->consumed_strides = 0; 692 693 umr_wqe->ctrl.opmod_idx_opcode = 694 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) | 695 MLX5_OPCODE_UMR); 696 697 offset = (ix * rq->mpwqe.mtts_per_wqe) * sizeof(struct mlx5_mtt) / MLX5_OCTWORD; 698 umr_wqe->uctrl.xlt_offset = cpu_to_be16(offset); 699 700 sq->db.wqe_info[pi] = (struct mlx5e_icosq_wqe_info) { 701 .wqe_type = MLX5E_ICOSQ_WQE_UMR_RX, 702 .num_wqebbs = rq->mpwqe.umr_wqebbs, 703 .umr.rq = rq, 704 }; 705 706 sq->pc += rq->mpwqe.umr_wqebbs; 707 708 sq->doorbell_cseg = &umr_wqe->ctrl; 709 710 return 0; 711 712 err_unmap: 713 while (--i >= 0) { 714 frag_page--; 715 mlx5e_page_release_fragmented(rq, frag_page, true); 716 } 717 718 err: 719 rq->stats->buff_alloc_err++; 720 721 return err; 722 } 723 724 /* This function is responsible to dealloc SHAMPO header buffer. 725 * close == true specifies that we are in the middle of closing RQ operation so 726 * we go over all the entries and if they are not in use we free them, 727 * otherwise we only go over a specific range inside the header buffer that are 728 * not in use. 729 */ 730 void mlx5e_shampo_dealloc_hd(struct mlx5e_rq *rq, u16 len, u16 start, bool close) 731 { 732 struct mlx5e_shampo_hd *shampo = rq->mpwqe.shampo; 733 struct mlx5e_frag_page *deleted_page = NULL; 734 int hd_per_wq = shampo->hd_per_wq; 735 struct mlx5e_dma_info *hd_info; 736 int i, index = start; 737 738 for (i = 0; i < len; i++, index++) { 739 if (index == hd_per_wq) 740 index = 0; 741 742 if (close && !test_bit(index, shampo->bitmap)) 743 continue; 744 745 hd_info = &shampo->info[index]; 746 hd_info->addr = ALIGN_DOWN(hd_info->addr, PAGE_SIZE); 747 if (hd_info->frag_page && hd_info->frag_page != deleted_page) { 748 deleted_page = hd_info->frag_page; 749 mlx5e_page_release_fragmented(rq, hd_info->frag_page, false); 750 } 751 752 hd_info->frag_page = NULL; 753 } 754 755 if (start + len > hd_per_wq) { 756 len -= hd_per_wq - start; 757 bitmap_clear(shampo->bitmap, start, hd_per_wq - start); 758 start = 0; 759 } 760 761 bitmap_clear(shampo->bitmap, start, len); 762 } 763 764 static void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) 765 { 766 struct mlx5e_mpw_info *wi = mlx5e_get_mpw_info(rq, ix); 767 /* Don't recycle, this function is called on rq/netdev close */ 768 mlx5e_free_rx_mpwqe(rq, wi, false); 769 } 770 771 INDIRECT_CALLABLE_SCOPE bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq) 772 { 773 struct mlx5_wq_cyc *wq = &rq->wqe.wq; 774 int wqe_bulk, count; 775 bool busy = false; 776 u16 head; 777 778 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state))) 779 return false; 780 781 if (mlx5_wq_cyc_missing(wq) < rq->wqe.info.wqe_bulk) 782 return false; 783 784 if (rq->page_pool) 785 page_pool_nid_changed(rq->page_pool, numa_mem_id()); 786 787 wqe_bulk = mlx5_wq_cyc_missing(wq); 788 head = mlx5_wq_cyc_get_head(wq); 789 790 /* Don't allow any newly allocated WQEs to share the same page with old 791 * WQEs that aren't completed yet. Stop earlier. 792 */ 793 wqe_bulk -= (head + wqe_bulk) & rq->wqe.info.wqe_index_mask; 794 795 if (!rq->xsk_pool) 796 count = mlx5e_alloc_rx_wqes(rq, head, wqe_bulk); 797 else if (likely(!rq->xsk_pool->dma_need_sync)) 798 count = mlx5e_xsk_alloc_rx_wqes_batched(rq, head, wqe_bulk); 799 else 800 /* If dma_need_sync is true, it's more efficient to call 801 * xsk_buff_alloc in a loop, rather than xsk_buff_alloc_batch, 802 * because the latter does the same check and returns only one 803 * frame. 804 */ 805 count = mlx5e_xsk_alloc_rx_wqes(rq, head, wqe_bulk); 806 807 mlx5_wq_cyc_push_n(wq, count); 808 if (unlikely(count != wqe_bulk)) { 809 rq->stats->buff_alloc_err++; 810 busy = true; 811 } 812 813 /* ensure wqes are visible to device before updating doorbell record */ 814 dma_wmb(); 815 816 mlx5_wq_cyc_update_db_record(wq); 817 818 return busy; 819 } 820 821 void mlx5e_free_icosq_descs(struct mlx5e_icosq *sq) 822 { 823 u16 sqcc; 824 825 sqcc = sq->cc; 826 827 while (sqcc != sq->pc) { 828 struct mlx5e_icosq_wqe_info *wi; 829 u16 ci; 830 831 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc); 832 wi = &sq->db.wqe_info[ci]; 833 sqcc += wi->num_wqebbs; 834 #ifdef CONFIG_MLX5_EN_TLS 835 switch (wi->wqe_type) { 836 case MLX5E_ICOSQ_WQE_SET_PSV_TLS: 837 mlx5e_ktls_handle_ctx_completion(wi); 838 break; 839 case MLX5E_ICOSQ_WQE_GET_PSV_TLS: 840 mlx5e_ktls_handle_get_psv_completion(wi, sq); 841 break; 842 } 843 #endif 844 } 845 sq->cc = sqcc; 846 } 847 848 static void mlx5e_handle_shampo_hd_umr(struct mlx5e_shampo_umr umr, 849 struct mlx5e_icosq *sq) 850 { 851 struct mlx5e_channel *c = container_of(sq, struct mlx5e_channel, icosq); 852 struct mlx5e_shampo_hd *shampo; 853 /* assume 1:1 relationship between RQ and icosq */ 854 struct mlx5e_rq *rq = &c->rq; 855 int end, from, len = umr.len; 856 857 shampo = rq->mpwqe.shampo; 858 end = shampo->hd_per_wq; 859 from = shampo->ci; 860 if (from + len > shampo->hd_per_wq) { 861 len -= end - from; 862 bitmap_set(shampo->bitmap, from, end - from); 863 from = 0; 864 } 865 866 bitmap_set(shampo->bitmap, from, len); 867 shampo->ci = (shampo->ci + umr.len) & (shampo->hd_per_wq - 1); 868 } 869 870 int mlx5e_poll_ico_cq(struct mlx5e_cq *cq) 871 { 872 struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq); 873 struct mlx5_cqe64 *cqe; 874 u16 sqcc; 875 int i; 876 877 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state))) 878 return 0; 879 880 cqe = mlx5_cqwq_get_cqe(&cq->wq); 881 if (likely(!cqe)) 882 return 0; 883 884 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(), 885 * otherwise a cq overrun may occur 886 */ 887 sqcc = sq->cc; 888 889 i = 0; 890 do { 891 u16 wqe_counter; 892 bool last_wqe; 893 894 mlx5_cqwq_pop(&cq->wq); 895 896 wqe_counter = be16_to_cpu(cqe->wqe_counter); 897 898 do { 899 struct mlx5e_icosq_wqe_info *wi; 900 u16 ci; 901 902 last_wqe = (sqcc == wqe_counter); 903 904 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc); 905 wi = &sq->db.wqe_info[ci]; 906 sqcc += wi->num_wqebbs; 907 908 if (last_wqe && unlikely(get_cqe_opcode(cqe) != MLX5_CQE_REQ)) { 909 netdev_WARN_ONCE(cq->netdev, 910 "Bad OP in ICOSQ CQE: 0x%x\n", 911 get_cqe_opcode(cqe)); 912 mlx5e_dump_error_cqe(&sq->cq, sq->sqn, 913 (struct mlx5_err_cqe *)cqe); 914 mlx5_wq_cyc_wqe_dump(&sq->wq, ci, wi->num_wqebbs); 915 if (!test_and_set_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state)) 916 queue_work(cq->priv->wq, &sq->recover_work); 917 break; 918 } 919 920 switch (wi->wqe_type) { 921 case MLX5E_ICOSQ_WQE_UMR_RX: 922 wi->umr.rq->mpwqe.umr_completed++; 923 break; 924 case MLX5E_ICOSQ_WQE_NOP: 925 break; 926 case MLX5E_ICOSQ_WQE_SHAMPO_HD_UMR: 927 mlx5e_handle_shampo_hd_umr(wi->shampo, sq); 928 break; 929 #ifdef CONFIG_MLX5_EN_TLS 930 case MLX5E_ICOSQ_WQE_UMR_TLS: 931 break; 932 case MLX5E_ICOSQ_WQE_SET_PSV_TLS: 933 mlx5e_ktls_handle_ctx_completion(wi); 934 break; 935 case MLX5E_ICOSQ_WQE_GET_PSV_TLS: 936 mlx5e_ktls_handle_get_psv_completion(wi, sq); 937 break; 938 #endif 939 default: 940 netdev_WARN_ONCE(cq->netdev, 941 "Bad WQE type in ICOSQ WQE info: 0x%x\n", 942 wi->wqe_type); 943 } 944 } while (!last_wqe); 945 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq))); 946 947 sq->cc = sqcc; 948 949 mlx5_cqwq_update_db_record(&cq->wq); 950 951 return i; 952 } 953 954 INDIRECT_CALLABLE_SCOPE bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq) 955 { 956 struct mlx5_wq_ll *wq = &rq->mpwqe.wq; 957 u8 umr_completed = rq->mpwqe.umr_completed; 958 struct mlx5e_icosq *sq = rq->icosq; 959 int alloc_err = 0; 960 u8 missing, i; 961 u16 head; 962 963 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state))) 964 return false; 965 966 if (umr_completed) { 967 mlx5e_post_rx_mpwqe(rq, umr_completed); 968 rq->mpwqe.umr_in_progress -= umr_completed; 969 rq->mpwqe.umr_completed = 0; 970 } 971 972 missing = mlx5_wq_ll_missing(wq) - rq->mpwqe.umr_in_progress; 973 974 if (unlikely(rq->mpwqe.umr_in_progress > rq->mpwqe.umr_last_bulk)) 975 rq->stats->congst_umr++; 976 977 if (likely(missing < rq->mpwqe.min_wqe_bulk)) 978 return false; 979 980 if (rq->page_pool) 981 page_pool_nid_changed(rq->page_pool, numa_mem_id()); 982 983 head = rq->mpwqe.actual_wq_head; 984 i = missing; 985 do { 986 alloc_err = rq->xsk_pool ? mlx5e_xsk_alloc_rx_mpwqe(rq, head) : 987 mlx5e_alloc_rx_mpwqe(rq, head); 988 989 if (unlikely(alloc_err)) 990 break; 991 head = mlx5_wq_ll_get_wqe_next_ix(wq, head); 992 } while (--i); 993 994 rq->mpwqe.umr_last_bulk = missing - i; 995 if (sq->doorbell_cseg) { 996 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, sq->doorbell_cseg); 997 sq->doorbell_cseg = NULL; 998 } 999 1000 rq->mpwqe.umr_in_progress += rq->mpwqe.umr_last_bulk; 1001 rq->mpwqe.actual_wq_head = head; 1002 1003 /* If XSK Fill Ring doesn't have enough frames, report the error, so 1004 * that one of the actions can be performed: 1005 * 1. If need_wakeup is used, signal that the application has to kick 1006 * the driver when it refills the Fill Ring. 1007 * 2. Otherwise, busy poll by rescheduling the NAPI poll. 1008 */ 1009 if (unlikely(alloc_err == -ENOMEM && rq->xsk_pool)) 1010 return true; 1011 1012 return false; 1013 } 1014 1015 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp) 1016 { 1017 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe); 1018 u8 tcp_ack = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) || 1019 (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA); 1020 1021 tcp->check = 0; 1022 tcp->psh = get_cqe_lro_tcppsh(cqe); 1023 1024 if (tcp_ack) { 1025 tcp->ack = 1; 1026 tcp->ack_seq = cqe->lro.ack_seq_num; 1027 tcp->window = cqe->lro.tcp_win; 1028 } 1029 } 1030 1031 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe, 1032 u32 cqe_bcnt) 1033 { 1034 struct ethhdr *eth = (struct ethhdr *)(skb->data); 1035 struct tcphdr *tcp; 1036 int network_depth = 0; 1037 __wsum check; 1038 __be16 proto; 1039 u16 tot_len; 1040 void *ip_p; 1041 1042 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth); 1043 1044 tot_len = cqe_bcnt - network_depth; 1045 ip_p = skb->data + network_depth; 1046 1047 if (proto == htons(ETH_P_IP)) { 1048 struct iphdr *ipv4 = ip_p; 1049 1050 tcp = ip_p + sizeof(struct iphdr); 1051 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 1052 1053 ipv4->ttl = cqe->lro.min_ttl; 1054 ipv4->tot_len = cpu_to_be16(tot_len); 1055 ipv4->check = 0; 1056 ipv4->check = ip_fast_csum((unsigned char *)ipv4, 1057 ipv4->ihl); 1058 1059 mlx5e_lro_update_tcp_hdr(cqe, tcp); 1060 check = csum_partial(tcp, tcp->doff * 4, 1061 csum_unfold((__force __sum16)cqe->check_sum)); 1062 /* Almost done, don't forget the pseudo header */ 1063 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr, 1064 tot_len - sizeof(struct iphdr), 1065 IPPROTO_TCP, check); 1066 } else { 1067 u16 payload_len = tot_len - sizeof(struct ipv6hdr); 1068 struct ipv6hdr *ipv6 = ip_p; 1069 1070 tcp = ip_p + sizeof(struct ipv6hdr); 1071 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 1072 1073 ipv6->hop_limit = cqe->lro.min_ttl; 1074 ipv6->payload_len = cpu_to_be16(payload_len); 1075 1076 mlx5e_lro_update_tcp_hdr(cqe, tcp); 1077 check = csum_partial(tcp, tcp->doff * 4, 1078 csum_unfold((__force __sum16)cqe->check_sum)); 1079 /* Almost done, don't forget the pseudo header */ 1080 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len, 1081 IPPROTO_TCP, check); 1082 } 1083 } 1084 1085 static void *mlx5e_shampo_get_packet_hd(struct mlx5e_rq *rq, u16 header_index) 1086 { 1087 struct mlx5e_dma_info *last_head = &rq->mpwqe.shampo->info[header_index]; 1088 u16 head_offset = (last_head->addr & (PAGE_SIZE - 1)) + rq->buff.headroom; 1089 1090 return page_address(last_head->frag_page->page) + head_offset; 1091 } 1092 1093 static void mlx5e_shampo_update_ipv4_udp_hdr(struct mlx5e_rq *rq, struct iphdr *ipv4) 1094 { 1095 int udp_off = rq->hw_gro_data->fk.control.thoff; 1096 struct sk_buff *skb = rq->hw_gro_data->skb; 1097 struct udphdr *uh; 1098 1099 uh = (struct udphdr *)(skb->data + udp_off); 1100 uh->len = htons(skb->len - udp_off); 1101 1102 if (uh->check) 1103 uh->check = ~udp_v4_check(skb->len - udp_off, ipv4->saddr, 1104 ipv4->daddr, 0); 1105 1106 skb->csum_start = (unsigned char *)uh - skb->head; 1107 skb->csum_offset = offsetof(struct udphdr, check); 1108 1109 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_L4; 1110 } 1111 1112 static void mlx5e_shampo_update_ipv6_udp_hdr(struct mlx5e_rq *rq, struct ipv6hdr *ipv6) 1113 { 1114 int udp_off = rq->hw_gro_data->fk.control.thoff; 1115 struct sk_buff *skb = rq->hw_gro_data->skb; 1116 struct udphdr *uh; 1117 1118 uh = (struct udphdr *)(skb->data + udp_off); 1119 uh->len = htons(skb->len - udp_off); 1120 1121 if (uh->check) 1122 uh->check = ~udp_v6_check(skb->len - udp_off, &ipv6->saddr, 1123 &ipv6->daddr, 0); 1124 1125 skb->csum_start = (unsigned char *)uh - skb->head; 1126 skb->csum_offset = offsetof(struct udphdr, check); 1127 1128 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_L4; 1129 } 1130 1131 static void mlx5e_shampo_update_fin_psh_flags(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, 1132 struct tcphdr *skb_tcp_hd) 1133 { 1134 u16 header_index = mlx5e_shampo_get_cqe_header_index(rq, cqe); 1135 struct tcphdr *last_tcp_hd; 1136 void *last_hd_addr; 1137 1138 last_hd_addr = mlx5e_shampo_get_packet_hd(rq, header_index); 1139 last_tcp_hd = last_hd_addr + ETH_HLEN + rq->hw_gro_data->fk.control.thoff; 1140 tcp_flag_word(skb_tcp_hd) |= tcp_flag_word(last_tcp_hd) & (TCP_FLAG_FIN | TCP_FLAG_PSH); 1141 } 1142 1143 static void mlx5e_shampo_update_ipv4_tcp_hdr(struct mlx5e_rq *rq, struct iphdr *ipv4, 1144 struct mlx5_cqe64 *cqe, bool match) 1145 { 1146 int tcp_off = rq->hw_gro_data->fk.control.thoff; 1147 struct sk_buff *skb = rq->hw_gro_data->skb; 1148 struct tcphdr *tcp; 1149 1150 tcp = (struct tcphdr *)(skb->data + tcp_off); 1151 if (match) 1152 mlx5e_shampo_update_fin_psh_flags(rq, cqe, tcp); 1153 1154 tcp->check = ~tcp_v4_check(skb->len - tcp_off, ipv4->saddr, 1155 ipv4->daddr, 0); 1156 skb_shinfo(skb)->gso_type |= SKB_GSO_TCPV4; 1157 if (ntohs(ipv4->id) == rq->hw_gro_data->second_ip_id) 1158 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_FIXEDID; 1159 1160 skb->csum_start = (unsigned char *)tcp - skb->head; 1161 skb->csum_offset = offsetof(struct tcphdr, check); 1162 1163 if (tcp->cwr) 1164 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN; 1165 } 1166 1167 static void mlx5e_shampo_update_ipv6_tcp_hdr(struct mlx5e_rq *rq, struct ipv6hdr *ipv6, 1168 struct mlx5_cqe64 *cqe, bool match) 1169 { 1170 int tcp_off = rq->hw_gro_data->fk.control.thoff; 1171 struct sk_buff *skb = rq->hw_gro_data->skb; 1172 struct tcphdr *tcp; 1173 1174 tcp = (struct tcphdr *)(skb->data + tcp_off); 1175 if (match) 1176 mlx5e_shampo_update_fin_psh_flags(rq, cqe, tcp); 1177 1178 tcp->check = ~tcp_v6_check(skb->len - tcp_off, &ipv6->saddr, 1179 &ipv6->daddr, 0); 1180 skb_shinfo(skb)->gso_type |= SKB_GSO_TCPV6; 1181 skb->csum_start = (unsigned char *)tcp - skb->head; 1182 skb->csum_offset = offsetof(struct tcphdr, check); 1183 1184 if (tcp->cwr) 1185 skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN; 1186 } 1187 1188 static void mlx5e_shampo_update_hdr(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, bool match) 1189 { 1190 bool is_ipv4 = (rq->hw_gro_data->fk.basic.n_proto == htons(ETH_P_IP)); 1191 struct sk_buff *skb = rq->hw_gro_data->skb; 1192 1193 skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count; 1194 skb->ip_summed = CHECKSUM_PARTIAL; 1195 1196 if (is_ipv4) { 1197 int nhoff = rq->hw_gro_data->fk.control.thoff - sizeof(struct iphdr); 1198 struct iphdr *ipv4 = (struct iphdr *)(skb->data + nhoff); 1199 __be16 newlen = htons(skb->len - nhoff); 1200 1201 csum_replace2(&ipv4->check, ipv4->tot_len, newlen); 1202 ipv4->tot_len = newlen; 1203 1204 if (ipv4->protocol == IPPROTO_TCP) 1205 mlx5e_shampo_update_ipv4_tcp_hdr(rq, ipv4, cqe, match); 1206 else 1207 mlx5e_shampo_update_ipv4_udp_hdr(rq, ipv4); 1208 } else { 1209 int nhoff = rq->hw_gro_data->fk.control.thoff - sizeof(struct ipv6hdr); 1210 struct ipv6hdr *ipv6 = (struct ipv6hdr *)(skb->data + nhoff); 1211 1212 ipv6->payload_len = htons(skb->len - nhoff - sizeof(*ipv6)); 1213 1214 if (ipv6->nexthdr == IPPROTO_TCP) 1215 mlx5e_shampo_update_ipv6_tcp_hdr(rq, ipv6, cqe, match); 1216 else 1217 mlx5e_shampo_update_ipv6_udp_hdr(rq, ipv6); 1218 } 1219 } 1220 1221 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe, 1222 struct sk_buff *skb) 1223 { 1224 u8 cht = cqe->rss_hash_type; 1225 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 : 1226 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 : 1227 PKT_HASH_TYPE_NONE; 1228 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht); 1229 } 1230 1231 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth, 1232 __be16 *proto) 1233 { 1234 *proto = ((struct ethhdr *)skb->data)->h_proto; 1235 *proto = __vlan_get_protocol(skb, *proto, network_depth); 1236 1237 if (*proto == htons(ETH_P_IP)) 1238 return pskb_may_pull(skb, *network_depth + sizeof(struct iphdr)); 1239 1240 if (*proto == htons(ETH_P_IPV6)) 1241 return pskb_may_pull(skb, *network_depth + sizeof(struct ipv6hdr)); 1242 1243 return false; 1244 } 1245 1246 static inline void mlx5e_enable_ecn(struct mlx5e_rq *rq, struct sk_buff *skb) 1247 { 1248 int network_depth = 0; 1249 __be16 proto; 1250 void *ip; 1251 int rc; 1252 1253 if (unlikely(!is_last_ethertype_ip(skb, &network_depth, &proto))) 1254 return; 1255 1256 ip = skb->data + network_depth; 1257 rc = ((proto == htons(ETH_P_IP)) ? IP_ECN_set_ce((struct iphdr *)ip) : 1258 IP6_ECN_set_ce(skb, (struct ipv6hdr *)ip)); 1259 1260 rq->stats->ecn_mark += !!rc; 1261 } 1262 1263 static u8 get_ip_proto(struct sk_buff *skb, int network_depth, __be16 proto) 1264 { 1265 void *ip_p = skb->data + network_depth; 1266 1267 return (proto == htons(ETH_P_IP)) ? ((struct iphdr *)ip_p)->protocol : 1268 ((struct ipv6hdr *)ip_p)->nexthdr; 1269 } 1270 1271 #define short_frame(size) ((size) <= ETH_ZLEN + ETH_FCS_LEN) 1272 1273 #define MAX_PADDING 8 1274 1275 static void 1276 tail_padding_csum_slow(struct sk_buff *skb, int offset, int len, 1277 struct mlx5e_rq_stats *stats) 1278 { 1279 stats->csum_complete_tail_slow++; 1280 skb->csum = csum_block_add(skb->csum, 1281 skb_checksum(skb, offset, len, 0), 1282 offset); 1283 } 1284 1285 static void 1286 tail_padding_csum(struct sk_buff *skb, int offset, 1287 struct mlx5e_rq_stats *stats) 1288 { 1289 u8 tail_padding[MAX_PADDING]; 1290 int len = skb->len - offset; 1291 void *tail; 1292 1293 if (unlikely(len > MAX_PADDING)) { 1294 tail_padding_csum_slow(skb, offset, len, stats); 1295 return; 1296 } 1297 1298 tail = skb_header_pointer(skb, offset, len, tail_padding); 1299 if (unlikely(!tail)) { 1300 tail_padding_csum_slow(skb, offset, len, stats); 1301 return; 1302 } 1303 1304 stats->csum_complete_tail++; 1305 skb->csum = csum_block_add(skb->csum, csum_partial(tail, len, 0), offset); 1306 } 1307 1308 static void 1309 mlx5e_skb_csum_fixup(struct sk_buff *skb, int network_depth, __be16 proto, 1310 struct mlx5e_rq_stats *stats) 1311 { 1312 struct ipv6hdr *ip6; 1313 struct iphdr *ip4; 1314 int pkt_len; 1315 1316 /* Fixup vlan headers, if any */ 1317 if (network_depth > ETH_HLEN) 1318 /* CQE csum is calculated from the IP header and does 1319 * not cover VLAN headers (if present). This will add 1320 * the checksum manually. 1321 */ 1322 skb->csum = csum_partial(skb->data + ETH_HLEN, 1323 network_depth - ETH_HLEN, 1324 skb->csum); 1325 1326 /* Fixup tail padding, if any */ 1327 switch (proto) { 1328 case htons(ETH_P_IP): 1329 ip4 = (struct iphdr *)(skb->data + network_depth); 1330 pkt_len = network_depth + ntohs(ip4->tot_len); 1331 break; 1332 case htons(ETH_P_IPV6): 1333 ip6 = (struct ipv6hdr *)(skb->data + network_depth); 1334 pkt_len = network_depth + sizeof(*ip6) + ntohs(ip6->payload_len); 1335 break; 1336 default: 1337 return; 1338 } 1339 1340 if (likely(pkt_len >= skb->len)) 1341 return; 1342 1343 tail_padding_csum(skb, pkt_len, stats); 1344 } 1345 1346 static inline void mlx5e_handle_csum(struct net_device *netdev, 1347 struct mlx5_cqe64 *cqe, 1348 struct mlx5e_rq *rq, 1349 struct sk_buff *skb, 1350 bool lro) 1351 { 1352 struct mlx5e_rq_stats *stats = rq->stats; 1353 int network_depth = 0; 1354 __be16 proto; 1355 1356 if (unlikely(!(netdev->features & NETIF_F_RXCSUM))) 1357 goto csum_none; 1358 1359 if (lro) { 1360 skb->ip_summed = CHECKSUM_UNNECESSARY; 1361 stats->csum_unnecessary++; 1362 return; 1363 } 1364 1365 /* True when explicitly set via priv flag, or XDP prog is loaded */ 1366 if (test_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state) || 1367 get_cqe_tls_offload(cqe)) 1368 goto csum_unnecessary; 1369 1370 /* CQE csum doesn't cover padding octets in short ethernet 1371 * frames. And the pad field is appended prior to calculating 1372 * and appending the FCS field. 1373 * 1374 * Detecting these padded frames requires to verify and parse 1375 * IP headers, so we simply force all those small frames to be 1376 * CHECKSUM_UNNECESSARY even if they are not padded. 1377 */ 1378 if (short_frame(skb->len)) 1379 goto csum_unnecessary; 1380 1381 if (likely(is_last_ethertype_ip(skb, &network_depth, &proto))) { 1382 if (unlikely(get_ip_proto(skb, network_depth, proto) == IPPROTO_SCTP)) 1383 goto csum_unnecessary; 1384 1385 stats->csum_complete++; 1386 skb->ip_summed = CHECKSUM_COMPLETE; 1387 skb->csum = csum_unfold((__force __sum16)cqe->check_sum); 1388 1389 if (test_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state)) 1390 return; /* CQE csum covers all received bytes */ 1391 1392 /* csum might need some fixups ...*/ 1393 mlx5e_skb_csum_fixup(skb, network_depth, proto, stats); 1394 return; 1395 } 1396 1397 csum_unnecessary: 1398 if (likely((cqe->hds_ip_ext & CQE_L3_OK) && 1399 (cqe->hds_ip_ext & CQE_L4_OK))) { 1400 skb->ip_summed = CHECKSUM_UNNECESSARY; 1401 if (cqe_is_tunneled(cqe)) { 1402 skb->csum_level = 1; 1403 skb->encapsulation = 1; 1404 stats->csum_unnecessary_inner++; 1405 return; 1406 } 1407 stats->csum_unnecessary++; 1408 return; 1409 } 1410 csum_none: 1411 skb->ip_summed = CHECKSUM_NONE; 1412 stats->csum_none++; 1413 } 1414 1415 #define MLX5E_CE_BIT_MASK 0x80 1416 1417 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe, 1418 u32 cqe_bcnt, 1419 struct mlx5e_rq *rq, 1420 struct sk_buff *skb) 1421 { 1422 u8 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24; 1423 struct mlx5e_rq_stats *stats = rq->stats; 1424 struct net_device *netdev = rq->netdev; 1425 1426 skb->mac_len = ETH_HLEN; 1427 1428 if (unlikely(get_cqe_tls_offload(cqe))) 1429 mlx5e_ktls_handle_rx_skb(rq, skb, cqe, &cqe_bcnt); 1430 1431 if (unlikely(mlx5_ipsec_is_rx_flow(cqe))) 1432 mlx5e_ipsec_offload_handle_rx_skb(netdev, skb, cqe); 1433 1434 if (unlikely(mlx5e_macsec_is_rx_flow(cqe))) 1435 mlx5e_macsec_offload_handle_rx_skb(netdev, skb, cqe); 1436 1437 if (lro_num_seg > 1) { 1438 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt); 1439 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg); 1440 /* Subtract one since we already counted this as one 1441 * "regular" packet in mlx5e_complete_rx_cqe() 1442 */ 1443 stats->packets += lro_num_seg - 1; 1444 stats->lro_packets++; 1445 stats->lro_bytes += cqe_bcnt; 1446 } 1447 1448 if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp))) 1449 skb_hwtstamps(skb)->hwtstamp = mlx5e_cqe_ts_to_ns(rq->ptp_cyc2time, 1450 rq->clock, get_cqe_ts(cqe)); 1451 skb_record_rx_queue(skb, rq->ix); 1452 1453 if (likely(netdev->features & NETIF_F_RXHASH)) 1454 mlx5e_skb_set_hash(cqe, skb); 1455 1456 if (cqe_has_vlan(cqe)) { 1457 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1458 be16_to_cpu(cqe->vlan_info)); 1459 stats->removed_vlan_packets++; 1460 } 1461 1462 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK; 1463 1464 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg); 1465 /* checking CE bit in cqe - MSB in ml_path field */ 1466 if (unlikely(cqe->ml_path & MLX5E_CE_BIT_MASK)) 1467 mlx5e_enable_ecn(rq, skb); 1468 1469 skb->protocol = eth_type_trans(skb, netdev); 1470 1471 if (unlikely(mlx5e_skb_is_multicast(skb))) 1472 stats->mcast_packets++; 1473 } 1474 1475 static void mlx5e_shampo_complete_rx_cqe(struct mlx5e_rq *rq, 1476 struct mlx5_cqe64 *cqe, 1477 u32 cqe_bcnt, 1478 struct sk_buff *skb) 1479 { 1480 struct mlx5e_rq_stats *stats = rq->stats; 1481 1482 stats->packets++; 1483 stats->gro_packets++; 1484 stats->bytes += cqe_bcnt; 1485 stats->gro_bytes += cqe_bcnt; 1486 if (NAPI_GRO_CB(skb)->count != 1) 1487 return; 1488 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb); 1489 skb_reset_network_header(skb); 1490 if (!skb_flow_dissect_flow_keys(skb, &rq->hw_gro_data->fk, 0)) { 1491 napi_gro_receive(rq->cq.napi, skb); 1492 rq->hw_gro_data->skb = NULL; 1493 } 1494 } 1495 1496 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq, 1497 struct mlx5_cqe64 *cqe, 1498 u32 cqe_bcnt, 1499 struct sk_buff *skb) 1500 { 1501 struct mlx5e_rq_stats *stats = rq->stats; 1502 1503 stats->packets++; 1504 stats->bytes += cqe_bcnt; 1505 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb); 1506 } 1507 1508 static inline 1509 struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va, 1510 u32 frag_size, u16 headroom, 1511 u32 cqe_bcnt, u32 metasize) 1512 { 1513 struct sk_buff *skb = napi_build_skb(va, frag_size); 1514 1515 if (unlikely(!skb)) { 1516 rq->stats->buff_alloc_err++; 1517 return NULL; 1518 } 1519 1520 skb_reserve(skb, headroom); 1521 skb_put(skb, cqe_bcnt); 1522 1523 if (metasize) 1524 skb_metadata_set(skb, metasize); 1525 1526 return skb; 1527 } 1528 1529 static void mlx5e_fill_mxbuf(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, 1530 void *va, u16 headroom, u32 len, 1531 struct mlx5e_xdp_buff *mxbuf) 1532 { 1533 xdp_init_buff(&mxbuf->xdp, rq->buff.frame0_sz, &rq->xdp_rxq); 1534 xdp_prepare_buff(&mxbuf->xdp, va, headroom, len, true); 1535 mxbuf->cqe = cqe; 1536 mxbuf->rq = rq; 1537 } 1538 1539 static struct sk_buff * 1540 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5e_wqe_frag_info *wi, 1541 struct mlx5_cqe64 *cqe, u32 cqe_bcnt) 1542 { 1543 struct mlx5e_frag_page *frag_page = wi->frag_page; 1544 u16 rx_headroom = rq->buff.headroom; 1545 struct bpf_prog *prog; 1546 struct sk_buff *skb; 1547 u32 metasize = 0; 1548 void *va, *data; 1549 dma_addr_t addr; 1550 u32 frag_size; 1551 1552 va = page_address(frag_page->page) + wi->offset; 1553 data = va + rx_headroom; 1554 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt); 1555 1556 addr = page_pool_get_dma_addr(frag_page->page); 1557 dma_sync_single_range_for_cpu(rq->pdev, addr, wi->offset, 1558 frag_size, rq->buff.map_dir); 1559 net_prefetch(data); 1560 1561 prog = rcu_dereference(rq->xdp_prog); 1562 if (prog) { 1563 struct mlx5e_xdp_buff mxbuf; 1564 1565 net_prefetchw(va); /* xdp_frame data area */ 1566 mlx5e_fill_mxbuf(rq, cqe, va, rx_headroom, cqe_bcnt, &mxbuf); 1567 if (mlx5e_xdp_handle(rq, prog, &mxbuf)) 1568 return NULL; /* page/packet was consumed by XDP */ 1569 1570 rx_headroom = mxbuf.xdp.data - mxbuf.xdp.data_hard_start; 1571 metasize = mxbuf.xdp.data - mxbuf.xdp.data_meta; 1572 cqe_bcnt = mxbuf.xdp.data_end - mxbuf.xdp.data; 1573 } 1574 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt); 1575 skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt, metasize); 1576 if (unlikely(!skb)) 1577 return NULL; 1578 1579 /* queue up for recycling/reuse */ 1580 skb_mark_for_recycle(skb); 1581 frag_page->frags++; 1582 1583 return skb; 1584 } 1585 1586 static struct sk_buff * 1587 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5e_wqe_frag_info *wi, 1588 struct mlx5_cqe64 *cqe, u32 cqe_bcnt) 1589 { 1590 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0]; 1591 struct mlx5e_wqe_frag_info *head_wi = wi; 1592 u16 rx_headroom = rq->buff.headroom; 1593 struct mlx5e_frag_page *frag_page; 1594 struct skb_shared_info *sinfo; 1595 struct mlx5e_xdp_buff mxbuf; 1596 u32 frag_consumed_bytes; 1597 struct bpf_prog *prog; 1598 struct sk_buff *skb; 1599 dma_addr_t addr; 1600 u32 truesize; 1601 void *va; 1602 1603 frag_page = wi->frag_page; 1604 1605 va = page_address(frag_page->page) + wi->offset; 1606 frag_consumed_bytes = min_t(u32, frag_info->frag_size, cqe_bcnt); 1607 1608 addr = page_pool_get_dma_addr(frag_page->page); 1609 dma_sync_single_range_for_cpu(rq->pdev, addr, wi->offset, 1610 rq->buff.frame0_sz, rq->buff.map_dir); 1611 net_prefetchw(va); /* xdp_frame data area */ 1612 net_prefetch(va + rx_headroom); 1613 1614 mlx5e_fill_mxbuf(rq, cqe, va, rx_headroom, frag_consumed_bytes, &mxbuf); 1615 sinfo = xdp_get_shared_info_from_buff(&mxbuf.xdp); 1616 truesize = 0; 1617 1618 cqe_bcnt -= frag_consumed_bytes; 1619 frag_info++; 1620 wi++; 1621 1622 while (cqe_bcnt) { 1623 skb_frag_t *frag; 1624 1625 frag_page = wi->frag_page; 1626 1627 frag_consumed_bytes = min_t(u32, frag_info->frag_size, cqe_bcnt); 1628 1629 addr = page_pool_get_dma_addr(frag_page->page); 1630 dma_sync_single_for_cpu(rq->pdev, addr + wi->offset, 1631 frag_consumed_bytes, rq->buff.map_dir); 1632 1633 if (!xdp_buff_has_frags(&mxbuf.xdp)) { 1634 /* Init on the first fragment to avoid cold cache access 1635 * when possible. 1636 */ 1637 sinfo->nr_frags = 0; 1638 sinfo->xdp_frags_size = 0; 1639 xdp_buff_set_frags_flag(&mxbuf.xdp); 1640 } 1641 1642 frag = &sinfo->frags[sinfo->nr_frags++]; 1643 1644 __skb_frag_set_page(frag, frag_page->page); 1645 skb_frag_off_set(frag, wi->offset); 1646 skb_frag_size_set(frag, frag_consumed_bytes); 1647 1648 if (page_is_pfmemalloc(frag_page->page)) 1649 xdp_buff_set_frag_pfmemalloc(&mxbuf.xdp); 1650 1651 sinfo->xdp_frags_size += frag_consumed_bytes; 1652 truesize += frag_info->frag_stride; 1653 1654 cqe_bcnt -= frag_consumed_bytes; 1655 frag_info++; 1656 wi++; 1657 } 1658 1659 prog = rcu_dereference(rq->xdp_prog); 1660 if (prog && mlx5e_xdp_handle(rq, prog, &mxbuf)) { 1661 if (test_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) { 1662 int i; 1663 1664 for (i = wi - head_wi; i < rq->wqe.info.num_frags; i++) 1665 mlx5e_put_rx_frag(rq, &head_wi[i], true); 1666 } 1667 return NULL; /* page/packet was consumed by XDP */ 1668 } 1669 1670 skb = mlx5e_build_linear_skb(rq, mxbuf.xdp.data_hard_start, rq->buff.frame0_sz, 1671 mxbuf.xdp.data - mxbuf.xdp.data_hard_start, 1672 mxbuf.xdp.data_end - mxbuf.xdp.data, 1673 mxbuf.xdp.data - mxbuf.xdp.data_meta); 1674 if (unlikely(!skb)) 1675 return NULL; 1676 1677 skb_mark_for_recycle(skb); 1678 head_wi->frag_page->frags++; 1679 1680 if (xdp_buff_has_frags(&mxbuf.xdp)) { 1681 /* sinfo->nr_frags is reset by build_skb, calculate again. */ 1682 xdp_update_skb_shared_info(skb, wi - head_wi - 1, 1683 sinfo->xdp_frags_size, truesize, 1684 xdp_buff_is_frag_pfmemalloc(&mxbuf.xdp)); 1685 1686 for (struct mlx5e_wqe_frag_info *pwi = head_wi + 1; pwi < wi; pwi++) 1687 pwi->frag_page->frags++; 1688 } 1689 1690 return skb; 1691 } 1692 1693 static void trigger_report(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1694 { 1695 struct mlx5_err_cqe *err_cqe = (struct mlx5_err_cqe *)cqe; 1696 struct mlx5e_priv *priv = rq->priv; 1697 1698 if (cqe_syndrome_needs_recover(err_cqe->syndrome) && 1699 !test_and_set_bit(MLX5E_RQ_STATE_RECOVERING, &rq->state)) { 1700 mlx5e_dump_error_cqe(&rq->cq, rq->rqn, err_cqe); 1701 queue_work(priv->wq, &rq->recover_work); 1702 } 1703 } 1704 1705 static void mlx5e_handle_rx_err_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1706 { 1707 trigger_report(rq, cqe); 1708 rq->stats->wqe_err++; 1709 } 1710 1711 static void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1712 { 1713 struct mlx5_wq_cyc *wq = &rq->wqe.wq; 1714 struct mlx5e_wqe_frag_info *wi; 1715 struct sk_buff *skb; 1716 u32 cqe_bcnt; 1717 u16 ci; 1718 1719 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter)); 1720 wi = get_frag(rq, ci); 1721 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 1722 1723 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) { 1724 mlx5e_handle_rx_err_cqe(rq, cqe); 1725 goto free_wqe; 1726 } 1727 1728 skb = INDIRECT_CALL_3(rq->wqe.skb_from_cqe, 1729 mlx5e_skb_from_cqe_linear, 1730 mlx5e_skb_from_cqe_nonlinear, 1731 mlx5e_xsk_skb_from_cqe_linear, 1732 rq, wi, cqe, cqe_bcnt); 1733 if (!skb) { 1734 /* probably for XDP */ 1735 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) { 1736 /* do not return page to cache, 1737 * it will be returned on XDP_TX completion. 1738 */ 1739 goto wq_cyc_pop; 1740 } 1741 goto free_wqe; 1742 } 1743 1744 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1745 1746 if (mlx5e_cqe_regb_chain(cqe)) 1747 if (!mlx5e_tc_update_skb_nic(cqe, skb)) { 1748 dev_kfree_skb_any(skb); 1749 goto free_wqe; 1750 } 1751 1752 napi_gro_receive(rq->cq.napi, skb); 1753 1754 free_wqe: 1755 mlx5e_free_rx_wqe(rq, wi, true); 1756 wq_cyc_pop: 1757 mlx5_wq_cyc_pop(wq); 1758 } 1759 1760 #ifdef CONFIG_MLX5_ESWITCH 1761 static void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1762 { 1763 struct net_device *netdev = rq->netdev; 1764 struct mlx5e_priv *priv = netdev_priv(netdev); 1765 struct mlx5e_rep_priv *rpriv = priv->ppriv; 1766 struct mlx5_eswitch_rep *rep = rpriv->rep; 1767 struct mlx5_wq_cyc *wq = &rq->wqe.wq; 1768 struct mlx5e_wqe_frag_info *wi; 1769 struct sk_buff *skb; 1770 u32 cqe_bcnt; 1771 u16 ci; 1772 1773 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter)); 1774 wi = get_frag(rq, ci); 1775 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 1776 1777 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) { 1778 mlx5e_handle_rx_err_cqe(rq, cqe); 1779 goto free_wqe; 1780 } 1781 1782 skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe, 1783 mlx5e_skb_from_cqe_linear, 1784 mlx5e_skb_from_cqe_nonlinear, 1785 rq, wi, cqe, cqe_bcnt); 1786 if (!skb) { 1787 /* probably for XDP */ 1788 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) { 1789 /* do not return page to cache, 1790 * it will be returned on XDP_TX completion. 1791 */ 1792 goto wq_cyc_pop; 1793 } 1794 goto free_wqe; 1795 } 1796 1797 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1798 1799 if (rep->vlan && skb_vlan_tag_present(skb)) 1800 skb_vlan_pop(skb); 1801 1802 mlx5e_rep_tc_receive(cqe, rq, skb); 1803 1804 free_wqe: 1805 mlx5e_free_rx_wqe(rq, wi, true); 1806 wq_cyc_pop: 1807 mlx5_wq_cyc_pop(wq); 1808 } 1809 1810 static void mlx5e_handle_rx_cqe_mpwrq_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1811 { 1812 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe); 1813 u16 wqe_id = be16_to_cpu(cqe->wqe_id); 1814 struct mlx5e_mpw_info *wi = mlx5e_get_mpw_info(rq, wqe_id); 1815 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe); 1816 u32 wqe_offset = stride_ix << rq->mpwqe.log_stride_sz; 1817 u32 head_offset = wqe_offset & ((1 << rq->mpwqe.page_shift) - 1); 1818 u32 page_idx = wqe_offset >> rq->mpwqe.page_shift; 1819 struct mlx5e_rx_wqe_ll *wqe; 1820 struct mlx5_wq_ll *wq; 1821 struct sk_buff *skb; 1822 u16 cqe_bcnt; 1823 1824 wi->consumed_strides += cstrides; 1825 1826 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) { 1827 mlx5e_handle_rx_err_cqe(rq, cqe); 1828 goto mpwrq_cqe_out; 1829 } 1830 1831 if (unlikely(mpwrq_is_filler_cqe(cqe))) { 1832 struct mlx5e_rq_stats *stats = rq->stats; 1833 1834 stats->mpwqe_filler_cqes++; 1835 stats->mpwqe_filler_strides += cstrides; 1836 goto mpwrq_cqe_out; 1837 } 1838 1839 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe); 1840 1841 skb = INDIRECT_CALL_2(rq->mpwqe.skb_from_cqe_mpwrq, 1842 mlx5e_skb_from_cqe_mpwrq_linear, 1843 mlx5e_skb_from_cqe_mpwrq_nonlinear, 1844 rq, wi, cqe, cqe_bcnt, head_offset, page_idx); 1845 if (!skb) 1846 goto mpwrq_cqe_out; 1847 1848 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1849 1850 mlx5e_rep_tc_receive(cqe, rq, skb); 1851 1852 mpwrq_cqe_out: 1853 if (likely(wi->consumed_strides < rq->mpwqe.num_strides)) 1854 return; 1855 1856 wq = &rq->mpwqe.wq; 1857 wqe = mlx5_wq_ll_get_wqe(wq, wqe_id); 1858 mlx5e_free_rx_mpwqe(rq, wi, true); 1859 mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index); 1860 } 1861 1862 const struct mlx5e_rx_handlers mlx5e_rx_handlers_rep = { 1863 .handle_rx_cqe = mlx5e_handle_rx_cqe_rep, 1864 .handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq_rep, 1865 }; 1866 #endif 1867 1868 static void 1869 mlx5e_fill_skb_data(struct sk_buff *skb, struct mlx5e_rq *rq, 1870 struct mlx5e_frag_page *frag_page, 1871 u32 data_bcnt, u32 data_offset) 1872 { 1873 net_prefetchw(skb->data); 1874 1875 while (data_bcnt) { 1876 /* Non-linear mode, hence non-XSK, which always uses PAGE_SIZE. */ 1877 u32 pg_consumed_bytes = min_t(u32, PAGE_SIZE - data_offset, data_bcnt); 1878 unsigned int truesize; 1879 1880 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) 1881 truesize = pg_consumed_bytes; 1882 else 1883 truesize = ALIGN(pg_consumed_bytes, BIT(rq->mpwqe.log_stride_sz)); 1884 1885 frag_page->frags++; 1886 mlx5e_add_skb_frag(rq, skb, frag_page->page, data_offset, 1887 pg_consumed_bytes, truesize); 1888 1889 data_bcnt -= pg_consumed_bytes; 1890 data_offset = 0; 1891 frag_page++; 1892 } 1893 } 1894 1895 static struct sk_buff * 1896 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, 1897 struct mlx5_cqe64 *cqe, u16 cqe_bcnt, u32 head_offset, 1898 u32 page_idx) 1899 { 1900 struct mlx5e_frag_page *frag_page = &wi->alloc_units.frag_pages[page_idx]; 1901 u16 headlen = min_t(u16, MLX5E_RX_MAX_HEAD, cqe_bcnt); 1902 struct mlx5e_frag_page *head_page = frag_page; 1903 u32 frag_offset = head_offset + headlen; 1904 u32 byte_cnt = cqe_bcnt - headlen; 1905 struct sk_buff *skb; 1906 dma_addr_t addr; 1907 1908 skb = napi_alloc_skb(rq->cq.napi, 1909 ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long))); 1910 if (unlikely(!skb)) { 1911 rq->stats->buff_alloc_err++; 1912 return NULL; 1913 } 1914 1915 net_prefetchw(skb->data); 1916 1917 /* Non-linear mode, hence non-XSK, which always uses PAGE_SIZE. */ 1918 if (unlikely(frag_offset >= PAGE_SIZE)) { 1919 frag_page++; 1920 frag_offset -= PAGE_SIZE; 1921 } 1922 1923 skb_mark_for_recycle(skb); 1924 mlx5e_fill_skb_data(skb, rq, frag_page, byte_cnt, frag_offset); 1925 /* copy header */ 1926 addr = page_pool_get_dma_addr(head_page->page); 1927 mlx5e_copy_skb_header(rq, skb, head_page->page, addr, 1928 head_offset, head_offset, headlen); 1929 /* skb linear part was allocated with headlen and aligned to long */ 1930 skb->tail += headlen; 1931 skb->len += headlen; 1932 1933 return skb; 1934 } 1935 1936 static struct sk_buff * 1937 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, 1938 struct mlx5_cqe64 *cqe, u16 cqe_bcnt, u32 head_offset, 1939 u32 page_idx) 1940 { 1941 struct mlx5e_frag_page *frag_page = &wi->alloc_units.frag_pages[page_idx]; 1942 u16 rx_headroom = rq->buff.headroom; 1943 struct bpf_prog *prog; 1944 struct sk_buff *skb; 1945 u32 metasize = 0; 1946 void *va, *data; 1947 dma_addr_t addr; 1948 u32 frag_size; 1949 1950 /* Check packet size. Note LRO doesn't use linear SKB */ 1951 if (unlikely(cqe_bcnt > rq->hw_mtu)) { 1952 rq->stats->oversize_pkts_sw_drop++; 1953 return NULL; 1954 } 1955 1956 va = page_address(frag_page->page) + head_offset; 1957 data = va + rx_headroom; 1958 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt); 1959 1960 addr = page_pool_get_dma_addr(frag_page->page); 1961 dma_sync_single_range_for_cpu(rq->pdev, addr, head_offset, 1962 frag_size, rq->buff.map_dir); 1963 net_prefetch(data); 1964 1965 prog = rcu_dereference(rq->xdp_prog); 1966 if (prog) { 1967 struct mlx5e_xdp_buff mxbuf; 1968 1969 net_prefetchw(va); /* xdp_frame data area */ 1970 mlx5e_fill_mxbuf(rq, cqe, va, rx_headroom, cqe_bcnt, &mxbuf); 1971 if (mlx5e_xdp_handle(rq, prog, &mxbuf)) { 1972 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) 1973 __set_bit(page_idx, wi->xdp_xmit_bitmap); /* non-atomic */ 1974 return NULL; /* page/packet was consumed by XDP */ 1975 } 1976 1977 rx_headroom = mxbuf.xdp.data - mxbuf.xdp.data_hard_start; 1978 metasize = mxbuf.xdp.data - mxbuf.xdp.data_meta; 1979 cqe_bcnt = mxbuf.xdp.data_end - mxbuf.xdp.data; 1980 } 1981 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt); 1982 skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt, metasize); 1983 if (unlikely(!skb)) 1984 return NULL; 1985 1986 /* queue up for recycling/reuse */ 1987 skb_mark_for_recycle(skb); 1988 frag_page->frags++; 1989 1990 return skb; 1991 } 1992 1993 static struct sk_buff * 1994 mlx5e_skb_from_cqe_shampo(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, 1995 struct mlx5_cqe64 *cqe, u16 header_index) 1996 { 1997 struct mlx5e_dma_info *head = &rq->mpwqe.shampo->info[header_index]; 1998 u16 head_offset = head->addr & (PAGE_SIZE - 1); 1999 u16 head_size = cqe->shampo.header_size; 2000 u16 rx_headroom = rq->buff.headroom; 2001 struct sk_buff *skb = NULL; 2002 void *hdr, *data; 2003 u32 frag_size; 2004 2005 hdr = page_address(head->frag_page->page) + head_offset; 2006 data = hdr + rx_headroom; 2007 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + head_size); 2008 2009 if (likely(frag_size <= BIT(MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE))) { 2010 /* build SKB around header */ 2011 dma_sync_single_range_for_cpu(rq->pdev, head->addr, 0, frag_size, rq->buff.map_dir); 2012 prefetchw(hdr); 2013 prefetch(data); 2014 skb = mlx5e_build_linear_skb(rq, hdr, frag_size, rx_headroom, head_size, 0); 2015 2016 if (unlikely(!skb)) 2017 return NULL; 2018 2019 head->frag_page->frags++; 2020 } else { 2021 /* allocate SKB and copy header for large header */ 2022 rq->stats->gro_large_hds++; 2023 skb = napi_alloc_skb(rq->cq.napi, 2024 ALIGN(head_size, sizeof(long))); 2025 if (unlikely(!skb)) { 2026 rq->stats->buff_alloc_err++; 2027 return NULL; 2028 } 2029 2030 prefetchw(skb->data); 2031 mlx5e_copy_skb_header(rq, skb, head->frag_page->page, head->addr, 2032 head_offset + rx_headroom, 2033 rx_headroom, head_size); 2034 /* skb linear part was allocated with headlen and aligned to long */ 2035 skb->tail += head_size; 2036 skb->len += head_size; 2037 } 2038 2039 /* queue up for recycling/reuse */ 2040 skb_mark_for_recycle(skb); 2041 2042 return skb; 2043 } 2044 2045 static void 2046 mlx5e_shampo_align_fragment(struct sk_buff *skb, u8 log_stride_sz) 2047 { 2048 skb_frag_t *last_frag = &skb_shinfo(skb)->frags[skb_shinfo(skb)->nr_frags - 1]; 2049 unsigned int frag_size = skb_frag_size(last_frag); 2050 unsigned int frag_truesize; 2051 2052 frag_truesize = ALIGN(frag_size, BIT(log_stride_sz)); 2053 skb->truesize += frag_truesize - frag_size; 2054 } 2055 2056 static void 2057 mlx5e_shampo_flush_skb(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, bool match) 2058 { 2059 struct sk_buff *skb = rq->hw_gro_data->skb; 2060 struct mlx5e_rq_stats *stats = rq->stats; 2061 2062 stats->gro_skbs++; 2063 if (likely(skb_shinfo(skb)->nr_frags)) 2064 mlx5e_shampo_align_fragment(skb, rq->mpwqe.log_stride_sz); 2065 if (NAPI_GRO_CB(skb)->count > 1) 2066 mlx5e_shampo_update_hdr(rq, cqe, match); 2067 napi_gro_receive(rq->cq.napi, skb); 2068 rq->hw_gro_data->skb = NULL; 2069 } 2070 2071 static bool 2072 mlx5e_hw_gro_skb_has_enough_space(struct sk_buff *skb, u16 data_bcnt) 2073 { 2074 int nr_frags = skb_shinfo(skb)->nr_frags; 2075 2076 return PAGE_SIZE * nr_frags + data_bcnt <= GRO_LEGACY_MAX_SIZE; 2077 } 2078 2079 static void 2080 mlx5e_free_rx_shampo_hd_entry(struct mlx5e_rq *rq, u16 header_index) 2081 { 2082 struct mlx5e_shampo_hd *shampo = rq->mpwqe.shampo; 2083 u64 addr = shampo->info[header_index].addr; 2084 2085 if (((header_index + 1) & (MLX5E_SHAMPO_WQ_HEADER_PER_PAGE - 1)) == 0) { 2086 struct mlx5e_dma_info *dma_info = &shampo->info[header_index]; 2087 2088 dma_info->addr = ALIGN_DOWN(addr, PAGE_SIZE); 2089 mlx5e_page_release_fragmented(rq, dma_info->frag_page, true); 2090 } 2091 bitmap_clear(shampo->bitmap, header_index, 1); 2092 } 2093 2094 static void mlx5e_handle_rx_cqe_mpwrq_shampo(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 2095 { 2096 u16 data_bcnt = mpwrq_get_cqe_byte_cnt(cqe) - cqe->shampo.header_size; 2097 u16 header_index = mlx5e_shampo_get_cqe_header_index(rq, cqe); 2098 u32 wqe_offset = be32_to_cpu(cqe->shampo.data_offset); 2099 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe); 2100 u32 data_offset = wqe_offset & (PAGE_SIZE - 1); 2101 u32 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe); 2102 u16 wqe_id = be16_to_cpu(cqe->wqe_id); 2103 u32 page_idx = wqe_offset >> PAGE_SHIFT; 2104 u16 head_size = cqe->shampo.header_size; 2105 struct sk_buff **skb = &rq->hw_gro_data->skb; 2106 bool flush = cqe->shampo.flush; 2107 bool match = cqe->shampo.match; 2108 struct mlx5e_rq_stats *stats = rq->stats; 2109 struct mlx5e_rx_wqe_ll *wqe; 2110 struct mlx5e_mpw_info *wi; 2111 struct mlx5_wq_ll *wq; 2112 2113 wi = mlx5e_get_mpw_info(rq, wqe_id); 2114 wi->consumed_strides += cstrides; 2115 2116 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) { 2117 mlx5e_handle_rx_err_cqe(rq, cqe); 2118 goto mpwrq_cqe_out; 2119 } 2120 2121 if (unlikely(mpwrq_is_filler_cqe(cqe))) { 2122 stats->mpwqe_filler_cqes++; 2123 stats->mpwqe_filler_strides += cstrides; 2124 goto mpwrq_cqe_out; 2125 } 2126 2127 stats->gro_match_packets += match; 2128 2129 if (*skb && (!match || !(mlx5e_hw_gro_skb_has_enough_space(*skb, data_bcnt)))) { 2130 match = false; 2131 mlx5e_shampo_flush_skb(rq, cqe, match); 2132 } 2133 2134 if (!*skb) { 2135 if (likely(head_size)) 2136 *skb = mlx5e_skb_from_cqe_shampo(rq, wi, cqe, header_index); 2137 else 2138 *skb = mlx5e_skb_from_cqe_mpwrq_nonlinear(rq, wi, cqe, cqe_bcnt, 2139 data_offset, page_idx); 2140 if (unlikely(!*skb)) 2141 goto free_hd_entry; 2142 2143 NAPI_GRO_CB(*skb)->count = 1; 2144 skb_shinfo(*skb)->gso_size = cqe_bcnt - head_size; 2145 } else { 2146 NAPI_GRO_CB(*skb)->count++; 2147 if (NAPI_GRO_CB(*skb)->count == 2 && 2148 rq->hw_gro_data->fk.basic.n_proto == htons(ETH_P_IP)) { 2149 void *hd_addr = mlx5e_shampo_get_packet_hd(rq, header_index); 2150 int nhoff = ETH_HLEN + rq->hw_gro_data->fk.control.thoff - 2151 sizeof(struct iphdr); 2152 struct iphdr *iph = (struct iphdr *)(hd_addr + nhoff); 2153 2154 rq->hw_gro_data->second_ip_id = ntohs(iph->id); 2155 } 2156 } 2157 2158 if (likely(head_size)) { 2159 struct mlx5e_frag_page *frag_page; 2160 2161 frag_page = &wi->alloc_units.frag_pages[page_idx]; 2162 mlx5e_fill_skb_data(*skb, rq, frag_page, data_bcnt, data_offset); 2163 } 2164 2165 mlx5e_shampo_complete_rx_cqe(rq, cqe, cqe_bcnt, *skb); 2166 if (flush) 2167 mlx5e_shampo_flush_skb(rq, cqe, match); 2168 free_hd_entry: 2169 mlx5e_free_rx_shampo_hd_entry(rq, header_index); 2170 mpwrq_cqe_out: 2171 if (likely(wi->consumed_strides < rq->mpwqe.num_strides)) 2172 return; 2173 2174 wq = &rq->mpwqe.wq; 2175 wqe = mlx5_wq_ll_get_wqe(wq, wqe_id); 2176 mlx5e_free_rx_mpwqe(rq, wi, true); 2177 mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index); 2178 } 2179 2180 static void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 2181 { 2182 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe); 2183 u16 wqe_id = be16_to_cpu(cqe->wqe_id); 2184 struct mlx5e_mpw_info *wi = mlx5e_get_mpw_info(rq, wqe_id); 2185 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe); 2186 u32 wqe_offset = stride_ix << rq->mpwqe.log_stride_sz; 2187 u32 head_offset = wqe_offset & ((1 << rq->mpwqe.page_shift) - 1); 2188 u32 page_idx = wqe_offset >> rq->mpwqe.page_shift; 2189 struct mlx5e_rx_wqe_ll *wqe; 2190 struct mlx5_wq_ll *wq; 2191 struct sk_buff *skb; 2192 u16 cqe_bcnt; 2193 2194 wi->consumed_strides += cstrides; 2195 2196 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) { 2197 mlx5e_handle_rx_err_cqe(rq, cqe); 2198 goto mpwrq_cqe_out; 2199 } 2200 2201 if (unlikely(mpwrq_is_filler_cqe(cqe))) { 2202 struct mlx5e_rq_stats *stats = rq->stats; 2203 2204 stats->mpwqe_filler_cqes++; 2205 stats->mpwqe_filler_strides += cstrides; 2206 goto mpwrq_cqe_out; 2207 } 2208 2209 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe); 2210 2211 skb = INDIRECT_CALL_3(rq->mpwqe.skb_from_cqe_mpwrq, 2212 mlx5e_skb_from_cqe_mpwrq_linear, 2213 mlx5e_skb_from_cqe_mpwrq_nonlinear, 2214 mlx5e_xsk_skb_from_cqe_mpwrq_linear, 2215 rq, wi, cqe, cqe_bcnt, head_offset, 2216 page_idx); 2217 if (!skb) 2218 goto mpwrq_cqe_out; 2219 2220 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 2221 2222 if (mlx5e_cqe_regb_chain(cqe)) 2223 if (!mlx5e_tc_update_skb_nic(cqe, skb)) { 2224 dev_kfree_skb_any(skb); 2225 goto mpwrq_cqe_out; 2226 } 2227 2228 napi_gro_receive(rq->cq.napi, skb); 2229 2230 mpwrq_cqe_out: 2231 if (likely(wi->consumed_strides < rq->mpwqe.num_strides)) 2232 return; 2233 2234 wq = &rq->mpwqe.wq; 2235 wqe = mlx5_wq_ll_get_wqe(wq, wqe_id); 2236 mlx5e_free_rx_mpwqe(rq, wi, true); 2237 mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index); 2238 } 2239 2240 static int mlx5e_rx_cq_process_enhanced_cqe_comp(struct mlx5e_rq *rq, 2241 struct mlx5_cqwq *cqwq, 2242 int budget_rem) 2243 { 2244 struct mlx5_cqe64 *cqe, *title_cqe = NULL; 2245 struct mlx5e_cq_decomp *cqd = &rq->cqd; 2246 int work_done = 0; 2247 2248 cqe = mlx5_cqwq_get_cqe_enahnced_comp(cqwq); 2249 if (!cqe) 2250 return work_done; 2251 2252 if (cqd->last_cqe_title && 2253 (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED)) { 2254 rq->stats->cqe_compress_blks++; 2255 cqd->last_cqe_title = false; 2256 } 2257 2258 do { 2259 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) { 2260 if (title_cqe) { 2261 mlx5e_read_enhanced_title_slot(rq, title_cqe); 2262 title_cqe = NULL; 2263 rq->stats->cqe_compress_blks++; 2264 } 2265 work_done += 2266 mlx5e_decompress_enhanced_cqe(rq, cqwq, cqe, 2267 budget_rem - work_done); 2268 continue; 2269 } 2270 title_cqe = cqe; 2271 mlx5_cqwq_pop(cqwq); 2272 2273 INDIRECT_CALL_3(rq->handle_rx_cqe, mlx5e_handle_rx_cqe_mpwrq, 2274 mlx5e_handle_rx_cqe, mlx5e_handle_rx_cqe_mpwrq_shampo, 2275 rq, cqe); 2276 work_done++; 2277 } while (work_done < budget_rem && 2278 (cqe = mlx5_cqwq_get_cqe_enahnced_comp(cqwq))); 2279 2280 /* last cqe might be title on next poll bulk */ 2281 if (title_cqe) { 2282 mlx5e_read_enhanced_title_slot(rq, title_cqe); 2283 cqd->last_cqe_title = true; 2284 } 2285 2286 return work_done; 2287 } 2288 2289 static int mlx5e_rx_cq_process_basic_cqe_comp(struct mlx5e_rq *rq, 2290 struct mlx5_cqwq *cqwq, 2291 int budget_rem) 2292 { 2293 struct mlx5_cqe64 *cqe; 2294 int work_done = 0; 2295 2296 if (rq->cqd.left) 2297 work_done += mlx5e_decompress_cqes_cont(rq, cqwq, 0, budget_rem); 2298 2299 while (work_done < budget_rem && (cqe = mlx5_cqwq_get_cqe(cqwq))) { 2300 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) { 2301 work_done += 2302 mlx5e_decompress_cqes_start(rq, cqwq, 2303 budget_rem - work_done); 2304 continue; 2305 } 2306 2307 mlx5_cqwq_pop(cqwq); 2308 INDIRECT_CALL_3(rq->handle_rx_cqe, mlx5e_handle_rx_cqe_mpwrq, 2309 mlx5e_handle_rx_cqe, mlx5e_handle_rx_cqe_mpwrq_shampo, 2310 rq, cqe); 2311 work_done++; 2312 } 2313 2314 return work_done; 2315 } 2316 2317 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget) 2318 { 2319 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq); 2320 struct mlx5_cqwq *cqwq = &cq->wq; 2321 int work_done; 2322 2323 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state))) 2324 return 0; 2325 2326 if (test_bit(MLX5E_RQ_STATE_MINI_CQE_ENHANCED, &rq->state)) 2327 work_done = mlx5e_rx_cq_process_enhanced_cqe_comp(rq, cqwq, 2328 budget); 2329 else 2330 work_done = mlx5e_rx_cq_process_basic_cqe_comp(rq, cqwq, 2331 budget); 2332 2333 if (work_done == 0) 2334 return 0; 2335 2336 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state) && rq->hw_gro_data->skb) 2337 mlx5e_shampo_flush_skb(rq, NULL, false); 2338 2339 if (rcu_access_pointer(rq->xdp_prog)) 2340 mlx5e_xdp_rx_poll_complete(rq); 2341 2342 mlx5_cqwq_update_db_record(cqwq); 2343 2344 /* ensure cq space is freed before enabling more cqes */ 2345 wmb(); 2346 2347 return work_done; 2348 } 2349 2350 #ifdef CONFIG_MLX5_CORE_IPOIB 2351 2352 #define MLX5_IB_GRH_SGID_OFFSET 8 2353 #define MLX5_IB_GRH_DGID_OFFSET 24 2354 #define MLX5_GID_SIZE 16 2355 2356 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq, 2357 struct mlx5_cqe64 *cqe, 2358 u32 cqe_bcnt, 2359 struct sk_buff *skb) 2360 { 2361 struct hwtstamp_config *tstamp; 2362 struct mlx5e_rq_stats *stats; 2363 struct net_device *netdev; 2364 struct mlx5e_priv *priv; 2365 char *pseudo_header; 2366 u32 flags_rqpn; 2367 u32 qpn; 2368 u8 *dgid; 2369 u8 g; 2370 2371 qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff; 2372 netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn); 2373 2374 /* No mapping present, cannot process SKB. This might happen if a child 2375 * interface is going down while having unprocessed CQEs on parent RQ 2376 */ 2377 if (unlikely(!netdev)) { 2378 /* TODO: add drop counters support */ 2379 skb->dev = NULL; 2380 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn); 2381 return; 2382 } 2383 2384 priv = mlx5i_epriv(netdev); 2385 tstamp = &priv->tstamp; 2386 stats = &priv->channel_stats[rq->ix]->rq; 2387 2388 flags_rqpn = be32_to_cpu(cqe->flags_rqpn); 2389 g = (flags_rqpn >> 28) & 3; 2390 dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET; 2391 if ((!g) || dgid[0] != 0xff) 2392 skb->pkt_type = PACKET_HOST; 2393 else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0) 2394 skb->pkt_type = PACKET_BROADCAST; 2395 else 2396 skb->pkt_type = PACKET_MULTICAST; 2397 2398 /* Drop packets that this interface sent, ie multicast packets 2399 * that the HCA has replicated. 2400 */ 2401 if (g && (qpn == (flags_rqpn & 0xffffff)) && 2402 (memcmp(netdev->dev_addr + 4, skb->data + MLX5_IB_GRH_SGID_OFFSET, 2403 MLX5_GID_SIZE) == 0)) { 2404 skb->dev = NULL; 2405 return; 2406 } 2407 2408 skb_pull(skb, MLX5_IB_GRH_BYTES); 2409 2410 skb->protocol = *((__be16 *)(skb->data)); 2411 2412 if (netdev->features & NETIF_F_RXCSUM) { 2413 skb->ip_summed = CHECKSUM_COMPLETE; 2414 skb->csum = csum_unfold((__force __sum16)cqe->check_sum); 2415 stats->csum_complete++; 2416 } else { 2417 skb->ip_summed = CHECKSUM_NONE; 2418 stats->csum_none++; 2419 } 2420 2421 if (unlikely(mlx5e_rx_hw_stamp(tstamp))) 2422 skb_hwtstamps(skb)->hwtstamp = mlx5e_cqe_ts_to_ns(rq->ptp_cyc2time, 2423 rq->clock, get_cqe_ts(cqe)); 2424 skb_record_rx_queue(skb, rq->ix); 2425 2426 if (likely(netdev->features & NETIF_F_RXHASH)) 2427 mlx5e_skb_set_hash(cqe, skb); 2428 2429 /* 20 bytes of ipoib header and 4 for encap existing */ 2430 pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN); 2431 memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN); 2432 skb_reset_mac_header(skb); 2433 skb_pull(skb, MLX5_IPOIB_HARD_LEN); 2434 2435 skb->dev = netdev; 2436 2437 stats->packets++; 2438 stats->bytes += cqe_bcnt; 2439 } 2440 2441 static void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 2442 { 2443 struct mlx5_wq_cyc *wq = &rq->wqe.wq; 2444 struct mlx5e_wqe_frag_info *wi; 2445 struct sk_buff *skb; 2446 u32 cqe_bcnt; 2447 u16 ci; 2448 2449 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter)); 2450 wi = get_frag(rq, ci); 2451 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 2452 2453 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) { 2454 rq->stats->wqe_err++; 2455 goto wq_free_wqe; 2456 } 2457 2458 skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe, 2459 mlx5e_skb_from_cqe_linear, 2460 mlx5e_skb_from_cqe_nonlinear, 2461 rq, wi, cqe, cqe_bcnt); 2462 if (!skb) 2463 goto wq_free_wqe; 2464 2465 mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 2466 if (unlikely(!skb->dev)) { 2467 dev_kfree_skb_any(skb); 2468 goto wq_free_wqe; 2469 } 2470 napi_gro_receive(rq->cq.napi, skb); 2471 2472 wq_free_wqe: 2473 mlx5e_free_rx_wqe(rq, wi, true); 2474 mlx5_wq_cyc_pop(wq); 2475 } 2476 2477 const struct mlx5e_rx_handlers mlx5i_rx_handlers = { 2478 .handle_rx_cqe = mlx5i_handle_rx_cqe, 2479 .handle_rx_cqe_mpwqe = NULL, /* Not supported */ 2480 }; 2481 #endif /* CONFIG_MLX5_CORE_IPOIB */ 2482 2483 int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk) 2484 { 2485 struct net_device *netdev = rq->netdev; 2486 struct mlx5_core_dev *mdev = rq->mdev; 2487 struct mlx5e_priv *priv = rq->priv; 2488 2489 switch (rq->wq_type) { 2490 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 2491 rq->mpwqe.skb_from_cqe_mpwrq = xsk ? 2492 mlx5e_xsk_skb_from_cqe_mpwrq_linear : 2493 mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) ? 2494 mlx5e_skb_from_cqe_mpwrq_linear : 2495 mlx5e_skb_from_cqe_mpwrq_nonlinear; 2496 rq->post_wqes = mlx5e_post_rx_mpwqes; 2497 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe; 2498 2499 if (params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) { 2500 rq->handle_rx_cqe = priv->profile->rx_handlers->handle_rx_cqe_mpwqe_shampo; 2501 if (!rq->handle_rx_cqe) { 2502 netdev_err(netdev, "RX handler of SHAMPO MPWQE RQ is not set\n"); 2503 return -EINVAL; 2504 } 2505 } else { 2506 rq->handle_rx_cqe = priv->profile->rx_handlers->handle_rx_cqe_mpwqe; 2507 if (!rq->handle_rx_cqe) { 2508 netdev_err(netdev, "RX handler of MPWQE RQ is not set\n"); 2509 return -EINVAL; 2510 } 2511 } 2512 2513 break; 2514 default: /* MLX5_WQ_TYPE_CYCLIC */ 2515 rq->wqe.skb_from_cqe = xsk ? 2516 mlx5e_xsk_skb_from_cqe_linear : 2517 mlx5e_rx_is_linear_skb(mdev, params, NULL) ? 2518 mlx5e_skb_from_cqe_linear : 2519 mlx5e_skb_from_cqe_nonlinear; 2520 rq->post_wqes = mlx5e_post_rx_wqes; 2521 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe; 2522 rq->handle_rx_cqe = priv->profile->rx_handlers->handle_rx_cqe; 2523 if (!rq->handle_rx_cqe) { 2524 netdev_err(netdev, "RX handler of RQ is not set\n"); 2525 return -EINVAL; 2526 } 2527 } 2528 2529 return 0; 2530 } 2531 2532 static void mlx5e_trap_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 2533 { 2534 struct mlx5_wq_cyc *wq = &rq->wqe.wq; 2535 struct mlx5e_wqe_frag_info *wi; 2536 struct sk_buff *skb; 2537 u32 cqe_bcnt; 2538 u16 trap_id; 2539 u16 ci; 2540 2541 trap_id = get_cqe_flow_tag(cqe); 2542 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter)); 2543 wi = get_frag(rq, ci); 2544 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 2545 2546 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) { 2547 rq->stats->wqe_err++; 2548 goto free_wqe; 2549 } 2550 2551 skb = mlx5e_skb_from_cqe_nonlinear(rq, wi, cqe, cqe_bcnt); 2552 if (!skb) 2553 goto free_wqe; 2554 2555 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 2556 skb_push(skb, ETH_HLEN); 2557 2558 mlx5_devlink_trap_report(rq->mdev, trap_id, skb, 2559 rq->netdev->devlink_port); 2560 dev_kfree_skb_any(skb); 2561 2562 free_wqe: 2563 mlx5e_free_rx_wqe(rq, wi, false); 2564 mlx5_wq_cyc_pop(wq); 2565 } 2566 2567 void mlx5e_rq_set_trap_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params) 2568 { 2569 rq->wqe.skb_from_cqe = mlx5e_rx_is_linear_skb(rq->mdev, params, NULL) ? 2570 mlx5e_skb_from_cqe_linear : 2571 mlx5e_skb_from_cqe_nonlinear; 2572 rq->post_wqes = mlx5e_post_rx_wqes; 2573 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe; 2574 rq->handle_rx_cqe = mlx5e_trap_handle_rx_cqe; 2575 } 2576