1 /* 2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/prefetch.h> 34 #include <linux/ip.h> 35 #include <linux/ipv6.h> 36 #include <linux/tcp.h> 37 #include <linux/bpf_trace.h> 38 #include <net/busy_poll.h> 39 #include "en.h" 40 #include "en_tc.h" 41 #include "eswitch.h" 42 43 static inline bool mlx5e_rx_hw_stamp(struct mlx5e_tstamp *tstamp) 44 { 45 return tstamp->hwtstamp_config.rx_filter == HWTSTAMP_FILTER_ALL; 46 } 47 48 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc, 49 void *data) 50 { 51 u32 ci = cqcc & cq->wq.sz_m1; 52 53 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64)); 54 } 55 56 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq, 57 struct mlx5e_cq *cq, u32 cqcc) 58 { 59 mlx5e_read_cqe_slot(cq, cqcc, &cq->title); 60 cq->decmprs_left = be32_to_cpu(cq->title.byte_cnt); 61 cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter); 62 rq->stats.cqe_compress_blks++; 63 } 64 65 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc) 66 { 67 mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr); 68 cq->mini_arr_idx = 0; 69 } 70 71 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n) 72 { 73 u8 op_own = (cqcc >> cq->wq.log_sz) & 1; 74 u32 wq_sz = 1 << cq->wq.log_sz; 75 u32 ci = cqcc & cq->wq.sz_m1; 76 u32 ci_top = min_t(u32, wq_sz, ci + n); 77 78 for (; ci < ci_top; ci++, n--) { 79 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci); 80 81 cqe->op_own = op_own; 82 } 83 84 if (unlikely(ci == wq_sz)) { 85 op_own = !op_own; 86 for (ci = 0; ci < n; ci++) { 87 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci); 88 89 cqe->op_own = op_own; 90 } 91 } 92 } 93 94 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq, 95 struct mlx5e_cq *cq, u32 cqcc) 96 { 97 cq->title.byte_cnt = cq->mini_arr[cq->mini_arr_idx].byte_cnt; 98 cq->title.check_sum = cq->mini_arr[cq->mini_arr_idx].checksum; 99 cq->title.op_own &= 0xf0; 100 cq->title.op_own |= 0x01 & (cqcc >> cq->wq.log_sz); 101 cq->title.wqe_counter = cpu_to_be16(cq->decmprs_wqe_counter); 102 103 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) 104 cq->decmprs_wqe_counter += 105 mpwrq_get_cqe_consumed_strides(&cq->title); 106 else 107 cq->decmprs_wqe_counter = 108 (cq->decmprs_wqe_counter + 1) & rq->wq.sz_m1; 109 } 110 111 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq, 112 struct mlx5e_cq *cq, u32 cqcc) 113 { 114 mlx5e_decompress_cqe(rq, cq, cqcc); 115 cq->title.rss_hash_type = 0; 116 cq->title.rss_hash_result = 0; 117 } 118 119 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq, 120 struct mlx5e_cq *cq, 121 int update_owner_only, 122 int budget_rem) 123 { 124 u32 cqcc = cq->wq.cc + update_owner_only; 125 u32 cqe_count; 126 u32 i; 127 128 cqe_count = min_t(u32, cq->decmprs_left, budget_rem); 129 130 for (i = update_owner_only; i < cqe_count; 131 i++, cq->mini_arr_idx++, cqcc++) { 132 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE) 133 mlx5e_read_mini_arr_slot(cq, cqcc); 134 135 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc); 136 rq->handle_rx_cqe(rq, &cq->title); 137 } 138 mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc); 139 cq->wq.cc = cqcc; 140 cq->decmprs_left -= cqe_count; 141 rq->stats.cqe_compress_pkts += cqe_count; 142 143 return cqe_count; 144 } 145 146 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq, 147 struct mlx5e_cq *cq, 148 int budget_rem) 149 { 150 mlx5e_read_title_slot(rq, cq, cq->wq.cc); 151 mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1); 152 mlx5e_decompress_cqe(rq, cq, cq->wq.cc); 153 rq->handle_rx_cqe(rq, &cq->title); 154 cq->mini_arr_idx++; 155 156 return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1; 157 } 158 159 void mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val) 160 { 161 bool was_opened; 162 163 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression)) 164 return; 165 166 if (MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS) == val) 167 return; 168 169 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 170 if (was_opened) 171 mlx5e_close_locked(priv->netdev); 172 173 MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS, val); 174 mlx5e_set_rq_type_params(priv, priv->params.rq_wq_type); 175 176 if (was_opened) 177 mlx5e_open_locked(priv->netdev); 178 179 } 180 181 #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT) 182 183 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq, 184 struct mlx5e_dma_info *dma_info) 185 { 186 struct mlx5e_page_cache *cache = &rq->page_cache; 187 u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1); 188 189 if (tail_next == cache->head) { 190 rq->stats.cache_full++; 191 return false; 192 } 193 194 if (unlikely(page_is_pfmemalloc(dma_info->page))) 195 return false; 196 197 cache->page_cache[cache->tail] = *dma_info; 198 cache->tail = tail_next; 199 return true; 200 } 201 202 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq, 203 struct mlx5e_dma_info *dma_info) 204 { 205 struct mlx5e_page_cache *cache = &rq->page_cache; 206 207 if (unlikely(cache->head == cache->tail)) { 208 rq->stats.cache_empty++; 209 return false; 210 } 211 212 if (page_ref_count(cache->page_cache[cache->head].page) != 1) { 213 rq->stats.cache_busy++; 214 return false; 215 } 216 217 *dma_info = cache->page_cache[cache->head]; 218 cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1); 219 rq->stats.cache_reuse++; 220 221 dma_sync_single_for_device(rq->pdev, dma_info->addr, 222 RQ_PAGE_SIZE(rq), 223 DMA_FROM_DEVICE); 224 return true; 225 } 226 227 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq, 228 struct mlx5e_dma_info *dma_info) 229 { 230 struct page *page; 231 232 if (mlx5e_rx_cache_get(rq, dma_info)) 233 return 0; 234 235 page = dev_alloc_pages(rq->buff.page_order); 236 if (unlikely(!page)) 237 return -ENOMEM; 238 239 dma_info->page = page; 240 dma_info->addr = dma_map_page(rq->pdev, page, 0, 241 RQ_PAGE_SIZE(rq), rq->buff.map_dir); 242 if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) { 243 put_page(page); 244 return -ENOMEM; 245 } 246 247 return 0; 248 } 249 250 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info, 251 bool recycle) 252 { 253 if (likely(recycle) && mlx5e_rx_cache_put(rq, dma_info)) 254 return; 255 256 dma_unmap_page(rq->pdev, dma_info->addr, RQ_PAGE_SIZE(rq), 257 rq->buff.map_dir); 258 put_page(dma_info->page); 259 } 260 261 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix) 262 { 263 struct mlx5e_dma_info *di = &rq->dma_info[ix]; 264 265 if (unlikely(mlx5e_page_alloc_mapped(rq, di))) 266 return -ENOMEM; 267 268 wqe->data.addr = cpu_to_be64(di->addr + rq->rx_headroom); 269 return 0; 270 } 271 272 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix) 273 { 274 struct mlx5e_dma_info *di = &rq->dma_info[ix]; 275 276 mlx5e_page_release(rq, di, true); 277 } 278 279 static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq) 280 { 281 return rq->mpwqe_num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER; 282 } 283 284 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq, 285 struct sk_buff *skb, 286 struct mlx5e_mpw_info *wi, 287 u32 page_idx, u32 frag_offset, 288 u32 len) 289 { 290 unsigned int truesize = ALIGN(len, rq->mpwqe_stride_sz); 291 292 dma_sync_single_for_cpu(rq->pdev, 293 wi->umr.dma_info[page_idx].addr + frag_offset, 294 len, DMA_FROM_DEVICE); 295 wi->skbs_frags[page_idx]++; 296 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 297 wi->umr.dma_info[page_idx].page, frag_offset, 298 len, truesize); 299 } 300 301 static inline void 302 mlx5e_copy_skb_header_mpwqe(struct device *pdev, 303 struct sk_buff *skb, 304 struct mlx5e_mpw_info *wi, 305 u32 page_idx, u32 offset, 306 u32 headlen) 307 { 308 u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset); 309 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx]; 310 unsigned int len; 311 312 /* Aligning len to sizeof(long) optimizes memcpy performance */ 313 len = ALIGN(headlen_pg, sizeof(long)); 314 dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len, 315 DMA_FROM_DEVICE); 316 skb_copy_to_linear_data_offset(skb, 0, 317 page_address(dma_info->page) + offset, 318 len); 319 if (unlikely(offset + headlen > PAGE_SIZE)) { 320 dma_info++; 321 headlen_pg = len; 322 len = ALIGN(headlen - headlen_pg, sizeof(long)); 323 dma_sync_single_for_cpu(pdev, dma_info->addr, len, 324 DMA_FROM_DEVICE); 325 skb_copy_to_linear_data_offset(skb, headlen_pg, 326 page_address(dma_info->page), 327 len); 328 } 329 } 330 331 static inline void mlx5e_post_umr_wqe(struct mlx5e_rq *rq, u16 ix) 332 { 333 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 334 struct mlx5e_sq *sq = &rq->channel->icosq; 335 struct mlx5_wq_cyc *wq = &sq->wq; 336 struct mlx5e_umr_wqe *wqe; 337 u8 num_wqebbs = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_BB); 338 u16 pi; 339 340 /* fill sq edge with nops to avoid wqe wrap around */ 341 while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) { 342 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP; 343 sq->db.ico_wqe[pi].num_wqebbs = 1; 344 mlx5e_send_nop(sq, false); 345 } 346 347 wqe = mlx5_wq_cyc_get_wqe(wq, pi); 348 memcpy(wqe, &wi->umr.wqe, sizeof(*wqe)); 349 wqe->ctrl.opmod_idx_opcode = 350 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) | 351 MLX5_OPCODE_UMR); 352 353 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR; 354 sq->db.ico_wqe[pi].num_wqebbs = num_wqebbs; 355 sq->pc += num_wqebbs; 356 mlx5e_tx_notify_hw(sq, &wqe->ctrl); 357 } 358 359 static int mlx5e_alloc_rx_umr_mpwqe(struct mlx5e_rq *rq, 360 struct mlx5e_rx_wqe *wqe, 361 u16 ix) 362 { 363 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 364 u64 dma_offset = (u64)mlx5e_get_wqe_mtt_offset(rq, ix) << PAGE_SHIFT; 365 int pg_strides = mlx5e_mpwqe_strides_per_page(rq); 366 int err; 367 int i; 368 369 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) { 370 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[i]; 371 372 err = mlx5e_page_alloc_mapped(rq, dma_info); 373 if (unlikely(err)) 374 goto err_unmap; 375 wi->umr.mtt[i] = cpu_to_be64(dma_info->addr | MLX5_EN_WR); 376 page_ref_add(dma_info->page, pg_strides); 377 wi->skbs_frags[i] = 0; 378 } 379 380 wi->consumed_strides = 0; 381 wqe->data.addr = cpu_to_be64(dma_offset); 382 383 return 0; 384 385 err_unmap: 386 while (--i >= 0) { 387 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[i]; 388 389 page_ref_sub(dma_info->page, pg_strides); 390 mlx5e_page_release(rq, dma_info, true); 391 } 392 393 return err; 394 } 395 396 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi) 397 { 398 int pg_strides = mlx5e_mpwqe_strides_per_page(rq); 399 int i; 400 401 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) { 402 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[i]; 403 404 page_ref_sub(dma_info->page, pg_strides - wi->skbs_frags[i]); 405 mlx5e_page_release(rq, dma_info, true); 406 } 407 } 408 409 void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq) 410 { 411 struct mlx5_wq_ll *wq = &rq->wq; 412 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); 413 414 clear_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state); 415 416 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state))) { 417 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]); 418 return; 419 } 420 421 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); 422 423 /* ensure wqes are visible to device before updating doorbell record */ 424 dma_wmb(); 425 426 mlx5_wq_ll_update_db_record(wq); 427 } 428 429 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix) 430 { 431 int err; 432 433 err = mlx5e_alloc_rx_umr_mpwqe(rq, wqe, ix); 434 if (unlikely(err)) 435 return err; 436 set_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state); 437 mlx5e_post_umr_wqe(rq, ix); 438 return -EBUSY; 439 } 440 441 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) 442 { 443 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 444 445 mlx5e_free_rx_mpwqe(rq, wi); 446 } 447 448 #define RQ_CANNOT_POST(rq) \ 449 (!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state) || \ 450 test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state)) 451 452 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq) 453 { 454 struct mlx5_wq_ll *wq = &rq->wq; 455 456 if (unlikely(RQ_CANNOT_POST(rq))) 457 return false; 458 459 while (!mlx5_wq_ll_is_full(wq)) { 460 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); 461 int err; 462 463 err = rq->alloc_wqe(rq, wqe, wq->head); 464 if (err == -EBUSY) 465 return true; 466 if (unlikely(err)) { 467 rq->stats.buff_alloc_err++; 468 break; 469 } 470 471 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); 472 } 473 474 /* ensure wqes are visible to device before updating doorbell record */ 475 dma_wmb(); 476 477 mlx5_wq_ll_update_db_record(wq); 478 479 return !mlx5_wq_ll_is_full(wq); 480 } 481 482 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe, 483 u32 cqe_bcnt) 484 { 485 struct ethhdr *eth = (struct ethhdr *)(skb->data); 486 struct iphdr *ipv4; 487 struct ipv6hdr *ipv6; 488 struct tcphdr *tcp; 489 int network_depth = 0; 490 __be16 proto; 491 u16 tot_len; 492 493 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe); 494 int tcp_ack = ((CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA == l4_hdr_type) || 495 (CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA == l4_hdr_type)); 496 497 skb->mac_len = ETH_HLEN; 498 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth); 499 500 ipv4 = (struct iphdr *)(skb->data + network_depth); 501 ipv6 = (struct ipv6hdr *)(skb->data + network_depth); 502 tot_len = cqe_bcnt - network_depth; 503 504 if (proto == htons(ETH_P_IP)) { 505 tcp = (struct tcphdr *)(skb->data + network_depth + 506 sizeof(struct iphdr)); 507 ipv6 = NULL; 508 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 509 } else { 510 tcp = (struct tcphdr *)(skb->data + network_depth + 511 sizeof(struct ipv6hdr)); 512 ipv4 = NULL; 513 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 514 } 515 516 if (get_cqe_lro_tcppsh(cqe)) 517 tcp->psh = 1; 518 519 if (tcp_ack) { 520 tcp->ack = 1; 521 tcp->ack_seq = cqe->lro_ack_seq_num; 522 tcp->window = cqe->lro_tcp_win; 523 } 524 525 if (ipv4) { 526 ipv4->ttl = cqe->lro_min_ttl; 527 ipv4->tot_len = cpu_to_be16(tot_len); 528 ipv4->check = 0; 529 ipv4->check = ip_fast_csum((unsigned char *)ipv4, 530 ipv4->ihl); 531 } else { 532 ipv6->hop_limit = cqe->lro_min_ttl; 533 ipv6->payload_len = cpu_to_be16(tot_len - 534 sizeof(struct ipv6hdr)); 535 } 536 } 537 538 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe, 539 struct sk_buff *skb) 540 { 541 u8 cht = cqe->rss_hash_type; 542 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 : 543 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 : 544 PKT_HASH_TYPE_NONE; 545 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht); 546 } 547 548 static inline bool is_first_ethertype_ip(struct sk_buff *skb) 549 { 550 __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto; 551 552 return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6)); 553 } 554 555 static inline void mlx5e_handle_csum(struct net_device *netdev, 556 struct mlx5_cqe64 *cqe, 557 struct mlx5e_rq *rq, 558 struct sk_buff *skb, 559 bool lro) 560 { 561 if (unlikely(!(netdev->features & NETIF_F_RXCSUM))) 562 goto csum_none; 563 564 if (lro) { 565 skb->ip_summed = CHECKSUM_UNNECESSARY; 566 return; 567 } 568 569 if (is_first_ethertype_ip(skb)) { 570 skb->ip_summed = CHECKSUM_COMPLETE; 571 skb->csum = csum_unfold((__force __sum16)cqe->check_sum); 572 rq->stats.csum_complete++; 573 return; 574 } 575 576 if (likely((cqe->hds_ip_ext & CQE_L3_OK) && 577 (cqe->hds_ip_ext & CQE_L4_OK))) { 578 skb->ip_summed = CHECKSUM_UNNECESSARY; 579 if (cqe_is_tunneled(cqe)) { 580 skb->csum_level = 1; 581 skb->encapsulation = 1; 582 rq->stats.csum_unnecessary_inner++; 583 } 584 return; 585 } 586 csum_none: 587 skb->ip_summed = CHECKSUM_NONE; 588 rq->stats.csum_none++; 589 } 590 591 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe, 592 u32 cqe_bcnt, 593 struct mlx5e_rq *rq, 594 struct sk_buff *skb) 595 { 596 struct net_device *netdev = rq->netdev; 597 struct mlx5e_tstamp *tstamp = rq->tstamp; 598 int lro_num_seg; 599 600 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24; 601 if (lro_num_seg > 1) { 602 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt); 603 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg); 604 /* Subtract one since we already counted this as one 605 * "regular" packet in mlx5e_complete_rx_cqe() 606 */ 607 rq->stats.packets += lro_num_seg - 1; 608 rq->stats.lro_packets++; 609 rq->stats.lro_bytes += cqe_bcnt; 610 } 611 612 if (unlikely(mlx5e_rx_hw_stamp(tstamp))) 613 mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb)); 614 615 skb_record_rx_queue(skb, rq->ix); 616 617 if (likely(netdev->features & NETIF_F_RXHASH)) 618 mlx5e_skb_set_hash(cqe, skb); 619 620 if (cqe_has_vlan(cqe)) 621 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 622 be16_to_cpu(cqe->vlan_info)); 623 624 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK; 625 626 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg); 627 skb->protocol = eth_type_trans(skb, netdev); 628 } 629 630 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq, 631 struct mlx5_cqe64 *cqe, 632 u32 cqe_bcnt, 633 struct sk_buff *skb) 634 { 635 rq->stats.packets++; 636 rq->stats.bytes += cqe_bcnt; 637 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb); 638 } 639 640 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_sq *sq) 641 { 642 struct mlx5_wq_cyc *wq = &sq->wq; 643 struct mlx5e_tx_wqe *wqe; 644 u16 pi = (sq->pc - MLX5E_XDP_TX_WQEBBS) & wq->sz_m1; /* last pi */ 645 646 wqe = mlx5_wq_cyc_get_wqe(wq, pi); 647 648 wqe->ctrl.fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE; 649 mlx5e_tx_notify_hw(sq, &wqe->ctrl); 650 } 651 652 static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq, 653 struct mlx5e_dma_info *di, 654 const struct xdp_buff *xdp) 655 { 656 struct mlx5e_sq *sq = &rq->channel->xdp_sq; 657 struct mlx5_wq_cyc *wq = &sq->wq; 658 u16 pi = sq->pc & wq->sz_m1; 659 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi); 660 struct mlx5e_sq_wqe_info *wi = &sq->db.xdp.wqe_info[pi]; 661 662 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; 663 struct mlx5_wqe_eth_seg *eseg = &wqe->eth; 664 struct mlx5_wqe_data_seg *dseg; 665 u8 ds_cnt = MLX5E_XDP_TX_DS_COUNT; 666 667 ptrdiff_t data_offset = xdp->data - xdp->data_hard_start; 668 dma_addr_t dma_addr = di->addr + data_offset; 669 unsigned int dma_len = xdp->data_end - xdp->data; 670 671 if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE || 672 MLX5E_SW2HW_MTU(rq->netdev->mtu) < dma_len)) { 673 rq->stats.xdp_drop++; 674 mlx5e_page_release(rq, di, true); 675 return false; 676 } 677 678 if (unlikely(!mlx5e_sq_has_room_for(sq, MLX5E_XDP_TX_WQEBBS))) { 679 if (sq->db.xdp.doorbell) { 680 /* SQ is full, ring doorbell */ 681 mlx5e_xmit_xdp_doorbell(sq); 682 sq->db.xdp.doorbell = false; 683 } 684 rq->stats.xdp_tx_full++; 685 mlx5e_page_release(rq, di, true); 686 return false; 687 } 688 689 dma_sync_single_for_device(sq->pdev, dma_addr, dma_len, 690 PCI_DMA_TODEVICE); 691 692 memset(wqe, 0, sizeof(*wqe)); 693 694 dseg = (struct mlx5_wqe_data_seg *)eseg + 1; 695 /* copy the inline part if required */ 696 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) { 697 memcpy(eseg->inline_hdr.start, xdp->data, MLX5E_XDP_MIN_INLINE); 698 eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE); 699 dma_len -= MLX5E_XDP_MIN_INLINE; 700 dma_addr += MLX5E_XDP_MIN_INLINE; 701 702 ds_cnt += MLX5E_XDP_IHS_DS_COUNT; 703 dseg++; 704 } 705 706 /* write the dma part */ 707 dseg->addr = cpu_to_be64(dma_addr); 708 dseg->byte_count = cpu_to_be32(dma_len); 709 dseg->lkey = sq->mkey_be; 710 711 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND); 712 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt); 713 714 sq->db.xdp.di[pi] = *di; 715 wi->opcode = MLX5_OPCODE_SEND; 716 wi->num_wqebbs = MLX5E_XDP_TX_WQEBBS; 717 sq->pc += MLX5E_XDP_TX_WQEBBS; 718 719 sq->db.xdp.doorbell = true; 720 rq->stats.xdp_tx++; 721 return true; 722 } 723 724 /* returns true if packet was consumed by xdp */ 725 static inline int mlx5e_xdp_handle(struct mlx5e_rq *rq, 726 struct mlx5e_dma_info *di, 727 void *va, u16 *rx_headroom, u32 *len) 728 { 729 const struct bpf_prog *prog = READ_ONCE(rq->xdp_prog); 730 struct xdp_buff xdp; 731 u32 act; 732 733 if (!prog) 734 return false; 735 736 xdp.data = va + *rx_headroom; 737 xdp.data_end = xdp.data + *len; 738 xdp.data_hard_start = va; 739 740 act = bpf_prog_run_xdp(prog, &xdp); 741 switch (act) { 742 case XDP_PASS: 743 *rx_headroom = xdp.data - xdp.data_hard_start; 744 *len = xdp.data_end - xdp.data; 745 return false; 746 case XDP_TX: 747 if (unlikely(!mlx5e_xmit_xdp_frame(rq, di, &xdp))) 748 trace_xdp_exception(rq->netdev, prog, act); 749 return true; 750 default: 751 bpf_warn_invalid_xdp_action(act); 752 case XDP_ABORTED: 753 trace_xdp_exception(rq->netdev, prog, act); 754 case XDP_DROP: 755 rq->stats.xdp_drop++; 756 mlx5e_page_release(rq, di, true); 757 return true; 758 } 759 } 760 761 static inline 762 struct sk_buff *skb_from_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, 763 u16 wqe_counter, u32 cqe_bcnt) 764 { 765 struct mlx5e_dma_info *di; 766 struct sk_buff *skb; 767 void *va, *data; 768 u16 rx_headroom = rq->rx_headroom; 769 bool consumed; 770 771 di = &rq->dma_info[wqe_counter]; 772 va = page_address(di->page); 773 data = va + rx_headroom; 774 775 dma_sync_single_range_for_cpu(rq->pdev, 776 di->addr, 777 rx_headroom, 778 rq->buff.wqe_sz, 779 DMA_FROM_DEVICE); 780 prefetch(data); 781 782 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { 783 rq->stats.wqe_err++; 784 mlx5e_page_release(rq, di, true); 785 return NULL; 786 } 787 788 rcu_read_lock(); 789 consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt); 790 rcu_read_unlock(); 791 if (consumed) 792 return NULL; /* page/packet was consumed by XDP */ 793 794 skb = build_skb(va, RQ_PAGE_SIZE(rq)); 795 if (unlikely(!skb)) { 796 rq->stats.buff_alloc_err++; 797 mlx5e_page_release(rq, di, true); 798 return NULL; 799 } 800 801 /* queue up for recycling ..*/ 802 page_ref_inc(di->page); 803 mlx5e_page_release(rq, di, true); 804 805 skb_reserve(skb, rx_headroom); 806 skb_put(skb, cqe_bcnt); 807 808 return skb; 809 } 810 811 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 812 { 813 struct mlx5e_rx_wqe *wqe; 814 __be16 wqe_counter_be; 815 struct sk_buff *skb; 816 u16 wqe_counter; 817 u32 cqe_bcnt; 818 819 wqe_counter_be = cqe->wqe_counter; 820 wqe_counter = be16_to_cpu(wqe_counter_be); 821 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 822 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 823 824 skb = skb_from_cqe(rq, cqe, wqe_counter, cqe_bcnt); 825 if (!skb) 826 goto wq_ll_pop; 827 828 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 829 napi_gro_receive(rq->cq.napi, skb); 830 831 wq_ll_pop: 832 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 833 &wqe->next.next_wqe_index); 834 } 835 836 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 837 { 838 struct net_device *netdev = rq->netdev; 839 struct mlx5e_priv *priv = netdev_priv(netdev); 840 struct mlx5_eswitch_rep *rep = priv->ppriv; 841 struct mlx5e_rx_wqe *wqe; 842 struct sk_buff *skb; 843 __be16 wqe_counter_be; 844 u16 wqe_counter; 845 u32 cqe_bcnt; 846 847 wqe_counter_be = cqe->wqe_counter; 848 wqe_counter = be16_to_cpu(wqe_counter_be); 849 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 850 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 851 852 skb = skb_from_cqe(rq, cqe, wqe_counter, cqe_bcnt); 853 if (!skb) 854 goto wq_ll_pop; 855 856 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 857 858 if (rep->vlan && skb_vlan_tag_present(skb)) 859 skb_vlan_pop(skb); 860 861 napi_gro_receive(rq->cq.napi, skb); 862 863 wq_ll_pop: 864 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 865 &wqe->next.next_wqe_index); 866 } 867 868 static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq, 869 struct mlx5_cqe64 *cqe, 870 struct mlx5e_mpw_info *wi, 871 u32 cqe_bcnt, 872 struct sk_buff *skb) 873 { 874 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe); 875 u32 wqe_offset = stride_ix * rq->mpwqe_stride_sz; 876 u32 head_offset = wqe_offset & (PAGE_SIZE - 1); 877 u32 page_idx = wqe_offset >> PAGE_SHIFT; 878 u32 head_page_idx = page_idx; 879 u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt); 880 u32 frag_offset = head_offset + headlen; 881 u16 byte_cnt = cqe_bcnt - headlen; 882 883 if (unlikely(frag_offset >= PAGE_SIZE)) { 884 page_idx++; 885 frag_offset -= PAGE_SIZE; 886 } 887 888 while (byte_cnt) { 889 u32 pg_consumed_bytes = 890 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt); 891 892 mlx5e_add_skb_frag_mpwqe(rq, skb, wi, page_idx, frag_offset, 893 pg_consumed_bytes); 894 byte_cnt -= pg_consumed_bytes; 895 frag_offset = 0; 896 page_idx++; 897 } 898 /* copy header */ 899 mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, wi, head_page_idx, 900 head_offset, headlen); 901 /* skb linear part was allocated with headlen and aligned to long */ 902 skb->tail += headlen; 903 skb->len += headlen; 904 } 905 906 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 907 { 908 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe); 909 u16 wqe_id = be16_to_cpu(cqe->wqe_id); 910 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id]; 911 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id); 912 struct sk_buff *skb; 913 u16 cqe_bcnt; 914 915 wi->consumed_strides += cstrides; 916 917 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { 918 rq->stats.wqe_err++; 919 goto mpwrq_cqe_out; 920 } 921 922 if (unlikely(mpwrq_is_filler_cqe(cqe))) { 923 rq->stats.mpwqe_filler++; 924 goto mpwrq_cqe_out; 925 } 926 927 skb = napi_alloc_skb(rq->cq.napi, 928 ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, 929 sizeof(long))); 930 if (unlikely(!skb)) { 931 rq->stats.buff_alloc_err++; 932 goto mpwrq_cqe_out; 933 } 934 935 prefetch(skb->data); 936 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe); 937 938 mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb); 939 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 940 napi_gro_receive(rq->cq.napi, skb); 941 942 mpwrq_cqe_out: 943 if (likely(wi->consumed_strides < rq->mpwqe_num_strides)) 944 return; 945 946 mlx5e_free_rx_mpwqe(rq, wi); 947 mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index); 948 } 949 950 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget) 951 { 952 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq); 953 struct mlx5e_sq *xdp_sq = &rq->channel->xdp_sq; 954 int work_done = 0; 955 956 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state))) 957 return 0; 958 959 if (cq->decmprs_left) 960 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget); 961 962 for (; work_done < budget; work_done++) { 963 struct mlx5_cqe64 *cqe = mlx5e_get_cqe(cq); 964 965 if (!cqe) 966 break; 967 968 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) { 969 work_done += 970 mlx5e_decompress_cqes_start(rq, cq, 971 budget - work_done); 972 continue; 973 } 974 975 mlx5_cqwq_pop(&cq->wq); 976 977 rq->handle_rx_cqe(rq, cqe); 978 } 979 980 if (xdp_sq->db.xdp.doorbell) { 981 mlx5e_xmit_xdp_doorbell(xdp_sq); 982 xdp_sq->db.xdp.doorbell = false; 983 } 984 985 mlx5_cqwq_update_db_record(&cq->wq); 986 987 /* ensure cq space is freed before enabling more cqes */ 988 wmb(); 989 990 return work_done; 991 } 992