1 /* 2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/prefetch.h> 34 #include <linux/ip.h> 35 #include <linux/ipv6.h> 36 #include <linux/tcp.h> 37 #include <linux/bpf_trace.h> 38 #include <net/busy_poll.h> 39 #include "en.h" 40 #include "en_tc.h" 41 #include "eswitch.h" 42 #include "en_rep.h" 43 #include "ipoib/ipoib.h" 44 #include "en_accel/ipsec_rxtx.h" 45 46 static inline bool mlx5e_rx_hw_stamp(struct mlx5e_tstamp *tstamp) 47 { 48 return tstamp->hwtstamp_config.rx_filter == HWTSTAMP_FILTER_ALL; 49 } 50 51 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc, 52 void *data) 53 { 54 u32 ci = cqcc & cq->wq.sz_m1; 55 56 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64)); 57 } 58 59 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq, 60 struct mlx5e_cq *cq, u32 cqcc) 61 { 62 mlx5e_read_cqe_slot(cq, cqcc, &cq->title); 63 cq->decmprs_left = be32_to_cpu(cq->title.byte_cnt); 64 cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter); 65 rq->stats.cqe_compress_blks++; 66 } 67 68 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc) 69 { 70 mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr); 71 cq->mini_arr_idx = 0; 72 } 73 74 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n) 75 { 76 u8 op_own = (cqcc >> cq->wq.log_sz) & 1; 77 u32 wq_sz = 1 << cq->wq.log_sz; 78 u32 ci = cqcc & cq->wq.sz_m1; 79 u32 ci_top = min_t(u32, wq_sz, ci + n); 80 81 for (; ci < ci_top; ci++, n--) { 82 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci); 83 84 cqe->op_own = op_own; 85 } 86 87 if (unlikely(ci == wq_sz)) { 88 op_own = !op_own; 89 for (ci = 0; ci < n; ci++) { 90 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci); 91 92 cqe->op_own = op_own; 93 } 94 } 95 } 96 97 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq, 98 struct mlx5e_cq *cq, u32 cqcc) 99 { 100 cq->title.byte_cnt = cq->mini_arr[cq->mini_arr_idx].byte_cnt; 101 cq->title.check_sum = cq->mini_arr[cq->mini_arr_idx].checksum; 102 cq->title.op_own &= 0xf0; 103 cq->title.op_own |= 0x01 & (cqcc >> cq->wq.log_sz); 104 cq->title.wqe_counter = cpu_to_be16(cq->decmprs_wqe_counter); 105 106 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) 107 cq->decmprs_wqe_counter += 108 mpwrq_get_cqe_consumed_strides(&cq->title); 109 else 110 cq->decmprs_wqe_counter = 111 (cq->decmprs_wqe_counter + 1) & rq->wq.sz_m1; 112 } 113 114 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq, 115 struct mlx5e_cq *cq, u32 cqcc) 116 { 117 mlx5e_decompress_cqe(rq, cq, cqcc); 118 cq->title.rss_hash_type = 0; 119 cq->title.rss_hash_result = 0; 120 } 121 122 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq, 123 struct mlx5e_cq *cq, 124 int update_owner_only, 125 int budget_rem) 126 { 127 u32 cqcc = cq->wq.cc + update_owner_only; 128 u32 cqe_count; 129 u32 i; 130 131 cqe_count = min_t(u32, cq->decmprs_left, budget_rem); 132 133 for (i = update_owner_only; i < cqe_count; 134 i++, cq->mini_arr_idx++, cqcc++) { 135 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE) 136 mlx5e_read_mini_arr_slot(cq, cqcc); 137 138 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc); 139 rq->handle_rx_cqe(rq, &cq->title); 140 } 141 mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc); 142 cq->wq.cc = cqcc; 143 cq->decmprs_left -= cqe_count; 144 rq->stats.cqe_compress_pkts += cqe_count; 145 146 return cqe_count; 147 } 148 149 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq, 150 struct mlx5e_cq *cq, 151 int budget_rem) 152 { 153 mlx5e_read_title_slot(rq, cq, cq->wq.cc); 154 mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1); 155 mlx5e_decompress_cqe(rq, cq, cq->wq.cc); 156 rq->handle_rx_cqe(rq, &cq->title); 157 cq->mini_arr_idx++; 158 159 return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1; 160 } 161 162 #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT) 163 164 static inline bool mlx5e_page_is_reserved(struct page *page) 165 { 166 return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id(); 167 } 168 169 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq, 170 struct mlx5e_dma_info *dma_info) 171 { 172 struct mlx5e_page_cache *cache = &rq->page_cache; 173 u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1); 174 175 if (tail_next == cache->head) { 176 rq->stats.cache_full++; 177 return false; 178 } 179 180 if (unlikely(mlx5e_page_is_reserved(dma_info->page))) { 181 rq->stats.cache_waive++; 182 return false; 183 } 184 185 cache->page_cache[cache->tail] = *dma_info; 186 cache->tail = tail_next; 187 return true; 188 } 189 190 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq, 191 struct mlx5e_dma_info *dma_info) 192 { 193 struct mlx5e_page_cache *cache = &rq->page_cache; 194 195 if (unlikely(cache->head == cache->tail)) { 196 rq->stats.cache_empty++; 197 return false; 198 } 199 200 if (page_ref_count(cache->page_cache[cache->head].page) != 1) { 201 rq->stats.cache_busy++; 202 return false; 203 } 204 205 *dma_info = cache->page_cache[cache->head]; 206 cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1); 207 rq->stats.cache_reuse++; 208 209 dma_sync_single_for_device(rq->pdev, dma_info->addr, 210 RQ_PAGE_SIZE(rq), 211 DMA_FROM_DEVICE); 212 return true; 213 } 214 215 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq, 216 struct mlx5e_dma_info *dma_info) 217 { 218 struct page *page; 219 220 if (mlx5e_rx_cache_get(rq, dma_info)) 221 return 0; 222 223 page = dev_alloc_pages(rq->buff.page_order); 224 if (unlikely(!page)) 225 return -ENOMEM; 226 227 dma_info->addr = dma_map_page(rq->pdev, page, 0, 228 RQ_PAGE_SIZE(rq), rq->buff.map_dir); 229 if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) { 230 put_page(page); 231 return -ENOMEM; 232 } 233 dma_info->page = page; 234 235 return 0; 236 } 237 238 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info, 239 bool recycle) 240 { 241 if (likely(recycle) && mlx5e_rx_cache_put(rq, dma_info)) 242 return; 243 244 dma_unmap_page(rq->pdev, dma_info->addr, RQ_PAGE_SIZE(rq), 245 rq->buff.map_dir); 246 put_page(dma_info->page); 247 } 248 249 static inline bool mlx5e_page_reuse(struct mlx5e_rq *rq, 250 struct mlx5e_wqe_frag_info *wi) 251 { 252 return rq->wqe.page_reuse && wi->di.page && 253 (wi->offset + rq->wqe.frag_sz <= RQ_PAGE_SIZE(rq)) && 254 !mlx5e_page_is_reserved(wi->di.page); 255 } 256 257 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix) 258 { 259 struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix]; 260 261 /* check if page exists, hence can be reused */ 262 if (!wi->di.page) { 263 if (unlikely(mlx5e_page_alloc_mapped(rq, &wi->di))) 264 return -ENOMEM; 265 wi->offset = 0; 266 } 267 268 wqe->data.addr = cpu_to_be64(wi->di.addr + wi->offset + rq->buff.headroom); 269 return 0; 270 } 271 272 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq, 273 struct mlx5e_wqe_frag_info *wi) 274 { 275 mlx5e_page_release(rq, &wi->di, true); 276 wi->di.page = NULL; 277 } 278 279 static inline void mlx5e_free_rx_wqe_reuse(struct mlx5e_rq *rq, 280 struct mlx5e_wqe_frag_info *wi) 281 { 282 if (mlx5e_page_reuse(rq, wi)) { 283 rq->stats.page_reuse++; 284 return; 285 } 286 287 mlx5e_free_rx_wqe(rq, wi); 288 } 289 290 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix) 291 { 292 struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix]; 293 294 if (wi->di.page) 295 mlx5e_free_rx_wqe(rq, wi); 296 } 297 298 static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq) 299 { 300 return rq->mpwqe.num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER; 301 } 302 303 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq, 304 struct sk_buff *skb, 305 struct mlx5e_mpw_info *wi, 306 u32 page_idx, u32 frag_offset, 307 u32 len) 308 { 309 unsigned int truesize = ALIGN(len, BIT(rq->mpwqe.log_stride_sz)); 310 311 dma_sync_single_for_cpu(rq->pdev, 312 wi->umr.dma_info[page_idx].addr + frag_offset, 313 len, DMA_FROM_DEVICE); 314 wi->skbs_frags[page_idx]++; 315 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 316 wi->umr.dma_info[page_idx].page, frag_offset, 317 len, truesize); 318 } 319 320 static inline void 321 mlx5e_copy_skb_header_mpwqe(struct device *pdev, 322 struct sk_buff *skb, 323 struct mlx5e_mpw_info *wi, 324 u32 page_idx, u32 offset, 325 u32 headlen) 326 { 327 u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset); 328 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx]; 329 unsigned int len; 330 331 /* Aligning len to sizeof(long) optimizes memcpy performance */ 332 len = ALIGN(headlen_pg, sizeof(long)); 333 dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len, 334 DMA_FROM_DEVICE); 335 skb_copy_to_linear_data_offset(skb, 0, 336 page_address(dma_info->page) + offset, 337 len); 338 if (unlikely(offset + headlen > PAGE_SIZE)) { 339 dma_info++; 340 headlen_pg = len; 341 len = ALIGN(headlen - headlen_pg, sizeof(long)); 342 dma_sync_single_for_cpu(pdev, dma_info->addr, len, 343 DMA_FROM_DEVICE); 344 skb_copy_to_linear_data_offset(skb, headlen_pg, 345 page_address(dma_info->page), 346 len); 347 } 348 } 349 350 static inline void mlx5e_post_umr_wqe(struct mlx5e_rq *rq, u16 ix) 351 { 352 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 353 struct mlx5e_icosq *sq = &rq->channel->icosq; 354 struct mlx5_wq_cyc *wq = &sq->wq; 355 struct mlx5e_umr_wqe *wqe; 356 u8 num_wqebbs = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_BB); 357 u16 pi; 358 359 /* fill sq edge with nops to avoid wqe wrap around */ 360 while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) { 361 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP; 362 mlx5e_post_nop(wq, sq->sqn, &sq->pc); 363 } 364 365 wqe = mlx5_wq_cyc_get_wqe(wq, pi); 366 memcpy(wqe, &wi->umr.wqe, sizeof(*wqe)); 367 wqe->ctrl.opmod_idx_opcode = 368 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) | 369 MLX5_OPCODE_UMR); 370 371 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR; 372 sq->pc += num_wqebbs; 373 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &wqe->ctrl); 374 } 375 376 static int mlx5e_alloc_rx_umr_mpwqe(struct mlx5e_rq *rq, 377 u16 ix) 378 { 379 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 380 int pg_strides = mlx5e_mpwqe_strides_per_page(rq); 381 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0]; 382 int err; 383 int i; 384 385 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) { 386 err = mlx5e_page_alloc_mapped(rq, dma_info); 387 if (unlikely(err)) 388 goto err_unmap; 389 wi->umr.mtt[i] = cpu_to_be64(dma_info->addr | MLX5_EN_WR); 390 page_ref_add(dma_info->page, pg_strides); 391 } 392 393 memset(wi->skbs_frags, 0, sizeof(*wi->skbs_frags) * MLX5_MPWRQ_PAGES_PER_WQE); 394 wi->consumed_strides = 0; 395 396 return 0; 397 398 err_unmap: 399 while (--i >= 0) { 400 dma_info--; 401 page_ref_sub(dma_info->page, pg_strides); 402 mlx5e_page_release(rq, dma_info, true); 403 } 404 405 return err; 406 } 407 408 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi) 409 { 410 int pg_strides = mlx5e_mpwqe_strides_per_page(rq); 411 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0]; 412 int i; 413 414 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) { 415 page_ref_sub(dma_info->page, pg_strides - wi->skbs_frags[i]); 416 mlx5e_page_release(rq, dma_info, true); 417 } 418 } 419 420 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq) 421 { 422 struct mlx5_wq_ll *wq = &rq->wq; 423 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); 424 425 rq->mpwqe.umr_in_progress = false; 426 427 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); 428 429 /* ensure wqes are visible to device before updating doorbell record */ 430 dma_wmb(); 431 432 mlx5_wq_ll_update_db_record(wq); 433 } 434 435 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) 436 { 437 int err; 438 439 err = mlx5e_alloc_rx_umr_mpwqe(rq, ix); 440 if (unlikely(err)) { 441 rq->stats.buff_alloc_err++; 442 return err; 443 } 444 rq->mpwqe.umr_in_progress = true; 445 mlx5e_post_umr_wqe(rq, ix); 446 return 0; 447 } 448 449 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) 450 { 451 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 452 453 mlx5e_free_rx_mpwqe(rq, wi); 454 } 455 456 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq) 457 { 458 struct mlx5_wq_ll *wq = &rq->wq; 459 int err; 460 461 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED))) 462 return false; 463 464 if (mlx5_wq_ll_is_full(wq)) 465 return false; 466 467 do { 468 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); 469 470 err = mlx5e_alloc_rx_wqe(rq, wqe, wq->head); 471 if (unlikely(err)) { 472 rq->stats.buff_alloc_err++; 473 break; 474 } 475 476 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); 477 } while (!mlx5_wq_ll_is_full(wq)); 478 479 /* ensure wqes are visible to device before updating doorbell record */ 480 dma_wmb(); 481 482 mlx5_wq_ll_update_db_record(wq); 483 484 return !!err; 485 } 486 487 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq, 488 struct mlx5e_icosq *sq, 489 struct mlx5e_rq *rq, 490 struct mlx5_cqe64 *cqe) 491 { 492 struct mlx5_wq_cyc *wq = &sq->wq; 493 u16 ci = be16_to_cpu(cqe->wqe_counter) & wq->sz_m1; 494 struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci]; 495 496 mlx5_cqwq_pop(&cq->wq); 497 498 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) { 499 WARN_ONCE(true, "mlx5e: Bad OP in ICOSQ CQE: 0x%x\n", 500 cqe->op_own); 501 return; 502 } 503 504 if (likely(icowi->opcode == MLX5_OPCODE_UMR)) { 505 mlx5e_post_rx_mpwqe(rq); 506 return; 507 } 508 509 if (unlikely(icowi->opcode != MLX5_OPCODE_NOP)) 510 WARN_ONCE(true, 511 "mlx5e: Bad OPCODE in ICOSQ WQE info: 0x%x\n", 512 icowi->opcode); 513 } 514 515 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq) 516 { 517 struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq); 518 struct mlx5_cqe64 *cqe; 519 520 if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED))) 521 return; 522 523 cqe = mlx5_cqwq_get_cqe(&cq->wq); 524 if (likely(!cqe)) 525 return; 526 527 /* by design, there's only a single cqe */ 528 mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe); 529 530 mlx5_cqwq_update_db_record(&cq->wq); 531 } 532 533 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq) 534 { 535 struct mlx5_wq_ll *wq = &rq->wq; 536 537 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED))) 538 return false; 539 540 mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq); 541 542 if (mlx5_wq_ll_is_full(wq)) 543 return false; 544 545 if (!rq->mpwqe.umr_in_progress) 546 mlx5e_alloc_rx_mpwqe(rq, wq->head); 547 548 return true; 549 } 550 551 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe, 552 u32 cqe_bcnt) 553 { 554 struct ethhdr *eth = (struct ethhdr *)(skb->data); 555 struct tcphdr *tcp; 556 int network_depth = 0; 557 __be16 proto; 558 u16 tot_len; 559 void *ip_p; 560 561 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe); 562 u8 tcp_ack = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) || 563 (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA); 564 565 skb->mac_len = ETH_HLEN; 566 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth); 567 568 tot_len = cqe_bcnt - network_depth; 569 ip_p = skb->data + network_depth; 570 571 if (proto == htons(ETH_P_IP)) { 572 struct iphdr *ipv4 = ip_p; 573 574 tcp = ip_p + sizeof(struct iphdr); 575 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 576 577 ipv4->ttl = cqe->lro_min_ttl; 578 ipv4->tot_len = cpu_to_be16(tot_len); 579 ipv4->check = 0; 580 ipv4->check = ip_fast_csum((unsigned char *)ipv4, 581 ipv4->ihl); 582 } else { 583 struct ipv6hdr *ipv6 = ip_p; 584 585 tcp = ip_p + sizeof(struct ipv6hdr); 586 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 587 588 ipv6->hop_limit = cqe->lro_min_ttl; 589 ipv6->payload_len = cpu_to_be16(tot_len - 590 sizeof(struct ipv6hdr)); 591 } 592 593 tcp->psh = get_cqe_lro_tcppsh(cqe); 594 595 if (tcp_ack) { 596 tcp->ack = 1; 597 tcp->ack_seq = cqe->lro_ack_seq_num; 598 tcp->window = cqe->lro_tcp_win; 599 } 600 } 601 602 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe, 603 struct sk_buff *skb) 604 { 605 u8 cht = cqe->rss_hash_type; 606 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 : 607 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 : 608 PKT_HASH_TYPE_NONE; 609 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht); 610 } 611 612 static inline bool is_first_ethertype_ip(struct sk_buff *skb) 613 { 614 __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto; 615 616 return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6)); 617 } 618 619 static inline void mlx5e_handle_csum(struct net_device *netdev, 620 struct mlx5_cqe64 *cqe, 621 struct mlx5e_rq *rq, 622 struct sk_buff *skb, 623 bool lro) 624 { 625 if (unlikely(!(netdev->features & NETIF_F_RXCSUM))) 626 goto csum_none; 627 628 if (lro) { 629 skb->ip_summed = CHECKSUM_UNNECESSARY; 630 rq->stats.csum_unnecessary++; 631 return; 632 } 633 634 if (is_first_ethertype_ip(skb)) { 635 skb->ip_summed = CHECKSUM_COMPLETE; 636 skb->csum = csum_unfold((__force __sum16)cqe->check_sum); 637 rq->stats.csum_complete++; 638 return; 639 } 640 641 if (likely((cqe->hds_ip_ext & CQE_L3_OK) && 642 (cqe->hds_ip_ext & CQE_L4_OK))) { 643 skb->ip_summed = CHECKSUM_UNNECESSARY; 644 if (cqe_is_tunneled(cqe)) { 645 skb->csum_level = 1; 646 skb->encapsulation = 1; 647 rq->stats.csum_unnecessary_inner++; 648 return; 649 } 650 rq->stats.csum_unnecessary++; 651 return; 652 } 653 csum_none: 654 skb->ip_summed = CHECKSUM_NONE; 655 rq->stats.csum_none++; 656 } 657 658 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe, 659 u32 cqe_bcnt, 660 struct mlx5e_rq *rq, 661 struct sk_buff *skb) 662 { 663 struct net_device *netdev = rq->netdev; 664 struct mlx5e_tstamp *tstamp = rq->tstamp; 665 int lro_num_seg; 666 667 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24; 668 if (lro_num_seg > 1) { 669 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt); 670 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg); 671 /* Subtract one since we already counted this as one 672 * "regular" packet in mlx5e_complete_rx_cqe() 673 */ 674 rq->stats.packets += lro_num_seg - 1; 675 rq->stats.lro_packets++; 676 rq->stats.lro_bytes += cqe_bcnt; 677 } 678 679 if (unlikely(mlx5e_rx_hw_stamp(tstamp))) 680 mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb)); 681 682 skb_record_rx_queue(skb, rq->ix); 683 684 if (likely(netdev->features & NETIF_F_RXHASH)) 685 mlx5e_skb_set_hash(cqe, skb); 686 687 if (cqe_has_vlan(cqe)) 688 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 689 be16_to_cpu(cqe->vlan_info)); 690 691 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK; 692 693 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg); 694 skb->protocol = eth_type_trans(skb, netdev); 695 } 696 697 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq, 698 struct mlx5_cqe64 *cqe, 699 u32 cqe_bcnt, 700 struct sk_buff *skb) 701 { 702 rq->stats.packets++; 703 rq->stats.bytes += cqe_bcnt; 704 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb); 705 } 706 707 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq) 708 { 709 struct mlx5_wq_cyc *wq = &sq->wq; 710 struct mlx5e_tx_wqe *wqe; 711 u16 pi = (sq->pc - 1) & wq->sz_m1; /* last pi */ 712 713 wqe = mlx5_wq_cyc_get_wqe(wq, pi); 714 715 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &wqe->ctrl); 716 } 717 718 static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq, 719 struct mlx5e_dma_info *di, 720 const struct xdp_buff *xdp) 721 { 722 struct mlx5e_xdpsq *sq = &rq->xdpsq; 723 struct mlx5_wq_cyc *wq = &sq->wq; 724 u16 pi = sq->pc & wq->sz_m1; 725 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi); 726 727 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; 728 struct mlx5_wqe_eth_seg *eseg = &wqe->eth; 729 struct mlx5_wqe_data_seg *dseg; 730 731 ptrdiff_t data_offset = xdp->data - xdp->data_hard_start; 732 dma_addr_t dma_addr = di->addr + data_offset; 733 unsigned int dma_len = xdp->data_end - xdp->data; 734 735 prefetchw(wqe); 736 737 if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE || 738 MLX5E_SW2HW_MTU(rq->channel->priv, rq->netdev->mtu) < dma_len)) { 739 rq->stats.xdp_drop++; 740 return false; 741 } 742 743 if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1))) { 744 if (sq->db.doorbell) { 745 /* SQ is full, ring doorbell */ 746 mlx5e_xmit_xdp_doorbell(sq); 747 sq->db.doorbell = false; 748 } 749 rq->stats.xdp_tx_full++; 750 return false; 751 } 752 753 dma_sync_single_for_device(sq->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE); 754 755 cseg->fm_ce_se = 0; 756 757 dseg = (struct mlx5_wqe_data_seg *)eseg + 1; 758 759 /* copy the inline part if required */ 760 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) { 761 memcpy(eseg->inline_hdr.start, xdp->data, MLX5E_XDP_MIN_INLINE); 762 eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE); 763 dma_len -= MLX5E_XDP_MIN_INLINE; 764 dma_addr += MLX5E_XDP_MIN_INLINE; 765 dseg++; 766 } 767 768 /* write the dma part */ 769 dseg->addr = cpu_to_be64(dma_addr); 770 dseg->byte_count = cpu_to_be32(dma_len); 771 772 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND); 773 774 /* move page to reference to sq responsibility, 775 * and mark so it's not put back in page-cache. 776 */ 777 rq->wqe.xdp_xmit = true; 778 sq->db.di[pi] = *di; 779 sq->pc++; 780 781 sq->db.doorbell = true; 782 783 rq->stats.xdp_tx++; 784 return true; 785 } 786 787 /* returns true if packet was consumed by xdp */ 788 static inline int mlx5e_xdp_handle(struct mlx5e_rq *rq, 789 struct mlx5e_dma_info *di, 790 void *va, u16 *rx_headroom, u32 *len) 791 { 792 const struct bpf_prog *prog = READ_ONCE(rq->xdp_prog); 793 struct xdp_buff xdp; 794 u32 act; 795 796 if (!prog) 797 return false; 798 799 xdp.data = va + *rx_headroom; 800 xdp.data_end = xdp.data + *len; 801 xdp.data_hard_start = va; 802 803 act = bpf_prog_run_xdp(prog, &xdp); 804 switch (act) { 805 case XDP_PASS: 806 *rx_headroom = xdp.data - xdp.data_hard_start; 807 *len = xdp.data_end - xdp.data; 808 return false; 809 case XDP_TX: 810 if (unlikely(!mlx5e_xmit_xdp_frame(rq, di, &xdp))) 811 trace_xdp_exception(rq->netdev, prog, act); 812 return true; 813 default: 814 bpf_warn_invalid_xdp_action(act); 815 case XDP_ABORTED: 816 trace_xdp_exception(rq->netdev, prog, act); 817 case XDP_DROP: 818 rq->stats.xdp_drop++; 819 return true; 820 } 821 } 822 823 static inline 824 struct sk_buff *skb_from_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, 825 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt) 826 { 827 struct mlx5e_dma_info *di = &wi->di; 828 u16 rx_headroom = rq->buff.headroom; 829 struct sk_buff *skb; 830 void *va, *data; 831 bool consumed; 832 u32 frag_size; 833 834 va = page_address(di->page) + wi->offset; 835 data = va + rx_headroom; 836 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt); 837 838 dma_sync_single_range_for_cpu(rq->pdev, 839 di->addr + wi->offset, 840 0, frag_size, 841 DMA_FROM_DEVICE); 842 prefetch(data); 843 wi->offset += frag_size; 844 845 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { 846 rq->stats.wqe_err++; 847 return NULL; 848 } 849 850 rcu_read_lock(); 851 consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt); 852 rcu_read_unlock(); 853 if (consumed) 854 return NULL; /* page/packet was consumed by XDP */ 855 856 skb = build_skb(va, frag_size); 857 if (unlikely(!skb)) { 858 rq->stats.buff_alloc_err++; 859 return NULL; 860 } 861 862 /* queue up for recycling/reuse */ 863 page_ref_inc(di->page); 864 865 skb_reserve(skb, rx_headroom); 866 skb_put(skb, cqe_bcnt); 867 868 return skb; 869 } 870 871 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 872 { 873 struct mlx5e_wqe_frag_info *wi; 874 struct mlx5e_rx_wqe *wqe; 875 __be16 wqe_counter_be; 876 struct sk_buff *skb; 877 u16 wqe_counter; 878 u32 cqe_bcnt; 879 880 wqe_counter_be = cqe->wqe_counter; 881 wqe_counter = be16_to_cpu(wqe_counter_be); 882 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 883 wi = &rq->wqe.frag_info[wqe_counter]; 884 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 885 886 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 887 if (!skb) { 888 /* probably for XDP */ 889 if (rq->wqe.xdp_xmit) { 890 wi->di.page = NULL; 891 rq->wqe.xdp_xmit = false; 892 /* do not return page to cache, it will be returned on XDP_TX completion */ 893 goto wq_ll_pop; 894 } 895 /* probably an XDP_DROP, save the page-reuse checks */ 896 mlx5e_free_rx_wqe(rq, wi); 897 goto wq_ll_pop; 898 } 899 900 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 901 napi_gro_receive(rq->cq.napi, skb); 902 903 mlx5e_free_rx_wqe_reuse(rq, wi); 904 wq_ll_pop: 905 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 906 &wqe->next.next_wqe_index); 907 } 908 909 #ifdef CONFIG_MLX5_ESWITCH 910 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 911 { 912 struct net_device *netdev = rq->netdev; 913 struct mlx5e_priv *priv = netdev_priv(netdev); 914 struct mlx5e_rep_priv *rpriv = priv->ppriv; 915 struct mlx5_eswitch_rep *rep = rpriv->rep; 916 struct mlx5e_wqe_frag_info *wi; 917 struct mlx5e_rx_wqe *wqe; 918 struct sk_buff *skb; 919 __be16 wqe_counter_be; 920 u16 wqe_counter; 921 u32 cqe_bcnt; 922 923 wqe_counter_be = cqe->wqe_counter; 924 wqe_counter = be16_to_cpu(wqe_counter_be); 925 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 926 wi = &rq->wqe.frag_info[wqe_counter]; 927 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 928 929 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 930 if (!skb) { 931 if (rq->wqe.xdp_xmit) { 932 wi->di.page = NULL; 933 rq->wqe.xdp_xmit = false; 934 /* do not return page to cache, it will be returned on XDP_TX completion */ 935 goto wq_ll_pop; 936 } 937 /* probably an XDP_DROP, save the page-reuse checks */ 938 mlx5e_free_rx_wqe(rq, wi); 939 goto wq_ll_pop; 940 } 941 942 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 943 944 if (rep->vlan && skb_vlan_tag_present(skb)) 945 skb_vlan_pop(skb); 946 947 napi_gro_receive(rq->cq.napi, skb); 948 949 mlx5e_free_rx_wqe_reuse(rq, wi); 950 wq_ll_pop: 951 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 952 &wqe->next.next_wqe_index); 953 } 954 #endif 955 956 static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq, 957 struct mlx5_cqe64 *cqe, 958 struct mlx5e_mpw_info *wi, 959 u32 cqe_bcnt, 960 struct sk_buff *skb) 961 { 962 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe); 963 u32 wqe_offset = stride_ix << rq->mpwqe.log_stride_sz; 964 u32 head_offset = wqe_offset & (PAGE_SIZE - 1); 965 u32 page_idx = wqe_offset >> PAGE_SHIFT; 966 u32 head_page_idx = page_idx; 967 u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt); 968 u32 frag_offset = head_offset + headlen; 969 u16 byte_cnt = cqe_bcnt - headlen; 970 971 if (unlikely(frag_offset >= PAGE_SIZE)) { 972 page_idx++; 973 frag_offset -= PAGE_SIZE; 974 } 975 976 while (byte_cnt) { 977 u32 pg_consumed_bytes = 978 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt); 979 980 mlx5e_add_skb_frag_mpwqe(rq, skb, wi, page_idx, frag_offset, 981 pg_consumed_bytes); 982 byte_cnt -= pg_consumed_bytes; 983 frag_offset = 0; 984 page_idx++; 985 } 986 /* copy header */ 987 mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, wi, head_page_idx, 988 head_offset, headlen); 989 /* skb linear part was allocated with headlen and aligned to long */ 990 skb->tail += headlen; 991 skb->len += headlen; 992 } 993 994 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 995 { 996 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe); 997 u16 wqe_id = be16_to_cpu(cqe->wqe_id); 998 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id]; 999 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id); 1000 struct sk_buff *skb; 1001 u16 cqe_bcnt; 1002 1003 wi->consumed_strides += cstrides; 1004 1005 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { 1006 rq->stats.wqe_err++; 1007 goto mpwrq_cqe_out; 1008 } 1009 1010 if (unlikely(mpwrq_is_filler_cqe(cqe))) { 1011 rq->stats.mpwqe_filler++; 1012 goto mpwrq_cqe_out; 1013 } 1014 1015 skb = napi_alloc_skb(rq->cq.napi, 1016 ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, 1017 sizeof(long))); 1018 if (unlikely(!skb)) { 1019 rq->stats.buff_alloc_err++; 1020 goto mpwrq_cqe_out; 1021 } 1022 1023 prefetchw(skb->data); 1024 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe); 1025 1026 mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb); 1027 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1028 napi_gro_receive(rq->cq.napi, skb); 1029 1030 mpwrq_cqe_out: 1031 if (likely(wi->consumed_strides < rq->mpwqe.num_strides)) 1032 return; 1033 1034 mlx5e_free_rx_mpwqe(rq, wi); 1035 mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index); 1036 } 1037 1038 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget) 1039 { 1040 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq); 1041 struct mlx5e_xdpsq *xdpsq; 1042 struct mlx5_cqe64 *cqe; 1043 int work_done = 0; 1044 1045 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED))) 1046 return 0; 1047 1048 if (cq->decmprs_left) 1049 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget); 1050 1051 cqe = mlx5_cqwq_get_cqe(&cq->wq); 1052 if (!cqe) 1053 return 0; 1054 1055 xdpsq = &rq->xdpsq; 1056 1057 do { 1058 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) { 1059 work_done += 1060 mlx5e_decompress_cqes_start(rq, cq, 1061 budget - work_done); 1062 continue; 1063 } 1064 1065 mlx5_cqwq_pop(&cq->wq); 1066 1067 rq->handle_rx_cqe(rq, cqe); 1068 } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq))); 1069 1070 if (xdpsq->db.doorbell) { 1071 mlx5e_xmit_xdp_doorbell(xdpsq); 1072 xdpsq->db.doorbell = false; 1073 } 1074 1075 mlx5_cqwq_update_db_record(&cq->wq); 1076 1077 /* ensure cq space is freed before enabling more cqes */ 1078 wmb(); 1079 1080 return work_done; 1081 } 1082 1083 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq) 1084 { 1085 struct mlx5e_xdpsq *sq; 1086 struct mlx5_cqe64 *cqe; 1087 struct mlx5e_rq *rq; 1088 u16 sqcc; 1089 int i; 1090 1091 sq = container_of(cq, struct mlx5e_xdpsq, cq); 1092 1093 if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED))) 1094 return false; 1095 1096 cqe = mlx5_cqwq_get_cqe(&cq->wq); 1097 if (!cqe) 1098 return false; 1099 1100 rq = container_of(sq, struct mlx5e_rq, xdpsq); 1101 1102 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(), 1103 * otherwise a cq overrun may occur 1104 */ 1105 sqcc = sq->cc; 1106 1107 i = 0; 1108 do { 1109 u16 wqe_counter; 1110 bool last_wqe; 1111 1112 mlx5_cqwq_pop(&cq->wq); 1113 1114 wqe_counter = be16_to_cpu(cqe->wqe_counter); 1115 1116 do { 1117 struct mlx5e_dma_info *di; 1118 u16 ci; 1119 1120 last_wqe = (sqcc == wqe_counter); 1121 1122 ci = sqcc & sq->wq.sz_m1; 1123 di = &sq->db.di[ci]; 1124 1125 sqcc++; 1126 /* Recycle RX page */ 1127 mlx5e_page_release(rq, di, true); 1128 } while (!last_wqe); 1129 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq))); 1130 1131 mlx5_cqwq_update_db_record(&cq->wq); 1132 1133 /* ensure cq space is freed before enabling more cqes */ 1134 wmb(); 1135 1136 sq->cc = sqcc; 1137 return (i == MLX5E_TX_CQ_POLL_BUDGET); 1138 } 1139 1140 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq) 1141 { 1142 struct mlx5e_rq *rq = container_of(sq, struct mlx5e_rq, xdpsq); 1143 struct mlx5e_dma_info *di; 1144 u16 ci; 1145 1146 while (sq->cc != sq->pc) { 1147 ci = sq->cc & sq->wq.sz_m1; 1148 di = &sq->db.di[ci]; 1149 sq->cc++; 1150 1151 mlx5e_page_release(rq, di, false); 1152 } 1153 } 1154 1155 #ifdef CONFIG_MLX5_CORE_IPOIB 1156 1157 #define MLX5_IB_GRH_DGID_OFFSET 24 1158 #define MLX5_GID_SIZE 16 1159 1160 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq, 1161 struct mlx5_cqe64 *cqe, 1162 u32 cqe_bcnt, 1163 struct sk_buff *skb) 1164 { 1165 struct net_device *netdev = rq->netdev; 1166 struct mlx5e_tstamp *tstamp = rq->tstamp; 1167 char *pseudo_header; 1168 u8 *dgid; 1169 u8 g; 1170 1171 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3; 1172 dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET; 1173 if ((!g) || dgid[0] != 0xff) 1174 skb->pkt_type = PACKET_HOST; 1175 else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0) 1176 skb->pkt_type = PACKET_BROADCAST; 1177 else 1178 skb->pkt_type = PACKET_MULTICAST; 1179 1180 /* TODO: IB/ipoib: Allow mcast packets from other VFs 1181 * 68996a6e760e5c74654723eeb57bf65628ae87f4 1182 */ 1183 1184 skb_pull(skb, MLX5_IB_GRH_BYTES); 1185 1186 skb->protocol = *((__be16 *)(skb->data)); 1187 1188 skb->ip_summed = CHECKSUM_COMPLETE; 1189 skb->csum = csum_unfold((__force __sum16)cqe->check_sum); 1190 1191 if (unlikely(mlx5e_rx_hw_stamp(tstamp))) 1192 mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb)); 1193 1194 skb_record_rx_queue(skb, rq->ix); 1195 1196 if (likely(netdev->features & NETIF_F_RXHASH)) 1197 mlx5e_skb_set_hash(cqe, skb); 1198 1199 /* 20 bytes of ipoib header and 4 for encap existing */ 1200 pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN); 1201 memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN); 1202 skb_reset_mac_header(skb); 1203 skb_pull(skb, MLX5_IPOIB_HARD_LEN); 1204 1205 skb->dev = netdev; 1206 1207 rq->stats.csum_complete++; 1208 rq->stats.packets++; 1209 rq->stats.bytes += cqe_bcnt; 1210 } 1211 1212 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1213 { 1214 struct mlx5e_wqe_frag_info *wi; 1215 struct mlx5e_rx_wqe *wqe; 1216 __be16 wqe_counter_be; 1217 struct sk_buff *skb; 1218 u16 wqe_counter; 1219 u32 cqe_bcnt; 1220 1221 wqe_counter_be = cqe->wqe_counter; 1222 wqe_counter = be16_to_cpu(wqe_counter_be); 1223 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 1224 wi = &rq->wqe.frag_info[wqe_counter]; 1225 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 1226 1227 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 1228 if (!skb) 1229 goto wq_free_wqe; 1230 1231 mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1232 napi_gro_receive(rq->cq.napi, skb); 1233 1234 wq_free_wqe: 1235 mlx5e_free_rx_wqe_reuse(rq, wi); 1236 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 1237 &wqe->next.next_wqe_index); 1238 } 1239 1240 #endif /* CONFIG_MLX5_CORE_IPOIB */ 1241 1242 #ifdef CONFIG_MLX5_EN_IPSEC 1243 1244 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1245 { 1246 struct mlx5e_wqe_frag_info *wi; 1247 struct mlx5e_rx_wqe *wqe; 1248 __be16 wqe_counter_be; 1249 struct sk_buff *skb; 1250 u16 wqe_counter; 1251 u32 cqe_bcnt; 1252 1253 wqe_counter_be = cqe->wqe_counter; 1254 wqe_counter = be16_to_cpu(wqe_counter_be); 1255 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 1256 wi = &rq->wqe.frag_info[wqe_counter]; 1257 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 1258 1259 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 1260 if (unlikely(!skb)) { 1261 /* a DROP, save the page-reuse checks */ 1262 mlx5e_free_rx_wqe(rq, wi); 1263 goto wq_ll_pop; 1264 } 1265 skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb); 1266 if (unlikely(!skb)) { 1267 mlx5e_free_rx_wqe(rq, wi); 1268 goto wq_ll_pop; 1269 } 1270 1271 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1272 napi_gro_receive(rq->cq.napi, skb); 1273 1274 mlx5e_free_rx_wqe_reuse(rq, wi); 1275 wq_ll_pop: 1276 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 1277 &wqe->next.next_wqe_index); 1278 } 1279 1280 #endif /* CONFIG_MLX5_EN_IPSEC */ 1281