1 /* 2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/ip.h> 34 #include <linux/ipv6.h> 35 #include <linux/tcp.h> 36 #include <net/busy_poll.h> 37 #include "en.h" 38 #include "en_tc.h" 39 40 static inline bool mlx5e_rx_hw_stamp(struct mlx5e_tstamp *tstamp) 41 { 42 return tstamp->hwtstamp_config.rx_filter == HWTSTAMP_FILTER_ALL; 43 } 44 45 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc, 46 void *data) 47 { 48 u32 ci = cqcc & cq->wq.sz_m1; 49 50 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64)); 51 } 52 53 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq, 54 struct mlx5e_cq *cq, u32 cqcc) 55 { 56 mlx5e_read_cqe_slot(cq, cqcc, &cq->title); 57 cq->decmprs_left = be32_to_cpu(cq->title.byte_cnt); 58 cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter); 59 rq->stats.cqe_compress_blks++; 60 } 61 62 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc) 63 { 64 mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr); 65 cq->mini_arr_idx = 0; 66 } 67 68 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n) 69 { 70 u8 op_own = (cqcc >> cq->wq.log_sz) & 1; 71 u32 wq_sz = 1 << cq->wq.log_sz; 72 u32 ci = cqcc & cq->wq.sz_m1; 73 u32 ci_top = min_t(u32, wq_sz, ci + n); 74 75 for (; ci < ci_top; ci++, n--) { 76 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci); 77 78 cqe->op_own = op_own; 79 } 80 81 if (unlikely(ci == wq_sz)) { 82 op_own = !op_own; 83 for (ci = 0; ci < n; ci++) { 84 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci); 85 86 cqe->op_own = op_own; 87 } 88 } 89 } 90 91 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq, 92 struct mlx5e_cq *cq, u32 cqcc) 93 { 94 u16 wqe_cnt_step; 95 96 cq->title.byte_cnt = cq->mini_arr[cq->mini_arr_idx].byte_cnt; 97 cq->title.check_sum = cq->mini_arr[cq->mini_arr_idx].checksum; 98 cq->title.op_own &= 0xf0; 99 cq->title.op_own |= 0x01 & (cqcc >> cq->wq.log_sz); 100 cq->title.wqe_counter = cpu_to_be16(cq->decmprs_wqe_counter); 101 102 wqe_cnt_step = 103 rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ? 104 mpwrq_get_cqe_consumed_strides(&cq->title) : 1; 105 cq->decmprs_wqe_counter = 106 (cq->decmprs_wqe_counter + wqe_cnt_step) & rq->wq.sz_m1; 107 } 108 109 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq, 110 struct mlx5e_cq *cq, u32 cqcc) 111 { 112 mlx5e_decompress_cqe(rq, cq, cqcc); 113 cq->title.rss_hash_type = 0; 114 cq->title.rss_hash_result = 0; 115 } 116 117 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq, 118 struct mlx5e_cq *cq, 119 int update_owner_only, 120 int budget_rem) 121 { 122 u32 cqcc = cq->wq.cc + update_owner_only; 123 u32 cqe_count; 124 u32 i; 125 126 cqe_count = min_t(u32, cq->decmprs_left, budget_rem); 127 128 for (i = update_owner_only; i < cqe_count; 129 i++, cq->mini_arr_idx++, cqcc++) { 130 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE) 131 mlx5e_read_mini_arr_slot(cq, cqcc); 132 133 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc); 134 rq->handle_rx_cqe(rq, &cq->title); 135 } 136 mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc); 137 cq->wq.cc = cqcc; 138 cq->decmprs_left -= cqe_count; 139 rq->stats.cqe_compress_pkts += cqe_count; 140 141 return cqe_count; 142 } 143 144 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq, 145 struct mlx5e_cq *cq, 146 int budget_rem) 147 { 148 mlx5e_read_title_slot(rq, cq, cq->wq.cc); 149 mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1); 150 mlx5e_decompress_cqe(rq, cq, cq->wq.cc); 151 rq->handle_rx_cqe(rq, &cq->title); 152 cq->mini_arr_idx++; 153 154 return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1; 155 } 156 157 void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val) 158 { 159 bool was_opened; 160 161 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression)) 162 return; 163 164 mutex_lock(&priv->state_lock); 165 166 if (priv->params.rx_cqe_compress == val) 167 goto unlock; 168 169 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 170 if (was_opened) 171 mlx5e_close_locked(priv->netdev); 172 173 priv->params.rx_cqe_compress = val; 174 175 if (was_opened) 176 mlx5e_open_locked(priv->netdev); 177 178 unlock: 179 mutex_unlock(&priv->state_lock); 180 } 181 182 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix) 183 { 184 struct sk_buff *skb; 185 dma_addr_t dma_addr; 186 187 skb = napi_alloc_skb(rq->cq.napi, rq->wqe_sz); 188 if (unlikely(!skb)) 189 return -ENOMEM; 190 191 dma_addr = dma_map_single(rq->pdev, 192 /* hw start padding */ 193 skb->data, 194 /* hw end padding */ 195 rq->wqe_sz, 196 DMA_FROM_DEVICE); 197 198 if (unlikely(dma_mapping_error(rq->pdev, dma_addr))) 199 goto err_free_skb; 200 201 *((dma_addr_t *)skb->cb) = dma_addr; 202 wqe->data.addr = cpu_to_be64(dma_addr); 203 204 rq->skb[ix] = skb; 205 206 return 0; 207 208 err_free_skb: 209 dev_kfree_skb(skb); 210 211 return -ENOMEM; 212 } 213 214 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix) 215 { 216 struct sk_buff *skb = rq->skb[ix]; 217 218 if (skb) { 219 rq->skb[ix] = NULL; 220 dma_unmap_single(rq->pdev, 221 *((dma_addr_t *)skb->cb), 222 rq->wqe_sz, 223 DMA_FROM_DEVICE); 224 dev_kfree_skb(skb); 225 } 226 } 227 228 static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq) 229 { 230 return rq->mpwqe_num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER; 231 } 232 233 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq, 234 struct sk_buff *skb, 235 struct mlx5e_mpw_info *wi, 236 u32 page_idx, u32 frag_offset, 237 u32 len) 238 { 239 unsigned int truesize = ALIGN(len, rq->mpwqe_stride_sz); 240 241 dma_sync_single_for_cpu(rq->pdev, 242 wi->umr.dma_info[page_idx].addr + frag_offset, 243 len, DMA_FROM_DEVICE); 244 wi->skbs_frags[page_idx]++; 245 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 246 wi->umr.dma_info[page_idx].page, frag_offset, 247 len, truesize); 248 } 249 250 static inline void 251 mlx5e_copy_skb_header_mpwqe(struct device *pdev, 252 struct sk_buff *skb, 253 struct mlx5e_mpw_info *wi, 254 u32 page_idx, u32 offset, 255 u32 headlen) 256 { 257 u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset); 258 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx]; 259 unsigned int len; 260 261 /* Aligning len to sizeof(long) optimizes memcpy performance */ 262 len = ALIGN(headlen_pg, sizeof(long)); 263 dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len, 264 DMA_FROM_DEVICE); 265 skb_copy_to_linear_data_offset(skb, 0, 266 page_address(dma_info->page) + offset, 267 len); 268 if (unlikely(offset + headlen > PAGE_SIZE)) { 269 dma_info++; 270 headlen_pg = len; 271 len = ALIGN(headlen - headlen_pg, sizeof(long)); 272 dma_sync_single_for_cpu(pdev, dma_info->addr, len, 273 DMA_FROM_DEVICE); 274 skb_copy_to_linear_data_offset(skb, headlen_pg, 275 page_address(dma_info->page), 276 len); 277 } 278 } 279 280 static inline void mlx5e_post_umr_wqe(struct mlx5e_rq *rq, u16 ix) 281 { 282 struct mlx5e_mpw_info *wi = &rq->wqe_info[ix]; 283 struct mlx5e_sq *sq = &rq->channel->icosq; 284 struct mlx5_wq_cyc *wq = &sq->wq; 285 struct mlx5e_umr_wqe *wqe; 286 u8 num_wqebbs = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_BB); 287 u16 pi; 288 289 /* fill sq edge with nops to avoid wqe wrap around */ 290 while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) { 291 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_NOP; 292 sq->ico_wqe_info[pi].num_wqebbs = 1; 293 mlx5e_send_nop(sq, true); 294 } 295 296 wqe = mlx5_wq_cyc_get_wqe(wq, pi); 297 memcpy(wqe, &wi->umr.wqe, sizeof(*wqe)); 298 wqe->ctrl.opmod_idx_opcode = 299 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) | 300 MLX5_OPCODE_UMR); 301 302 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_UMR; 303 sq->ico_wqe_info[pi].num_wqebbs = num_wqebbs; 304 sq->pc += num_wqebbs; 305 mlx5e_tx_notify_hw(sq, &wqe->ctrl, 0); 306 } 307 308 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq, 309 struct mlx5e_dma_info *dma_info) 310 { 311 struct mlx5e_page_cache *cache = &rq->page_cache; 312 u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1); 313 314 if (tail_next == cache->head) { 315 rq->stats.cache_full++; 316 return false; 317 } 318 319 cache->page_cache[cache->tail] = *dma_info; 320 cache->tail = tail_next; 321 return true; 322 } 323 324 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq, 325 struct mlx5e_dma_info *dma_info) 326 { 327 struct mlx5e_page_cache *cache = &rq->page_cache; 328 329 if (unlikely(cache->head == cache->tail)) { 330 rq->stats.cache_empty++; 331 return false; 332 } 333 334 if (page_ref_count(cache->page_cache[cache->head].page) != 1) { 335 rq->stats.cache_busy++; 336 return false; 337 } 338 339 *dma_info = cache->page_cache[cache->head]; 340 cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1); 341 rq->stats.cache_reuse++; 342 343 dma_sync_single_for_device(rq->pdev, dma_info->addr, PAGE_SIZE, 344 DMA_FROM_DEVICE); 345 return true; 346 } 347 348 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq, 349 struct mlx5e_dma_info *dma_info) 350 { 351 struct page *page; 352 353 if (mlx5e_rx_cache_get(rq, dma_info)) 354 return 0; 355 356 page = dev_alloc_page(); 357 if (unlikely(!page)) 358 return -ENOMEM; 359 360 dma_info->page = page; 361 dma_info->addr = dma_map_page(rq->pdev, page, 0, PAGE_SIZE, 362 DMA_FROM_DEVICE); 363 if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) { 364 put_page(page); 365 return -ENOMEM; 366 } 367 368 return 0; 369 } 370 371 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info, 372 bool recycle) 373 { 374 if (likely(recycle) && mlx5e_rx_cache_put(rq, dma_info)) 375 return; 376 377 dma_unmap_page(rq->pdev, dma_info->addr, PAGE_SIZE, DMA_FROM_DEVICE); 378 put_page(dma_info->page); 379 } 380 381 static int mlx5e_alloc_rx_umr_mpwqe(struct mlx5e_rq *rq, 382 struct mlx5e_rx_wqe *wqe, 383 u16 ix) 384 { 385 struct mlx5e_mpw_info *wi = &rq->wqe_info[ix]; 386 u64 dma_offset = (u64)mlx5e_get_wqe_mtt_offset(rq, ix) << PAGE_SHIFT; 387 int pg_strides = mlx5e_mpwqe_strides_per_page(rq); 388 int err; 389 int i; 390 391 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) { 392 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[i]; 393 394 err = mlx5e_page_alloc_mapped(rq, dma_info); 395 if (unlikely(err)) 396 goto err_unmap; 397 wi->umr.mtt[i] = cpu_to_be64(dma_info->addr | MLX5_EN_WR); 398 page_ref_add(dma_info->page, pg_strides); 399 wi->skbs_frags[i] = 0; 400 } 401 402 wi->consumed_strides = 0; 403 wqe->data.addr = cpu_to_be64(dma_offset); 404 405 return 0; 406 407 err_unmap: 408 while (--i >= 0) { 409 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[i]; 410 411 page_ref_sub(dma_info->page, pg_strides); 412 mlx5e_page_release(rq, dma_info, true); 413 } 414 415 return err; 416 } 417 418 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi) 419 { 420 int pg_strides = mlx5e_mpwqe_strides_per_page(rq); 421 int i; 422 423 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) { 424 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[i]; 425 426 page_ref_sub(dma_info->page, pg_strides - wi->skbs_frags[i]); 427 mlx5e_page_release(rq, dma_info, true); 428 } 429 } 430 431 void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq) 432 { 433 struct mlx5_wq_ll *wq = &rq->wq; 434 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); 435 436 clear_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state); 437 438 if (unlikely(test_bit(MLX5E_RQ_STATE_FLUSH, &rq->state))) { 439 mlx5e_free_rx_mpwqe(rq, &rq->wqe_info[wq->head]); 440 return; 441 } 442 443 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); 444 445 /* ensure wqes are visible to device before updating doorbell record */ 446 dma_wmb(); 447 448 mlx5_wq_ll_update_db_record(wq); 449 } 450 451 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix) 452 { 453 int err; 454 455 err = mlx5e_alloc_rx_umr_mpwqe(rq, wqe, ix); 456 if (unlikely(err)) 457 return err; 458 set_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state); 459 mlx5e_post_umr_wqe(rq, ix); 460 return -EBUSY; 461 } 462 463 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) 464 { 465 struct mlx5e_mpw_info *wi = &rq->wqe_info[ix]; 466 467 mlx5e_free_rx_mpwqe(rq, wi); 468 } 469 470 #define RQ_CANNOT_POST(rq) \ 471 (test_bit(MLX5E_RQ_STATE_FLUSH, &rq->state) || \ 472 test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state)) 473 474 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq) 475 { 476 struct mlx5_wq_ll *wq = &rq->wq; 477 478 if (unlikely(RQ_CANNOT_POST(rq))) 479 return false; 480 481 while (!mlx5_wq_ll_is_full(wq)) { 482 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); 483 int err; 484 485 err = rq->alloc_wqe(rq, wqe, wq->head); 486 if (err == -EBUSY) 487 return true; 488 if (unlikely(err)) { 489 rq->stats.buff_alloc_err++; 490 break; 491 } 492 493 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); 494 } 495 496 /* ensure wqes are visible to device before updating doorbell record */ 497 dma_wmb(); 498 499 mlx5_wq_ll_update_db_record(wq); 500 501 return !mlx5_wq_ll_is_full(wq); 502 } 503 504 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe, 505 u32 cqe_bcnt) 506 { 507 struct ethhdr *eth = (struct ethhdr *)(skb->data); 508 struct iphdr *ipv4; 509 struct ipv6hdr *ipv6; 510 struct tcphdr *tcp; 511 int network_depth = 0; 512 __be16 proto; 513 u16 tot_len; 514 515 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe); 516 int tcp_ack = ((CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA == l4_hdr_type) || 517 (CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA == l4_hdr_type)); 518 519 skb->mac_len = ETH_HLEN; 520 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth); 521 522 ipv4 = (struct iphdr *)(skb->data + network_depth); 523 ipv6 = (struct ipv6hdr *)(skb->data + network_depth); 524 tot_len = cqe_bcnt - network_depth; 525 526 if (proto == htons(ETH_P_IP)) { 527 tcp = (struct tcphdr *)(skb->data + network_depth + 528 sizeof(struct iphdr)); 529 ipv6 = NULL; 530 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 531 } else { 532 tcp = (struct tcphdr *)(skb->data + network_depth + 533 sizeof(struct ipv6hdr)); 534 ipv4 = NULL; 535 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 536 } 537 538 if (get_cqe_lro_tcppsh(cqe)) 539 tcp->psh = 1; 540 541 if (tcp_ack) { 542 tcp->ack = 1; 543 tcp->ack_seq = cqe->lro_ack_seq_num; 544 tcp->window = cqe->lro_tcp_win; 545 } 546 547 if (ipv4) { 548 ipv4->ttl = cqe->lro_min_ttl; 549 ipv4->tot_len = cpu_to_be16(tot_len); 550 ipv4->check = 0; 551 ipv4->check = ip_fast_csum((unsigned char *)ipv4, 552 ipv4->ihl); 553 } else { 554 ipv6->hop_limit = cqe->lro_min_ttl; 555 ipv6->payload_len = cpu_to_be16(tot_len - 556 sizeof(struct ipv6hdr)); 557 } 558 } 559 560 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe, 561 struct sk_buff *skb) 562 { 563 u8 cht = cqe->rss_hash_type; 564 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 : 565 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 : 566 PKT_HASH_TYPE_NONE; 567 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht); 568 } 569 570 static inline bool is_first_ethertype_ip(struct sk_buff *skb) 571 { 572 __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto; 573 574 return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6)); 575 } 576 577 static inline void mlx5e_handle_csum(struct net_device *netdev, 578 struct mlx5_cqe64 *cqe, 579 struct mlx5e_rq *rq, 580 struct sk_buff *skb, 581 bool lro) 582 { 583 if (unlikely(!(netdev->features & NETIF_F_RXCSUM))) 584 goto csum_none; 585 586 if (lro) { 587 skb->ip_summed = CHECKSUM_UNNECESSARY; 588 return; 589 } 590 591 if (is_first_ethertype_ip(skb)) { 592 skb->ip_summed = CHECKSUM_COMPLETE; 593 skb->csum = csum_unfold((__force __sum16)cqe->check_sum); 594 rq->stats.csum_complete++; 595 return; 596 } 597 598 if (likely((cqe->hds_ip_ext & CQE_L3_OK) && 599 (cqe->hds_ip_ext & CQE_L4_OK))) { 600 skb->ip_summed = CHECKSUM_UNNECESSARY; 601 if (cqe_is_tunneled(cqe)) { 602 skb->csum_level = 1; 603 skb->encapsulation = 1; 604 rq->stats.csum_unnecessary_inner++; 605 } 606 return; 607 } 608 csum_none: 609 skb->ip_summed = CHECKSUM_NONE; 610 rq->stats.csum_none++; 611 } 612 613 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe, 614 u32 cqe_bcnt, 615 struct mlx5e_rq *rq, 616 struct sk_buff *skb) 617 { 618 struct net_device *netdev = rq->netdev; 619 struct mlx5e_tstamp *tstamp = rq->tstamp; 620 int lro_num_seg; 621 622 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24; 623 if (lro_num_seg > 1) { 624 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt); 625 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg); 626 rq->stats.lro_packets++; 627 rq->stats.lro_bytes += cqe_bcnt; 628 } 629 630 if (unlikely(mlx5e_rx_hw_stamp(tstamp))) 631 mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb)); 632 633 skb_record_rx_queue(skb, rq->ix); 634 635 if (likely(netdev->features & NETIF_F_RXHASH)) 636 mlx5e_skb_set_hash(cqe, skb); 637 638 if (cqe_has_vlan(cqe)) 639 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 640 be16_to_cpu(cqe->vlan_info)); 641 642 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK; 643 644 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg); 645 skb->protocol = eth_type_trans(skb, netdev); 646 } 647 648 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq, 649 struct mlx5_cqe64 *cqe, 650 u32 cqe_bcnt, 651 struct sk_buff *skb) 652 { 653 rq->stats.packets++; 654 rq->stats.bytes += cqe_bcnt; 655 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb); 656 napi_gro_receive(rq->cq.napi, skb); 657 } 658 659 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 660 { 661 struct mlx5e_rx_wqe *wqe; 662 struct sk_buff *skb; 663 __be16 wqe_counter_be; 664 u16 wqe_counter; 665 u32 cqe_bcnt; 666 667 wqe_counter_be = cqe->wqe_counter; 668 wqe_counter = be16_to_cpu(wqe_counter_be); 669 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 670 skb = rq->skb[wqe_counter]; 671 prefetch(skb->data); 672 rq->skb[wqe_counter] = NULL; 673 674 dma_unmap_single(rq->pdev, 675 *((dma_addr_t *)skb->cb), 676 rq->wqe_sz, 677 DMA_FROM_DEVICE); 678 679 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { 680 rq->stats.wqe_err++; 681 dev_kfree_skb(skb); 682 goto wq_ll_pop; 683 } 684 685 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 686 skb_put(skb, cqe_bcnt); 687 688 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 689 690 wq_ll_pop: 691 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 692 &wqe->next.next_wqe_index); 693 } 694 695 static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq, 696 struct mlx5_cqe64 *cqe, 697 struct mlx5e_mpw_info *wi, 698 u32 cqe_bcnt, 699 struct sk_buff *skb) 700 { 701 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe); 702 u32 wqe_offset = stride_ix * rq->mpwqe_stride_sz; 703 u32 head_offset = wqe_offset & (PAGE_SIZE - 1); 704 u32 page_idx = wqe_offset >> PAGE_SHIFT; 705 u32 head_page_idx = page_idx; 706 u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt); 707 u32 frag_offset = head_offset + headlen; 708 u16 byte_cnt = cqe_bcnt - headlen; 709 710 if (unlikely(frag_offset >= PAGE_SIZE)) { 711 page_idx++; 712 frag_offset -= PAGE_SIZE; 713 } 714 715 while (byte_cnt) { 716 u32 pg_consumed_bytes = 717 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt); 718 719 mlx5e_add_skb_frag_mpwqe(rq, skb, wi, page_idx, frag_offset, 720 pg_consumed_bytes); 721 byte_cnt -= pg_consumed_bytes; 722 frag_offset = 0; 723 page_idx++; 724 } 725 /* copy header */ 726 mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, wi, head_page_idx, 727 head_offset, headlen); 728 /* skb linear part was allocated with headlen and aligned to long */ 729 skb->tail += headlen; 730 skb->len += headlen; 731 } 732 733 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 734 { 735 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe); 736 u16 wqe_id = be16_to_cpu(cqe->wqe_id); 737 struct mlx5e_mpw_info *wi = &rq->wqe_info[wqe_id]; 738 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id); 739 struct sk_buff *skb; 740 u16 cqe_bcnt; 741 742 wi->consumed_strides += cstrides; 743 744 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { 745 rq->stats.wqe_err++; 746 goto mpwrq_cqe_out; 747 } 748 749 if (unlikely(mpwrq_is_filler_cqe(cqe))) { 750 rq->stats.mpwqe_filler++; 751 goto mpwrq_cqe_out; 752 } 753 754 skb = napi_alloc_skb(rq->cq.napi, 755 ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, 756 sizeof(long))); 757 if (unlikely(!skb)) { 758 rq->stats.buff_alloc_err++; 759 goto mpwrq_cqe_out; 760 } 761 762 prefetch(skb->data); 763 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe); 764 765 mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb); 766 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 767 768 mpwrq_cqe_out: 769 if (likely(wi->consumed_strides < rq->mpwqe_num_strides)) 770 return; 771 772 mlx5e_free_rx_mpwqe(rq, wi); 773 mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index); 774 } 775 776 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget) 777 { 778 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq); 779 int work_done = 0; 780 781 if (unlikely(test_bit(MLX5E_RQ_STATE_FLUSH, &rq->state))) 782 return 0; 783 784 if (cq->decmprs_left) 785 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget); 786 787 for (; work_done < budget; work_done++) { 788 struct mlx5_cqe64 *cqe = mlx5e_get_cqe(cq); 789 790 if (!cqe) 791 break; 792 793 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) { 794 work_done += 795 mlx5e_decompress_cqes_start(rq, cq, 796 budget - work_done); 797 continue; 798 } 799 800 mlx5_cqwq_pop(&cq->wq); 801 802 rq->handle_rx_cqe(rq, cqe); 803 } 804 805 mlx5_cqwq_update_db_record(&cq->wq); 806 807 /* ensure cq space is freed before enabling more cqes */ 808 wmb(); 809 810 return work_done; 811 } 812