1 /* 2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/prefetch.h> 34 #include <linux/ip.h> 35 #include <linux/ipv6.h> 36 #include <linux/tcp.h> 37 #include <linux/bpf_trace.h> 38 #include <net/busy_poll.h> 39 #include "en.h" 40 #include "en_tc.h" 41 #include "eswitch.h" 42 #include "en_rep.h" 43 #include "ipoib/ipoib.h" 44 #include "en_accel/ipsec_rxtx.h" 45 46 static inline bool mlx5e_rx_hw_stamp(struct mlx5e_tstamp *tstamp) 47 { 48 return tstamp->hwtstamp_config.rx_filter == HWTSTAMP_FILTER_ALL; 49 } 50 51 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc, 52 void *data) 53 { 54 u32 ci = cqcc & cq->wq.sz_m1; 55 56 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64)); 57 } 58 59 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq, 60 struct mlx5e_cq *cq, u32 cqcc) 61 { 62 mlx5e_read_cqe_slot(cq, cqcc, &cq->title); 63 cq->decmprs_left = be32_to_cpu(cq->title.byte_cnt); 64 cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter); 65 rq->stats.cqe_compress_blks++; 66 } 67 68 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc) 69 { 70 mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr); 71 cq->mini_arr_idx = 0; 72 } 73 74 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n) 75 { 76 u8 op_own = (cqcc >> cq->wq.log_sz) & 1; 77 u32 wq_sz = 1 << cq->wq.log_sz; 78 u32 ci = cqcc & cq->wq.sz_m1; 79 u32 ci_top = min_t(u32, wq_sz, ci + n); 80 81 for (; ci < ci_top; ci++, n--) { 82 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci); 83 84 cqe->op_own = op_own; 85 } 86 87 if (unlikely(ci == wq_sz)) { 88 op_own = !op_own; 89 for (ci = 0; ci < n; ci++) { 90 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci); 91 92 cqe->op_own = op_own; 93 } 94 } 95 } 96 97 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq, 98 struct mlx5e_cq *cq, u32 cqcc) 99 { 100 cq->title.byte_cnt = cq->mini_arr[cq->mini_arr_idx].byte_cnt; 101 cq->title.check_sum = cq->mini_arr[cq->mini_arr_idx].checksum; 102 cq->title.op_own &= 0xf0; 103 cq->title.op_own |= 0x01 & (cqcc >> cq->wq.log_sz); 104 cq->title.wqe_counter = cpu_to_be16(cq->decmprs_wqe_counter); 105 106 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) 107 cq->decmprs_wqe_counter += 108 mpwrq_get_cqe_consumed_strides(&cq->title); 109 else 110 cq->decmprs_wqe_counter = 111 (cq->decmprs_wqe_counter + 1) & rq->wq.sz_m1; 112 } 113 114 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq, 115 struct mlx5e_cq *cq, u32 cqcc) 116 { 117 mlx5e_decompress_cqe(rq, cq, cqcc); 118 cq->title.rss_hash_type = 0; 119 cq->title.rss_hash_result = 0; 120 } 121 122 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq, 123 struct mlx5e_cq *cq, 124 int update_owner_only, 125 int budget_rem) 126 { 127 u32 cqcc = cq->wq.cc + update_owner_only; 128 u32 cqe_count; 129 u32 i; 130 131 cqe_count = min_t(u32, cq->decmprs_left, budget_rem); 132 133 for (i = update_owner_only; i < cqe_count; 134 i++, cq->mini_arr_idx++, cqcc++) { 135 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE) 136 mlx5e_read_mini_arr_slot(cq, cqcc); 137 138 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc); 139 rq->handle_rx_cqe(rq, &cq->title); 140 } 141 mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc); 142 cq->wq.cc = cqcc; 143 cq->decmprs_left -= cqe_count; 144 rq->stats.cqe_compress_pkts += cqe_count; 145 146 return cqe_count; 147 } 148 149 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq, 150 struct mlx5e_cq *cq, 151 int budget_rem) 152 { 153 mlx5e_read_title_slot(rq, cq, cq->wq.cc); 154 mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1); 155 mlx5e_decompress_cqe(rq, cq, cq->wq.cc); 156 rq->handle_rx_cqe(rq, &cq->title); 157 cq->mini_arr_idx++; 158 159 return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1; 160 } 161 162 #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT) 163 164 static inline bool mlx5e_page_is_reserved(struct page *page) 165 { 166 return page_is_pfmemalloc(page) || page_to_nid(page) != numa_node_id(); 167 } 168 169 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq, 170 struct mlx5e_dma_info *dma_info) 171 { 172 struct mlx5e_page_cache *cache = &rq->page_cache; 173 u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1); 174 175 if (tail_next == cache->head) { 176 rq->stats.cache_full++; 177 return false; 178 } 179 180 if (unlikely(page_is_pfmemalloc(dma_info->page))) 181 return false; 182 183 cache->page_cache[cache->tail] = *dma_info; 184 cache->tail = tail_next; 185 return true; 186 } 187 188 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq, 189 struct mlx5e_dma_info *dma_info) 190 { 191 struct mlx5e_page_cache *cache = &rq->page_cache; 192 193 if (unlikely(cache->head == cache->tail)) { 194 rq->stats.cache_empty++; 195 return false; 196 } 197 198 if (page_ref_count(cache->page_cache[cache->head].page) != 1) { 199 rq->stats.cache_busy++; 200 return false; 201 } 202 203 *dma_info = cache->page_cache[cache->head]; 204 cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1); 205 rq->stats.cache_reuse++; 206 207 dma_sync_single_for_device(rq->pdev, dma_info->addr, 208 RQ_PAGE_SIZE(rq), 209 DMA_FROM_DEVICE); 210 return true; 211 } 212 213 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq, 214 struct mlx5e_dma_info *dma_info) 215 { 216 struct page *page; 217 218 if (mlx5e_rx_cache_get(rq, dma_info)) 219 return 0; 220 221 page = dev_alloc_pages(rq->buff.page_order); 222 if (unlikely(!page)) 223 return -ENOMEM; 224 225 dma_info->addr = dma_map_page(rq->pdev, page, 0, 226 RQ_PAGE_SIZE(rq), rq->buff.map_dir); 227 if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) { 228 put_page(page); 229 return -ENOMEM; 230 } 231 dma_info->page = page; 232 233 return 0; 234 } 235 236 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info, 237 bool recycle) 238 { 239 if (likely(recycle) && mlx5e_rx_cache_put(rq, dma_info)) 240 return; 241 242 dma_unmap_page(rq->pdev, dma_info->addr, RQ_PAGE_SIZE(rq), 243 rq->buff.map_dir); 244 put_page(dma_info->page); 245 } 246 247 static inline bool mlx5e_page_reuse(struct mlx5e_rq *rq, 248 struct mlx5e_wqe_frag_info *wi) 249 { 250 return rq->wqe.page_reuse && wi->di.page && 251 (wi->offset + rq->wqe.frag_sz <= RQ_PAGE_SIZE(rq)) && 252 !mlx5e_page_is_reserved(wi->di.page); 253 } 254 255 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix) 256 { 257 struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix]; 258 259 /* check if page exists, hence can be reused */ 260 if (!wi->di.page) { 261 if (unlikely(mlx5e_page_alloc_mapped(rq, &wi->di))) 262 return -ENOMEM; 263 wi->offset = 0; 264 } 265 266 wqe->data.addr = cpu_to_be64(wi->di.addr + wi->offset + rq->buff.headroom); 267 return 0; 268 } 269 270 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq, 271 struct mlx5e_wqe_frag_info *wi) 272 { 273 mlx5e_page_release(rq, &wi->di, true); 274 wi->di.page = NULL; 275 } 276 277 static inline void mlx5e_free_rx_wqe_reuse(struct mlx5e_rq *rq, 278 struct mlx5e_wqe_frag_info *wi) 279 { 280 if (mlx5e_page_reuse(rq, wi)) { 281 rq->stats.page_reuse++; 282 return; 283 } 284 285 mlx5e_free_rx_wqe(rq, wi); 286 } 287 288 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix) 289 { 290 struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix]; 291 292 if (wi->di.page) 293 mlx5e_free_rx_wqe(rq, wi); 294 } 295 296 static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq) 297 { 298 return rq->mpwqe.num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER; 299 } 300 301 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq, 302 struct sk_buff *skb, 303 struct mlx5e_mpw_info *wi, 304 u32 page_idx, u32 frag_offset, 305 u32 len) 306 { 307 unsigned int truesize = ALIGN(len, BIT(rq->mpwqe.log_stride_sz)); 308 309 dma_sync_single_for_cpu(rq->pdev, 310 wi->umr.dma_info[page_idx].addr + frag_offset, 311 len, DMA_FROM_DEVICE); 312 wi->skbs_frags[page_idx]++; 313 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 314 wi->umr.dma_info[page_idx].page, frag_offset, 315 len, truesize); 316 } 317 318 static inline void 319 mlx5e_copy_skb_header_mpwqe(struct device *pdev, 320 struct sk_buff *skb, 321 struct mlx5e_mpw_info *wi, 322 u32 page_idx, u32 offset, 323 u32 headlen) 324 { 325 u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset); 326 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx]; 327 unsigned int len; 328 329 /* Aligning len to sizeof(long) optimizes memcpy performance */ 330 len = ALIGN(headlen_pg, sizeof(long)); 331 dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len, 332 DMA_FROM_DEVICE); 333 skb_copy_to_linear_data_offset(skb, 0, 334 page_address(dma_info->page) + offset, 335 len); 336 if (unlikely(offset + headlen > PAGE_SIZE)) { 337 dma_info++; 338 headlen_pg = len; 339 len = ALIGN(headlen - headlen_pg, sizeof(long)); 340 dma_sync_single_for_cpu(pdev, dma_info->addr, len, 341 DMA_FROM_DEVICE); 342 skb_copy_to_linear_data_offset(skb, headlen_pg, 343 page_address(dma_info->page), 344 len); 345 } 346 } 347 348 static inline void mlx5e_post_umr_wqe(struct mlx5e_rq *rq, u16 ix) 349 { 350 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 351 struct mlx5e_icosq *sq = &rq->channel->icosq; 352 struct mlx5_wq_cyc *wq = &sq->wq; 353 struct mlx5e_umr_wqe *wqe; 354 u8 num_wqebbs = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_BB); 355 u16 pi; 356 357 /* fill sq edge with nops to avoid wqe wrap around */ 358 while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) { 359 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP; 360 mlx5e_post_nop(wq, sq->sqn, &sq->pc); 361 } 362 363 wqe = mlx5_wq_cyc_get_wqe(wq, pi); 364 memcpy(wqe, &wi->umr.wqe, sizeof(*wqe)); 365 wqe->ctrl.opmod_idx_opcode = 366 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) | 367 MLX5_OPCODE_UMR); 368 369 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR; 370 sq->pc += num_wqebbs; 371 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &wqe->ctrl); 372 } 373 374 static int mlx5e_alloc_rx_umr_mpwqe(struct mlx5e_rq *rq, 375 u16 ix) 376 { 377 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 378 int pg_strides = mlx5e_mpwqe_strides_per_page(rq); 379 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0]; 380 int err; 381 int i; 382 383 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) { 384 err = mlx5e_page_alloc_mapped(rq, dma_info); 385 if (unlikely(err)) 386 goto err_unmap; 387 wi->umr.mtt[i] = cpu_to_be64(dma_info->addr | MLX5_EN_WR); 388 page_ref_add(dma_info->page, pg_strides); 389 } 390 391 memset(wi->skbs_frags, 0, sizeof(*wi->skbs_frags) * MLX5_MPWRQ_PAGES_PER_WQE); 392 wi->consumed_strides = 0; 393 394 return 0; 395 396 err_unmap: 397 while (--i >= 0) { 398 dma_info--; 399 page_ref_sub(dma_info->page, pg_strides); 400 mlx5e_page_release(rq, dma_info, true); 401 } 402 403 return err; 404 } 405 406 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi) 407 { 408 int pg_strides = mlx5e_mpwqe_strides_per_page(rq); 409 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0]; 410 int i; 411 412 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) { 413 page_ref_sub(dma_info->page, pg_strides - wi->skbs_frags[i]); 414 mlx5e_page_release(rq, dma_info, true); 415 } 416 } 417 418 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq) 419 { 420 struct mlx5_wq_ll *wq = &rq->wq; 421 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); 422 423 rq->mpwqe.umr_in_progress = false; 424 425 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); 426 427 /* ensure wqes are visible to device before updating doorbell record */ 428 dma_wmb(); 429 430 mlx5_wq_ll_update_db_record(wq); 431 } 432 433 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) 434 { 435 int err; 436 437 err = mlx5e_alloc_rx_umr_mpwqe(rq, ix); 438 if (unlikely(err)) { 439 rq->stats.buff_alloc_err++; 440 return err; 441 } 442 rq->mpwqe.umr_in_progress = true; 443 mlx5e_post_umr_wqe(rq, ix); 444 return 0; 445 } 446 447 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) 448 { 449 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 450 451 mlx5e_free_rx_mpwqe(rq, wi); 452 } 453 454 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq) 455 { 456 struct mlx5_wq_ll *wq = &rq->wq; 457 int err; 458 459 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED))) 460 return false; 461 462 if (mlx5_wq_ll_is_full(wq)) 463 return false; 464 465 do { 466 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); 467 468 err = mlx5e_alloc_rx_wqe(rq, wqe, wq->head); 469 if (unlikely(err)) { 470 rq->stats.buff_alloc_err++; 471 break; 472 } 473 474 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); 475 } while (!mlx5_wq_ll_is_full(wq)); 476 477 /* ensure wqes are visible to device before updating doorbell record */ 478 dma_wmb(); 479 480 mlx5_wq_ll_update_db_record(wq); 481 482 return !!err; 483 } 484 485 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq, 486 struct mlx5e_icosq *sq, 487 struct mlx5e_rq *rq, 488 struct mlx5_cqe64 *cqe) 489 { 490 struct mlx5_wq_cyc *wq = &sq->wq; 491 u16 ci = be16_to_cpu(cqe->wqe_counter) & wq->sz_m1; 492 struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci]; 493 494 mlx5_cqwq_pop(&cq->wq); 495 496 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) { 497 WARN_ONCE(true, "mlx5e: Bad OP in ICOSQ CQE: 0x%x\n", 498 cqe->op_own); 499 return; 500 } 501 502 if (likely(icowi->opcode == MLX5_OPCODE_UMR)) { 503 mlx5e_post_rx_mpwqe(rq); 504 return; 505 } 506 507 if (unlikely(icowi->opcode != MLX5_OPCODE_NOP)) 508 WARN_ONCE(true, 509 "mlx5e: Bad OPCODE in ICOSQ WQE info: 0x%x\n", 510 icowi->opcode); 511 } 512 513 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq) 514 { 515 struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq); 516 struct mlx5_cqe64 *cqe; 517 518 if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED))) 519 return; 520 521 cqe = mlx5_cqwq_get_cqe(&cq->wq); 522 if (likely(!cqe)) 523 return; 524 525 /* by design, there's only a single cqe */ 526 mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe); 527 528 mlx5_cqwq_update_db_record(&cq->wq); 529 } 530 531 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq) 532 { 533 struct mlx5_wq_ll *wq = &rq->wq; 534 535 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED))) 536 return false; 537 538 mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq); 539 540 if (mlx5_wq_ll_is_full(wq)) 541 return false; 542 543 if (!rq->mpwqe.umr_in_progress) 544 mlx5e_alloc_rx_mpwqe(rq, wq->head); 545 546 return true; 547 } 548 549 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe, 550 u32 cqe_bcnt) 551 { 552 struct ethhdr *eth = (struct ethhdr *)(skb->data); 553 struct tcphdr *tcp; 554 int network_depth = 0; 555 __be16 proto; 556 u16 tot_len; 557 void *ip_p; 558 559 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe); 560 u8 tcp_ack = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) || 561 (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA); 562 563 skb->mac_len = ETH_HLEN; 564 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth); 565 566 tot_len = cqe_bcnt - network_depth; 567 ip_p = skb->data + network_depth; 568 569 if (proto == htons(ETH_P_IP)) { 570 struct iphdr *ipv4 = ip_p; 571 572 tcp = ip_p + sizeof(struct iphdr); 573 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 574 575 ipv4->ttl = cqe->lro_min_ttl; 576 ipv4->tot_len = cpu_to_be16(tot_len); 577 ipv4->check = 0; 578 ipv4->check = ip_fast_csum((unsigned char *)ipv4, 579 ipv4->ihl); 580 } else { 581 struct ipv6hdr *ipv6 = ip_p; 582 583 tcp = ip_p + sizeof(struct ipv6hdr); 584 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 585 586 ipv6->hop_limit = cqe->lro_min_ttl; 587 ipv6->payload_len = cpu_to_be16(tot_len - 588 sizeof(struct ipv6hdr)); 589 } 590 591 tcp->psh = get_cqe_lro_tcppsh(cqe); 592 593 if (tcp_ack) { 594 tcp->ack = 1; 595 tcp->ack_seq = cqe->lro_ack_seq_num; 596 tcp->window = cqe->lro_tcp_win; 597 } 598 } 599 600 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe, 601 struct sk_buff *skb) 602 { 603 u8 cht = cqe->rss_hash_type; 604 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 : 605 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 : 606 PKT_HASH_TYPE_NONE; 607 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht); 608 } 609 610 static inline bool is_first_ethertype_ip(struct sk_buff *skb) 611 { 612 __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto; 613 614 return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6)); 615 } 616 617 static inline void mlx5e_handle_csum(struct net_device *netdev, 618 struct mlx5_cqe64 *cqe, 619 struct mlx5e_rq *rq, 620 struct sk_buff *skb, 621 bool lro) 622 { 623 if (unlikely(!(netdev->features & NETIF_F_RXCSUM))) 624 goto csum_none; 625 626 if (lro) { 627 skb->ip_summed = CHECKSUM_UNNECESSARY; 628 return; 629 } 630 631 if (is_first_ethertype_ip(skb)) { 632 skb->ip_summed = CHECKSUM_COMPLETE; 633 skb->csum = csum_unfold((__force __sum16)cqe->check_sum); 634 rq->stats.csum_complete++; 635 return; 636 } 637 638 if (likely((cqe->hds_ip_ext & CQE_L3_OK) && 639 (cqe->hds_ip_ext & CQE_L4_OK))) { 640 skb->ip_summed = CHECKSUM_UNNECESSARY; 641 if (cqe_is_tunneled(cqe)) { 642 skb->csum_level = 1; 643 skb->encapsulation = 1; 644 rq->stats.csum_unnecessary_inner++; 645 } 646 return; 647 } 648 csum_none: 649 skb->ip_summed = CHECKSUM_NONE; 650 rq->stats.csum_none++; 651 } 652 653 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe, 654 u32 cqe_bcnt, 655 struct mlx5e_rq *rq, 656 struct sk_buff *skb) 657 { 658 struct net_device *netdev = rq->netdev; 659 struct mlx5e_tstamp *tstamp = rq->tstamp; 660 int lro_num_seg; 661 662 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24; 663 if (lro_num_seg > 1) { 664 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt); 665 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg); 666 /* Subtract one since we already counted this as one 667 * "regular" packet in mlx5e_complete_rx_cqe() 668 */ 669 rq->stats.packets += lro_num_seg - 1; 670 rq->stats.lro_packets++; 671 rq->stats.lro_bytes += cqe_bcnt; 672 } 673 674 if (unlikely(mlx5e_rx_hw_stamp(tstamp))) 675 mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb)); 676 677 skb_record_rx_queue(skb, rq->ix); 678 679 if (likely(netdev->features & NETIF_F_RXHASH)) 680 mlx5e_skb_set_hash(cqe, skb); 681 682 if (cqe_has_vlan(cqe)) 683 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 684 be16_to_cpu(cqe->vlan_info)); 685 686 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK; 687 688 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg); 689 skb->protocol = eth_type_trans(skb, netdev); 690 } 691 692 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq, 693 struct mlx5_cqe64 *cqe, 694 u32 cqe_bcnt, 695 struct sk_buff *skb) 696 { 697 rq->stats.packets++; 698 rq->stats.bytes += cqe_bcnt; 699 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb); 700 } 701 702 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq) 703 { 704 struct mlx5_wq_cyc *wq = &sq->wq; 705 struct mlx5e_tx_wqe *wqe; 706 u16 pi = (sq->pc - 1) & wq->sz_m1; /* last pi */ 707 708 wqe = mlx5_wq_cyc_get_wqe(wq, pi); 709 710 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &wqe->ctrl); 711 } 712 713 static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq, 714 struct mlx5e_dma_info *di, 715 const struct xdp_buff *xdp) 716 { 717 struct mlx5e_xdpsq *sq = &rq->xdpsq; 718 struct mlx5_wq_cyc *wq = &sq->wq; 719 u16 pi = sq->pc & wq->sz_m1; 720 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi); 721 722 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; 723 struct mlx5_wqe_eth_seg *eseg = &wqe->eth; 724 struct mlx5_wqe_data_seg *dseg; 725 726 ptrdiff_t data_offset = xdp->data - xdp->data_hard_start; 727 dma_addr_t dma_addr = di->addr + data_offset; 728 unsigned int dma_len = xdp->data_end - xdp->data; 729 730 prefetchw(wqe); 731 732 if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE || 733 MLX5E_SW2HW_MTU(rq->channel->priv, rq->netdev->mtu) < dma_len)) { 734 rq->stats.xdp_drop++; 735 return false; 736 } 737 738 if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1))) { 739 if (sq->db.doorbell) { 740 /* SQ is full, ring doorbell */ 741 mlx5e_xmit_xdp_doorbell(sq); 742 sq->db.doorbell = false; 743 } 744 rq->stats.xdp_tx_full++; 745 return false; 746 } 747 748 dma_sync_single_for_device(sq->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE); 749 750 cseg->fm_ce_se = 0; 751 752 dseg = (struct mlx5_wqe_data_seg *)eseg + 1; 753 754 /* copy the inline part if required */ 755 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) { 756 memcpy(eseg->inline_hdr.start, xdp->data, MLX5E_XDP_MIN_INLINE); 757 eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE); 758 dma_len -= MLX5E_XDP_MIN_INLINE; 759 dma_addr += MLX5E_XDP_MIN_INLINE; 760 dseg++; 761 } 762 763 /* write the dma part */ 764 dseg->addr = cpu_to_be64(dma_addr); 765 dseg->byte_count = cpu_to_be32(dma_len); 766 767 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND); 768 769 /* move page to reference to sq responsibility, 770 * and mark so it's not put back in page-cache. 771 */ 772 rq->wqe.xdp_xmit = true; 773 sq->db.di[pi] = *di; 774 sq->pc++; 775 776 sq->db.doorbell = true; 777 778 rq->stats.xdp_tx++; 779 return true; 780 } 781 782 /* returns true if packet was consumed by xdp */ 783 static inline int mlx5e_xdp_handle(struct mlx5e_rq *rq, 784 struct mlx5e_dma_info *di, 785 void *va, u16 *rx_headroom, u32 *len) 786 { 787 const struct bpf_prog *prog = READ_ONCE(rq->xdp_prog); 788 struct xdp_buff xdp; 789 u32 act; 790 791 if (!prog) 792 return false; 793 794 xdp.data = va + *rx_headroom; 795 xdp.data_end = xdp.data + *len; 796 xdp.data_hard_start = va; 797 798 act = bpf_prog_run_xdp(prog, &xdp); 799 switch (act) { 800 case XDP_PASS: 801 *rx_headroom = xdp.data - xdp.data_hard_start; 802 *len = xdp.data_end - xdp.data; 803 return false; 804 case XDP_TX: 805 if (unlikely(!mlx5e_xmit_xdp_frame(rq, di, &xdp))) 806 trace_xdp_exception(rq->netdev, prog, act); 807 return true; 808 default: 809 bpf_warn_invalid_xdp_action(act); 810 case XDP_ABORTED: 811 trace_xdp_exception(rq->netdev, prog, act); 812 case XDP_DROP: 813 rq->stats.xdp_drop++; 814 return true; 815 } 816 } 817 818 static inline 819 struct sk_buff *skb_from_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, 820 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt) 821 { 822 struct mlx5e_dma_info *di = &wi->di; 823 u16 rx_headroom = rq->buff.headroom; 824 struct sk_buff *skb; 825 void *va, *data; 826 bool consumed; 827 u32 frag_size; 828 829 va = page_address(di->page) + wi->offset; 830 data = va + rx_headroom; 831 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt); 832 833 dma_sync_single_range_for_cpu(rq->pdev, 834 di->addr + wi->offset, 835 0, frag_size, 836 DMA_FROM_DEVICE); 837 prefetch(data); 838 wi->offset += frag_size; 839 840 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { 841 rq->stats.wqe_err++; 842 return NULL; 843 } 844 845 rcu_read_lock(); 846 consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt); 847 rcu_read_unlock(); 848 if (consumed) 849 return NULL; /* page/packet was consumed by XDP */ 850 851 skb = build_skb(va, frag_size); 852 if (unlikely(!skb)) { 853 rq->stats.buff_alloc_err++; 854 return NULL; 855 } 856 857 /* queue up for recycling/reuse */ 858 page_ref_inc(di->page); 859 860 skb_reserve(skb, rx_headroom); 861 skb_put(skb, cqe_bcnt); 862 863 return skb; 864 } 865 866 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 867 { 868 struct mlx5e_wqe_frag_info *wi; 869 struct mlx5e_rx_wqe *wqe; 870 __be16 wqe_counter_be; 871 struct sk_buff *skb; 872 u16 wqe_counter; 873 u32 cqe_bcnt; 874 875 wqe_counter_be = cqe->wqe_counter; 876 wqe_counter = be16_to_cpu(wqe_counter_be); 877 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 878 wi = &rq->wqe.frag_info[wqe_counter]; 879 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 880 881 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 882 if (!skb) { 883 /* probably for XDP */ 884 if (rq->wqe.xdp_xmit) { 885 wi->di.page = NULL; 886 rq->wqe.xdp_xmit = false; 887 /* do not return page to cache, it will be returned on XDP_TX completion */ 888 goto wq_ll_pop; 889 } 890 /* probably an XDP_DROP, save the page-reuse checks */ 891 mlx5e_free_rx_wqe(rq, wi); 892 goto wq_ll_pop; 893 } 894 895 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 896 napi_gro_receive(rq->cq.napi, skb); 897 898 mlx5e_free_rx_wqe_reuse(rq, wi); 899 wq_ll_pop: 900 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 901 &wqe->next.next_wqe_index); 902 } 903 904 #ifdef CONFIG_MLX5_ESWITCH 905 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 906 { 907 struct net_device *netdev = rq->netdev; 908 struct mlx5e_priv *priv = netdev_priv(netdev); 909 struct mlx5e_rep_priv *rpriv = priv->ppriv; 910 struct mlx5_eswitch_rep *rep = rpriv->rep; 911 struct mlx5e_wqe_frag_info *wi; 912 struct mlx5e_rx_wqe *wqe; 913 struct sk_buff *skb; 914 __be16 wqe_counter_be; 915 u16 wqe_counter; 916 u32 cqe_bcnt; 917 918 wqe_counter_be = cqe->wqe_counter; 919 wqe_counter = be16_to_cpu(wqe_counter_be); 920 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 921 wi = &rq->wqe.frag_info[wqe_counter]; 922 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 923 924 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 925 if (!skb) { 926 if (rq->wqe.xdp_xmit) { 927 wi->di.page = NULL; 928 rq->wqe.xdp_xmit = false; 929 /* do not return page to cache, it will be returned on XDP_TX completion */ 930 goto wq_ll_pop; 931 } 932 /* probably an XDP_DROP, save the page-reuse checks */ 933 mlx5e_free_rx_wqe(rq, wi); 934 goto wq_ll_pop; 935 } 936 937 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 938 939 if (rep->vlan && skb_vlan_tag_present(skb)) 940 skb_vlan_pop(skb); 941 942 napi_gro_receive(rq->cq.napi, skb); 943 944 mlx5e_free_rx_wqe_reuse(rq, wi); 945 wq_ll_pop: 946 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 947 &wqe->next.next_wqe_index); 948 } 949 #endif 950 951 static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq, 952 struct mlx5_cqe64 *cqe, 953 struct mlx5e_mpw_info *wi, 954 u32 cqe_bcnt, 955 struct sk_buff *skb) 956 { 957 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe); 958 u32 wqe_offset = stride_ix << rq->mpwqe.log_stride_sz; 959 u32 head_offset = wqe_offset & (PAGE_SIZE - 1); 960 u32 page_idx = wqe_offset >> PAGE_SHIFT; 961 u32 head_page_idx = page_idx; 962 u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt); 963 u32 frag_offset = head_offset + headlen; 964 u16 byte_cnt = cqe_bcnt - headlen; 965 966 if (unlikely(frag_offset >= PAGE_SIZE)) { 967 page_idx++; 968 frag_offset -= PAGE_SIZE; 969 } 970 971 while (byte_cnt) { 972 u32 pg_consumed_bytes = 973 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt); 974 975 mlx5e_add_skb_frag_mpwqe(rq, skb, wi, page_idx, frag_offset, 976 pg_consumed_bytes); 977 byte_cnt -= pg_consumed_bytes; 978 frag_offset = 0; 979 page_idx++; 980 } 981 /* copy header */ 982 mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, wi, head_page_idx, 983 head_offset, headlen); 984 /* skb linear part was allocated with headlen and aligned to long */ 985 skb->tail += headlen; 986 skb->len += headlen; 987 } 988 989 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 990 { 991 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe); 992 u16 wqe_id = be16_to_cpu(cqe->wqe_id); 993 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id]; 994 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id); 995 struct sk_buff *skb; 996 u16 cqe_bcnt; 997 998 wi->consumed_strides += cstrides; 999 1000 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { 1001 rq->stats.wqe_err++; 1002 goto mpwrq_cqe_out; 1003 } 1004 1005 if (unlikely(mpwrq_is_filler_cqe(cqe))) { 1006 rq->stats.mpwqe_filler++; 1007 goto mpwrq_cqe_out; 1008 } 1009 1010 skb = napi_alloc_skb(rq->cq.napi, 1011 ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, 1012 sizeof(long))); 1013 if (unlikely(!skb)) { 1014 rq->stats.buff_alloc_err++; 1015 goto mpwrq_cqe_out; 1016 } 1017 1018 prefetchw(skb->data); 1019 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe); 1020 1021 mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb); 1022 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1023 napi_gro_receive(rq->cq.napi, skb); 1024 1025 mpwrq_cqe_out: 1026 if (likely(wi->consumed_strides < rq->mpwqe.num_strides)) 1027 return; 1028 1029 mlx5e_free_rx_mpwqe(rq, wi); 1030 mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index); 1031 } 1032 1033 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget) 1034 { 1035 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq); 1036 struct mlx5e_xdpsq *xdpsq; 1037 struct mlx5_cqe64 *cqe; 1038 int work_done = 0; 1039 1040 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED))) 1041 return 0; 1042 1043 if (cq->decmprs_left) 1044 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget); 1045 1046 cqe = mlx5_cqwq_get_cqe(&cq->wq); 1047 if (!cqe) 1048 return 0; 1049 1050 xdpsq = &rq->xdpsq; 1051 1052 do { 1053 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) { 1054 work_done += 1055 mlx5e_decompress_cqes_start(rq, cq, 1056 budget - work_done); 1057 continue; 1058 } 1059 1060 mlx5_cqwq_pop(&cq->wq); 1061 1062 rq->handle_rx_cqe(rq, cqe); 1063 } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq))); 1064 1065 if (xdpsq->db.doorbell) { 1066 mlx5e_xmit_xdp_doorbell(xdpsq); 1067 xdpsq->db.doorbell = false; 1068 } 1069 1070 mlx5_cqwq_update_db_record(&cq->wq); 1071 1072 /* ensure cq space is freed before enabling more cqes */ 1073 wmb(); 1074 1075 return work_done; 1076 } 1077 1078 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq) 1079 { 1080 struct mlx5e_xdpsq *sq; 1081 struct mlx5_cqe64 *cqe; 1082 struct mlx5e_rq *rq; 1083 u16 sqcc; 1084 int i; 1085 1086 sq = container_of(cq, struct mlx5e_xdpsq, cq); 1087 1088 if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED))) 1089 return false; 1090 1091 cqe = mlx5_cqwq_get_cqe(&cq->wq); 1092 if (!cqe) 1093 return false; 1094 1095 rq = container_of(sq, struct mlx5e_rq, xdpsq); 1096 1097 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(), 1098 * otherwise a cq overrun may occur 1099 */ 1100 sqcc = sq->cc; 1101 1102 i = 0; 1103 do { 1104 u16 wqe_counter; 1105 bool last_wqe; 1106 1107 mlx5_cqwq_pop(&cq->wq); 1108 1109 wqe_counter = be16_to_cpu(cqe->wqe_counter); 1110 1111 do { 1112 struct mlx5e_dma_info *di; 1113 u16 ci; 1114 1115 last_wqe = (sqcc == wqe_counter); 1116 1117 ci = sqcc & sq->wq.sz_m1; 1118 di = &sq->db.di[ci]; 1119 1120 sqcc++; 1121 /* Recycle RX page */ 1122 mlx5e_page_release(rq, di, true); 1123 } while (!last_wqe); 1124 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq))); 1125 1126 mlx5_cqwq_update_db_record(&cq->wq); 1127 1128 /* ensure cq space is freed before enabling more cqes */ 1129 wmb(); 1130 1131 sq->cc = sqcc; 1132 return (i == MLX5E_TX_CQ_POLL_BUDGET); 1133 } 1134 1135 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq) 1136 { 1137 struct mlx5e_rq *rq = container_of(sq, struct mlx5e_rq, xdpsq); 1138 struct mlx5e_dma_info *di; 1139 u16 ci; 1140 1141 while (sq->cc != sq->pc) { 1142 ci = sq->cc & sq->wq.sz_m1; 1143 di = &sq->db.di[ci]; 1144 sq->cc++; 1145 1146 mlx5e_page_release(rq, di, false); 1147 } 1148 } 1149 1150 #ifdef CONFIG_MLX5_CORE_IPOIB 1151 1152 #define MLX5_IB_GRH_DGID_OFFSET 24 1153 #define MLX5_GID_SIZE 16 1154 1155 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq, 1156 struct mlx5_cqe64 *cqe, 1157 u32 cqe_bcnt, 1158 struct sk_buff *skb) 1159 { 1160 struct net_device *netdev = rq->netdev; 1161 struct mlx5e_tstamp *tstamp = rq->tstamp; 1162 char *pseudo_header; 1163 u8 *dgid; 1164 u8 g; 1165 1166 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3; 1167 dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET; 1168 if ((!g) || dgid[0] != 0xff) 1169 skb->pkt_type = PACKET_HOST; 1170 else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0) 1171 skb->pkt_type = PACKET_BROADCAST; 1172 else 1173 skb->pkt_type = PACKET_MULTICAST; 1174 1175 /* TODO: IB/ipoib: Allow mcast packets from other VFs 1176 * 68996a6e760e5c74654723eeb57bf65628ae87f4 1177 */ 1178 1179 skb_pull(skb, MLX5_IB_GRH_BYTES); 1180 1181 skb->protocol = *((__be16 *)(skb->data)); 1182 1183 skb->ip_summed = CHECKSUM_COMPLETE; 1184 skb->csum = csum_unfold((__force __sum16)cqe->check_sum); 1185 1186 if (unlikely(mlx5e_rx_hw_stamp(tstamp))) 1187 mlx5e_fill_hwstamp(tstamp, get_cqe_ts(cqe), skb_hwtstamps(skb)); 1188 1189 skb_record_rx_queue(skb, rq->ix); 1190 1191 if (likely(netdev->features & NETIF_F_RXHASH)) 1192 mlx5e_skb_set_hash(cqe, skb); 1193 1194 /* 20 bytes of ipoib header and 4 for encap existing */ 1195 pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN); 1196 memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN); 1197 skb_reset_mac_header(skb); 1198 skb_pull(skb, MLX5_IPOIB_HARD_LEN); 1199 1200 skb->dev = netdev; 1201 1202 rq->stats.csum_complete++; 1203 rq->stats.packets++; 1204 rq->stats.bytes += cqe_bcnt; 1205 } 1206 1207 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1208 { 1209 struct mlx5e_wqe_frag_info *wi; 1210 struct mlx5e_rx_wqe *wqe; 1211 __be16 wqe_counter_be; 1212 struct sk_buff *skb; 1213 u16 wqe_counter; 1214 u32 cqe_bcnt; 1215 1216 wqe_counter_be = cqe->wqe_counter; 1217 wqe_counter = be16_to_cpu(wqe_counter_be); 1218 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 1219 wi = &rq->wqe.frag_info[wqe_counter]; 1220 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 1221 1222 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 1223 if (!skb) 1224 goto wq_free_wqe; 1225 1226 mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1227 napi_gro_receive(rq->cq.napi, skb); 1228 1229 wq_free_wqe: 1230 mlx5e_free_rx_wqe_reuse(rq, wi); 1231 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 1232 &wqe->next.next_wqe_index); 1233 } 1234 1235 #endif /* CONFIG_MLX5_CORE_IPOIB */ 1236 1237 #ifdef CONFIG_MLX5_EN_IPSEC 1238 1239 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1240 { 1241 struct mlx5e_wqe_frag_info *wi; 1242 struct mlx5e_rx_wqe *wqe; 1243 __be16 wqe_counter_be; 1244 struct sk_buff *skb; 1245 u16 wqe_counter; 1246 u32 cqe_bcnt; 1247 1248 wqe_counter_be = cqe->wqe_counter; 1249 wqe_counter = be16_to_cpu(wqe_counter_be); 1250 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 1251 wi = &rq->wqe.frag_info[wqe_counter]; 1252 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 1253 1254 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 1255 if (unlikely(!skb)) { 1256 /* a DROP, save the page-reuse checks */ 1257 mlx5e_free_rx_wqe(rq, wi); 1258 goto wq_ll_pop; 1259 } 1260 skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb); 1261 if (unlikely(!skb)) { 1262 mlx5e_free_rx_wqe(rq, wi); 1263 goto wq_ll_pop; 1264 } 1265 1266 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1267 napi_gro_receive(rq->cq.napi, skb); 1268 1269 mlx5e_free_rx_wqe_reuse(rq, wi); 1270 wq_ll_pop: 1271 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 1272 &wqe->next.next_wqe_index); 1273 } 1274 1275 #endif /* CONFIG_MLX5_EN_IPSEC */ 1276