1 /* 2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/prefetch.h> 34 #include <linux/ip.h> 35 #include <linux/ipv6.h> 36 #include <linux/tcp.h> 37 #include <linux/bpf_trace.h> 38 #include <net/busy_poll.h> 39 #include <net/ip6_checksum.h> 40 #include "en.h" 41 #include "en_tc.h" 42 #include "eswitch.h" 43 #include "en_rep.h" 44 #include "ipoib/ipoib.h" 45 #include "en_accel/ipsec_rxtx.h" 46 #include "lib/clock.h" 47 48 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config) 49 { 50 return config->rx_filter == HWTSTAMP_FILTER_ALL; 51 } 52 53 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc, 54 void *data) 55 { 56 u32 ci = cqcc & cq->wq.fbc.sz_m1; 57 58 memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64)); 59 } 60 61 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq, 62 struct mlx5e_cq *cq, u32 cqcc) 63 { 64 mlx5e_read_cqe_slot(cq, cqcc, &cq->title); 65 cq->decmprs_left = be32_to_cpu(cq->title.byte_cnt); 66 cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter); 67 rq->stats.cqe_compress_blks++; 68 } 69 70 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc) 71 { 72 mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr); 73 cq->mini_arr_idx = 0; 74 } 75 76 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n) 77 { 78 struct mlx5_frag_buf_ctrl *fbc = &cq->wq.fbc; 79 u8 op_own = (cqcc >> fbc->log_sz) & 1; 80 u32 wq_sz = 1 << fbc->log_sz; 81 u32 ci = cqcc & fbc->sz_m1; 82 u32 ci_top = min_t(u32, wq_sz, ci + n); 83 84 for (; ci < ci_top; ci++, n--) { 85 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci); 86 87 cqe->op_own = op_own; 88 } 89 90 if (unlikely(ci == wq_sz)) { 91 op_own = !op_own; 92 for (ci = 0; ci < n; ci++) { 93 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci); 94 95 cqe->op_own = op_own; 96 } 97 } 98 } 99 100 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq, 101 struct mlx5e_cq *cq, u32 cqcc) 102 { 103 cq->title.byte_cnt = cq->mini_arr[cq->mini_arr_idx].byte_cnt; 104 cq->title.check_sum = cq->mini_arr[cq->mini_arr_idx].checksum; 105 cq->title.op_own &= 0xf0; 106 cq->title.op_own |= 0x01 & (cqcc >> cq->wq.fbc.log_sz); 107 cq->title.wqe_counter = cpu_to_be16(cq->decmprs_wqe_counter); 108 109 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) 110 cq->decmprs_wqe_counter += 111 mpwrq_get_cqe_consumed_strides(&cq->title); 112 else 113 cq->decmprs_wqe_counter = 114 (cq->decmprs_wqe_counter + 1) & rq->wq.sz_m1; 115 } 116 117 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq, 118 struct mlx5e_cq *cq, u32 cqcc) 119 { 120 mlx5e_decompress_cqe(rq, cq, cqcc); 121 cq->title.rss_hash_type = 0; 122 cq->title.rss_hash_result = 0; 123 } 124 125 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq, 126 struct mlx5e_cq *cq, 127 int update_owner_only, 128 int budget_rem) 129 { 130 u32 cqcc = cq->wq.cc + update_owner_only; 131 u32 cqe_count; 132 u32 i; 133 134 cqe_count = min_t(u32, cq->decmprs_left, budget_rem); 135 136 for (i = update_owner_only; i < cqe_count; 137 i++, cq->mini_arr_idx++, cqcc++) { 138 if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE) 139 mlx5e_read_mini_arr_slot(cq, cqcc); 140 141 mlx5e_decompress_cqe_no_hash(rq, cq, cqcc); 142 rq->handle_rx_cqe(rq, &cq->title); 143 } 144 mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc); 145 cq->wq.cc = cqcc; 146 cq->decmprs_left -= cqe_count; 147 rq->stats.cqe_compress_pkts += cqe_count; 148 149 return cqe_count; 150 } 151 152 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq, 153 struct mlx5e_cq *cq, 154 int budget_rem) 155 { 156 mlx5e_read_title_slot(rq, cq, cq->wq.cc); 157 mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1); 158 mlx5e_decompress_cqe(rq, cq, cq->wq.cc); 159 rq->handle_rx_cqe(rq, &cq->title); 160 cq->mini_arr_idx++; 161 162 return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1; 163 } 164 165 #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT) 166 167 static inline bool mlx5e_page_is_reserved(struct page *page) 168 { 169 return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id(); 170 } 171 172 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq, 173 struct mlx5e_dma_info *dma_info) 174 { 175 struct mlx5e_page_cache *cache = &rq->page_cache; 176 u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1); 177 178 if (tail_next == cache->head) { 179 rq->stats.cache_full++; 180 return false; 181 } 182 183 if (unlikely(mlx5e_page_is_reserved(dma_info->page))) { 184 rq->stats.cache_waive++; 185 return false; 186 } 187 188 cache->page_cache[cache->tail] = *dma_info; 189 cache->tail = tail_next; 190 return true; 191 } 192 193 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq, 194 struct mlx5e_dma_info *dma_info) 195 { 196 struct mlx5e_page_cache *cache = &rq->page_cache; 197 198 if (unlikely(cache->head == cache->tail)) { 199 rq->stats.cache_empty++; 200 return false; 201 } 202 203 if (page_ref_count(cache->page_cache[cache->head].page) != 1) { 204 rq->stats.cache_busy++; 205 return false; 206 } 207 208 *dma_info = cache->page_cache[cache->head]; 209 cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1); 210 rq->stats.cache_reuse++; 211 212 dma_sync_single_for_device(rq->pdev, dma_info->addr, 213 RQ_PAGE_SIZE(rq), 214 DMA_FROM_DEVICE); 215 return true; 216 } 217 218 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq, 219 struct mlx5e_dma_info *dma_info) 220 { 221 if (mlx5e_rx_cache_get(rq, dma_info)) 222 return 0; 223 224 dma_info->page = dev_alloc_pages(rq->buff.page_order); 225 if (unlikely(!dma_info->page)) 226 return -ENOMEM; 227 228 dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0, 229 RQ_PAGE_SIZE(rq), rq->buff.map_dir); 230 if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) { 231 put_page(dma_info->page); 232 dma_info->page = NULL; 233 return -ENOMEM; 234 } 235 236 return 0; 237 } 238 239 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info, 240 bool recycle) 241 { 242 if (likely(recycle) && mlx5e_rx_cache_put(rq, dma_info)) 243 return; 244 245 dma_unmap_page(rq->pdev, dma_info->addr, RQ_PAGE_SIZE(rq), 246 rq->buff.map_dir); 247 put_page(dma_info->page); 248 } 249 250 static inline bool mlx5e_page_reuse(struct mlx5e_rq *rq, 251 struct mlx5e_wqe_frag_info *wi) 252 { 253 return rq->wqe.page_reuse && wi->di.page && 254 (wi->offset + rq->wqe.frag_sz <= RQ_PAGE_SIZE(rq)) && 255 !mlx5e_page_is_reserved(wi->di.page); 256 } 257 258 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix) 259 { 260 struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix]; 261 262 /* check if page exists, hence can be reused */ 263 if (!wi->di.page) { 264 if (unlikely(mlx5e_page_alloc_mapped(rq, &wi->di))) 265 return -ENOMEM; 266 wi->offset = 0; 267 } 268 269 wqe->data.addr = cpu_to_be64(wi->di.addr + wi->offset + rq->buff.headroom); 270 return 0; 271 } 272 273 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq, 274 struct mlx5e_wqe_frag_info *wi) 275 { 276 mlx5e_page_release(rq, &wi->di, true); 277 wi->di.page = NULL; 278 } 279 280 static inline void mlx5e_free_rx_wqe_reuse(struct mlx5e_rq *rq, 281 struct mlx5e_wqe_frag_info *wi) 282 { 283 if (mlx5e_page_reuse(rq, wi)) { 284 rq->stats.page_reuse++; 285 return; 286 } 287 288 mlx5e_free_rx_wqe(rq, wi); 289 } 290 291 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix) 292 { 293 struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix]; 294 295 if (wi->di.page) 296 mlx5e_free_rx_wqe(rq, wi); 297 } 298 299 static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq *rq) 300 { 301 return rq->mpwqe.num_strides >> MLX5_MPWRQ_WQE_PAGE_ORDER; 302 } 303 304 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq, 305 struct sk_buff *skb, 306 struct mlx5e_mpw_info *wi, 307 u32 page_idx, u32 frag_offset, 308 u32 len) 309 { 310 unsigned int truesize = ALIGN(len, BIT(rq->mpwqe.log_stride_sz)); 311 312 dma_sync_single_for_cpu(rq->pdev, 313 wi->umr.dma_info[page_idx].addr + frag_offset, 314 len, DMA_FROM_DEVICE); 315 wi->skbs_frags[page_idx]++; 316 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 317 wi->umr.dma_info[page_idx].page, frag_offset, 318 len, truesize); 319 } 320 321 static inline void 322 mlx5e_copy_skb_header_mpwqe(struct device *pdev, 323 struct sk_buff *skb, 324 struct mlx5e_mpw_info *wi, 325 u32 page_idx, u32 offset, 326 u32 headlen) 327 { 328 u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset); 329 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[page_idx]; 330 unsigned int len; 331 332 /* Aligning len to sizeof(long) optimizes memcpy performance */ 333 len = ALIGN(headlen_pg, sizeof(long)); 334 dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len, 335 DMA_FROM_DEVICE); 336 skb_copy_to_linear_data(skb, page_address(dma_info->page) + offset, len); 337 338 if (unlikely(offset + headlen > PAGE_SIZE)) { 339 dma_info++; 340 headlen_pg = len; 341 len = ALIGN(headlen - headlen_pg, sizeof(long)); 342 dma_sync_single_for_cpu(pdev, dma_info->addr, len, 343 DMA_FROM_DEVICE); 344 skb_copy_to_linear_data_offset(skb, headlen_pg, 345 page_address(dma_info->page), 346 len); 347 } 348 } 349 350 static inline void mlx5e_post_umr_wqe(struct mlx5e_rq *rq, u16 ix) 351 { 352 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 353 struct mlx5e_icosq *sq = &rq->channel->icosq; 354 struct mlx5_wq_cyc *wq = &sq->wq; 355 struct mlx5e_umr_wqe *wqe; 356 u8 num_wqebbs = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_BB); 357 u16 pi; 358 359 /* fill sq edge with nops to avoid wqe wrap around */ 360 while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) { 361 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP; 362 mlx5e_post_nop(wq, sq->sqn, &sq->pc); 363 } 364 365 wqe = mlx5_wq_cyc_get_wqe(wq, pi); 366 memcpy(wqe, &wi->umr.wqe, sizeof(*wqe)); 367 wqe->ctrl.opmod_idx_opcode = 368 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) | 369 MLX5_OPCODE_UMR); 370 371 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR; 372 sq->pc += num_wqebbs; 373 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &wqe->ctrl); 374 } 375 376 static int mlx5e_alloc_rx_umr_mpwqe(struct mlx5e_rq *rq, 377 u16 ix) 378 { 379 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 380 int pg_strides = mlx5e_mpwqe_strides_per_page(rq); 381 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0]; 382 int err; 383 int i; 384 385 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) { 386 err = mlx5e_page_alloc_mapped(rq, dma_info); 387 if (unlikely(err)) 388 goto err_unmap; 389 wi->umr.mtt[i] = cpu_to_be64(dma_info->addr | MLX5_EN_WR); 390 page_ref_add(dma_info->page, pg_strides); 391 } 392 393 memset(wi->skbs_frags, 0, sizeof(*wi->skbs_frags) * MLX5_MPWRQ_PAGES_PER_WQE); 394 wi->consumed_strides = 0; 395 396 return 0; 397 398 err_unmap: 399 while (--i >= 0) { 400 dma_info--; 401 page_ref_sub(dma_info->page, pg_strides); 402 mlx5e_page_release(rq, dma_info, true); 403 } 404 405 return err; 406 } 407 408 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi) 409 { 410 int pg_strides = mlx5e_mpwqe_strides_per_page(rq); 411 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0]; 412 int i; 413 414 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) { 415 page_ref_sub(dma_info->page, pg_strides - wi->skbs_frags[i]); 416 mlx5e_page_release(rq, dma_info, true); 417 } 418 } 419 420 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq) 421 { 422 struct mlx5_wq_ll *wq = &rq->wq; 423 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); 424 425 rq->mpwqe.umr_in_progress = false; 426 427 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); 428 429 /* ensure wqes are visible to device before updating doorbell record */ 430 dma_wmb(); 431 432 mlx5_wq_ll_update_db_record(wq); 433 } 434 435 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) 436 { 437 int err; 438 439 err = mlx5e_alloc_rx_umr_mpwqe(rq, ix); 440 if (unlikely(err)) { 441 rq->stats.buff_alloc_err++; 442 return err; 443 } 444 rq->mpwqe.umr_in_progress = true; 445 mlx5e_post_umr_wqe(rq, ix); 446 return 0; 447 } 448 449 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) 450 { 451 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; 452 453 mlx5e_free_rx_mpwqe(rq, wi); 454 } 455 456 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq) 457 { 458 struct mlx5_wq_ll *wq = &rq->wq; 459 int err; 460 461 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED))) 462 return false; 463 464 if (mlx5_wq_ll_is_full(wq)) 465 return false; 466 467 do { 468 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); 469 470 err = mlx5e_alloc_rx_wqe(rq, wqe, wq->head); 471 if (unlikely(err)) { 472 rq->stats.buff_alloc_err++; 473 break; 474 } 475 476 mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); 477 } while (!mlx5_wq_ll_is_full(wq)); 478 479 /* ensure wqes are visible to device before updating doorbell record */ 480 dma_wmb(); 481 482 mlx5_wq_ll_update_db_record(wq); 483 484 return !!err; 485 } 486 487 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq, 488 struct mlx5e_icosq *sq, 489 struct mlx5e_rq *rq, 490 struct mlx5_cqe64 *cqe) 491 { 492 struct mlx5_wq_cyc *wq = &sq->wq; 493 u16 ci = be16_to_cpu(cqe->wqe_counter) & wq->sz_m1; 494 struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci]; 495 496 mlx5_cqwq_pop(&cq->wq); 497 498 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) { 499 netdev_WARN_ONCE(cq->channel->netdev, 500 "Bad OP in ICOSQ CQE: 0x%x\n", cqe->op_own); 501 return; 502 } 503 504 if (likely(icowi->opcode == MLX5_OPCODE_UMR)) { 505 mlx5e_post_rx_mpwqe(rq); 506 return; 507 } 508 509 if (unlikely(icowi->opcode != MLX5_OPCODE_NOP)) 510 netdev_WARN_ONCE(cq->channel->netdev, 511 "Bad OPCODE in ICOSQ WQE info: 0x%x\n", icowi->opcode); 512 } 513 514 static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq) 515 { 516 struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq); 517 struct mlx5_cqe64 *cqe; 518 519 if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED))) 520 return; 521 522 cqe = mlx5_cqwq_get_cqe(&cq->wq); 523 if (likely(!cqe)) 524 return; 525 526 /* by design, there's only a single cqe */ 527 mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe); 528 529 mlx5_cqwq_update_db_record(&cq->wq); 530 } 531 532 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq) 533 { 534 struct mlx5_wq_ll *wq = &rq->wq; 535 536 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED))) 537 return false; 538 539 mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq); 540 541 if (mlx5_wq_ll_is_full(wq)) 542 return false; 543 544 if (!rq->mpwqe.umr_in_progress) 545 mlx5e_alloc_rx_mpwqe(rq, wq->head); 546 547 return true; 548 } 549 550 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp) 551 { 552 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe); 553 u8 tcp_ack = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) || 554 (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA); 555 556 tcp->check = 0; 557 tcp->psh = get_cqe_lro_tcppsh(cqe); 558 559 if (tcp_ack) { 560 tcp->ack = 1; 561 tcp->ack_seq = cqe->lro_ack_seq_num; 562 tcp->window = cqe->lro_tcp_win; 563 } 564 } 565 566 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe, 567 u32 cqe_bcnt) 568 { 569 struct ethhdr *eth = (struct ethhdr *)(skb->data); 570 struct tcphdr *tcp; 571 int network_depth = 0; 572 __wsum check; 573 __be16 proto; 574 u16 tot_len; 575 void *ip_p; 576 577 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth); 578 579 tot_len = cqe_bcnt - network_depth; 580 ip_p = skb->data + network_depth; 581 582 if (proto == htons(ETH_P_IP)) { 583 struct iphdr *ipv4 = ip_p; 584 585 tcp = ip_p + sizeof(struct iphdr); 586 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 587 588 ipv4->ttl = cqe->lro_min_ttl; 589 ipv4->tot_len = cpu_to_be16(tot_len); 590 ipv4->check = 0; 591 ipv4->check = ip_fast_csum((unsigned char *)ipv4, 592 ipv4->ihl); 593 594 mlx5e_lro_update_tcp_hdr(cqe, tcp); 595 check = csum_partial(tcp, tcp->doff * 4, 596 csum_unfold((__force __sum16)cqe->check_sum)); 597 /* Almost done, don't forget the pseudo header */ 598 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr, 599 tot_len - sizeof(struct iphdr), 600 IPPROTO_TCP, check); 601 } else { 602 u16 payload_len = tot_len - sizeof(struct ipv6hdr); 603 struct ipv6hdr *ipv6 = ip_p; 604 605 tcp = ip_p + sizeof(struct ipv6hdr); 606 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; 607 608 ipv6->hop_limit = cqe->lro_min_ttl; 609 ipv6->payload_len = cpu_to_be16(payload_len); 610 611 mlx5e_lro_update_tcp_hdr(cqe, tcp); 612 check = csum_partial(tcp, tcp->doff * 4, 613 csum_unfold((__force __sum16)cqe->check_sum)); 614 /* Almost done, don't forget the pseudo header */ 615 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len, 616 IPPROTO_TCP, check); 617 } 618 } 619 620 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe, 621 struct sk_buff *skb) 622 { 623 u8 cht = cqe->rss_hash_type; 624 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 : 625 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 : 626 PKT_HASH_TYPE_NONE; 627 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht); 628 } 629 630 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth) 631 { 632 __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto; 633 634 ethertype = __vlan_get_protocol(skb, ethertype, network_depth); 635 return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6)); 636 } 637 638 static inline void mlx5e_handle_csum(struct net_device *netdev, 639 struct mlx5_cqe64 *cqe, 640 struct mlx5e_rq *rq, 641 struct sk_buff *skb, 642 bool lro) 643 { 644 int network_depth = 0; 645 646 if (unlikely(!(netdev->features & NETIF_F_RXCSUM))) 647 goto csum_none; 648 649 if (lro) { 650 skb->ip_summed = CHECKSUM_UNNECESSARY; 651 rq->stats.csum_unnecessary++; 652 return; 653 } 654 655 if (likely(is_last_ethertype_ip(skb, &network_depth))) { 656 skb->ip_summed = CHECKSUM_COMPLETE; 657 skb->csum = csum_unfold((__force __sum16)cqe->check_sum); 658 if (network_depth > ETH_HLEN) 659 /* CQE csum is calculated from the IP header and does 660 * not cover VLAN headers (if present). This will add 661 * the checksum manually. 662 */ 663 skb->csum = csum_partial(skb->data + ETH_HLEN, 664 network_depth - ETH_HLEN, 665 skb->csum); 666 rq->stats.csum_complete++; 667 return; 668 } 669 670 if (likely((cqe->hds_ip_ext & CQE_L3_OK) && 671 (cqe->hds_ip_ext & CQE_L4_OK))) { 672 skb->ip_summed = CHECKSUM_UNNECESSARY; 673 if (cqe_is_tunneled(cqe)) { 674 skb->csum_level = 1; 675 skb->encapsulation = 1; 676 rq->stats.csum_unnecessary_inner++; 677 return; 678 } 679 rq->stats.csum_unnecessary++; 680 return; 681 } 682 csum_none: 683 skb->ip_summed = CHECKSUM_NONE; 684 rq->stats.csum_none++; 685 } 686 687 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe, 688 u32 cqe_bcnt, 689 struct mlx5e_rq *rq, 690 struct sk_buff *skb) 691 { 692 struct net_device *netdev = rq->netdev; 693 int lro_num_seg; 694 695 skb->mac_len = ETH_HLEN; 696 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24; 697 if (lro_num_seg > 1) { 698 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt); 699 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg); 700 /* Subtract one since we already counted this as one 701 * "regular" packet in mlx5e_complete_rx_cqe() 702 */ 703 rq->stats.packets += lro_num_seg - 1; 704 rq->stats.lro_packets++; 705 rq->stats.lro_bytes += cqe_bcnt; 706 } 707 708 if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp))) 709 skb_hwtstamps(skb)->hwtstamp = 710 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe)); 711 712 skb_record_rx_queue(skb, rq->ix); 713 714 if (likely(netdev->features & NETIF_F_RXHASH)) 715 mlx5e_skb_set_hash(cqe, skb); 716 717 if (cqe_has_vlan(cqe)) { 718 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 719 be16_to_cpu(cqe->vlan_info)); 720 rq->stats.removed_vlan_packets++; 721 } 722 723 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK; 724 725 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg); 726 skb->protocol = eth_type_trans(skb, netdev); 727 } 728 729 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq, 730 struct mlx5_cqe64 *cqe, 731 u32 cqe_bcnt, 732 struct sk_buff *skb) 733 { 734 rq->stats.packets++; 735 rq->stats.bytes += cqe_bcnt; 736 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb); 737 } 738 739 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq) 740 { 741 struct mlx5_wq_cyc *wq = &sq->wq; 742 struct mlx5e_tx_wqe *wqe; 743 u16 pi = (sq->pc - 1) & wq->sz_m1; /* last pi */ 744 745 wqe = mlx5_wq_cyc_get_wqe(wq, pi); 746 747 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &wqe->ctrl); 748 } 749 750 static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq, 751 struct mlx5e_dma_info *di, 752 const struct xdp_buff *xdp) 753 { 754 struct mlx5e_xdpsq *sq = &rq->xdpsq; 755 struct mlx5_wq_cyc *wq = &sq->wq; 756 u16 pi = sq->pc & wq->sz_m1; 757 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi); 758 759 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; 760 struct mlx5_wqe_eth_seg *eseg = &wqe->eth; 761 struct mlx5_wqe_data_seg *dseg; 762 763 ptrdiff_t data_offset = xdp->data - xdp->data_hard_start; 764 dma_addr_t dma_addr = di->addr + data_offset; 765 unsigned int dma_len = xdp->data_end - xdp->data; 766 767 prefetchw(wqe); 768 769 if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE || 770 MLX5E_SW2HW_MTU(rq->channel->priv, rq->netdev->mtu) < dma_len)) { 771 rq->stats.xdp_drop++; 772 return false; 773 } 774 775 if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1))) { 776 if (sq->db.doorbell) { 777 /* SQ is full, ring doorbell */ 778 mlx5e_xmit_xdp_doorbell(sq); 779 sq->db.doorbell = false; 780 } 781 rq->stats.xdp_tx_full++; 782 return false; 783 } 784 785 dma_sync_single_for_device(sq->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE); 786 787 cseg->fm_ce_se = 0; 788 789 dseg = (struct mlx5_wqe_data_seg *)eseg + 1; 790 791 /* copy the inline part if required */ 792 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) { 793 memcpy(eseg->inline_hdr.start, xdp->data, MLX5E_XDP_MIN_INLINE); 794 eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE); 795 dma_len -= MLX5E_XDP_MIN_INLINE; 796 dma_addr += MLX5E_XDP_MIN_INLINE; 797 dseg++; 798 } 799 800 /* write the dma part */ 801 dseg->addr = cpu_to_be64(dma_addr); 802 dseg->byte_count = cpu_to_be32(dma_len); 803 804 cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND); 805 806 /* move page to reference to sq responsibility, 807 * and mark so it's not put back in page-cache. 808 */ 809 rq->wqe.xdp_xmit = true; 810 sq->db.di[pi] = *di; 811 sq->pc++; 812 813 sq->db.doorbell = true; 814 815 rq->stats.xdp_tx++; 816 return true; 817 } 818 819 /* returns true if packet was consumed by xdp */ 820 static inline int mlx5e_xdp_handle(struct mlx5e_rq *rq, 821 struct mlx5e_dma_info *di, 822 void *va, u16 *rx_headroom, u32 *len) 823 { 824 const struct bpf_prog *prog = READ_ONCE(rq->xdp_prog); 825 struct xdp_buff xdp; 826 u32 act; 827 828 if (!prog) 829 return false; 830 831 xdp.data = va + *rx_headroom; 832 xdp_set_data_meta_invalid(&xdp); 833 xdp.data_end = xdp.data + *len; 834 xdp.data_hard_start = va; 835 xdp.rxq = &rq->xdp_rxq; 836 837 act = bpf_prog_run_xdp(prog, &xdp); 838 switch (act) { 839 case XDP_PASS: 840 *rx_headroom = xdp.data - xdp.data_hard_start; 841 *len = xdp.data_end - xdp.data; 842 return false; 843 case XDP_TX: 844 if (unlikely(!mlx5e_xmit_xdp_frame(rq, di, &xdp))) 845 trace_xdp_exception(rq->netdev, prog, act); 846 return true; 847 default: 848 bpf_warn_invalid_xdp_action(act); 849 case XDP_ABORTED: 850 trace_xdp_exception(rq->netdev, prog, act); 851 case XDP_DROP: 852 rq->stats.xdp_drop++; 853 return true; 854 } 855 } 856 857 static inline 858 struct sk_buff *skb_from_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, 859 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt) 860 { 861 struct mlx5e_dma_info *di = &wi->di; 862 u16 rx_headroom = rq->buff.headroom; 863 struct sk_buff *skb; 864 void *va, *data; 865 bool consumed; 866 u32 frag_size; 867 868 va = page_address(di->page) + wi->offset; 869 data = va + rx_headroom; 870 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt); 871 872 dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset, 873 frag_size, DMA_FROM_DEVICE); 874 prefetch(data); 875 wi->offset += frag_size; 876 877 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { 878 rq->stats.wqe_err++; 879 return NULL; 880 } 881 882 rcu_read_lock(); 883 consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt); 884 rcu_read_unlock(); 885 if (consumed) 886 return NULL; /* page/packet was consumed by XDP */ 887 888 skb = build_skb(va, frag_size); 889 if (unlikely(!skb)) { 890 rq->stats.buff_alloc_err++; 891 return NULL; 892 } 893 894 /* queue up for recycling/reuse */ 895 page_ref_inc(di->page); 896 897 skb_reserve(skb, rx_headroom); 898 skb_put(skb, cqe_bcnt); 899 900 return skb; 901 } 902 903 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 904 { 905 struct mlx5e_wqe_frag_info *wi; 906 struct mlx5e_rx_wqe *wqe; 907 __be16 wqe_counter_be; 908 struct sk_buff *skb; 909 u16 wqe_counter; 910 u32 cqe_bcnt; 911 912 wqe_counter_be = cqe->wqe_counter; 913 wqe_counter = be16_to_cpu(wqe_counter_be); 914 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 915 wi = &rq->wqe.frag_info[wqe_counter]; 916 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 917 918 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 919 if (!skb) { 920 /* probably for XDP */ 921 if (rq->wqe.xdp_xmit) { 922 wi->di.page = NULL; 923 rq->wqe.xdp_xmit = false; 924 /* do not return page to cache, it will be returned on XDP_TX completion */ 925 goto wq_ll_pop; 926 } 927 /* probably an XDP_DROP, save the page-reuse checks */ 928 mlx5e_free_rx_wqe(rq, wi); 929 goto wq_ll_pop; 930 } 931 932 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 933 napi_gro_receive(rq->cq.napi, skb); 934 935 mlx5e_free_rx_wqe_reuse(rq, wi); 936 wq_ll_pop: 937 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 938 &wqe->next.next_wqe_index); 939 } 940 941 #ifdef CONFIG_MLX5_ESWITCH 942 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 943 { 944 struct net_device *netdev = rq->netdev; 945 struct mlx5e_priv *priv = netdev_priv(netdev); 946 struct mlx5e_rep_priv *rpriv = priv->ppriv; 947 struct mlx5_eswitch_rep *rep = rpriv->rep; 948 struct mlx5e_wqe_frag_info *wi; 949 struct mlx5e_rx_wqe *wqe; 950 struct sk_buff *skb; 951 __be16 wqe_counter_be; 952 u16 wqe_counter; 953 u32 cqe_bcnt; 954 955 wqe_counter_be = cqe->wqe_counter; 956 wqe_counter = be16_to_cpu(wqe_counter_be); 957 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 958 wi = &rq->wqe.frag_info[wqe_counter]; 959 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 960 961 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 962 if (!skb) { 963 if (rq->wqe.xdp_xmit) { 964 wi->di.page = NULL; 965 rq->wqe.xdp_xmit = false; 966 /* do not return page to cache, it will be returned on XDP_TX completion */ 967 goto wq_ll_pop; 968 } 969 /* probably an XDP_DROP, save the page-reuse checks */ 970 mlx5e_free_rx_wqe(rq, wi); 971 goto wq_ll_pop; 972 } 973 974 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 975 976 if (rep->vlan && skb_vlan_tag_present(skb)) 977 skb_vlan_pop(skb); 978 979 napi_gro_receive(rq->cq.napi, skb); 980 981 mlx5e_free_rx_wqe_reuse(rq, wi); 982 wq_ll_pop: 983 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 984 &wqe->next.next_wqe_index); 985 } 986 #endif 987 988 static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq *rq, 989 struct mlx5_cqe64 *cqe, 990 struct mlx5e_mpw_info *wi, 991 u32 cqe_bcnt, 992 struct sk_buff *skb) 993 { 994 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe); 995 u32 wqe_offset = stride_ix << rq->mpwqe.log_stride_sz; 996 u32 head_offset = wqe_offset & (PAGE_SIZE - 1); 997 u32 page_idx = wqe_offset >> PAGE_SHIFT; 998 u32 head_page_idx = page_idx; 999 u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt); 1000 u32 frag_offset = head_offset + headlen; 1001 u16 byte_cnt = cqe_bcnt - headlen; 1002 1003 if (unlikely(frag_offset >= PAGE_SIZE)) { 1004 page_idx++; 1005 frag_offset -= PAGE_SIZE; 1006 } 1007 1008 while (byte_cnt) { 1009 u32 pg_consumed_bytes = 1010 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt); 1011 1012 mlx5e_add_skb_frag_mpwqe(rq, skb, wi, page_idx, frag_offset, 1013 pg_consumed_bytes); 1014 byte_cnt -= pg_consumed_bytes; 1015 frag_offset = 0; 1016 page_idx++; 1017 } 1018 /* copy header */ 1019 mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, wi, head_page_idx, 1020 head_offset, headlen); 1021 /* skb linear part was allocated with headlen and aligned to long */ 1022 skb->tail += headlen; 1023 skb->len += headlen; 1024 } 1025 1026 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1027 { 1028 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe); 1029 u16 wqe_id = be16_to_cpu(cqe->wqe_id); 1030 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id]; 1031 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id); 1032 struct sk_buff *skb; 1033 u16 cqe_bcnt; 1034 1035 wi->consumed_strides += cstrides; 1036 1037 if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { 1038 rq->stats.wqe_err++; 1039 goto mpwrq_cqe_out; 1040 } 1041 1042 if (unlikely(mpwrq_is_filler_cqe(cqe))) { 1043 rq->stats.mpwqe_filler++; 1044 goto mpwrq_cqe_out; 1045 } 1046 1047 skb = napi_alloc_skb(rq->cq.napi, 1048 ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, 1049 sizeof(long))); 1050 if (unlikely(!skb)) { 1051 rq->stats.buff_alloc_err++; 1052 goto mpwrq_cqe_out; 1053 } 1054 1055 prefetchw(skb->data); 1056 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe); 1057 1058 mlx5e_mpwqe_fill_rx_skb(rq, cqe, wi, cqe_bcnt, skb); 1059 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1060 napi_gro_receive(rq->cq.napi, skb); 1061 1062 mpwrq_cqe_out: 1063 if (likely(wi->consumed_strides < rq->mpwqe.num_strides)) 1064 return; 1065 1066 mlx5e_free_rx_mpwqe(rq, wi); 1067 mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index); 1068 } 1069 1070 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget) 1071 { 1072 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq); 1073 struct mlx5e_xdpsq *xdpsq; 1074 struct mlx5_cqe64 *cqe; 1075 int work_done = 0; 1076 1077 if (unlikely(!MLX5E_TEST_BIT(rq->state, MLX5E_RQ_STATE_ENABLED))) 1078 return 0; 1079 1080 if (cq->decmprs_left) 1081 work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget); 1082 1083 cqe = mlx5_cqwq_get_cqe(&cq->wq); 1084 if (!cqe) 1085 return 0; 1086 1087 xdpsq = &rq->xdpsq; 1088 1089 do { 1090 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) { 1091 work_done += 1092 mlx5e_decompress_cqes_start(rq, cq, 1093 budget - work_done); 1094 continue; 1095 } 1096 1097 mlx5_cqwq_pop(&cq->wq); 1098 1099 rq->handle_rx_cqe(rq, cqe); 1100 } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq))); 1101 1102 if (xdpsq->db.doorbell) { 1103 mlx5e_xmit_xdp_doorbell(xdpsq); 1104 xdpsq->db.doorbell = false; 1105 } 1106 1107 mlx5_cqwq_update_db_record(&cq->wq); 1108 1109 /* ensure cq space is freed before enabling more cqes */ 1110 wmb(); 1111 1112 return work_done; 1113 } 1114 1115 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq) 1116 { 1117 struct mlx5e_xdpsq *sq; 1118 struct mlx5_cqe64 *cqe; 1119 struct mlx5e_rq *rq; 1120 u16 sqcc; 1121 int i; 1122 1123 sq = container_of(cq, struct mlx5e_xdpsq, cq); 1124 1125 if (unlikely(!MLX5E_TEST_BIT(sq->state, MLX5E_SQ_STATE_ENABLED))) 1126 return false; 1127 1128 cqe = mlx5_cqwq_get_cqe(&cq->wq); 1129 if (!cqe) 1130 return false; 1131 1132 rq = container_of(sq, struct mlx5e_rq, xdpsq); 1133 1134 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(), 1135 * otherwise a cq overrun may occur 1136 */ 1137 sqcc = sq->cc; 1138 1139 i = 0; 1140 do { 1141 u16 wqe_counter; 1142 bool last_wqe; 1143 1144 mlx5_cqwq_pop(&cq->wq); 1145 1146 wqe_counter = be16_to_cpu(cqe->wqe_counter); 1147 1148 do { 1149 struct mlx5e_dma_info *di; 1150 u16 ci; 1151 1152 last_wqe = (sqcc == wqe_counter); 1153 1154 ci = sqcc & sq->wq.sz_m1; 1155 di = &sq->db.di[ci]; 1156 1157 sqcc++; 1158 /* Recycle RX page */ 1159 mlx5e_page_release(rq, di, true); 1160 } while (!last_wqe); 1161 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq))); 1162 1163 mlx5_cqwq_update_db_record(&cq->wq); 1164 1165 /* ensure cq space is freed before enabling more cqes */ 1166 wmb(); 1167 1168 sq->cc = sqcc; 1169 return (i == MLX5E_TX_CQ_POLL_BUDGET); 1170 } 1171 1172 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq) 1173 { 1174 struct mlx5e_rq *rq = container_of(sq, struct mlx5e_rq, xdpsq); 1175 struct mlx5e_dma_info *di; 1176 u16 ci; 1177 1178 while (sq->cc != sq->pc) { 1179 ci = sq->cc & sq->wq.sz_m1; 1180 di = &sq->db.di[ci]; 1181 sq->cc++; 1182 1183 mlx5e_page_release(rq, di, false); 1184 } 1185 } 1186 1187 #ifdef CONFIG_MLX5_CORE_IPOIB 1188 1189 #define MLX5_IB_GRH_DGID_OFFSET 24 1190 #define MLX5_GID_SIZE 16 1191 1192 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq, 1193 struct mlx5_cqe64 *cqe, 1194 u32 cqe_bcnt, 1195 struct sk_buff *skb) 1196 { 1197 struct hwtstamp_config *tstamp; 1198 struct net_device *netdev; 1199 struct mlx5e_priv *priv; 1200 char *pseudo_header; 1201 u32 qpn; 1202 u8 *dgid; 1203 u8 g; 1204 1205 qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff; 1206 netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn); 1207 1208 /* No mapping present, cannot process SKB. This might happen if a child 1209 * interface is going down while having unprocessed CQEs on parent RQ 1210 */ 1211 if (unlikely(!netdev)) { 1212 /* TODO: add drop counters support */ 1213 skb->dev = NULL; 1214 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn); 1215 return; 1216 } 1217 1218 priv = mlx5i_epriv(netdev); 1219 tstamp = &priv->tstamp; 1220 1221 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3; 1222 dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET; 1223 if ((!g) || dgid[0] != 0xff) 1224 skb->pkt_type = PACKET_HOST; 1225 else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0) 1226 skb->pkt_type = PACKET_BROADCAST; 1227 else 1228 skb->pkt_type = PACKET_MULTICAST; 1229 1230 /* TODO: IB/ipoib: Allow mcast packets from other VFs 1231 * 68996a6e760e5c74654723eeb57bf65628ae87f4 1232 */ 1233 1234 skb_pull(skb, MLX5_IB_GRH_BYTES); 1235 1236 skb->protocol = *((__be16 *)(skb->data)); 1237 1238 skb->ip_summed = CHECKSUM_COMPLETE; 1239 skb->csum = csum_unfold((__force __sum16)cqe->check_sum); 1240 1241 if (unlikely(mlx5e_rx_hw_stamp(tstamp))) 1242 skb_hwtstamps(skb)->hwtstamp = 1243 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe)); 1244 1245 skb_record_rx_queue(skb, rq->ix); 1246 1247 if (likely(netdev->features & NETIF_F_RXHASH)) 1248 mlx5e_skb_set_hash(cqe, skb); 1249 1250 /* 20 bytes of ipoib header and 4 for encap existing */ 1251 pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN); 1252 memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN); 1253 skb_reset_mac_header(skb); 1254 skb_pull(skb, MLX5_IPOIB_HARD_LEN); 1255 1256 skb->dev = netdev; 1257 1258 rq->stats.csum_complete++; 1259 rq->stats.packets++; 1260 rq->stats.bytes += cqe_bcnt; 1261 } 1262 1263 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1264 { 1265 struct mlx5e_wqe_frag_info *wi; 1266 struct mlx5e_rx_wqe *wqe; 1267 __be16 wqe_counter_be; 1268 struct sk_buff *skb; 1269 u16 wqe_counter; 1270 u32 cqe_bcnt; 1271 1272 wqe_counter_be = cqe->wqe_counter; 1273 wqe_counter = be16_to_cpu(wqe_counter_be); 1274 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 1275 wi = &rq->wqe.frag_info[wqe_counter]; 1276 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 1277 1278 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 1279 if (!skb) 1280 goto wq_free_wqe; 1281 1282 mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1283 if (unlikely(!skb->dev)) { 1284 dev_kfree_skb_any(skb); 1285 goto wq_free_wqe; 1286 } 1287 napi_gro_receive(rq->cq.napi, skb); 1288 1289 wq_free_wqe: 1290 mlx5e_free_rx_wqe_reuse(rq, wi); 1291 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 1292 &wqe->next.next_wqe_index); 1293 } 1294 1295 #endif /* CONFIG_MLX5_CORE_IPOIB */ 1296 1297 #ifdef CONFIG_MLX5_EN_IPSEC 1298 1299 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 1300 { 1301 struct mlx5e_wqe_frag_info *wi; 1302 struct mlx5e_rx_wqe *wqe; 1303 __be16 wqe_counter_be; 1304 struct sk_buff *skb; 1305 u16 wqe_counter; 1306 u32 cqe_bcnt; 1307 1308 wqe_counter_be = cqe->wqe_counter; 1309 wqe_counter = be16_to_cpu(wqe_counter_be); 1310 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); 1311 wi = &rq->wqe.frag_info[wqe_counter]; 1312 cqe_bcnt = be32_to_cpu(cqe->byte_cnt); 1313 1314 skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); 1315 if (unlikely(!skb)) { 1316 /* a DROP, save the page-reuse checks */ 1317 mlx5e_free_rx_wqe(rq, wi); 1318 goto wq_ll_pop; 1319 } 1320 skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb); 1321 if (unlikely(!skb)) { 1322 mlx5e_free_rx_wqe(rq, wi); 1323 goto wq_ll_pop; 1324 } 1325 1326 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); 1327 napi_gro_receive(rq->cq.napi, skb); 1328 1329 mlx5e_free_rx_wqe_reuse(rq, wi); 1330 wq_ll_pop: 1331 mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, 1332 &wqe->next.next_wqe_index); 1333 } 1334 1335 #endif /* CONFIG_MLX5_EN_IPSEC */ 1336