1 /* 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <net/tc_act/tc_gact.h> 34 #include <net/pkt_cls.h> 35 #include <linux/mlx5/fs.h> 36 #include <net/vxlan.h> 37 #include <net/geneve.h> 38 #include <linux/bpf.h> 39 #include <linux/if_bridge.h> 40 #include <net/page_pool.h> 41 #include <net/xdp_sock_drv.h> 42 #include "eswitch.h" 43 #include "en.h" 44 #include "en/txrx.h" 45 #include "en_tc.h" 46 #include "en_rep.h" 47 #include "en_accel/ipsec.h" 48 #include "en_accel/en_accel.h" 49 #include "en_accel/tls.h" 50 #include "accel/ipsec.h" 51 #include "accel/tls.h" 52 #include "lib/vxlan.h" 53 #include "lib/clock.h" 54 #include "en/port.h" 55 #include "en/xdp.h" 56 #include "lib/eq.h" 57 #include "en/monitor_stats.h" 58 #include "en/health.h" 59 #include "en/params.h" 60 #include "en/xsk/pool.h" 61 #include "en/xsk/setup.h" 62 #include "en/xsk/rx.h" 63 #include "en/xsk/tx.h" 64 #include "en/hv_vhca_stats.h" 65 #include "en/devlink.h" 66 #include "lib/mlx5.h" 67 #include "en/ptp.h" 68 #include "qos.h" 69 #include "en/trap.h" 70 #include "fpga/ipsec.h" 71 72 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev) 73 { 74 bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) && 75 MLX5_CAP_GEN(mdev, umr_ptr_rlky) && 76 MLX5_CAP_ETH(mdev, reg_umr_sq); 77 u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq); 78 bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap; 79 80 if (!striding_rq_umr) 81 return false; 82 if (!inline_umr) { 83 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n", 84 (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap); 85 return false; 86 } 87 return true; 88 } 89 90 void mlx5e_update_carrier(struct mlx5e_priv *priv) 91 { 92 struct mlx5_core_dev *mdev = priv->mdev; 93 u8 port_state; 94 95 port_state = mlx5_query_vport_state(mdev, 96 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT, 97 0); 98 99 if (port_state == VPORT_STATE_UP) { 100 netdev_info(priv->netdev, "Link up\n"); 101 netif_carrier_on(priv->netdev); 102 } else { 103 netdev_info(priv->netdev, "Link down\n"); 104 netif_carrier_off(priv->netdev); 105 } 106 } 107 108 static void mlx5e_update_carrier_work(struct work_struct *work) 109 { 110 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, 111 update_carrier_work); 112 113 mutex_lock(&priv->state_lock); 114 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) 115 if (priv->profile->update_carrier) 116 priv->profile->update_carrier(priv); 117 mutex_unlock(&priv->state_lock); 118 } 119 120 static void mlx5e_update_stats_work(struct work_struct *work) 121 { 122 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, 123 update_stats_work); 124 125 mutex_lock(&priv->state_lock); 126 priv->profile->update_stats(priv); 127 mutex_unlock(&priv->state_lock); 128 } 129 130 void mlx5e_queue_update_stats(struct mlx5e_priv *priv) 131 { 132 if (!priv->profile->update_stats) 133 return; 134 135 if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state))) 136 return; 137 138 queue_work(priv->wq, &priv->update_stats_work); 139 } 140 141 static int async_event(struct notifier_block *nb, unsigned long event, void *data) 142 { 143 struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb); 144 struct mlx5_eqe *eqe = data; 145 146 if (event != MLX5_EVENT_TYPE_PORT_CHANGE) 147 return NOTIFY_DONE; 148 149 switch (eqe->sub_type) { 150 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 151 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 152 queue_work(priv->wq, &priv->update_carrier_work); 153 break; 154 default: 155 return NOTIFY_DONE; 156 } 157 158 return NOTIFY_OK; 159 } 160 161 static void mlx5e_enable_async_events(struct mlx5e_priv *priv) 162 { 163 priv->events_nb.notifier_call = async_event; 164 mlx5_notifier_register(priv->mdev, &priv->events_nb); 165 } 166 167 static void mlx5e_disable_async_events(struct mlx5e_priv *priv) 168 { 169 mlx5_notifier_unregister(priv->mdev, &priv->events_nb); 170 } 171 172 static int blocking_event(struct notifier_block *nb, unsigned long event, void *data) 173 { 174 struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, blocking_events_nb); 175 int err; 176 177 switch (event) { 178 case MLX5_DRIVER_EVENT_TYPE_TRAP: 179 err = mlx5e_handle_trap_event(priv, data); 180 break; 181 default: 182 netdev_warn(priv->netdev, "Sync event: Unknown event %ld\n", event); 183 err = -EINVAL; 184 } 185 return err; 186 } 187 188 static void mlx5e_enable_blocking_events(struct mlx5e_priv *priv) 189 { 190 priv->blocking_events_nb.notifier_call = blocking_event; 191 mlx5_blocking_notifier_register(priv->mdev, &priv->blocking_events_nb); 192 } 193 194 static void mlx5e_disable_blocking_events(struct mlx5e_priv *priv) 195 { 196 mlx5_blocking_notifier_unregister(priv->mdev, &priv->blocking_events_nb); 197 } 198 199 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, 200 struct mlx5e_icosq *sq, 201 struct mlx5e_umr_wqe *wqe) 202 { 203 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; 204 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl; 205 u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS); 206 207 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) | 208 ds_cnt); 209 cseg->umr_mkey = rq->mkey_be; 210 211 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE; 212 ucseg->xlt_octowords = 213 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE)); 214 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 215 } 216 217 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, int node) 218 { 219 int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq); 220 221 rq->mpwqe.info = kvzalloc_node(array_size(wq_sz, 222 sizeof(*rq->mpwqe.info)), 223 GFP_KERNEL, node); 224 if (!rq->mpwqe.info) 225 return -ENOMEM; 226 227 mlx5e_build_umr_wqe(rq, rq->icosq, &rq->mpwqe.umr_wqe); 228 229 return 0; 230 } 231 232 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev, 233 u64 npages, u8 page_shift, 234 struct mlx5_core_mkey *umr_mkey, 235 dma_addr_t filler_addr) 236 { 237 struct mlx5_mtt *mtt; 238 int inlen; 239 void *mkc; 240 u32 *in; 241 int err; 242 int i; 243 244 inlen = MLX5_ST_SZ_BYTES(create_mkey_in) + sizeof(*mtt) * npages; 245 246 in = kvzalloc(inlen, GFP_KERNEL); 247 if (!in) 248 return -ENOMEM; 249 250 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 251 252 MLX5_SET(mkc, mkc, free, 1); 253 MLX5_SET(mkc, mkc, umr_en, 1); 254 MLX5_SET(mkc, mkc, lw, 1); 255 MLX5_SET(mkc, mkc, lr, 1); 256 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 257 mlx5e_mkey_set_relaxed_ordering(mdev, mkc); 258 MLX5_SET(mkc, mkc, qpn, 0xffffff); 259 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn); 260 MLX5_SET64(mkc, mkc, len, npages << page_shift); 261 MLX5_SET(mkc, mkc, translations_octword_size, 262 MLX5_MTT_OCTW(npages)); 263 MLX5_SET(mkc, mkc, log_page_size, page_shift); 264 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 265 MLX5_MTT_OCTW(npages)); 266 267 /* Initialize the mkey with all MTTs pointing to a default 268 * page (filler_addr). When the channels are activated, UMR 269 * WQEs will redirect the RX WQEs to the actual memory from 270 * the RQ's pool, while the gaps (wqe_overflow) remain mapped 271 * to the default page. 272 */ 273 mtt = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt); 274 for (i = 0 ; i < npages ; i++) 275 mtt[i].ptag = cpu_to_be64(filler_addr); 276 277 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen); 278 279 kvfree(in); 280 return err; 281 } 282 283 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq) 284 { 285 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq)); 286 287 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey, 288 rq->wqe_overflow.addr); 289 } 290 291 static u64 mlx5e_get_mpwqe_offset(u16 wqe_ix) 292 { 293 return MLX5E_REQUIRED_MTTS(wqe_ix) << PAGE_SHIFT; 294 } 295 296 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq) 297 { 298 struct mlx5e_wqe_frag_info next_frag = {}; 299 struct mlx5e_wqe_frag_info *prev = NULL; 300 int i; 301 302 next_frag.di = &rq->wqe.di[0]; 303 304 for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) { 305 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0]; 306 struct mlx5e_wqe_frag_info *frag = 307 &rq->wqe.frags[i << rq->wqe.info.log_num_frags]; 308 int f; 309 310 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) { 311 if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) { 312 next_frag.di++; 313 next_frag.offset = 0; 314 if (prev) 315 prev->last_in_page = true; 316 } 317 *frag = next_frag; 318 319 /* prepare next */ 320 next_frag.offset += frag_info[f].frag_stride; 321 prev = frag; 322 } 323 } 324 325 if (prev) 326 prev->last_in_page = true; 327 } 328 329 int mlx5e_init_di_list(struct mlx5e_rq *rq, int wq_sz, int node) 330 { 331 int len = wq_sz << rq->wqe.info.log_num_frags; 332 333 rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)), GFP_KERNEL, node); 334 if (!rq->wqe.di) 335 return -ENOMEM; 336 337 mlx5e_init_frags_partition(rq); 338 339 return 0; 340 } 341 342 void mlx5e_free_di_list(struct mlx5e_rq *rq) 343 { 344 kvfree(rq->wqe.di); 345 } 346 347 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work) 348 { 349 struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work); 350 351 mlx5e_reporter_rq_cqe_err(rq); 352 } 353 354 static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq *rq) 355 { 356 rq->wqe_overflow.page = alloc_page(GFP_KERNEL); 357 if (!rq->wqe_overflow.page) 358 return -ENOMEM; 359 360 rq->wqe_overflow.addr = dma_map_page(rq->pdev, rq->wqe_overflow.page, 0, 361 PAGE_SIZE, rq->buff.map_dir); 362 if (dma_mapping_error(rq->pdev, rq->wqe_overflow.addr)) { 363 __free_page(rq->wqe_overflow.page); 364 return -ENOMEM; 365 } 366 return 0; 367 } 368 369 static void mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq *rq) 370 { 371 dma_unmap_page(rq->pdev, rq->wqe_overflow.addr, PAGE_SIZE, 372 rq->buff.map_dir); 373 __free_page(rq->wqe_overflow.page); 374 } 375 376 static int mlx5e_init_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params, 377 struct mlx5e_rq *rq) 378 { 379 struct mlx5_core_dev *mdev = c->mdev; 380 int err; 381 382 rq->wq_type = params->rq_wq_type; 383 rq->pdev = c->pdev; 384 rq->netdev = c->netdev; 385 rq->priv = c->priv; 386 rq->tstamp = c->tstamp; 387 rq->clock = &mdev->clock; 388 rq->icosq = &c->icosq; 389 rq->ix = c->ix; 390 rq->mdev = mdev; 391 rq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu); 392 rq->xdpsq = &c->rq_xdpsq; 393 rq->stats = &c->priv->channel_stats[c->ix].rq; 394 rq->ptp_cyc2time = mlx5_rq_ts_translator(mdev); 395 err = mlx5e_rq_set_handlers(rq, params, NULL); 396 if (err) 397 return err; 398 399 return xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix, 0); 400 } 401 402 static int mlx5e_alloc_rq(struct mlx5e_params *params, 403 struct mlx5e_xsk_param *xsk, 404 struct mlx5e_rq_param *rqp, 405 int node, struct mlx5e_rq *rq) 406 { 407 struct page_pool_params pp_params = { 0 }; 408 struct mlx5_core_dev *mdev = rq->mdev; 409 void *rqc = rqp->rqc; 410 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); 411 u32 pool_size; 412 int wq_sz; 413 int err; 414 int i; 415 416 rqp->wq.db_numa_node = node; 417 INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work); 418 419 if (params->xdp_prog) 420 bpf_prog_inc(params->xdp_prog); 421 RCU_INIT_POINTER(rq->xdp_prog, params->xdp_prog); 422 423 rq->buff.map_dir = params->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; 424 rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk); 425 pool_size = 1 << params->log_rq_mtu_frames; 426 427 switch (rq->wq_type) { 428 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 429 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq, 430 &rq->wq_ctrl); 431 if (err) 432 goto err_rq_xdp_prog; 433 434 err = mlx5e_alloc_mpwqe_rq_drop_page(rq); 435 if (err) 436 goto err_rq_wq_destroy; 437 438 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR]; 439 440 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq); 441 442 pool_size = MLX5_MPWRQ_PAGES_PER_WQE << 443 mlx5e_mpwqe_get_log_rq_size(params, xsk); 444 445 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk); 446 rq->mpwqe.num_strides = 447 BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk)); 448 449 rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz); 450 451 err = mlx5e_create_rq_umr_mkey(mdev, rq); 452 if (err) 453 goto err_rq_drop_page; 454 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key); 455 456 err = mlx5e_rq_alloc_mpwqe_info(rq, node); 457 if (err) 458 goto err_rq_mkey; 459 break; 460 default: /* MLX5_WQ_TYPE_CYCLIC */ 461 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq, 462 &rq->wq_ctrl); 463 if (err) 464 goto err_rq_xdp_prog; 465 466 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR]; 467 468 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq); 469 470 rq->wqe.info = rqp->frags_info; 471 rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride; 472 473 rq->wqe.frags = 474 kvzalloc_node(array_size(sizeof(*rq->wqe.frags), 475 (wq_sz << rq->wqe.info.log_num_frags)), 476 GFP_KERNEL, node); 477 if (!rq->wqe.frags) { 478 err = -ENOMEM; 479 goto err_rq_wq_destroy; 480 } 481 482 err = mlx5e_init_di_list(rq, wq_sz, node); 483 if (err) 484 goto err_rq_frags; 485 486 rq->mkey_be = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey.key); 487 } 488 489 if (xsk) { 490 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq, 491 MEM_TYPE_XSK_BUFF_POOL, NULL); 492 xsk_pool_set_rxq_info(rq->xsk_pool, &rq->xdp_rxq); 493 } else { 494 /* Create a page_pool and register it with rxq */ 495 pp_params.order = 0; 496 pp_params.flags = 0; /* No-internal DMA mapping in page_pool */ 497 pp_params.pool_size = pool_size; 498 pp_params.nid = node; 499 pp_params.dev = rq->pdev; 500 pp_params.dma_dir = rq->buff.map_dir; 501 502 /* page_pool can be used even when there is no rq->xdp_prog, 503 * given page_pool does not handle DMA mapping there is no 504 * required state to clear. And page_pool gracefully handle 505 * elevated refcnt. 506 */ 507 rq->page_pool = page_pool_create(&pp_params); 508 if (IS_ERR(rq->page_pool)) { 509 err = PTR_ERR(rq->page_pool); 510 rq->page_pool = NULL; 511 goto err_free_by_rq_type; 512 } 513 if (xdp_rxq_info_is_reg(&rq->xdp_rxq)) 514 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq, 515 MEM_TYPE_PAGE_POOL, rq->page_pool); 516 } 517 if (err) 518 goto err_free_by_rq_type; 519 520 for (i = 0; i < wq_sz; i++) { 521 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) { 522 struct mlx5e_rx_wqe_ll *wqe = 523 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i); 524 u32 byte_count = 525 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz; 526 u64 dma_offset = mlx5e_get_mpwqe_offset(i); 527 528 wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom); 529 wqe->data[0].byte_count = cpu_to_be32(byte_count); 530 wqe->data[0].lkey = rq->mkey_be; 531 } else { 532 struct mlx5e_rx_wqe_cyc *wqe = 533 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i); 534 int f; 535 536 for (f = 0; f < rq->wqe.info.num_frags; f++) { 537 u32 frag_size = rq->wqe.info.arr[f].frag_size | 538 MLX5_HW_START_PADDING; 539 540 wqe->data[f].byte_count = cpu_to_be32(frag_size); 541 wqe->data[f].lkey = rq->mkey_be; 542 } 543 /* check if num_frags is not a pow of two */ 544 if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) { 545 wqe->data[f].byte_count = 0; 546 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 547 wqe->data[f].addr = 0; 548 } 549 } 550 } 551 552 INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work); 553 554 switch (params->rx_cq_moderation.cq_period_mode) { 555 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE: 556 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE; 557 break; 558 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE: 559 default: 560 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 561 } 562 563 rq->page_cache.head = 0; 564 rq->page_cache.tail = 0; 565 566 return 0; 567 568 err_free_by_rq_type: 569 switch (rq->wq_type) { 570 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 571 kvfree(rq->mpwqe.info); 572 err_rq_mkey: 573 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey); 574 err_rq_drop_page: 575 mlx5e_free_mpwqe_rq_drop_page(rq); 576 break; 577 default: /* MLX5_WQ_TYPE_CYCLIC */ 578 mlx5e_free_di_list(rq); 579 err_rq_frags: 580 kvfree(rq->wqe.frags); 581 } 582 err_rq_wq_destroy: 583 mlx5_wq_destroy(&rq->wq_ctrl); 584 err_rq_xdp_prog: 585 if (params->xdp_prog) 586 bpf_prog_put(params->xdp_prog); 587 588 return err; 589 } 590 591 static void mlx5e_free_rq(struct mlx5e_rq *rq) 592 { 593 struct bpf_prog *old_prog; 594 int i; 595 596 if (xdp_rxq_info_is_reg(&rq->xdp_rxq)) { 597 old_prog = rcu_dereference_protected(rq->xdp_prog, 598 lockdep_is_held(&rq->priv->state_lock)); 599 if (old_prog) 600 bpf_prog_put(old_prog); 601 } 602 603 switch (rq->wq_type) { 604 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 605 kvfree(rq->mpwqe.info); 606 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey); 607 mlx5e_free_mpwqe_rq_drop_page(rq); 608 break; 609 default: /* MLX5_WQ_TYPE_CYCLIC */ 610 kvfree(rq->wqe.frags); 611 mlx5e_free_di_list(rq); 612 } 613 614 for (i = rq->page_cache.head; i != rq->page_cache.tail; 615 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) { 616 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i]; 617 618 /* With AF_XDP, page_cache is not used, so this loop is not 619 * entered, and it's safe to call mlx5e_page_release_dynamic 620 * directly. 621 */ 622 mlx5e_page_release_dynamic(rq, dma_info, false); 623 } 624 625 xdp_rxq_info_unreg(&rq->xdp_rxq); 626 page_pool_destroy(rq->page_pool); 627 mlx5_wq_destroy(&rq->wq_ctrl); 628 } 629 630 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param) 631 { 632 struct mlx5_core_dev *mdev = rq->mdev; 633 u8 ts_format; 634 void *in; 635 void *rqc; 636 void *wq; 637 int inlen; 638 int err; 639 640 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + 641 sizeof(u64) * rq->wq_ctrl.buf.npages; 642 in = kvzalloc(inlen, GFP_KERNEL); 643 if (!in) 644 return -ENOMEM; 645 646 ts_format = mlx5_is_real_time_rq(mdev) ? 647 MLX5_RQC_TIMESTAMP_FORMAT_REAL_TIME : 648 MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING; 649 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 650 wq = MLX5_ADDR_OF(rqc, rqc, wq); 651 652 memcpy(rqc, param->rqc, sizeof(param->rqc)); 653 654 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn); 655 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 656 MLX5_SET(rqc, rqc, ts_format, ts_format); 657 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift - 658 MLX5_ADAPTER_PAGE_SHIFT); 659 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma); 660 661 mlx5_fill_page_frag_array(&rq->wq_ctrl.buf, 662 (__be64 *)MLX5_ADDR_OF(wq, wq, pas)); 663 664 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn); 665 666 kvfree(in); 667 668 return err; 669 } 670 671 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state) 672 { 673 struct mlx5_core_dev *mdev = rq->mdev; 674 675 void *in; 676 void *rqc; 677 int inlen; 678 int err; 679 680 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 681 in = kvzalloc(inlen, GFP_KERNEL); 682 if (!in) 683 return -ENOMEM; 684 685 if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY) 686 mlx5e_rqwq_reset(rq); 687 688 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 689 690 MLX5_SET(modify_rq_in, in, rq_state, curr_state); 691 MLX5_SET(rqc, rqc, state, next_state); 692 693 err = mlx5_core_modify_rq(mdev, rq->rqn, in); 694 695 kvfree(in); 696 697 return err; 698 } 699 700 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable) 701 { 702 struct mlx5_core_dev *mdev = rq->mdev; 703 704 void *in; 705 void *rqc; 706 int inlen; 707 int err; 708 709 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 710 in = kvzalloc(inlen, GFP_KERNEL); 711 if (!in) 712 return -ENOMEM; 713 714 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 715 716 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY); 717 MLX5_SET64(modify_rq_in, in, modify_bitmask, 718 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS); 719 MLX5_SET(rqc, rqc, scatter_fcs, enable); 720 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY); 721 722 err = mlx5_core_modify_rq(mdev, rq->rqn, in); 723 724 kvfree(in); 725 726 return err; 727 } 728 729 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd) 730 { 731 struct mlx5_core_dev *mdev = rq->mdev; 732 void *in; 733 void *rqc; 734 int inlen; 735 int err; 736 737 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 738 in = kvzalloc(inlen, GFP_KERNEL); 739 if (!in) 740 return -ENOMEM; 741 742 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 743 744 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY); 745 MLX5_SET64(modify_rq_in, in, modify_bitmask, 746 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); 747 MLX5_SET(rqc, rqc, vsd, vsd); 748 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY); 749 750 err = mlx5_core_modify_rq(mdev, rq->rqn, in); 751 752 kvfree(in); 753 754 return err; 755 } 756 757 void mlx5e_destroy_rq(struct mlx5e_rq *rq) 758 { 759 mlx5_core_destroy_rq(rq->mdev, rq->rqn); 760 } 761 762 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time) 763 { 764 unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time); 765 766 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq)); 767 768 do { 769 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes) 770 return 0; 771 772 msleep(20); 773 } while (time_before(jiffies, exp_time)); 774 775 netdev_warn(rq->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n", 776 rq->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes); 777 778 mlx5e_reporter_rx_timeout(rq); 779 return -ETIMEDOUT; 780 } 781 782 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq *rq) 783 { 784 struct mlx5_wq_ll *wq; 785 u16 head; 786 int i; 787 788 if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) 789 return; 790 791 wq = &rq->mpwqe.wq; 792 head = wq->head; 793 794 /* Outstanding UMR WQEs (in progress) start at wq->head */ 795 for (i = 0; i < rq->mpwqe.umr_in_progress; i++) { 796 rq->dealloc_wqe(rq, head); 797 head = mlx5_wq_ll_get_wqe_next_ix(wq, head); 798 } 799 800 rq->mpwqe.actual_wq_head = wq->head; 801 rq->mpwqe.umr_in_progress = 0; 802 rq->mpwqe.umr_completed = 0; 803 } 804 805 void mlx5e_free_rx_descs(struct mlx5e_rq *rq) 806 { 807 __be16 wqe_ix_be; 808 u16 wqe_ix; 809 810 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) { 811 struct mlx5_wq_ll *wq = &rq->mpwqe.wq; 812 813 mlx5e_free_rx_in_progress_descs(rq); 814 815 while (!mlx5_wq_ll_is_empty(wq)) { 816 struct mlx5e_rx_wqe_ll *wqe; 817 818 wqe_ix_be = *wq->tail_next; 819 wqe_ix = be16_to_cpu(wqe_ix_be); 820 wqe = mlx5_wq_ll_get_wqe(wq, wqe_ix); 821 rq->dealloc_wqe(rq, wqe_ix); 822 mlx5_wq_ll_pop(wq, wqe_ix_be, 823 &wqe->next.next_wqe_index); 824 } 825 } else { 826 struct mlx5_wq_cyc *wq = &rq->wqe.wq; 827 828 while (!mlx5_wq_cyc_is_empty(wq)) { 829 wqe_ix = mlx5_wq_cyc_get_tail(wq); 830 rq->dealloc_wqe(rq, wqe_ix); 831 mlx5_wq_cyc_pop(wq); 832 } 833 } 834 835 } 836 837 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param, 838 struct mlx5e_xsk_param *xsk, int node, 839 struct mlx5e_rq *rq) 840 { 841 struct mlx5_core_dev *mdev = rq->mdev; 842 int err; 843 844 err = mlx5e_alloc_rq(params, xsk, param, node, rq); 845 if (err) 846 return err; 847 848 err = mlx5e_create_rq(rq, param); 849 if (err) 850 goto err_free_rq; 851 852 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 853 if (err) 854 goto err_destroy_rq; 855 856 if (mlx5e_is_tls_on(rq->priv) && !mlx5_accel_is_ktls_device(mdev)) 857 __set_bit(MLX5E_RQ_STATE_FPGA_TLS, &rq->state); /* must be FPGA */ 858 859 if (MLX5_CAP_ETH(mdev, cqe_checksum_full)) 860 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state); 861 862 if (params->rx_dim_enabled) 863 __set_bit(MLX5E_RQ_STATE_AM, &rq->state); 864 865 /* We disable csum_complete when XDP is enabled since 866 * XDP programs might manipulate packets which will render 867 * skb->checksum incorrect. 868 */ 869 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || params->xdp_prog) 870 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state); 871 872 /* For CQE compression on striding RQ, use stride index provided by 873 * HW if capability is supported. 874 */ 875 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) && 876 MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index)) 877 __set_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &rq->state); 878 879 return 0; 880 881 err_destroy_rq: 882 mlx5e_destroy_rq(rq); 883 err_free_rq: 884 mlx5e_free_rq(rq); 885 886 return err; 887 } 888 889 void mlx5e_activate_rq(struct mlx5e_rq *rq) 890 { 891 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state); 892 if (rq->icosq) 893 mlx5e_trigger_irq(rq->icosq); 894 else 895 napi_schedule(rq->cq.napi); 896 } 897 898 void mlx5e_deactivate_rq(struct mlx5e_rq *rq) 899 { 900 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state); 901 synchronize_net(); /* Sync with NAPI to prevent mlx5e_post_rx_wqes. */ 902 } 903 904 void mlx5e_close_rq(struct mlx5e_rq *rq) 905 { 906 cancel_work_sync(&rq->dim.work); 907 if (rq->icosq) 908 cancel_work_sync(&rq->icosq->recover_work); 909 cancel_work_sync(&rq->recover_work); 910 mlx5e_destroy_rq(rq); 911 mlx5e_free_rx_descs(rq); 912 mlx5e_free_rq(rq); 913 } 914 915 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq) 916 { 917 kvfree(sq->db.xdpi_fifo.xi); 918 kvfree(sq->db.wqe_info); 919 } 920 921 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa) 922 { 923 struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo; 924 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 925 int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS; 926 927 xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq, 928 GFP_KERNEL, numa); 929 if (!xdpi_fifo->xi) 930 return -ENOMEM; 931 932 xdpi_fifo->pc = &sq->xdpi_fifo_pc; 933 xdpi_fifo->cc = &sq->xdpi_fifo_cc; 934 xdpi_fifo->mask = dsegs_per_wq - 1; 935 936 return 0; 937 } 938 939 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa) 940 { 941 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 942 int err; 943 944 sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz, 945 GFP_KERNEL, numa); 946 if (!sq->db.wqe_info) 947 return -ENOMEM; 948 949 err = mlx5e_alloc_xdpsq_fifo(sq, numa); 950 if (err) { 951 mlx5e_free_xdpsq_db(sq); 952 return err; 953 } 954 955 return 0; 956 } 957 958 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c, 959 struct mlx5e_params *params, 960 struct xsk_buff_pool *xsk_pool, 961 struct mlx5e_sq_param *param, 962 struct mlx5e_xdpsq *sq, 963 bool is_redirect) 964 { 965 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq); 966 struct mlx5_core_dev *mdev = c->mdev; 967 struct mlx5_wq_cyc *wq = &sq->wq; 968 int err; 969 970 sq->pdev = c->pdev; 971 sq->mkey_be = c->mkey_be; 972 sq->channel = c; 973 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map; 974 sq->min_inline_mode = params->tx_min_inline_mode; 975 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu); 976 sq->xsk_pool = xsk_pool; 977 978 sq->stats = sq->xsk_pool ? 979 &c->priv->channel_stats[c->ix].xsksq : 980 is_redirect ? 981 &c->priv->channel_stats[c->ix].xdpsq : 982 &c->priv->channel_stats[c->ix].rq_xdpsq; 983 984 param->wq.db_numa_node = cpu_to_node(c->cpu); 985 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl); 986 if (err) 987 return err; 988 wq->db = &wq->db[MLX5_SND_DBR]; 989 990 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu)); 991 if (err) 992 goto err_sq_wq_destroy; 993 994 return 0; 995 996 err_sq_wq_destroy: 997 mlx5_wq_destroy(&sq->wq_ctrl); 998 999 return err; 1000 } 1001 1002 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq) 1003 { 1004 mlx5e_free_xdpsq_db(sq); 1005 mlx5_wq_destroy(&sq->wq_ctrl); 1006 } 1007 1008 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq) 1009 { 1010 kvfree(sq->db.wqe_info); 1011 } 1012 1013 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa) 1014 { 1015 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1016 size_t size; 1017 1018 size = array_size(wq_sz, sizeof(*sq->db.wqe_info)); 1019 sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa); 1020 if (!sq->db.wqe_info) 1021 return -ENOMEM; 1022 1023 return 0; 1024 } 1025 1026 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work) 1027 { 1028 struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq, 1029 recover_work); 1030 1031 mlx5e_reporter_icosq_cqe_err(sq); 1032 } 1033 1034 static int mlx5e_alloc_icosq(struct mlx5e_channel *c, 1035 struct mlx5e_sq_param *param, 1036 struct mlx5e_icosq *sq) 1037 { 1038 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq); 1039 struct mlx5_core_dev *mdev = c->mdev; 1040 struct mlx5_wq_cyc *wq = &sq->wq; 1041 int err; 1042 1043 sq->channel = c; 1044 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map; 1045 sq->reserved_room = param->stop_room; 1046 1047 param->wq.db_numa_node = cpu_to_node(c->cpu); 1048 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl); 1049 if (err) 1050 return err; 1051 wq->db = &wq->db[MLX5_SND_DBR]; 1052 1053 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu)); 1054 if (err) 1055 goto err_sq_wq_destroy; 1056 1057 INIT_WORK(&sq->recover_work, mlx5e_icosq_err_cqe_work); 1058 1059 return 0; 1060 1061 err_sq_wq_destroy: 1062 mlx5_wq_destroy(&sq->wq_ctrl); 1063 1064 return err; 1065 } 1066 1067 static void mlx5e_free_icosq(struct mlx5e_icosq *sq) 1068 { 1069 mlx5e_free_icosq_db(sq); 1070 mlx5_wq_destroy(&sq->wq_ctrl); 1071 } 1072 1073 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq) 1074 { 1075 kvfree(sq->db.wqe_info); 1076 kvfree(sq->db.skb_fifo.fifo); 1077 kvfree(sq->db.dma_fifo); 1078 } 1079 1080 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa) 1081 { 1082 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1083 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS; 1084 1085 sq->db.dma_fifo = kvzalloc_node(array_size(df_sz, 1086 sizeof(*sq->db.dma_fifo)), 1087 GFP_KERNEL, numa); 1088 sq->db.skb_fifo.fifo = kvzalloc_node(array_size(df_sz, 1089 sizeof(*sq->db.skb_fifo.fifo)), 1090 GFP_KERNEL, numa); 1091 sq->db.wqe_info = kvzalloc_node(array_size(wq_sz, 1092 sizeof(*sq->db.wqe_info)), 1093 GFP_KERNEL, numa); 1094 if (!sq->db.dma_fifo || !sq->db.skb_fifo.fifo || !sq->db.wqe_info) { 1095 mlx5e_free_txqsq_db(sq); 1096 return -ENOMEM; 1097 } 1098 1099 sq->dma_fifo_mask = df_sz - 1; 1100 1101 sq->db.skb_fifo.pc = &sq->skb_fifo_pc; 1102 sq->db.skb_fifo.cc = &sq->skb_fifo_cc; 1103 sq->db.skb_fifo.mask = df_sz - 1; 1104 1105 return 0; 1106 } 1107 1108 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c, 1109 int txq_ix, 1110 struct mlx5e_params *params, 1111 struct mlx5e_sq_param *param, 1112 struct mlx5e_txqsq *sq, 1113 int tc) 1114 { 1115 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq); 1116 struct mlx5_core_dev *mdev = c->mdev; 1117 struct mlx5_wq_cyc *wq = &sq->wq; 1118 int err; 1119 1120 sq->pdev = c->pdev; 1121 sq->tstamp = c->tstamp; 1122 sq->clock = &mdev->clock; 1123 sq->mkey_be = c->mkey_be; 1124 sq->netdev = c->netdev; 1125 sq->mdev = c->mdev; 1126 sq->priv = c->priv; 1127 sq->ch_ix = c->ix; 1128 sq->txq_ix = txq_ix; 1129 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map; 1130 sq->min_inline_mode = params->tx_min_inline_mode; 1131 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu); 1132 INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work); 1133 if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert)) 1134 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state); 1135 if (MLX5_IPSEC_DEV(c->priv->mdev)) 1136 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state); 1137 if (param->is_mpw) 1138 set_bit(MLX5E_SQ_STATE_MPWQE, &sq->state); 1139 sq->stop_room = param->stop_room; 1140 sq->ptp_cyc2time = mlx5_sq_ts_translator(mdev); 1141 1142 param->wq.db_numa_node = cpu_to_node(c->cpu); 1143 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl); 1144 if (err) 1145 return err; 1146 wq->db = &wq->db[MLX5_SND_DBR]; 1147 1148 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu)); 1149 if (err) 1150 goto err_sq_wq_destroy; 1151 1152 INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work); 1153 sq->dim.mode = params->tx_cq_moderation.cq_period_mode; 1154 1155 return 0; 1156 1157 err_sq_wq_destroy: 1158 mlx5_wq_destroy(&sq->wq_ctrl); 1159 1160 return err; 1161 } 1162 1163 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq) 1164 { 1165 mlx5e_free_txqsq_db(sq); 1166 mlx5_wq_destroy(&sq->wq_ctrl); 1167 } 1168 1169 static int mlx5e_create_sq(struct mlx5_core_dev *mdev, 1170 struct mlx5e_sq_param *param, 1171 struct mlx5e_create_sq_param *csp, 1172 u32 *sqn) 1173 { 1174 u8 ts_format; 1175 void *in; 1176 void *sqc; 1177 void *wq; 1178 int inlen; 1179 int err; 1180 1181 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + 1182 sizeof(u64) * csp->wq_ctrl->buf.npages; 1183 in = kvzalloc(inlen, GFP_KERNEL); 1184 if (!in) 1185 return -ENOMEM; 1186 1187 ts_format = mlx5_is_real_time_sq(mdev) ? 1188 MLX5_SQC_TIMESTAMP_FORMAT_REAL_TIME : 1189 MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING; 1190 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1191 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1192 1193 memcpy(sqc, param->sqc, sizeof(param->sqc)); 1194 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz); 1195 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn); 1196 MLX5_SET(sqc, sqc, cqn, csp->cqn); 1197 MLX5_SET(sqc, sqc, ts_cqe_to_dest_cqn, csp->ts_cqe_to_dest_cqn); 1198 MLX5_SET(sqc, sqc, ts_format, ts_format); 1199 1200 1201 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) 1202 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode); 1203 1204 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1205 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1206 1207 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1208 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.hw_objs.bfreg.index); 1209 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift - 1210 MLX5_ADAPTER_PAGE_SHIFT); 1211 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma); 1212 1213 mlx5_fill_page_frag_array(&csp->wq_ctrl->buf, 1214 (__be64 *)MLX5_ADDR_OF(wq, wq, pas)); 1215 1216 err = mlx5_core_create_sq(mdev, in, inlen, sqn); 1217 1218 kvfree(in); 1219 1220 return err; 1221 } 1222 1223 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn, 1224 struct mlx5e_modify_sq_param *p) 1225 { 1226 u64 bitmask = 0; 1227 void *in; 1228 void *sqc; 1229 int inlen; 1230 int err; 1231 1232 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 1233 in = kvzalloc(inlen, GFP_KERNEL); 1234 if (!in) 1235 return -ENOMEM; 1236 1237 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1238 1239 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state); 1240 MLX5_SET(sqc, sqc, state, p->next_state); 1241 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) { 1242 bitmask |= 1; 1243 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index); 1244 } 1245 if (p->qos_update && p->next_state == MLX5_SQC_STATE_RDY) { 1246 bitmask |= 1 << 2; 1247 MLX5_SET(sqc, sqc, qos_queue_group_id, p->qos_queue_group_id); 1248 } 1249 MLX5_SET64(modify_sq_in, in, modify_bitmask, bitmask); 1250 1251 err = mlx5_core_modify_sq(mdev, sqn, in); 1252 1253 kvfree(in); 1254 1255 return err; 1256 } 1257 1258 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn) 1259 { 1260 mlx5_core_destroy_sq(mdev, sqn); 1261 } 1262 1263 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev, 1264 struct mlx5e_sq_param *param, 1265 struct mlx5e_create_sq_param *csp, 1266 u16 qos_queue_group_id, 1267 u32 *sqn) 1268 { 1269 struct mlx5e_modify_sq_param msp = {0}; 1270 int err; 1271 1272 err = mlx5e_create_sq(mdev, param, csp, sqn); 1273 if (err) 1274 return err; 1275 1276 msp.curr_state = MLX5_SQC_STATE_RST; 1277 msp.next_state = MLX5_SQC_STATE_RDY; 1278 if (qos_queue_group_id) { 1279 msp.qos_update = true; 1280 msp.qos_queue_group_id = qos_queue_group_id; 1281 } 1282 err = mlx5e_modify_sq(mdev, *sqn, &msp); 1283 if (err) 1284 mlx5e_destroy_sq(mdev, *sqn); 1285 1286 return err; 1287 } 1288 1289 static int mlx5e_set_sq_maxrate(struct net_device *dev, 1290 struct mlx5e_txqsq *sq, u32 rate); 1291 1292 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix, 1293 struct mlx5e_params *params, struct mlx5e_sq_param *param, 1294 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id, u16 qos_qid) 1295 { 1296 struct mlx5e_create_sq_param csp = {}; 1297 u32 tx_rate; 1298 int err; 1299 1300 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc); 1301 if (err) 1302 return err; 1303 1304 if (qos_queue_group_id) 1305 sq->stats = c->priv->htb.qos_sq_stats[qos_qid]; 1306 else 1307 sq->stats = &c->priv->channel_stats[c->ix].sq[tc]; 1308 1309 csp.tisn = tisn; 1310 csp.tis_lst_sz = 1; 1311 csp.cqn = sq->cq.mcq.cqn; 1312 csp.wq_ctrl = &sq->wq_ctrl; 1313 csp.min_inline_mode = sq->min_inline_mode; 1314 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, qos_queue_group_id, &sq->sqn); 1315 if (err) 1316 goto err_free_txqsq; 1317 1318 tx_rate = c->priv->tx_rates[sq->txq_ix]; 1319 if (tx_rate) 1320 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate); 1321 1322 if (params->tx_dim_enabled) 1323 sq->state |= BIT(MLX5E_SQ_STATE_AM); 1324 1325 return 0; 1326 1327 err_free_txqsq: 1328 mlx5e_free_txqsq(sq); 1329 1330 return err; 1331 } 1332 1333 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq) 1334 { 1335 sq->txq = netdev_get_tx_queue(sq->netdev, sq->txq_ix); 1336 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); 1337 netdev_tx_reset_queue(sq->txq); 1338 netif_tx_start_queue(sq->txq); 1339 } 1340 1341 void mlx5e_tx_disable_queue(struct netdev_queue *txq) 1342 { 1343 __netif_tx_lock_bh(txq); 1344 netif_tx_stop_queue(txq); 1345 __netif_tx_unlock_bh(txq); 1346 } 1347 1348 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq) 1349 { 1350 struct mlx5_wq_cyc *wq = &sq->wq; 1351 1352 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); 1353 synchronize_net(); /* Sync with NAPI to prevent netif_tx_wake_queue. */ 1354 1355 mlx5e_tx_disable_queue(sq->txq); 1356 1357 /* last doorbell out, godspeed .. */ 1358 if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) { 1359 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc); 1360 struct mlx5e_tx_wqe *nop; 1361 1362 sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) { 1363 .num_wqebbs = 1, 1364 }; 1365 1366 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc); 1367 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl); 1368 } 1369 } 1370 1371 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq) 1372 { 1373 struct mlx5_core_dev *mdev = sq->mdev; 1374 struct mlx5_rate_limit rl = {0}; 1375 1376 cancel_work_sync(&sq->dim.work); 1377 cancel_work_sync(&sq->recover_work); 1378 mlx5e_destroy_sq(mdev, sq->sqn); 1379 if (sq->rate_limit) { 1380 rl.rate = sq->rate_limit; 1381 mlx5_rl_remove_rate(mdev, &rl); 1382 } 1383 mlx5e_free_txqsq_descs(sq); 1384 mlx5e_free_txqsq(sq); 1385 } 1386 1387 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work) 1388 { 1389 struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq, 1390 recover_work); 1391 1392 mlx5e_reporter_tx_err_cqe(sq); 1393 } 1394 1395 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params, 1396 struct mlx5e_sq_param *param, struct mlx5e_icosq *sq) 1397 { 1398 struct mlx5e_create_sq_param csp = {}; 1399 int err; 1400 1401 err = mlx5e_alloc_icosq(c, param, sq); 1402 if (err) 1403 return err; 1404 1405 csp.cqn = sq->cq.mcq.cqn; 1406 csp.wq_ctrl = &sq->wq_ctrl; 1407 csp.min_inline_mode = params->tx_min_inline_mode; 1408 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn); 1409 if (err) 1410 goto err_free_icosq; 1411 1412 if (param->is_tls) { 1413 sq->ktls_resync = mlx5e_ktls_rx_resync_create_resp_list(); 1414 if (IS_ERR(sq->ktls_resync)) { 1415 err = PTR_ERR(sq->ktls_resync); 1416 goto err_destroy_icosq; 1417 } 1418 } 1419 return 0; 1420 1421 err_destroy_icosq: 1422 mlx5e_destroy_sq(c->mdev, sq->sqn); 1423 err_free_icosq: 1424 mlx5e_free_icosq(sq); 1425 1426 return err; 1427 } 1428 1429 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq) 1430 { 1431 set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state); 1432 } 1433 1434 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq) 1435 { 1436 clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state); 1437 synchronize_net(); /* Sync with NAPI. */ 1438 } 1439 1440 void mlx5e_close_icosq(struct mlx5e_icosq *sq) 1441 { 1442 struct mlx5e_channel *c = sq->channel; 1443 1444 if (sq->ktls_resync) 1445 mlx5e_ktls_rx_resync_destroy_resp_list(sq->ktls_resync); 1446 mlx5e_destroy_sq(c->mdev, sq->sqn); 1447 mlx5e_free_icosq_descs(sq); 1448 mlx5e_free_icosq(sq); 1449 } 1450 1451 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params, 1452 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool, 1453 struct mlx5e_xdpsq *sq, bool is_redirect) 1454 { 1455 struct mlx5e_create_sq_param csp = {}; 1456 int err; 1457 1458 err = mlx5e_alloc_xdpsq(c, params, xsk_pool, param, sq, is_redirect); 1459 if (err) 1460 return err; 1461 1462 csp.tis_lst_sz = 1; 1463 csp.tisn = c->priv->tisn[c->lag_port][0]; /* tc = 0 */ 1464 csp.cqn = sq->cq.mcq.cqn; 1465 csp.wq_ctrl = &sq->wq_ctrl; 1466 csp.min_inline_mode = sq->min_inline_mode; 1467 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); 1468 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn); 1469 if (err) 1470 goto err_free_xdpsq; 1471 1472 mlx5e_set_xmit_fp(sq, param->is_mpw); 1473 1474 if (!param->is_mpw) { 1475 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT; 1476 unsigned int inline_hdr_sz = 0; 1477 int i; 1478 1479 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) { 1480 inline_hdr_sz = MLX5E_XDP_MIN_INLINE; 1481 ds_cnt++; 1482 } 1483 1484 /* Pre initialize fixed WQE fields */ 1485 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) { 1486 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i); 1487 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; 1488 struct mlx5_wqe_eth_seg *eseg = &wqe->eth; 1489 struct mlx5_wqe_data_seg *dseg; 1490 1491 sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) { 1492 .num_wqebbs = 1, 1493 .num_pkts = 1, 1494 }; 1495 1496 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt); 1497 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz); 1498 1499 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1); 1500 dseg->lkey = sq->mkey_be; 1501 } 1502 } 1503 1504 return 0; 1505 1506 err_free_xdpsq: 1507 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); 1508 mlx5e_free_xdpsq(sq); 1509 1510 return err; 1511 } 1512 1513 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq) 1514 { 1515 struct mlx5e_channel *c = sq->channel; 1516 1517 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); 1518 synchronize_net(); /* Sync with NAPI. */ 1519 1520 mlx5e_destroy_sq(c->mdev, sq->sqn); 1521 mlx5e_free_xdpsq_descs(sq); 1522 mlx5e_free_xdpsq(sq); 1523 } 1524 1525 static int mlx5e_alloc_cq_common(struct mlx5e_priv *priv, 1526 struct mlx5e_cq_param *param, 1527 struct mlx5e_cq *cq) 1528 { 1529 struct mlx5_core_dev *mdev = priv->mdev; 1530 struct mlx5_core_cq *mcq = &cq->mcq; 1531 int eqn_not_used; 1532 unsigned int irqn; 1533 int err; 1534 u32 i; 1535 1536 err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn); 1537 if (err) 1538 return err; 1539 1540 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, 1541 &cq->wq_ctrl); 1542 if (err) 1543 return err; 1544 1545 mcq->cqe_sz = 64; 1546 mcq->set_ci_db = cq->wq_ctrl.db.db; 1547 mcq->arm_db = cq->wq_ctrl.db.db + 1; 1548 *mcq->set_ci_db = 0; 1549 *mcq->arm_db = 0; 1550 mcq->vector = param->eq_ix; 1551 mcq->comp = mlx5e_completion_event; 1552 mcq->event = mlx5e_cq_error_event; 1553 mcq->irqn = irqn; 1554 1555 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) { 1556 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i); 1557 1558 cqe->op_own = 0xf1; 1559 } 1560 1561 cq->mdev = mdev; 1562 cq->netdev = priv->netdev; 1563 cq->priv = priv; 1564 1565 return 0; 1566 } 1567 1568 static int mlx5e_alloc_cq(struct mlx5e_priv *priv, 1569 struct mlx5e_cq_param *param, 1570 struct mlx5e_create_cq_param *ccp, 1571 struct mlx5e_cq *cq) 1572 { 1573 int err; 1574 1575 param->wq.buf_numa_node = ccp->node; 1576 param->wq.db_numa_node = ccp->node; 1577 param->eq_ix = ccp->ix; 1578 1579 err = mlx5e_alloc_cq_common(priv, param, cq); 1580 1581 cq->napi = ccp->napi; 1582 cq->ch_stats = ccp->ch_stats; 1583 1584 return err; 1585 } 1586 1587 static void mlx5e_free_cq(struct mlx5e_cq *cq) 1588 { 1589 mlx5_wq_destroy(&cq->wq_ctrl); 1590 } 1591 1592 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param) 1593 { 1594 u32 out[MLX5_ST_SZ_DW(create_cq_out)]; 1595 struct mlx5_core_dev *mdev = cq->mdev; 1596 struct mlx5_core_cq *mcq = &cq->mcq; 1597 1598 void *in; 1599 void *cqc; 1600 int inlen; 1601 unsigned int irqn_not_used; 1602 int eqn; 1603 int err; 1604 1605 err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used); 1606 if (err) 1607 return err; 1608 1609 inlen = MLX5_ST_SZ_BYTES(create_cq_in) + 1610 sizeof(u64) * cq->wq_ctrl.buf.npages; 1611 in = kvzalloc(inlen, GFP_KERNEL); 1612 if (!in) 1613 return -ENOMEM; 1614 1615 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1616 1617 memcpy(cqc, param->cqc, sizeof(param->cqc)); 1618 1619 mlx5_fill_page_frag_array(&cq->wq_ctrl.buf, 1620 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas)); 1621 1622 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode); 1623 MLX5_SET(cqc, cqc, c_eqn, eqn); 1624 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index); 1625 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - 1626 MLX5_ADAPTER_PAGE_SHIFT); 1627 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); 1628 1629 err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out)); 1630 1631 kvfree(in); 1632 1633 if (err) 1634 return err; 1635 1636 mlx5e_cq_arm(cq); 1637 1638 return 0; 1639 } 1640 1641 static void mlx5e_destroy_cq(struct mlx5e_cq *cq) 1642 { 1643 mlx5_core_destroy_cq(cq->mdev, &cq->mcq); 1644 } 1645 1646 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder, 1647 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp, 1648 struct mlx5e_cq *cq) 1649 { 1650 struct mlx5_core_dev *mdev = priv->mdev; 1651 int err; 1652 1653 err = mlx5e_alloc_cq(priv, param, ccp, cq); 1654 if (err) 1655 return err; 1656 1657 err = mlx5e_create_cq(cq, param); 1658 if (err) 1659 goto err_free_cq; 1660 1661 if (MLX5_CAP_GEN(mdev, cq_moderation)) 1662 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts); 1663 return 0; 1664 1665 err_free_cq: 1666 mlx5e_free_cq(cq); 1667 1668 return err; 1669 } 1670 1671 void mlx5e_close_cq(struct mlx5e_cq *cq) 1672 { 1673 mlx5e_destroy_cq(cq); 1674 mlx5e_free_cq(cq); 1675 } 1676 1677 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c, 1678 struct mlx5e_params *params, 1679 struct mlx5e_create_cq_param *ccp, 1680 struct mlx5e_channel_param *cparam) 1681 { 1682 int err; 1683 int tc; 1684 1685 for (tc = 0; tc < c->num_tc; tc++) { 1686 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->txq_sq.cqp, 1687 ccp, &c->sq[tc].cq); 1688 if (err) 1689 goto err_close_tx_cqs; 1690 } 1691 1692 return 0; 1693 1694 err_close_tx_cqs: 1695 for (tc--; tc >= 0; tc--) 1696 mlx5e_close_cq(&c->sq[tc].cq); 1697 1698 return err; 1699 } 1700 1701 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c) 1702 { 1703 int tc; 1704 1705 for (tc = 0; tc < c->num_tc; tc++) 1706 mlx5e_close_cq(&c->sq[tc].cq); 1707 } 1708 1709 static int mlx5e_open_sqs(struct mlx5e_channel *c, 1710 struct mlx5e_params *params, 1711 struct mlx5e_channel_param *cparam) 1712 { 1713 int err, tc; 1714 1715 for (tc = 0; tc < params->num_tc; tc++) { 1716 int txq_ix = c->ix + tc * params->num_channels; 1717 1718 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix, 1719 params, &cparam->txq_sq, &c->sq[tc], tc, 0, 0); 1720 if (err) 1721 goto err_close_sqs; 1722 } 1723 1724 return 0; 1725 1726 err_close_sqs: 1727 for (tc--; tc >= 0; tc--) 1728 mlx5e_close_txqsq(&c->sq[tc]); 1729 1730 return err; 1731 } 1732 1733 static void mlx5e_close_sqs(struct mlx5e_channel *c) 1734 { 1735 int tc; 1736 1737 for (tc = 0; tc < c->num_tc; tc++) 1738 mlx5e_close_txqsq(&c->sq[tc]); 1739 } 1740 1741 static int mlx5e_set_sq_maxrate(struct net_device *dev, 1742 struct mlx5e_txqsq *sq, u32 rate) 1743 { 1744 struct mlx5e_priv *priv = netdev_priv(dev); 1745 struct mlx5_core_dev *mdev = priv->mdev; 1746 struct mlx5e_modify_sq_param msp = {0}; 1747 struct mlx5_rate_limit rl = {0}; 1748 u16 rl_index = 0; 1749 int err; 1750 1751 if (rate == sq->rate_limit) 1752 /* nothing to do */ 1753 return 0; 1754 1755 if (sq->rate_limit) { 1756 rl.rate = sq->rate_limit; 1757 /* remove current rl index to free space to next ones */ 1758 mlx5_rl_remove_rate(mdev, &rl); 1759 } 1760 1761 sq->rate_limit = 0; 1762 1763 if (rate) { 1764 rl.rate = rate; 1765 err = mlx5_rl_add_rate(mdev, &rl_index, &rl); 1766 if (err) { 1767 netdev_err(dev, "Failed configuring rate %u: %d\n", 1768 rate, err); 1769 return err; 1770 } 1771 } 1772 1773 msp.curr_state = MLX5_SQC_STATE_RDY; 1774 msp.next_state = MLX5_SQC_STATE_RDY; 1775 msp.rl_index = rl_index; 1776 msp.rl_update = true; 1777 err = mlx5e_modify_sq(mdev, sq->sqn, &msp); 1778 if (err) { 1779 netdev_err(dev, "Failed configuring rate %u: %d\n", 1780 rate, err); 1781 /* remove the rate from the table */ 1782 if (rate) 1783 mlx5_rl_remove_rate(mdev, &rl); 1784 return err; 1785 } 1786 1787 sq->rate_limit = rate; 1788 return 0; 1789 } 1790 1791 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate) 1792 { 1793 struct mlx5e_priv *priv = netdev_priv(dev); 1794 struct mlx5_core_dev *mdev = priv->mdev; 1795 struct mlx5e_txqsq *sq = priv->txq2sq[index]; 1796 int err = 0; 1797 1798 if (!mlx5_rl_is_supported(mdev)) { 1799 netdev_err(dev, "Rate limiting is not supported on this device\n"); 1800 return -EINVAL; 1801 } 1802 1803 /* rate is given in Mb/sec, HW config is in Kb/sec */ 1804 rate = rate << 10; 1805 1806 /* Check whether rate in valid range, 0 is always valid */ 1807 if (rate && !mlx5_rl_is_in_range(mdev, rate)) { 1808 netdev_err(dev, "TX rate %u, is not in range\n", rate); 1809 return -ERANGE; 1810 } 1811 1812 mutex_lock(&priv->state_lock); 1813 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) 1814 err = mlx5e_set_sq_maxrate(dev, sq, rate); 1815 if (!err) 1816 priv->tx_rates[index] = rate; 1817 mutex_unlock(&priv->state_lock); 1818 1819 return err; 1820 } 1821 1822 static int mlx5e_open_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params, 1823 struct mlx5e_rq_param *rq_params) 1824 { 1825 int err; 1826 1827 err = mlx5e_init_rxq_rq(c, params, &c->rq); 1828 if (err) 1829 return err; 1830 1831 return mlx5e_open_rq(params, rq_params, NULL, cpu_to_node(c->cpu), &c->rq); 1832 } 1833 1834 static int mlx5e_open_queues(struct mlx5e_channel *c, 1835 struct mlx5e_params *params, 1836 struct mlx5e_channel_param *cparam) 1837 { 1838 struct dim_cq_moder icocq_moder = {0, 0}; 1839 struct mlx5e_create_cq_param ccp; 1840 int err; 1841 1842 mlx5e_build_create_cq_param(&ccp, c); 1843 1844 err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->async_icosq.cqp, &ccp, 1845 &c->async_icosq.cq); 1846 if (err) 1847 return err; 1848 1849 err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->icosq.cqp, &ccp, 1850 &c->icosq.cq); 1851 if (err) 1852 goto err_close_async_icosq_cq; 1853 1854 err = mlx5e_open_tx_cqs(c, params, &ccp, cparam); 1855 if (err) 1856 goto err_close_icosq_cq; 1857 1858 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp, &ccp, 1859 &c->xdpsq.cq); 1860 if (err) 1861 goto err_close_tx_cqs; 1862 1863 err = mlx5e_open_cq(c->priv, params->rx_cq_moderation, &cparam->rq.cqp, &ccp, 1864 &c->rq.cq); 1865 if (err) 1866 goto err_close_xdp_tx_cqs; 1867 1868 err = c->xdp ? mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp, 1869 &ccp, &c->rq_xdpsq.cq) : 0; 1870 if (err) 1871 goto err_close_rx_cq; 1872 1873 spin_lock_init(&c->async_icosq_lock); 1874 1875 err = mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq); 1876 if (err) 1877 goto err_close_xdpsq_cq; 1878 1879 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq); 1880 if (err) 1881 goto err_close_async_icosq; 1882 1883 err = mlx5e_open_sqs(c, params, cparam); 1884 if (err) 1885 goto err_close_icosq; 1886 1887 if (c->xdp) { 1888 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, 1889 &c->rq_xdpsq, false); 1890 if (err) 1891 goto err_close_sqs; 1892 } 1893 1894 err = mlx5e_open_rxq_rq(c, params, &cparam->rq); 1895 if (err) 1896 goto err_close_xdp_sq; 1897 1898 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true); 1899 if (err) 1900 goto err_close_rq; 1901 1902 return 0; 1903 1904 err_close_rq: 1905 mlx5e_close_rq(&c->rq); 1906 1907 err_close_xdp_sq: 1908 if (c->xdp) 1909 mlx5e_close_xdpsq(&c->rq_xdpsq); 1910 1911 err_close_sqs: 1912 mlx5e_close_sqs(c); 1913 1914 err_close_icosq: 1915 mlx5e_close_icosq(&c->icosq); 1916 1917 err_close_async_icosq: 1918 mlx5e_close_icosq(&c->async_icosq); 1919 1920 err_close_xdpsq_cq: 1921 if (c->xdp) 1922 mlx5e_close_cq(&c->rq_xdpsq.cq); 1923 1924 err_close_rx_cq: 1925 mlx5e_close_cq(&c->rq.cq); 1926 1927 err_close_xdp_tx_cqs: 1928 mlx5e_close_cq(&c->xdpsq.cq); 1929 1930 err_close_tx_cqs: 1931 mlx5e_close_tx_cqs(c); 1932 1933 err_close_icosq_cq: 1934 mlx5e_close_cq(&c->icosq.cq); 1935 1936 err_close_async_icosq_cq: 1937 mlx5e_close_cq(&c->async_icosq.cq); 1938 1939 return err; 1940 } 1941 1942 static void mlx5e_close_queues(struct mlx5e_channel *c) 1943 { 1944 mlx5e_close_xdpsq(&c->xdpsq); 1945 mlx5e_close_rq(&c->rq); 1946 if (c->xdp) 1947 mlx5e_close_xdpsq(&c->rq_xdpsq); 1948 mlx5e_close_sqs(c); 1949 mlx5e_close_icosq(&c->icosq); 1950 mlx5e_close_icosq(&c->async_icosq); 1951 if (c->xdp) 1952 mlx5e_close_cq(&c->rq_xdpsq.cq); 1953 mlx5e_close_cq(&c->rq.cq); 1954 mlx5e_close_cq(&c->xdpsq.cq); 1955 mlx5e_close_tx_cqs(c); 1956 mlx5e_close_cq(&c->icosq.cq); 1957 mlx5e_close_cq(&c->async_icosq.cq); 1958 } 1959 1960 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix) 1961 { 1962 u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id); 1963 1964 return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev); 1965 } 1966 1967 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix, 1968 struct mlx5e_params *params, 1969 struct mlx5e_channel_param *cparam, 1970 struct xsk_buff_pool *xsk_pool, 1971 struct mlx5e_channel **cp) 1972 { 1973 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix)); 1974 struct net_device *netdev = priv->netdev; 1975 struct mlx5e_xsk_param xsk; 1976 struct mlx5e_channel *c; 1977 unsigned int irq; 1978 int err; 1979 int eqn; 1980 1981 err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq); 1982 if (err) 1983 return err; 1984 1985 c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu)); 1986 if (!c) 1987 return -ENOMEM; 1988 1989 c->priv = priv; 1990 c->mdev = priv->mdev; 1991 c->tstamp = &priv->tstamp; 1992 c->ix = ix; 1993 c->cpu = cpu; 1994 c->pdev = mlx5_core_dma_dev(priv->mdev); 1995 c->netdev = priv->netdev; 1996 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.hw_objs.mkey.key); 1997 c->num_tc = params->num_tc; 1998 c->xdp = !!params->xdp_prog; 1999 c->stats = &priv->channel_stats[ix].ch; 2000 c->aff_mask = irq_get_effective_affinity_mask(irq); 2001 c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix); 2002 2003 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64); 2004 2005 err = mlx5e_open_queues(c, params, cparam); 2006 if (unlikely(err)) 2007 goto err_napi_del; 2008 2009 if (xsk_pool) { 2010 mlx5e_build_xsk_param(xsk_pool, &xsk); 2011 err = mlx5e_open_xsk(priv, params, &xsk, xsk_pool, c); 2012 if (unlikely(err)) 2013 goto err_close_queues; 2014 } 2015 2016 *cp = c; 2017 2018 return 0; 2019 2020 err_close_queues: 2021 mlx5e_close_queues(c); 2022 2023 err_napi_del: 2024 netif_napi_del(&c->napi); 2025 2026 kvfree(c); 2027 2028 return err; 2029 } 2030 2031 static void mlx5e_activate_channel(struct mlx5e_channel *c) 2032 { 2033 int tc; 2034 2035 napi_enable(&c->napi); 2036 2037 for (tc = 0; tc < c->num_tc; tc++) 2038 mlx5e_activate_txqsq(&c->sq[tc]); 2039 mlx5e_activate_icosq(&c->icosq); 2040 mlx5e_activate_icosq(&c->async_icosq); 2041 mlx5e_activate_rq(&c->rq); 2042 2043 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) 2044 mlx5e_activate_xsk(c); 2045 } 2046 2047 static void mlx5e_deactivate_channel(struct mlx5e_channel *c) 2048 { 2049 int tc; 2050 2051 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) 2052 mlx5e_deactivate_xsk(c); 2053 2054 mlx5e_deactivate_rq(&c->rq); 2055 mlx5e_deactivate_icosq(&c->async_icosq); 2056 mlx5e_deactivate_icosq(&c->icosq); 2057 for (tc = 0; tc < c->num_tc; tc++) 2058 mlx5e_deactivate_txqsq(&c->sq[tc]); 2059 mlx5e_qos_deactivate_queues(c); 2060 2061 napi_disable(&c->napi); 2062 } 2063 2064 static void mlx5e_close_channel(struct mlx5e_channel *c) 2065 { 2066 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) 2067 mlx5e_close_xsk(c); 2068 mlx5e_close_queues(c); 2069 mlx5e_qos_close_queues(c); 2070 netif_napi_del(&c->napi); 2071 2072 kvfree(c); 2073 } 2074 2075 int mlx5e_open_channels(struct mlx5e_priv *priv, 2076 struct mlx5e_channels *chs) 2077 { 2078 struct mlx5e_channel_param *cparam; 2079 int err = -ENOMEM; 2080 int i; 2081 2082 chs->num = chs->params.num_channels; 2083 2084 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL); 2085 cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL); 2086 if (!chs->c || !cparam) 2087 goto err_free; 2088 2089 err = mlx5e_build_channel_param(priv->mdev, &chs->params, priv->q_counter, cparam); 2090 if (err) 2091 goto err_free; 2092 2093 for (i = 0; i < chs->num; i++) { 2094 struct xsk_buff_pool *xsk_pool = NULL; 2095 2096 if (chs->params.xdp_prog) 2097 xsk_pool = mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, i); 2098 2099 err = mlx5e_open_channel(priv, i, &chs->params, cparam, xsk_pool, &chs->c[i]); 2100 if (err) 2101 goto err_close_channels; 2102 } 2103 2104 if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS) || chs->params.ptp_rx) { 2105 err = mlx5e_ptp_open(priv, &chs->params, chs->c[0]->lag_port, &chs->ptp); 2106 if (err) 2107 goto err_close_channels; 2108 } 2109 2110 err = mlx5e_qos_open_queues(priv, chs); 2111 if (err) 2112 goto err_close_ptp; 2113 2114 mlx5e_health_channels_update(priv); 2115 kvfree(cparam); 2116 return 0; 2117 2118 err_close_ptp: 2119 if (chs->ptp) 2120 mlx5e_ptp_close(chs->ptp); 2121 2122 err_close_channels: 2123 for (i--; i >= 0; i--) 2124 mlx5e_close_channel(chs->c[i]); 2125 2126 err_free: 2127 kfree(chs->c); 2128 kvfree(cparam); 2129 chs->num = 0; 2130 return err; 2131 } 2132 2133 static void mlx5e_activate_channels(struct mlx5e_channels *chs) 2134 { 2135 int i; 2136 2137 for (i = 0; i < chs->num; i++) 2138 mlx5e_activate_channel(chs->c[i]); 2139 2140 if (chs->ptp) 2141 mlx5e_ptp_activate_channel(chs->ptp); 2142 } 2143 2144 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */ 2145 2146 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs) 2147 { 2148 int err = 0; 2149 int i; 2150 2151 for (i = 0; i < chs->num; i++) { 2152 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT; 2153 2154 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout); 2155 2156 /* Don't wait on the XSK RQ, because the newer xdpsock sample 2157 * doesn't provide any Fill Ring entries at the setup stage. 2158 */ 2159 } 2160 2161 return err ? -ETIMEDOUT : 0; 2162 } 2163 2164 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs) 2165 { 2166 int i; 2167 2168 if (chs->ptp) 2169 mlx5e_ptp_deactivate_channel(chs->ptp); 2170 2171 for (i = 0; i < chs->num; i++) 2172 mlx5e_deactivate_channel(chs->c[i]); 2173 } 2174 2175 void mlx5e_close_channels(struct mlx5e_channels *chs) 2176 { 2177 int i; 2178 2179 if (chs->ptp) { 2180 mlx5e_ptp_close(chs->ptp); 2181 chs->ptp = NULL; 2182 } 2183 for (i = 0; i < chs->num; i++) 2184 mlx5e_close_channel(chs->c[i]); 2185 2186 kfree(chs->c); 2187 chs->num = 0; 2188 } 2189 2190 static int 2191 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt) 2192 { 2193 struct mlx5_core_dev *mdev = priv->mdev; 2194 void *rqtc; 2195 int inlen; 2196 int err; 2197 u32 *in; 2198 int i; 2199 2200 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 2201 in = kvzalloc(inlen, GFP_KERNEL); 2202 if (!in) 2203 return -ENOMEM; 2204 2205 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 2206 2207 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 2208 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 2209 2210 for (i = 0; i < sz; i++) 2211 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn); 2212 2213 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn); 2214 if (!err) 2215 rqt->enabled = true; 2216 2217 kvfree(in); 2218 return err; 2219 } 2220 2221 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt) 2222 { 2223 rqt->enabled = false; 2224 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn); 2225 } 2226 2227 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv) 2228 { 2229 struct mlx5e_rqt *rqt = &priv->indir_rqt; 2230 int err; 2231 2232 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt); 2233 if (err) 2234 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err); 2235 return err; 2236 } 2237 2238 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs, int n) 2239 { 2240 int err; 2241 int ix; 2242 2243 for (ix = 0; ix < n; ix++) { 2244 err = mlx5e_create_rqt(priv, 1 /*size */, &tirs[ix].rqt); 2245 if (unlikely(err)) 2246 goto err_destroy_rqts; 2247 } 2248 2249 return 0; 2250 2251 err_destroy_rqts: 2252 mlx5_core_warn(priv->mdev, "create rqts failed, %d\n", err); 2253 for (ix--; ix >= 0; ix--) 2254 mlx5e_destroy_rqt(priv, &tirs[ix].rqt); 2255 2256 return err; 2257 } 2258 2259 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs, int n) 2260 { 2261 int i; 2262 2263 for (i = 0; i < n; i++) 2264 mlx5e_destroy_rqt(priv, &tirs[i].rqt); 2265 } 2266 2267 static int mlx5e_rx_hash_fn(int hfunc) 2268 { 2269 return (hfunc == ETH_RSS_HASH_TOP) ? 2270 MLX5_RX_HASH_FN_TOEPLITZ : 2271 MLX5_RX_HASH_FN_INVERTED_XOR8; 2272 } 2273 2274 int mlx5e_bits_invert(unsigned long a, int size) 2275 { 2276 int inv = 0; 2277 int i; 2278 2279 for (i = 0; i < size; i++) 2280 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i; 2281 2282 return inv; 2283 } 2284 2285 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz, 2286 struct mlx5e_redirect_rqt_param rrp, void *rqtc) 2287 { 2288 int i; 2289 2290 for (i = 0; i < sz; i++) { 2291 u32 rqn; 2292 2293 if (rrp.is_rss) { 2294 int ix = i; 2295 2296 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR) 2297 ix = mlx5e_bits_invert(i, ilog2(sz)); 2298 2299 ix = priv->rss_params.indirection_rqt[ix]; 2300 rqn = rrp.rss.channels->c[ix]->rq.rqn; 2301 } else { 2302 rqn = rrp.rqn; 2303 } 2304 MLX5_SET(rqtc, rqtc, rq_num[i], rqn); 2305 } 2306 } 2307 2308 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, 2309 struct mlx5e_redirect_rqt_param rrp) 2310 { 2311 struct mlx5_core_dev *mdev = priv->mdev; 2312 void *rqtc; 2313 int inlen; 2314 u32 *in; 2315 int err; 2316 2317 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz; 2318 in = kvzalloc(inlen, GFP_KERNEL); 2319 if (!in) 2320 return -ENOMEM; 2321 2322 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx); 2323 2324 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 2325 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1); 2326 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc); 2327 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen); 2328 2329 kvfree(in); 2330 return err; 2331 } 2332 2333 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix, 2334 struct mlx5e_redirect_rqt_param rrp) 2335 { 2336 if (!rrp.is_rss) 2337 return rrp.rqn; 2338 2339 if (ix >= rrp.rss.channels->num) 2340 return priv->drop_rq.rqn; 2341 2342 return rrp.rss.channels->c[ix]->rq.rqn; 2343 } 2344 2345 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv, 2346 struct mlx5e_redirect_rqt_param rrp, 2347 struct mlx5e_redirect_rqt_param *ptp_rrp) 2348 { 2349 u32 rqtn; 2350 int ix; 2351 2352 if (priv->indir_rqt.enabled) { 2353 /* RSS RQ table */ 2354 rqtn = priv->indir_rqt.rqtn; 2355 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp); 2356 } 2357 2358 for (ix = 0; ix < priv->max_nch; ix++) { 2359 struct mlx5e_redirect_rqt_param direct_rrp = { 2360 .is_rss = false, 2361 { 2362 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp) 2363 }, 2364 }; 2365 2366 /* Direct RQ Tables */ 2367 if (!priv->direct_tir[ix].rqt.enabled) 2368 continue; 2369 2370 rqtn = priv->direct_tir[ix].rqt.rqtn; 2371 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp); 2372 } 2373 if (ptp_rrp) { 2374 rqtn = priv->ptp_tir.rqt.rqtn; 2375 mlx5e_redirect_rqt(priv, rqtn, 1, *ptp_rrp); 2376 } 2377 } 2378 2379 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv, 2380 struct mlx5e_channels *chs) 2381 { 2382 bool rx_ptp_support = priv->profile->rx_ptp_support; 2383 struct mlx5e_redirect_rqt_param *ptp_rrp_p = NULL; 2384 struct mlx5e_redirect_rqt_param rrp = { 2385 .is_rss = true, 2386 { 2387 .rss = { 2388 .channels = chs, 2389 .hfunc = priv->rss_params.hfunc, 2390 } 2391 }, 2392 }; 2393 struct mlx5e_redirect_rqt_param ptp_rrp; 2394 2395 if (rx_ptp_support) { 2396 u32 ptp_rqn; 2397 2398 ptp_rrp.is_rss = false; 2399 ptp_rrp.rqn = mlx5e_ptp_get_rqn(priv->channels.ptp, &ptp_rqn) ? 2400 priv->drop_rq.rqn : ptp_rqn; 2401 ptp_rrp_p = &ptp_rrp; 2402 } 2403 mlx5e_redirect_rqts(priv, rrp, ptp_rrp_p); 2404 } 2405 2406 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv) 2407 { 2408 bool rx_ptp_support = priv->profile->rx_ptp_support; 2409 struct mlx5e_redirect_rqt_param drop_rrp = { 2410 .is_rss = false, 2411 { 2412 .rqn = priv->drop_rq.rqn, 2413 }, 2414 }; 2415 2416 mlx5e_redirect_rqts(priv, drop_rrp, rx_ptp_support ? &drop_rrp : NULL); 2417 } 2418 2419 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = { 2420 [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4, 2421 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP, 2422 .rx_hash_fields = MLX5_HASH_IP_L4PORTS, 2423 }, 2424 [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6, 2425 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP, 2426 .rx_hash_fields = MLX5_HASH_IP_L4PORTS, 2427 }, 2428 [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4, 2429 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP, 2430 .rx_hash_fields = MLX5_HASH_IP_L4PORTS, 2431 }, 2432 [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6, 2433 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP, 2434 .rx_hash_fields = MLX5_HASH_IP_L4PORTS, 2435 }, 2436 [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4, 2437 .l4_prot_type = 0, 2438 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI, 2439 }, 2440 [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6, 2441 .l4_prot_type = 0, 2442 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI, 2443 }, 2444 [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4, 2445 .l4_prot_type = 0, 2446 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI, 2447 }, 2448 [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6, 2449 .l4_prot_type = 0, 2450 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI, 2451 }, 2452 [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4, 2453 .l4_prot_type = 0, 2454 .rx_hash_fields = MLX5_HASH_IP, 2455 }, 2456 [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6, 2457 .l4_prot_type = 0, 2458 .rx_hash_fields = MLX5_HASH_IP, 2459 }, 2460 }; 2461 2462 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt) 2463 { 2464 return tirc_default_config[tt]; 2465 } 2466 2467 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc) 2468 { 2469 if (!params->lro_en) 2470 return; 2471 2472 #define ROUGH_MAX_L2_L3_HDR_SZ 256 2473 2474 MLX5_SET(tirc, tirc, lro_enable_mask, 2475 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO | 2476 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO); 2477 MLX5_SET(tirc, tirc, lro_max_ip_payload_size, 2478 (MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - ROUGH_MAX_L2_L3_HDR_SZ) >> 8); 2479 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout); 2480 } 2481 2482 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params, 2483 const struct mlx5e_tirc_config *ttconfig, 2484 void *tirc, bool inner) 2485 { 2486 void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) : 2487 MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 2488 2489 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc)); 2490 if (rss_params->hfunc == ETH_RSS_HASH_TOP) { 2491 void *rss_key = MLX5_ADDR_OF(tirc, tirc, 2492 rx_hash_toeplitz_key); 2493 size_t len = MLX5_FLD_SZ_BYTES(tirc, 2494 rx_hash_toeplitz_key); 2495 2496 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 2497 memcpy(rss_key, rss_params->toeplitz_hash_key, len); 2498 } 2499 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2500 ttconfig->l3_prot_type); 2501 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2502 ttconfig->l4_prot_type); 2503 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2504 ttconfig->rx_hash_fields); 2505 } 2506 2507 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig, 2508 enum mlx5e_traffic_types tt, 2509 u32 rx_hash_fields) 2510 { 2511 *ttconfig = tirc_default_config[tt]; 2512 ttconfig->rx_hash_fields = rx_hash_fields; 2513 } 2514 2515 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in) 2516 { 2517 void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx); 2518 struct mlx5e_rss_params *rss = &priv->rss_params; 2519 struct mlx5_core_dev *mdev = priv->mdev; 2520 int ctxlen = MLX5_ST_SZ_BYTES(tirc); 2521 struct mlx5e_tirc_config ttconfig; 2522 int tt; 2523 2524 MLX5_SET(modify_tir_in, in, bitmask.hash, 1); 2525 2526 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { 2527 memset(tirc, 0, ctxlen); 2528 mlx5e_update_rx_hash_fields(&ttconfig, tt, 2529 rss->rx_hash_fields[tt]); 2530 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false); 2531 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in); 2532 } 2533 2534 /* Verify inner tirs resources allocated */ 2535 if (!priv->inner_indir_tir[0].tirn) 2536 return; 2537 2538 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { 2539 memset(tirc, 0, ctxlen); 2540 mlx5e_update_rx_hash_fields(&ttconfig, tt, 2541 rss->rx_hash_fields[tt]); 2542 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true); 2543 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in); 2544 } 2545 } 2546 2547 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv) 2548 { 2549 struct mlx5_core_dev *mdev = priv->mdev; 2550 2551 void *in; 2552 void *tirc; 2553 int inlen; 2554 int err; 2555 int tt; 2556 int ix; 2557 2558 inlen = MLX5_ST_SZ_BYTES(modify_tir_in); 2559 in = kvzalloc(inlen, GFP_KERNEL); 2560 if (!in) 2561 return -ENOMEM; 2562 2563 MLX5_SET(modify_tir_in, in, bitmask.lro, 1); 2564 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx); 2565 2566 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc); 2567 2568 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { 2569 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in); 2570 if (err) 2571 goto free_in; 2572 } 2573 2574 for (ix = 0; ix < priv->max_nch; ix++) { 2575 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn, in); 2576 if (err) 2577 goto free_in; 2578 } 2579 2580 free_in: 2581 kvfree(in); 2582 2583 return err; 2584 } 2585 2586 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_lro); 2587 2588 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev, 2589 struct mlx5e_params *params, u16 mtu) 2590 { 2591 u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu); 2592 int err; 2593 2594 err = mlx5_set_port_mtu(mdev, hw_mtu, 1); 2595 if (err) 2596 return err; 2597 2598 /* Update vport context MTU */ 2599 mlx5_modify_nic_vport_mtu(mdev, hw_mtu); 2600 return 0; 2601 } 2602 2603 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev, 2604 struct mlx5e_params *params, u16 *mtu) 2605 { 2606 u16 hw_mtu = 0; 2607 int err; 2608 2609 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu); 2610 if (err || !hw_mtu) /* fallback to port oper mtu */ 2611 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1); 2612 2613 *mtu = MLX5E_HW2SW_MTU(params, hw_mtu); 2614 } 2615 2616 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv) 2617 { 2618 struct mlx5e_params *params = &priv->channels.params; 2619 struct net_device *netdev = priv->netdev; 2620 struct mlx5_core_dev *mdev = priv->mdev; 2621 u16 mtu; 2622 int err; 2623 2624 err = mlx5e_set_mtu(mdev, params, params->sw_mtu); 2625 if (err) 2626 return err; 2627 2628 mlx5e_query_mtu(mdev, params, &mtu); 2629 if (mtu != params->sw_mtu) 2630 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n", 2631 __func__, mtu, params->sw_mtu); 2632 2633 params->sw_mtu = mtu; 2634 return 0; 2635 } 2636 2637 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu); 2638 2639 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv) 2640 { 2641 struct mlx5e_params *params = &priv->channels.params; 2642 struct net_device *netdev = priv->netdev; 2643 struct mlx5_core_dev *mdev = priv->mdev; 2644 u16 max_mtu; 2645 2646 /* MTU range: 68 - hw-specific max */ 2647 netdev->min_mtu = ETH_MIN_MTU; 2648 2649 mlx5_query_port_max_mtu(mdev, &max_mtu, 1); 2650 netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu), 2651 ETH_MAX_MTU); 2652 } 2653 2654 static void mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc) 2655 { 2656 int tc; 2657 2658 netdev_reset_tc(netdev); 2659 2660 if (ntc == 1) 2661 return; 2662 2663 netdev_set_num_tc(netdev, ntc); 2664 2665 /* Map netdev TCs to offset 0 2666 * We have our own UP to TXQ mapping for QoS 2667 */ 2668 for (tc = 0; tc < ntc; tc++) 2669 netdev_set_tc_queue(netdev, tc, nch, 0); 2670 } 2671 2672 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv) 2673 { 2674 int qos_queues, nch, ntc, num_txqs, err; 2675 2676 qos_queues = mlx5e_qos_cur_leaf_nodes(priv); 2677 2678 nch = priv->channels.params.num_channels; 2679 ntc = priv->channels.params.num_tc; 2680 num_txqs = nch * ntc + qos_queues; 2681 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_PORT_TS)) 2682 num_txqs += ntc; 2683 2684 mlx5e_dbg(DRV, priv, "Setting num_txqs %d\n", num_txqs); 2685 err = netif_set_real_num_tx_queues(priv->netdev, num_txqs); 2686 if (err) 2687 netdev_warn(priv->netdev, "netif_set_real_num_tx_queues failed, %d\n", err); 2688 2689 return err; 2690 } 2691 2692 static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv) 2693 { 2694 struct net_device *netdev = priv->netdev; 2695 int old_num_txqs, old_ntc; 2696 int num_rxqs, nch, ntc; 2697 int err; 2698 2699 old_num_txqs = netdev->real_num_tx_queues; 2700 old_ntc = netdev->num_tc; 2701 2702 nch = priv->channels.params.num_channels; 2703 ntc = priv->channels.params.num_tc; 2704 num_rxqs = nch * priv->profile->rq_groups; 2705 if (priv->channels.params.ptp_rx) 2706 num_rxqs++; 2707 2708 mlx5e_netdev_set_tcs(netdev, nch, ntc); 2709 2710 err = mlx5e_update_tx_netdev_queues(priv); 2711 if (err) 2712 goto err_tcs; 2713 err = netif_set_real_num_rx_queues(netdev, num_rxqs); 2714 if (err) { 2715 netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err); 2716 goto err_txqs; 2717 } 2718 2719 return 0; 2720 2721 err_txqs: 2722 /* netif_set_real_num_rx_queues could fail only when nch increased. Only 2723 * one of nch and ntc is changed in this function. That means, the call 2724 * to netif_set_real_num_tx_queues below should not fail, because it 2725 * decreases the number of TX queues. 2726 */ 2727 WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs)); 2728 2729 err_tcs: 2730 mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc); 2731 return err; 2732 } 2733 2734 static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv, 2735 struct mlx5e_params *params) 2736 { 2737 struct mlx5_core_dev *mdev = priv->mdev; 2738 int num_comp_vectors, ix, irq; 2739 2740 num_comp_vectors = mlx5_comp_vectors_count(mdev); 2741 2742 for (ix = 0; ix < params->num_channels; ix++) { 2743 cpumask_clear(priv->scratchpad.cpumask); 2744 2745 for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) { 2746 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(mdev, irq)); 2747 2748 cpumask_set_cpu(cpu, priv->scratchpad.cpumask); 2749 } 2750 2751 netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix); 2752 } 2753 } 2754 2755 int mlx5e_num_channels_changed(struct mlx5e_priv *priv) 2756 { 2757 u16 count = priv->channels.params.num_channels; 2758 int err; 2759 2760 err = mlx5e_update_netdev_queues(priv); 2761 if (err) 2762 return err; 2763 2764 mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params); 2765 2766 if (!netif_is_rxfh_configured(priv->netdev)) 2767 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt, 2768 MLX5E_INDIR_RQT_SIZE, count); 2769 2770 return 0; 2771 } 2772 2773 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed); 2774 2775 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv) 2776 { 2777 int i, ch, tc, num_tc; 2778 2779 ch = priv->channels.num; 2780 num_tc = priv->channels.params.num_tc; 2781 2782 for (i = 0; i < ch; i++) { 2783 for (tc = 0; tc < num_tc; tc++) { 2784 struct mlx5e_channel *c = priv->channels.c[i]; 2785 struct mlx5e_txqsq *sq = &c->sq[tc]; 2786 2787 priv->txq2sq[sq->txq_ix] = sq; 2788 priv->channel_tc2realtxq[i][tc] = i + tc * ch; 2789 } 2790 } 2791 2792 if (!priv->channels.ptp) 2793 return; 2794 2795 if (!test_bit(MLX5E_PTP_STATE_TX, priv->channels.ptp->state)) 2796 return; 2797 2798 for (tc = 0; tc < num_tc; tc++) { 2799 struct mlx5e_ptp *c = priv->channels.ptp; 2800 struct mlx5e_txqsq *sq = &c->ptpsq[tc].txqsq; 2801 2802 priv->txq2sq[sq->txq_ix] = sq; 2803 priv->port_ptp_tc2realtxq[tc] = priv->num_tc_x_num_ch + tc; 2804 } 2805 } 2806 2807 static void mlx5e_update_num_tc_x_num_ch(struct mlx5e_priv *priv) 2808 { 2809 /* Sync with mlx5e_select_queue. */ 2810 WRITE_ONCE(priv->num_tc_x_num_ch, 2811 priv->channels.params.num_tc * priv->channels.num); 2812 } 2813 2814 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv) 2815 { 2816 mlx5e_update_num_tc_x_num_ch(priv); 2817 mlx5e_build_txq_maps(priv); 2818 mlx5e_activate_channels(&priv->channels); 2819 mlx5e_qos_activate_queues(priv); 2820 mlx5e_xdp_tx_enable(priv); 2821 netif_tx_start_all_queues(priv->netdev); 2822 2823 if (mlx5e_is_vport_rep(priv)) 2824 mlx5e_add_sqs_fwd_rules(priv); 2825 2826 mlx5e_wait_channels_min_rx_wqes(&priv->channels); 2827 mlx5e_redirect_rqts_to_channels(priv, &priv->channels); 2828 2829 mlx5e_xsk_redirect_rqts_to_channels(priv, &priv->channels); 2830 } 2831 2832 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv) 2833 { 2834 mlx5e_xsk_redirect_rqts_to_drop(priv, &priv->channels); 2835 2836 mlx5e_redirect_rqts_to_drop(priv); 2837 2838 if (mlx5e_is_vport_rep(priv)) 2839 mlx5e_remove_sqs_fwd_rules(priv); 2840 2841 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when 2842 * polling for inactive tx queues. 2843 */ 2844 netif_tx_stop_all_queues(priv->netdev); 2845 netif_tx_disable(priv->netdev); 2846 mlx5e_xdp_tx_disable(priv); 2847 mlx5e_deactivate_channels(&priv->channels); 2848 } 2849 2850 static int mlx5e_switch_priv_params(struct mlx5e_priv *priv, 2851 struct mlx5e_params *new_params, 2852 mlx5e_fp_preactivate preactivate, 2853 void *context) 2854 { 2855 struct mlx5e_params old_params; 2856 2857 old_params = priv->channels.params; 2858 priv->channels.params = *new_params; 2859 2860 if (preactivate) { 2861 int err; 2862 2863 err = preactivate(priv, context); 2864 if (err) { 2865 priv->channels.params = old_params; 2866 return err; 2867 } 2868 } 2869 2870 return 0; 2871 } 2872 2873 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv, 2874 struct mlx5e_channels *new_chs, 2875 mlx5e_fp_preactivate preactivate, 2876 void *context) 2877 { 2878 struct net_device *netdev = priv->netdev; 2879 struct mlx5e_channels old_chs; 2880 int carrier_ok; 2881 int err = 0; 2882 2883 carrier_ok = netif_carrier_ok(netdev); 2884 netif_carrier_off(netdev); 2885 2886 mlx5e_deactivate_priv_channels(priv); 2887 2888 old_chs = priv->channels; 2889 priv->channels = *new_chs; 2890 2891 /* New channels are ready to roll, call the preactivate hook if needed 2892 * to modify HW settings or update kernel parameters. 2893 */ 2894 if (preactivate) { 2895 err = preactivate(priv, context); 2896 if (err) { 2897 priv->channels = old_chs; 2898 goto out; 2899 } 2900 } 2901 2902 mlx5e_close_channels(&old_chs); 2903 priv->profile->update_rx(priv); 2904 2905 out: 2906 mlx5e_activate_priv_channels(priv); 2907 2908 /* return carrier back if needed */ 2909 if (carrier_ok) 2910 netif_carrier_on(netdev); 2911 2912 return err; 2913 } 2914 2915 int mlx5e_safe_switch_params(struct mlx5e_priv *priv, 2916 struct mlx5e_params *params, 2917 mlx5e_fp_preactivate preactivate, 2918 void *context, bool reset) 2919 { 2920 struct mlx5e_channels new_chs = {}; 2921 int err; 2922 2923 reset &= test_bit(MLX5E_STATE_OPENED, &priv->state); 2924 if (!reset) 2925 return mlx5e_switch_priv_params(priv, params, preactivate, context); 2926 2927 new_chs.params = *params; 2928 err = mlx5e_open_channels(priv, &new_chs); 2929 if (err) 2930 return err; 2931 err = mlx5e_switch_priv_channels(priv, &new_chs, preactivate, context); 2932 if (err) 2933 mlx5e_close_channels(&new_chs); 2934 2935 return err; 2936 } 2937 2938 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv) 2939 { 2940 return mlx5e_safe_switch_params(priv, &priv->channels.params, NULL, NULL, true); 2941 } 2942 2943 void mlx5e_timestamp_init(struct mlx5e_priv *priv) 2944 { 2945 priv->tstamp.tx_type = HWTSTAMP_TX_OFF; 2946 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE; 2947 } 2948 2949 static void mlx5e_modify_admin_state(struct mlx5_core_dev *mdev, 2950 enum mlx5_port_status state) 2951 { 2952 struct mlx5_eswitch *esw = mdev->priv.eswitch; 2953 int vport_admin_state; 2954 2955 mlx5_set_port_admin_status(mdev, state); 2956 2957 if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS || 2958 !MLX5_CAP_GEN(mdev, uplink_follow)) 2959 return; 2960 2961 if (state == MLX5_PORT_UP) 2962 vport_admin_state = MLX5_VPORT_ADMIN_STATE_AUTO; 2963 else 2964 vport_admin_state = MLX5_VPORT_ADMIN_STATE_DOWN; 2965 2966 mlx5_eswitch_set_vport_state(esw, MLX5_VPORT_UPLINK, vport_admin_state); 2967 } 2968 2969 int mlx5e_open_locked(struct net_device *netdev) 2970 { 2971 struct mlx5e_priv *priv = netdev_priv(netdev); 2972 int err; 2973 2974 set_bit(MLX5E_STATE_OPENED, &priv->state); 2975 2976 err = mlx5e_open_channels(priv, &priv->channels); 2977 if (err) 2978 goto err_clear_state_opened_flag; 2979 2980 priv->profile->update_rx(priv); 2981 mlx5e_activate_priv_channels(priv); 2982 mlx5e_apply_traps(priv, true); 2983 if (priv->profile->update_carrier) 2984 priv->profile->update_carrier(priv); 2985 2986 mlx5e_queue_update_stats(priv); 2987 return 0; 2988 2989 err_clear_state_opened_flag: 2990 clear_bit(MLX5E_STATE_OPENED, &priv->state); 2991 return err; 2992 } 2993 2994 int mlx5e_open(struct net_device *netdev) 2995 { 2996 struct mlx5e_priv *priv = netdev_priv(netdev); 2997 int err; 2998 2999 mutex_lock(&priv->state_lock); 3000 err = mlx5e_open_locked(netdev); 3001 if (!err) 3002 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_UP); 3003 mutex_unlock(&priv->state_lock); 3004 3005 return err; 3006 } 3007 3008 int mlx5e_close_locked(struct net_device *netdev) 3009 { 3010 struct mlx5e_priv *priv = netdev_priv(netdev); 3011 3012 /* May already be CLOSED in case a previous configuration operation 3013 * (e.g RX/TX queue size change) that involves close&open failed. 3014 */ 3015 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) 3016 return 0; 3017 3018 mlx5e_apply_traps(priv, false); 3019 clear_bit(MLX5E_STATE_OPENED, &priv->state); 3020 3021 netif_carrier_off(priv->netdev); 3022 mlx5e_deactivate_priv_channels(priv); 3023 mlx5e_close_channels(&priv->channels); 3024 3025 return 0; 3026 } 3027 3028 int mlx5e_close(struct net_device *netdev) 3029 { 3030 struct mlx5e_priv *priv = netdev_priv(netdev); 3031 int err; 3032 3033 if (!netif_device_present(netdev)) 3034 return -ENODEV; 3035 3036 mutex_lock(&priv->state_lock); 3037 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_DOWN); 3038 err = mlx5e_close_locked(netdev); 3039 mutex_unlock(&priv->state_lock); 3040 3041 return err; 3042 } 3043 3044 static void mlx5e_free_drop_rq(struct mlx5e_rq *rq) 3045 { 3046 mlx5_wq_destroy(&rq->wq_ctrl); 3047 } 3048 3049 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev, 3050 struct mlx5e_rq *rq, 3051 struct mlx5e_rq_param *param) 3052 { 3053 void *rqc = param->rqc; 3054 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); 3055 int err; 3056 3057 param->wq.db_numa_node = param->wq.buf_numa_node; 3058 3059 err = mlx5_wq_cyc_create(mdev, ¶m->wq, rqc_wq, &rq->wqe.wq, 3060 &rq->wq_ctrl); 3061 if (err) 3062 return err; 3063 3064 /* Mark as unused given "Drop-RQ" packets never reach XDP */ 3065 xdp_rxq_info_unused(&rq->xdp_rxq); 3066 3067 rq->mdev = mdev; 3068 3069 return 0; 3070 } 3071 3072 static int mlx5e_alloc_drop_cq(struct mlx5e_priv *priv, 3073 struct mlx5e_cq *cq, 3074 struct mlx5e_cq_param *param) 3075 { 3076 struct mlx5_core_dev *mdev = priv->mdev; 3077 3078 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev)); 3079 param->wq.db_numa_node = dev_to_node(mlx5_core_dma_dev(mdev)); 3080 3081 return mlx5e_alloc_cq_common(priv, param, cq); 3082 } 3083 3084 int mlx5e_open_drop_rq(struct mlx5e_priv *priv, 3085 struct mlx5e_rq *drop_rq) 3086 { 3087 struct mlx5_core_dev *mdev = priv->mdev; 3088 struct mlx5e_cq_param cq_param = {}; 3089 struct mlx5e_rq_param rq_param = {}; 3090 struct mlx5e_cq *cq = &drop_rq->cq; 3091 int err; 3092 3093 mlx5e_build_drop_rq_param(mdev, priv->drop_rq_q_counter, &rq_param); 3094 3095 err = mlx5e_alloc_drop_cq(priv, cq, &cq_param); 3096 if (err) 3097 return err; 3098 3099 err = mlx5e_create_cq(cq, &cq_param); 3100 if (err) 3101 goto err_free_cq; 3102 3103 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param); 3104 if (err) 3105 goto err_destroy_cq; 3106 3107 err = mlx5e_create_rq(drop_rq, &rq_param); 3108 if (err) 3109 goto err_free_rq; 3110 3111 err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 3112 if (err) 3113 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err); 3114 3115 return 0; 3116 3117 err_free_rq: 3118 mlx5e_free_drop_rq(drop_rq); 3119 3120 err_destroy_cq: 3121 mlx5e_destroy_cq(cq); 3122 3123 err_free_cq: 3124 mlx5e_free_cq(cq); 3125 3126 return err; 3127 } 3128 3129 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq) 3130 { 3131 mlx5e_destroy_rq(drop_rq); 3132 mlx5e_free_drop_rq(drop_rq); 3133 mlx5e_destroy_cq(&drop_rq->cq); 3134 mlx5e_free_cq(&drop_rq->cq); 3135 } 3136 3137 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn) 3138 { 3139 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 3140 3141 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.hw_objs.td.tdn); 3142 3143 if (MLX5_GET(tisc, tisc, tls_en)) 3144 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.hw_objs.pdn); 3145 3146 if (mlx5_lag_is_lacp_owner(mdev)) 3147 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1); 3148 3149 return mlx5_core_create_tis(mdev, in, tisn); 3150 } 3151 3152 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn) 3153 { 3154 mlx5_core_destroy_tis(mdev, tisn); 3155 } 3156 3157 void mlx5e_destroy_tises(struct mlx5e_priv *priv) 3158 { 3159 int tc, i; 3160 3161 for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) 3162 for (tc = 0; tc < priv->profile->max_tc; tc++) 3163 mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]); 3164 } 3165 3166 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev) 3167 { 3168 return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1; 3169 } 3170 3171 int mlx5e_create_tises(struct mlx5e_priv *priv) 3172 { 3173 int tc, i; 3174 int err; 3175 3176 for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) { 3177 for (tc = 0; tc < priv->profile->max_tc; tc++) { 3178 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {}; 3179 void *tisc; 3180 3181 tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 3182 3183 MLX5_SET(tisc, tisc, prio, tc << 1); 3184 3185 if (mlx5e_lag_should_assign_affinity(priv->mdev)) 3186 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1); 3187 3188 err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]); 3189 if (err) 3190 goto err_close_tises; 3191 } 3192 } 3193 3194 return 0; 3195 3196 err_close_tises: 3197 for (; i >= 0; i--) { 3198 for (tc--; tc >= 0; tc--) 3199 mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]); 3200 tc = priv->profile->max_tc; 3201 } 3202 3203 return err; 3204 } 3205 3206 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv) 3207 { 3208 mlx5e_destroy_tises(priv); 3209 } 3210 3211 static void mlx5e_build_indir_tir_ctx_common(struct mlx5e_priv *priv, 3212 u32 rqtn, u32 *tirc) 3213 { 3214 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.hw_objs.td.tdn); 3215 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); 3216 MLX5_SET(tirc, tirc, indirect_table, rqtn); 3217 MLX5_SET(tirc, tirc, tunneled_offload_en, 3218 priv->channels.params.tunneled_offload_en); 3219 3220 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc); 3221 } 3222 3223 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, 3224 enum mlx5e_traffic_types tt, 3225 u32 *tirc) 3226 { 3227 mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc); 3228 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, 3229 &tirc_default_config[tt], tirc, false); 3230 } 3231 3232 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc) 3233 { 3234 mlx5e_build_indir_tir_ctx_common(priv, rqtn, tirc); 3235 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8); 3236 } 3237 3238 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv, 3239 enum mlx5e_traffic_types tt, 3240 u32 *tirc) 3241 { 3242 mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc); 3243 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, 3244 &tirc_default_config[tt], tirc, true); 3245 } 3246 3247 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc) 3248 { 3249 struct mlx5e_tir *tir; 3250 void *tirc; 3251 int inlen; 3252 int i = 0; 3253 int err; 3254 u32 *in; 3255 int tt; 3256 3257 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 3258 in = kvzalloc(inlen, GFP_KERNEL); 3259 if (!in) 3260 return -ENOMEM; 3261 3262 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { 3263 memset(in, 0, inlen); 3264 tir = &priv->indir_tir[tt]; 3265 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 3266 mlx5e_build_indir_tir_ctx(priv, tt, tirc); 3267 err = mlx5e_create_tir(priv->mdev, tir, in); 3268 if (err) { 3269 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err); 3270 goto err_destroy_inner_tirs; 3271 } 3272 } 3273 3274 if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev)) 3275 goto out; 3276 3277 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) { 3278 memset(in, 0, inlen); 3279 tir = &priv->inner_indir_tir[i]; 3280 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 3281 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc); 3282 err = mlx5e_create_tir(priv->mdev, tir, in); 3283 if (err) { 3284 mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err); 3285 goto err_destroy_inner_tirs; 3286 } 3287 } 3288 3289 out: 3290 kvfree(in); 3291 3292 return 0; 3293 3294 err_destroy_inner_tirs: 3295 for (i--; i >= 0; i--) 3296 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]); 3297 3298 for (tt--; tt >= 0; tt--) 3299 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]); 3300 3301 kvfree(in); 3302 3303 return err; 3304 } 3305 3306 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs, int n) 3307 { 3308 struct mlx5e_tir *tir; 3309 void *tirc; 3310 int inlen; 3311 int err = 0; 3312 u32 *in; 3313 int ix; 3314 3315 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 3316 in = kvzalloc(inlen, GFP_KERNEL); 3317 if (!in) 3318 return -ENOMEM; 3319 3320 for (ix = 0; ix < n; ix++) { 3321 memset(in, 0, inlen); 3322 tir = &tirs[ix]; 3323 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 3324 mlx5e_build_direct_tir_ctx(priv, tir->rqt.rqtn, tirc); 3325 err = mlx5e_create_tir(priv->mdev, tir, in); 3326 if (unlikely(err)) 3327 goto err_destroy_ch_tirs; 3328 } 3329 3330 goto out; 3331 3332 err_destroy_ch_tirs: 3333 mlx5_core_warn(priv->mdev, "create tirs failed, %d\n", err); 3334 for (ix--; ix >= 0; ix--) 3335 mlx5e_destroy_tir(priv->mdev, &tirs[ix]); 3336 3337 out: 3338 kvfree(in); 3339 3340 return err; 3341 } 3342 3343 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv) 3344 { 3345 int i; 3346 3347 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) 3348 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]); 3349 3350 /* Verify inner tirs resources allocated */ 3351 if (!priv->inner_indir_tir[0].tirn) 3352 return; 3353 3354 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) 3355 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]); 3356 } 3357 3358 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs, int n) 3359 { 3360 int i; 3361 3362 for (i = 0; i < n; i++) 3363 mlx5e_destroy_tir(priv->mdev, &tirs[i]); 3364 } 3365 3366 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable) 3367 { 3368 int err = 0; 3369 int i; 3370 3371 for (i = 0; i < chs->num; i++) { 3372 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable); 3373 if (err) 3374 return err; 3375 } 3376 3377 return 0; 3378 } 3379 3380 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd) 3381 { 3382 int err = 0; 3383 int i; 3384 3385 for (i = 0; i < chs->num; i++) { 3386 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd); 3387 if (err) 3388 return err; 3389 } 3390 3391 return 0; 3392 } 3393 3394 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv, 3395 struct tc_mqprio_qopt *mqprio) 3396 { 3397 struct mlx5e_params new_params; 3398 u8 tc = mqprio->num_tc; 3399 int err = 0; 3400 3401 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 3402 3403 if (tc && tc != MLX5E_MAX_NUM_TC) 3404 return -EINVAL; 3405 3406 mutex_lock(&priv->state_lock); 3407 3408 /* MQPRIO is another toplevel qdisc that can't be attached 3409 * simultaneously with the offloaded HTB. 3410 */ 3411 if (WARN_ON(priv->htb.maj_id)) { 3412 err = -EINVAL; 3413 goto out; 3414 } 3415 3416 new_params = priv->channels.params; 3417 new_params.num_tc = tc ? tc : 1; 3418 3419 err = mlx5e_safe_switch_params(priv, &new_params, 3420 mlx5e_num_channels_changed_ctx, NULL, true); 3421 3422 out: 3423 priv->max_opened_tc = max_t(u8, priv->max_opened_tc, 3424 priv->channels.params.num_tc); 3425 mutex_unlock(&priv->state_lock); 3426 return err; 3427 } 3428 3429 static int mlx5e_setup_tc_htb(struct mlx5e_priv *priv, struct tc_htb_qopt_offload *htb) 3430 { 3431 int res; 3432 3433 switch (htb->command) { 3434 case TC_HTB_CREATE: 3435 return mlx5e_htb_root_add(priv, htb->parent_classid, htb->classid, 3436 htb->extack); 3437 case TC_HTB_DESTROY: 3438 return mlx5e_htb_root_del(priv); 3439 case TC_HTB_LEAF_ALLOC_QUEUE: 3440 res = mlx5e_htb_leaf_alloc_queue(priv, htb->classid, htb->parent_classid, 3441 htb->rate, htb->ceil, htb->extack); 3442 if (res < 0) 3443 return res; 3444 htb->qid = res; 3445 return 0; 3446 case TC_HTB_LEAF_TO_INNER: 3447 return mlx5e_htb_leaf_to_inner(priv, htb->parent_classid, htb->classid, 3448 htb->rate, htb->ceil, htb->extack); 3449 case TC_HTB_LEAF_DEL: 3450 return mlx5e_htb_leaf_del(priv, htb->classid, &htb->moved_qid, &htb->qid, 3451 htb->extack); 3452 case TC_HTB_LEAF_DEL_LAST: 3453 case TC_HTB_LEAF_DEL_LAST_FORCE: 3454 return mlx5e_htb_leaf_del_last(priv, htb->classid, 3455 htb->command == TC_HTB_LEAF_DEL_LAST_FORCE, 3456 htb->extack); 3457 case TC_HTB_NODE_MODIFY: 3458 return mlx5e_htb_node_modify(priv, htb->classid, htb->rate, htb->ceil, 3459 htb->extack); 3460 case TC_HTB_LEAF_QUERY_QUEUE: 3461 res = mlx5e_get_txq_by_classid(priv, htb->classid); 3462 if (res < 0) 3463 return res; 3464 htb->qid = res; 3465 return 0; 3466 default: 3467 return -EOPNOTSUPP; 3468 } 3469 } 3470 3471 static LIST_HEAD(mlx5e_block_cb_list); 3472 3473 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type, 3474 void *type_data) 3475 { 3476 struct mlx5e_priv *priv = netdev_priv(dev); 3477 bool tc_unbind = false; 3478 int err; 3479 3480 if (type == TC_SETUP_BLOCK && 3481 ((struct flow_block_offload *)type_data)->command == FLOW_BLOCK_UNBIND) 3482 tc_unbind = true; 3483 3484 if (!netif_device_present(dev) && !tc_unbind) 3485 return -ENODEV; 3486 3487 switch (type) { 3488 case TC_SETUP_BLOCK: { 3489 struct flow_block_offload *f = type_data; 3490 3491 f->unlocked_driver_cb = true; 3492 return flow_block_cb_setup_simple(type_data, 3493 &mlx5e_block_cb_list, 3494 mlx5e_setup_tc_block_cb, 3495 priv, priv, true); 3496 } 3497 case TC_SETUP_QDISC_MQPRIO: 3498 return mlx5e_setup_tc_mqprio(priv, type_data); 3499 case TC_SETUP_QDISC_HTB: 3500 mutex_lock(&priv->state_lock); 3501 err = mlx5e_setup_tc_htb(priv, type_data); 3502 mutex_unlock(&priv->state_lock); 3503 return err; 3504 default: 3505 return -EOPNOTSUPP; 3506 } 3507 } 3508 3509 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s) 3510 { 3511 int i; 3512 3513 for (i = 0; i < priv->max_nch; i++) { 3514 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i]; 3515 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq; 3516 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq; 3517 int j; 3518 3519 s->rx_packets += rq_stats->packets + xskrq_stats->packets; 3520 s->rx_bytes += rq_stats->bytes + xskrq_stats->bytes; 3521 s->multicast += rq_stats->mcast_packets + xskrq_stats->mcast_packets; 3522 3523 for (j = 0; j < priv->max_opened_tc; j++) { 3524 struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j]; 3525 3526 s->tx_packets += sq_stats->packets; 3527 s->tx_bytes += sq_stats->bytes; 3528 s->tx_dropped += sq_stats->dropped; 3529 } 3530 } 3531 if (priv->tx_ptp_opened) { 3532 for (i = 0; i < priv->max_opened_tc; i++) { 3533 struct mlx5e_sq_stats *sq_stats = &priv->ptp_stats.sq[i]; 3534 3535 s->tx_packets += sq_stats->packets; 3536 s->tx_bytes += sq_stats->bytes; 3537 s->tx_dropped += sq_stats->dropped; 3538 } 3539 } 3540 if (priv->rx_ptp_opened) { 3541 struct mlx5e_rq_stats *rq_stats = &priv->ptp_stats.rq; 3542 3543 s->rx_packets += rq_stats->packets; 3544 s->rx_bytes += rq_stats->bytes; 3545 s->multicast += rq_stats->mcast_packets; 3546 } 3547 } 3548 3549 void 3550 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats) 3551 { 3552 struct mlx5e_priv *priv = netdev_priv(dev); 3553 struct mlx5e_pport_stats *pstats = &priv->stats.pport; 3554 3555 if (!netif_device_present(dev)) 3556 return; 3557 3558 /* In switchdev mode, monitor counters doesn't monitor 3559 * rx/tx stats of 802_3. The update stats mechanism 3560 * should keep the 802_3 layout counters updated 3561 */ 3562 if (!mlx5e_monitor_counter_supported(priv) || 3563 mlx5e_is_uplink_rep(priv)) { 3564 /* update HW stats in background for next time */ 3565 mlx5e_queue_update_stats(priv); 3566 } 3567 3568 if (mlx5e_is_uplink_rep(priv)) { 3569 struct mlx5e_vport_stats *vstats = &priv->stats.vport; 3570 3571 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok); 3572 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok); 3573 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok); 3574 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok); 3575 3576 /* vport multicast also counts packets that are dropped due to steering 3577 * or rx out of buffer 3578 */ 3579 stats->multicast = VPORT_COUNTER_GET(vstats, received_eth_multicast.packets); 3580 } else { 3581 mlx5e_fold_sw_stats64(priv, stats); 3582 } 3583 3584 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer; 3585 3586 stats->rx_length_errors = 3587 PPORT_802_3_GET(pstats, a_in_range_length_errors) + 3588 PPORT_802_3_GET(pstats, a_out_of_range_length_field) + 3589 PPORT_802_3_GET(pstats, a_frame_too_long_errors); 3590 stats->rx_crc_errors = 3591 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors); 3592 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors); 3593 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards); 3594 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 3595 stats->rx_frame_errors; 3596 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors; 3597 } 3598 3599 static void mlx5e_nic_set_rx_mode(struct mlx5e_priv *priv) 3600 { 3601 if (mlx5e_is_uplink_rep(priv)) 3602 return; /* no rx mode for uplink rep */ 3603 3604 queue_work(priv->wq, &priv->set_rx_mode_work); 3605 } 3606 3607 static void mlx5e_set_rx_mode(struct net_device *dev) 3608 { 3609 struct mlx5e_priv *priv = netdev_priv(dev); 3610 3611 mlx5e_nic_set_rx_mode(priv); 3612 } 3613 3614 static int mlx5e_set_mac(struct net_device *netdev, void *addr) 3615 { 3616 struct mlx5e_priv *priv = netdev_priv(netdev); 3617 struct sockaddr *saddr = addr; 3618 3619 if (!is_valid_ether_addr(saddr->sa_data)) 3620 return -EADDRNOTAVAIL; 3621 3622 netif_addr_lock_bh(netdev); 3623 ether_addr_copy(netdev->dev_addr, saddr->sa_data); 3624 netif_addr_unlock_bh(netdev); 3625 3626 mlx5e_nic_set_rx_mode(priv); 3627 3628 return 0; 3629 } 3630 3631 #define MLX5E_SET_FEATURE(features, feature, enable) \ 3632 do { \ 3633 if (enable) \ 3634 *features |= feature; \ 3635 else \ 3636 *features &= ~feature; \ 3637 } while (0) 3638 3639 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable); 3640 3641 static int set_feature_lro(struct net_device *netdev, bool enable) 3642 { 3643 struct mlx5e_priv *priv = netdev_priv(netdev); 3644 struct mlx5_core_dev *mdev = priv->mdev; 3645 struct mlx5e_params *cur_params; 3646 struct mlx5e_params new_params; 3647 bool reset = true; 3648 int err = 0; 3649 3650 mutex_lock(&priv->state_lock); 3651 3652 if (enable && priv->xsk.refcnt) { 3653 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%u XSKs are active)\n", 3654 priv->xsk.refcnt); 3655 err = -EINVAL; 3656 goto out; 3657 } 3658 3659 cur_params = &priv->channels.params; 3660 if (enable && !MLX5E_GET_PFLAG(cur_params, MLX5E_PFLAG_RX_STRIDING_RQ)) { 3661 netdev_warn(netdev, "can't set LRO with legacy RQ\n"); 3662 err = -EINVAL; 3663 goto out; 3664 } 3665 3666 new_params = *cur_params; 3667 new_params.lro_en = enable; 3668 3669 if (cur_params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) { 3670 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, cur_params, NULL) == 3671 mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_params, NULL)) 3672 reset = false; 3673 } 3674 3675 err = mlx5e_safe_switch_params(priv, &new_params, 3676 mlx5e_modify_tirs_lro_ctx, NULL, reset); 3677 out: 3678 mutex_unlock(&priv->state_lock); 3679 return err; 3680 } 3681 3682 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable) 3683 { 3684 struct mlx5e_priv *priv = netdev_priv(netdev); 3685 3686 if (enable) 3687 mlx5e_enable_cvlan_filter(priv); 3688 else 3689 mlx5e_disable_cvlan_filter(priv); 3690 3691 return 0; 3692 } 3693 3694 static int set_feature_hw_tc(struct net_device *netdev, bool enable) 3695 { 3696 struct mlx5e_priv *priv = netdev_priv(netdev); 3697 3698 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT) 3699 if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) { 3700 netdev_err(netdev, 3701 "Active offloaded tc filters, can't turn hw_tc_offload off\n"); 3702 return -EINVAL; 3703 } 3704 #endif 3705 3706 if (!enable && priv->htb.maj_id) { 3707 netdev_err(netdev, "Active HTB offload, can't turn hw_tc_offload off\n"); 3708 return -EINVAL; 3709 } 3710 3711 return 0; 3712 } 3713 3714 static int set_feature_rx_all(struct net_device *netdev, bool enable) 3715 { 3716 struct mlx5e_priv *priv = netdev_priv(netdev); 3717 struct mlx5_core_dev *mdev = priv->mdev; 3718 3719 return mlx5_set_port_fcs(mdev, !enable); 3720 } 3721 3722 static int set_feature_rx_fcs(struct net_device *netdev, bool enable) 3723 { 3724 struct mlx5e_priv *priv = netdev_priv(netdev); 3725 int err; 3726 3727 mutex_lock(&priv->state_lock); 3728 3729 priv->channels.params.scatter_fcs_en = enable; 3730 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable); 3731 if (err) 3732 priv->channels.params.scatter_fcs_en = !enable; 3733 3734 mutex_unlock(&priv->state_lock); 3735 3736 return err; 3737 } 3738 3739 static int set_feature_rx_vlan(struct net_device *netdev, bool enable) 3740 { 3741 struct mlx5e_priv *priv = netdev_priv(netdev); 3742 int err = 0; 3743 3744 mutex_lock(&priv->state_lock); 3745 3746 priv->channels.params.vlan_strip_disable = !enable; 3747 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) 3748 goto unlock; 3749 3750 err = mlx5e_modify_channels_vsd(&priv->channels, !enable); 3751 if (err) 3752 priv->channels.params.vlan_strip_disable = enable; 3753 3754 unlock: 3755 mutex_unlock(&priv->state_lock); 3756 3757 return err; 3758 } 3759 3760 #ifdef CONFIG_MLX5_EN_ARFS 3761 static int set_feature_arfs(struct net_device *netdev, bool enable) 3762 { 3763 struct mlx5e_priv *priv = netdev_priv(netdev); 3764 int err; 3765 3766 if (enable) 3767 err = mlx5e_arfs_enable(priv); 3768 else 3769 err = mlx5e_arfs_disable(priv); 3770 3771 return err; 3772 } 3773 #endif 3774 3775 static int mlx5e_handle_feature(struct net_device *netdev, 3776 netdev_features_t *features, 3777 netdev_features_t wanted_features, 3778 netdev_features_t feature, 3779 mlx5e_feature_handler feature_handler) 3780 { 3781 netdev_features_t changes = wanted_features ^ netdev->features; 3782 bool enable = !!(wanted_features & feature); 3783 int err; 3784 3785 if (!(changes & feature)) 3786 return 0; 3787 3788 err = feature_handler(netdev, enable); 3789 if (err) { 3790 netdev_err(netdev, "%s feature %pNF failed, err %d\n", 3791 enable ? "Enable" : "Disable", &feature, err); 3792 return err; 3793 } 3794 3795 MLX5E_SET_FEATURE(features, feature, enable); 3796 return 0; 3797 } 3798 3799 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features) 3800 { 3801 netdev_features_t oper_features = netdev->features; 3802 int err = 0; 3803 3804 #define MLX5E_HANDLE_FEATURE(feature, handler) \ 3805 mlx5e_handle_feature(netdev, &oper_features, features, feature, handler) 3806 3807 err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro); 3808 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER, 3809 set_feature_cvlan_filter); 3810 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_hw_tc); 3811 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all); 3812 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs); 3813 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan); 3814 #ifdef CONFIG_MLX5_EN_ARFS 3815 err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs); 3816 #endif 3817 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TLS_RX, mlx5e_ktls_set_feature_rx); 3818 3819 if (err) { 3820 netdev->features = oper_features; 3821 return -EINVAL; 3822 } 3823 3824 return 0; 3825 } 3826 3827 static netdev_features_t mlx5e_fix_features(struct net_device *netdev, 3828 netdev_features_t features) 3829 { 3830 struct mlx5e_priv *priv = netdev_priv(netdev); 3831 struct mlx5e_params *params; 3832 3833 mutex_lock(&priv->state_lock); 3834 params = &priv->channels.params; 3835 if (!priv->fs.vlan || 3836 !bitmap_empty(mlx5e_vlan_get_active_svlans(priv->fs.vlan), VLAN_N_VID)) { 3837 /* HW strips the outer C-tag header, this is a problem 3838 * for S-tag traffic. 3839 */ 3840 features &= ~NETIF_F_HW_VLAN_CTAG_RX; 3841 if (!params->vlan_strip_disable) 3842 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n"); 3843 } 3844 3845 if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) { 3846 if (features & NETIF_F_LRO) { 3847 netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n"); 3848 features &= ~NETIF_F_LRO; 3849 } 3850 } 3851 3852 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) { 3853 features &= ~NETIF_F_RXHASH; 3854 if (netdev->features & NETIF_F_RXHASH) 3855 netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n"); 3856 } 3857 3858 mutex_unlock(&priv->state_lock); 3859 3860 return features; 3861 } 3862 3863 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev, 3864 struct mlx5e_channels *chs, 3865 struct mlx5e_params *new_params, 3866 struct mlx5_core_dev *mdev) 3867 { 3868 u16 ix; 3869 3870 for (ix = 0; ix < chs->params.num_channels; ix++) { 3871 struct xsk_buff_pool *xsk_pool = 3872 mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, ix); 3873 struct mlx5e_xsk_param xsk; 3874 3875 if (!xsk_pool) 3876 continue; 3877 3878 mlx5e_build_xsk_param(xsk_pool, &xsk); 3879 3880 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) { 3881 u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk); 3882 int max_mtu_frame, max_mtu_page, max_mtu; 3883 3884 /* Two criteria must be met: 3885 * 1. HW MTU + all headrooms <= XSK frame size. 3886 * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE. 3887 */ 3888 max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr); 3889 max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk); 3890 max_mtu = min(max_mtu_frame, max_mtu_page); 3891 3892 netdev_err(netdev, "MTU %d is too big for an XSK running on channel %u. Try MTU <= %d\n", 3893 new_params->sw_mtu, ix, max_mtu); 3894 return false; 3895 } 3896 } 3897 3898 return true; 3899 } 3900 3901 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu, 3902 mlx5e_fp_preactivate preactivate) 3903 { 3904 struct mlx5e_priv *priv = netdev_priv(netdev); 3905 struct mlx5e_params new_params; 3906 struct mlx5e_params *params; 3907 bool reset = true; 3908 int err = 0; 3909 3910 mutex_lock(&priv->state_lock); 3911 3912 params = &priv->channels.params; 3913 3914 new_params = *params; 3915 new_params.sw_mtu = new_mtu; 3916 err = mlx5e_validate_params(priv->mdev, &new_params); 3917 if (err) 3918 goto out; 3919 3920 if (params->xdp_prog && 3921 !mlx5e_rx_is_linear_skb(&new_params, NULL)) { 3922 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n", 3923 new_mtu, mlx5e_xdp_max_mtu(params, NULL)); 3924 err = -EINVAL; 3925 goto out; 3926 } 3927 3928 if (priv->xsk.refcnt && 3929 !mlx5e_xsk_validate_mtu(netdev, &priv->channels, 3930 &new_params, priv->mdev)) { 3931 err = -EINVAL; 3932 goto out; 3933 } 3934 3935 if (params->lro_en) 3936 reset = false; 3937 3938 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) { 3939 bool is_linear_old = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, params, NULL); 3940 bool is_linear_new = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, 3941 &new_params, NULL); 3942 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL); 3943 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_params, NULL); 3944 3945 /* Always reset in linear mode - hw_mtu is used in data path. 3946 * Check that the mode was non-linear and didn't change. 3947 * If XSK is active, XSK RQs are linear. 3948 */ 3949 if (!is_linear_old && !is_linear_new && !priv->xsk.refcnt && 3950 ppw_old == ppw_new) 3951 reset = false; 3952 } 3953 3954 err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, reset); 3955 3956 out: 3957 netdev->mtu = params->sw_mtu; 3958 mutex_unlock(&priv->state_lock); 3959 return err; 3960 } 3961 3962 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu) 3963 { 3964 return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx); 3965 } 3966 3967 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx) 3968 { 3969 bool set = *(bool *)ctx; 3970 3971 return mlx5e_ptp_rx_manage_fs(priv, set); 3972 } 3973 3974 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr) 3975 { 3976 struct mlx5e_params new_params; 3977 struct hwtstamp_config config; 3978 bool rx_cqe_compress_def; 3979 int err; 3980 3981 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) || 3982 (mlx5_clock_get_ptp_index(priv->mdev) == -1)) 3983 return -EOPNOTSUPP; 3984 3985 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 3986 return -EFAULT; 3987 3988 /* TX HW timestamp */ 3989 switch (config.tx_type) { 3990 case HWTSTAMP_TX_OFF: 3991 case HWTSTAMP_TX_ON: 3992 break; 3993 default: 3994 return -ERANGE; 3995 } 3996 3997 mutex_lock(&priv->state_lock); 3998 new_params = priv->channels.params; 3999 rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def; 4000 4001 /* RX HW timestamp */ 4002 switch (config.rx_filter) { 4003 case HWTSTAMP_FILTER_NONE: 4004 new_params.ptp_rx = false; 4005 break; 4006 case HWTSTAMP_FILTER_ALL: 4007 case HWTSTAMP_FILTER_SOME: 4008 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 4009 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 4010 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 4011 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 4012 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 4013 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 4014 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 4015 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 4016 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 4017 case HWTSTAMP_FILTER_PTP_V2_EVENT: 4018 case HWTSTAMP_FILTER_PTP_V2_SYNC: 4019 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 4020 case HWTSTAMP_FILTER_NTP_ALL: 4021 new_params.ptp_rx = rx_cqe_compress_def; 4022 config.rx_filter = HWTSTAMP_FILTER_ALL; 4023 break; 4024 default: 4025 mutex_unlock(&priv->state_lock); 4026 return -ERANGE; 4027 } 4028 4029 if (new_params.ptp_rx == priv->channels.params.ptp_rx) 4030 goto out; 4031 4032 err = mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx, 4033 &new_params.ptp_rx, true); 4034 if (err) { 4035 mutex_unlock(&priv->state_lock); 4036 return err; 4037 } 4038 out: 4039 memcpy(&priv->tstamp, &config, sizeof(config)); 4040 mutex_unlock(&priv->state_lock); 4041 4042 /* might need to fix some features */ 4043 netdev_update_features(priv->netdev); 4044 4045 return copy_to_user(ifr->ifr_data, &config, 4046 sizeof(config)) ? -EFAULT : 0; 4047 } 4048 4049 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr) 4050 { 4051 struct hwtstamp_config *cfg = &priv->tstamp; 4052 4053 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz)) 4054 return -EOPNOTSUPP; 4055 4056 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0; 4057 } 4058 4059 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 4060 { 4061 struct mlx5e_priv *priv = netdev_priv(dev); 4062 4063 switch (cmd) { 4064 case SIOCSHWTSTAMP: 4065 return mlx5e_hwstamp_set(priv, ifr); 4066 case SIOCGHWTSTAMP: 4067 return mlx5e_hwstamp_get(priv, ifr); 4068 default: 4069 return -EOPNOTSUPP; 4070 } 4071 } 4072 4073 #ifdef CONFIG_MLX5_ESWITCH 4074 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac) 4075 { 4076 struct mlx5e_priv *priv = netdev_priv(dev); 4077 struct mlx5_core_dev *mdev = priv->mdev; 4078 4079 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac); 4080 } 4081 4082 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos, 4083 __be16 vlan_proto) 4084 { 4085 struct mlx5e_priv *priv = netdev_priv(dev); 4086 struct mlx5_core_dev *mdev = priv->mdev; 4087 4088 if (vlan_proto != htons(ETH_P_8021Q)) 4089 return -EPROTONOSUPPORT; 4090 4091 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1, 4092 vlan, qos); 4093 } 4094 4095 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting) 4096 { 4097 struct mlx5e_priv *priv = netdev_priv(dev); 4098 struct mlx5_core_dev *mdev = priv->mdev; 4099 4100 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting); 4101 } 4102 4103 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting) 4104 { 4105 struct mlx5e_priv *priv = netdev_priv(dev); 4106 struct mlx5_core_dev *mdev = priv->mdev; 4107 4108 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting); 4109 } 4110 4111 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, 4112 int max_tx_rate) 4113 { 4114 struct mlx5e_priv *priv = netdev_priv(dev); 4115 struct mlx5_core_dev *mdev = priv->mdev; 4116 4117 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1, 4118 max_tx_rate, min_tx_rate); 4119 } 4120 4121 static int mlx5_vport_link2ifla(u8 esw_link) 4122 { 4123 switch (esw_link) { 4124 case MLX5_VPORT_ADMIN_STATE_DOWN: 4125 return IFLA_VF_LINK_STATE_DISABLE; 4126 case MLX5_VPORT_ADMIN_STATE_UP: 4127 return IFLA_VF_LINK_STATE_ENABLE; 4128 } 4129 return IFLA_VF_LINK_STATE_AUTO; 4130 } 4131 4132 static int mlx5_ifla_link2vport(u8 ifla_link) 4133 { 4134 switch (ifla_link) { 4135 case IFLA_VF_LINK_STATE_DISABLE: 4136 return MLX5_VPORT_ADMIN_STATE_DOWN; 4137 case IFLA_VF_LINK_STATE_ENABLE: 4138 return MLX5_VPORT_ADMIN_STATE_UP; 4139 } 4140 return MLX5_VPORT_ADMIN_STATE_AUTO; 4141 } 4142 4143 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf, 4144 int link_state) 4145 { 4146 struct mlx5e_priv *priv = netdev_priv(dev); 4147 struct mlx5_core_dev *mdev = priv->mdev; 4148 4149 if (mlx5e_is_uplink_rep(priv)) 4150 return -EOPNOTSUPP; 4151 4152 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1, 4153 mlx5_ifla_link2vport(link_state)); 4154 } 4155 4156 int mlx5e_get_vf_config(struct net_device *dev, 4157 int vf, struct ifla_vf_info *ivi) 4158 { 4159 struct mlx5e_priv *priv = netdev_priv(dev); 4160 struct mlx5_core_dev *mdev = priv->mdev; 4161 int err; 4162 4163 if (!netif_device_present(dev)) 4164 return -EOPNOTSUPP; 4165 4166 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi); 4167 if (err) 4168 return err; 4169 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate); 4170 return 0; 4171 } 4172 4173 int mlx5e_get_vf_stats(struct net_device *dev, 4174 int vf, struct ifla_vf_stats *vf_stats) 4175 { 4176 struct mlx5e_priv *priv = netdev_priv(dev); 4177 struct mlx5_core_dev *mdev = priv->mdev; 4178 4179 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1, 4180 vf_stats); 4181 } 4182 4183 static bool 4184 mlx5e_has_offload_stats(const struct net_device *dev, int attr_id) 4185 { 4186 struct mlx5e_priv *priv = netdev_priv(dev); 4187 4188 if (!netif_device_present(dev)) 4189 return false; 4190 4191 if (!mlx5e_is_uplink_rep(priv)) 4192 return false; 4193 4194 return mlx5e_rep_has_offload_stats(dev, attr_id); 4195 } 4196 4197 static int 4198 mlx5e_get_offload_stats(int attr_id, const struct net_device *dev, 4199 void *sp) 4200 { 4201 struct mlx5e_priv *priv = netdev_priv(dev); 4202 4203 if (!mlx5e_is_uplink_rep(priv)) 4204 return -EOPNOTSUPP; 4205 4206 return mlx5e_rep_get_offload_stats(attr_id, dev, sp); 4207 } 4208 #endif 4209 4210 static bool mlx5e_tunnel_proto_supported_tx(struct mlx5_core_dev *mdev, u8 proto_type) 4211 { 4212 switch (proto_type) { 4213 case IPPROTO_GRE: 4214 return MLX5_CAP_ETH(mdev, tunnel_stateless_gre); 4215 case IPPROTO_IPIP: 4216 case IPPROTO_IPV6: 4217 return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) || 4218 MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_tx)); 4219 default: 4220 return false; 4221 } 4222 } 4223 4224 static bool mlx5e_gre_tunnel_inner_proto_offload_supported(struct mlx5_core_dev *mdev, 4225 struct sk_buff *skb) 4226 { 4227 switch (skb->inner_protocol) { 4228 case htons(ETH_P_IP): 4229 case htons(ETH_P_IPV6): 4230 case htons(ETH_P_TEB): 4231 return true; 4232 case htons(ETH_P_MPLS_UC): 4233 case htons(ETH_P_MPLS_MC): 4234 return MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre); 4235 } 4236 return false; 4237 } 4238 4239 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv, 4240 struct sk_buff *skb, 4241 netdev_features_t features) 4242 { 4243 unsigned int offset = 0; 4244 struct udphdr *udph; 4245 u8 proto; 4246 u16 port; 4247 4248 switch (vlan_get_protocol(skb)) { 4249 case htons(ETH_P_IP): 4250 proto = ip_hdr(skb)->protocol; 4251 break; 4252 case htons(ETH_P_IPV6): 4253 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL); 4254 break; 4255 default: 4256 goto out; 4257 } 4258 4259 switch (proto) { 4260 case IPPROTO_GRE: 4261 if (mlx5e_gre_tunnel_inner_proto_offload_supported(priv->mdev, skb)) 4262 return features; 4263 break; 4264 case IPPROTO_IPIP: 4265 case IPPROTO_IPV6: 4266 if (mlx5e_tunnel_proto_supported_tx(priv->mdev, IPPROTO_IPIP)) 4267 return features; 4268 break; 4269 case IPPROTO_UDP: 4270 udph = udp_hdr(skb); 4271 port = be16_to_cpu(udph->dest); 4272 4273 /* Verify if UDP port is being offloaded by HW */ 4274 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port)) 4275 return features; 4276 4277 #if IS_ENABLED(CONFIG_GENEVE) 4278 /* Support Geneve offload for default UDP port */ 4279 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev)) 4280 return features; 4281 #endif 4282 } 4283 4284 out: 4285 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */ 4286 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 4287 } 4288 4289 netdev_features_t mlx5e_features_check(struct sk_buff *skb, 4290 struct net_device *netdev, 4291 netdev_features_t features) 4292 { 4293 struct mlx5e_priv *priv = netdev_priv(netdev); 4294 4295 features = vlan_features_check(skb, features); 4296 features = vxlan_features_check(skb, features); 4297 4298 if (mlx5e_ipsec_feature_check(skb, netdev, features)) 4299 return features; 4300 4301 /* Validate if the tunneled packet is being offloaded by HW */ 4302 if (skb->encapsulation && 4303 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK)) 4304 return mlx5e_tunnel_features_check(priv, skb, features); 4305 4306 return features; 4307 } 4308 4309 static void mlx5e_tx_timeout_work(struct work_struct *work) 4310 { 4311 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, 4312 tx_timeout_work); 4313 struct net_device *netdev = priv->netdev; 4314 int i; 4315 4316 rtnl_lock(); 4317 mutex_lock(&priv->state_lock); 4318 4319 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) 4320 goto unlock; 4321 4322 for (i = 0; i < netdev->real_num_tx_queues; i++) { 4323 struct netdev_queue *dev_queue = 4324 netdev_get_tx_queue(netdev, i); 4325 struct mlx5e_txqsq *sq = priv->txq2sq[i]; 4326 4327 if (!netif_xmit_stopped(dev_queue)) 4328 continue; 4329 4330 if (mlx5e_reporter_tx_timeout(sq)) 4331 /* break if tried to reopened channels */ 4332 break; 4333 } 4334 4335 unlock: 4336 mutex_unlock(&priv->state_lock); 4337 rtnl_unlock(); 4338 } 4339 4340 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue) 4341 { 4342 struct mlx5e_priv *priv = netdev_priv(dev); 4343 4344 netdev_err(dev, "TX timeout detected\n"); 4345 queue_work(priv->wq, &priv->tx_timeout_work); 4346 } 4347 4348 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog) 4349 { 4350 struct net_device *netdev = priv->netdev; 4351 struct mlx5e_params new_params; 4352 4353 if (priv->channels.params.lro_en) { 4354 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n"); 4355 return -EINVAL; 4356 } 4357 4358 if (mlx5_fpga_is_ipsec_device(priv->mdev)) { 4359 netdev_warn(netdev, 4360 "XDP is not available on Innova cards with IPsec support\n"); 4361 return -EINVAL; 4362 } 4363 4364 new_params = priv->channels.params; 4365 new_params.xdp_prog = prog; 4366 4367 /* No XSK params: AF_XDP can't be enabled yet at the point of setting 4368 * the XDP program. 4369 */ 4370 if (!mlx5e_rx_is_linear_skb(&new_params, NULL)) { 4371 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n", 4372 new_params.sw_mtu, 4373 mlx5e_xdp_max_mtu(&new_params, NULL)); 4374 return -EINVAL; 4375 } 4376 4377 return 0; 4378 } 4379 4380 static void mlx5e_rq_replace_xdp_prog(struct mlx5e_rq *rq, struct bpf_prog *prog) 4381 { 4382 struct bpf_prog *old_prog; 4383 4384 old_prog = rcu_replace_pointer(rq->xdp_prog, prog, 4385 lockdep_is_held(&rq->priv->state_lock)); 4386 if (old_prog) 4387 bpf_prog_put(old_prog); 4388 } 4389 4390 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog) 4391 { 4392 struct mlx5e_priv *priv = netdev_priv(netdev); 4393 struct mlx5e_params new_params; 4394 struct bpf_prog *old_prog; 4395 int err = 0; 4396 bool reset; 4397 int i; 4398 4399 mutex_lock(&priv->state_lock); 4400 4401 if (prog) { 4402 err = mlx5e_xdp_allowed(priv, prog); 4403 if (err) 4404 goto unlock; 4405 } 4406 4407 /* no need for full reset when exchanging programs */ 4408 reset = (!priv->channels.params.xdp_prog || !prog); 4409 4410 new_params = priv->channels.params; 4411 new_params.xdp_prog = prog; 4412 if (reset) 4413 mlx5e_set_rq_type(priv->mdev, &new_params); 4414 old_prog = priv->channels.params.xdp_prog; 4415 4416 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset); 4417 if (err) 4418 goto unlock; 4419 4420 if (old_prog) 4421 bpf_prog_put(old_prog); 4422 4423 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset) 4424 goto unlock; 4425 4426 /* exchanging programs w/o reset, we update ref counts on behalf 4427 * of the channels RQs here. 4428 */ 4429 bpf_prog_add(prog, priv->channels.num); 4430 for (i = 0; i < priv->channels.num; i++) { 4431 struct mlx5e_channel *c = priv->channels.c[i]; 4432 4433 mlx5e_rq_replace_xdp_prog(&c->rq, prog); 4434 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) { 4435 bpf_prog_inc(prog); 4436 mlx5e_rq_replace_xdp_prog(&c->xskrq, prog); 4437 } 4438 } 4439 4440 unlock: 4441 mutex_unlock(&priv->state_lock); 4442 return err; 4443 } 4444 4445 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp) 4446 { 4447 switch (xdp->command) { 4448 case XDP_SETUP_PROG: 4449 return mlx5e_xdp_set(dev, xdp->prog); 4450 case XDP_SETUP_XSK_POOL: 4451 return mlx5e_xsk_setup_pool(dev, xdp->xsk.pool, 4452 xdp->xsk.queue_id); 4453 default: 4454 return -EINVAL; 4455 } 4456 } 4457 4458 #ifdef CONFIG_MLX5_ESWITCH 4459 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 4460 struct net_device *dev, u32 filter_mask, 4461 int nlflags) 4462 { 4463 struct mlx5e_priv *priv = netdev_priv(dev); 4464 struct mlx5_core_dev *mdev = priv->mdev; 4465 u8 mode, setting; 4466 int err; 4467 4468 err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting); 4469 if (err) 4470 return err; 4471 mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB; 4472 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, 4473 mode, 4474 0, 0, nlflags, filter_mask, NULL); 4475 } 4476 4477 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh, 4478 u16 flags, struct netlink_ext_ack *extack) 4479 { 4480 struct mlx5e_priv *priv = netdev_priv(dev); 4481 struct mlx5_core_dev *mdev = priv->mdev; 4482 struct nlattr *attr, *br_spec; 4483 u16 mode = BRIDGE_MODE_UNDEF; 4484 u8 setting; 4485 int rem; 4486 4487 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 4488 if (!br_spec) 4489 return -EINVAL; 4490 4491 nla_for_each_nested(attr, br_spec, rem) { 4492 if (nla_type(attr) != IFLA_BRIDGE_MODE) 4493 continue; 4494 4495 if (nla_len(attr) < sizeof(mode)) 4496 return -EINVAL; 4497 4498 mode = nla_get_u16(attr); 4499 if (mode > BRIDGE_MODE_VEPA) 4500 return -EINVAL; 4501 4502 break; 4503 } 4504 4505 if (mode == BRIDGE_MODE_UNDEF) 4506 return -EINVAL; 4507 4508 setting = (mode == BRIDGE_MODE_VEPA) ? 1 : 0; 4509 return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting); 4510 } 4511 #endif 4512 4513 const struct net_device_ops mlx5e_netdev_ops = { 4514 .ndo_open = mlx5e_open, 4515 .ndo_stop = mlx5e_close, 4516 .ndo_start_xmit = mlx5e_xmit, 4517 .ndo_setup_tc = mlx5e_setup_tc, 4518 .ndo_select_queue = mlx5e_select_queue, 4519 .ndo_get_stats64 = mlx5e_get_stats, 4520 .ndo_set_rx_mode = mlx5e_set_rx_mode, 4521 .ndo_set_mac_address = mlx5e_set_mac, 4522 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid, 4523 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid, 4524 .ndo_set_features = mlx5e_set_features, 4525 .ndo_fix_features = mlx5e_fix_features, 4526 .ndo_change_mtu = mlx5e_change_nic_mtu, 4527 .ndo_do_ioctl = mlx5e_ioctl, 4528 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate, 4529 .ndo_features_check = mlx5e_features_check, 4530 .ndo_tx_timeout = mlx5e_tx_timeout, 4531 .ndo_bpf = mlx5e_xdp, 4532 .ndo_xdp_xmit = mlx5e_xdp_xmit, 4533 .ndo_xsk_wakeup = mlx5e_xsk_wakeup, 4534 #ifdef CONFIG_MLX5_EN_ARFS 4535 .ndo_rx_flow_steer = mlx5e_rx_flow_steer, 4536 #endif 4537 #ifdef CONFIG_MLX5_ESWITCH 4538 .ndo_bridge_setlink = mlx5e_bridge_setlink, 4539 .ndo_bridge_getlink = mlx5e_bridge_getlink, 4540 4541 /* SRIOV E-Switch NDOs */ 4542 .ndo_set_vf_mac = mlx5e_set_vf_mac, 4543 .ndo_set_vf_vlan = mlx5e_set_vf_vlan, 4544 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk, 4545 .ndo_set_vf_trust = mlx5e_set_vf_trust, 4546 .ndo_set_vf_rate = mlx5e_set_vf_rate, 4547 .ndo_get_vf_config = mlx5e_get_vf_config, 4548 .ndo_set_vf_link_state = mlx5e_set_vf_link_state, 4549 .ndo_get_vf_stats = mlx5e_get_vf_stats, 4550 .ndo_has_offload_stats = mlx5e_has_offload_stats, 4551 .ndo_get_offload_stats = mlx5e_get_offload_stats, 4552 #endif 4553 .ndo_get_devlink_port = mlx5e_get_devlink_port, 4554 }; 4555 4556 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len, 4557 int num_channels) 4558 { 4559 int i; 4560 4561 for (i = 0; i < len; i++) 4562 indirection_rqt[i] = i % num_channels; 4563 } 4564 4565 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout) 4566 { 4567 int i; 4568 4569 /* The supported periods are organized in ascending order */ 4570 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++) 4571 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout) 4572 break; 4573 4574 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]); 4575 } 4576 4577 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params, 4578 u16 num_channels) 4579 { 4580 enum mlx5e_traffic_types tt; 4581 4582 rss_params->hfunc = ETH_RSS_HASH_TOP; 4583 netdev_rss_key_fill(rss_params->toeplitz_hash_key, 4584 sizeof(rss_params->toeplitz_hash_key)); 4585 mlx5e_build_default_indir_rqt(rss_params->indirection_rqt, 4586 MLX5E_INDIR_RQT_SIZE, num_channels); 4587 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) 4588 rss_params->rx_hash_fields[tt] = 4589 tirc_default_config[tt].rx_hash_fields; 4590 } 4591 4592 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu) 4593 { 4594 struct mlx5e_rss_params *rss_params = &priv->rss_params; 4595 struct mlx5e_params *params = &priv->channels.params; 4596 struct mlx5_core_dev *mdev = priv->mdev; 4597 u8 rx_cq_period_mode; 4598 4599 priv->max_nch = mlx5e_calc_max_nch(priv, priv->profile); 4600 4601 params->sw_mtu = mtu; 4602 params->hard_mtu = MLX5E_ETH_HARD_MTU; 4603 params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2, 4604 priv->max_nch); 4605 params->num_tc = 1; 4606 4607 /* Set an initial non-zero value, so that mlx5e_select_queue won't 4608 * divide by zero if called before first activating channels. 4609 */ 4610 priv->num_tc_x_num_ch = params->num_channels * params->num_tc; 4611 4612 /* SQ */ 4613 params->log_sq_size = is_kdump_kernel() ? 4614 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE : 4615 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; 4616 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE, 4617 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)); 4618 4619 /* XDP SQ */ 4620 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE, 4621 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)); 4622 4623 /* set CQE compression */ 4624 params->rx_cqe_compress_def = false; 4625 if (MLX5_CAP_GEN(mdev, cqe_compression) && 4626 MLX5_CAP_GEN(mdev, vport_group_manager)) 4627 params->rx_cqe_compress_def = slow_pci_heuristic(mdev); 4628 4629 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def); 4630 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false); 4631 4632 /* RQ */ 4633 mlx5e_build_rq_params(mdev, params); 4634 4635 /* HW LRO */ 4636 if (MLX5_CAP_ETH(mdev, lro_cap) && 4637 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) { 4638 /* No XSK params: checking the availability of striding RQ in general. */ 4639 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL)) 4640 params->lro_en = !slow_pci_heuristic(mdev); 4641 } 4642 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT); 4643 4644 /* CQ moderation params */ 4645 rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 4646 MLX5_CQ_PERIOD_MODE_START_FROM_CQE : 4647 MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 4648 params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation); 4649 params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation); 4650 mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode); 4651 mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 4652 4653 /* TX inline */ 4654 mlx5_query_min_inline(mdev, ¶ms->tx_min_inline_mode); 4655 4656 /* RSS */ 4657 mlx5e_build_rss_params(rss_params, params->num_channels); 4658 params->tunneled_offload_en = 4659 mlx5e_tunnel_inner_ft_supported(mdev); 4660 4661 /* AF_XDP */ 4662 params->xsk = xsk; 4663 4664 /* Do not update netdev->features directly in here 4665 * on mlx5e_attach_netdev() we will call mlx5e_update_features() 4666 * To update netdev->features please modify mlx5e_fix_features() 4667 */ 4668 } 4669 4670 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev) 4671 { 4672 struct mlx5e_priv *priv = netdev_priv(netdev); 4673 4674 mlx5_query_mac_address(priv->mdev, netdev->dev_addr); 4675 if (is_zero_ether_addr(netdev->dev_addr) && 4676 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) { 4677 eth_hw_addr_random(netdev); 4678 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr); 4679 } 4680 } 4681 4682 static int mlx5e_vxlan_set_port(struct net_device *netdev, unsigned int table, 4683 unsigned int entry, struct udp_tunnel_info *ti) 4684 { 4685 struct mlx5e_priv *priv = netdev_priv(netdev); 4686 4687 return mlx5_vxlan_add_port(priv->mdev->vxlan, ntohs(ti->port)); 4688 } 4689 4690 static int mlx5e_vxlan_unset_port(struct net_device *netdev, unsigned int table, 4691 unsigned int entry, struct udp_tunnel_info *ti) 4692 { 4693 struct mlx5e_priv *priv = netdev_priv(netdev); 4694 4695 return mlx5_vxlan_del_port(priv->mdev->vxlan, ntohs(ti->port)); 4696 } 4697 4698 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv) 4699 { 4700 if (!mlx5_vxlan_allowed(priv->mdev->vxlan)) 4701 return; 4702 4703 priv->nic_info.set_port = mlx5e_vxlan_set_port; 4704 priv->nic_info.unset_port = mlx5e_vxlan_unset_port; 4705 priv->nic_info.flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP | 4706 UDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN; 4707 priv->nic_info.tables[0].tunnel_types = UDP_TUNNEL_TYPE_VXLAN; 4708 /* Don't count the space hard-coded to the IANA port */ 4709 priv->nic_info.tables[0].n_entries = 4710 mlx5_vxlan_max_udp_ports(priv->mdev) - 1; 4711 4712 priv->netdev->udp_tunnel_nic_info = &priv->nic_info; 4713 } 4714 4715 static bool mlx5e_tunnel_any_tx_proto_supported(struct mlx5_core_dev *mdev) 4716 { 4717 int tt; 4718 4719 for (tt = 0; tt < MLX5E_NUM_TUNNEL_TT; tt++) { 4720 if (mlx5e_tunnel_proto_supported_tx(mdev, mlx5e_get_proto_by_tunnel_type(tt))) 4721 return true; 4722 } 4723 return (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)); 4724 } 4725 4726 static void mlx5e_build_nic_netdev(struct net_device *netdev) 4727 { 4728 struct mlx5e_priv *priv = netdev_priv(netdev); 4729 struct mlx5_core_dev *mdev = priv->mdev; 4730 bool fcs_supported; 4731 bool fcs_enabled; 4732 4733 SET_NETDEV_DEV(netdev, mdev->device); 4734 4735 netdev->netdev_ops = &mlx5e_netdev_ops; 4736 4737 mlx5e_dcbnl_build_netdev(netdev); 4738 4739 netdev->watchdog_timeo = 15 * HZ; 4740 4741 netdev->ethtool_ops = &mlx5e_ethtool_ops; 4742 4743 netdev->vlan_features |= NETIF_F_SG; 4744 netdev->vlan_features |= NETIF_F_HW_CSUM; 4745 netdev->vlan_features |= NETIF_F_GRO; 4746 netdev->vlan_features |= NETIF_F_TSO; 4747 netdev->vlan_features |= NETIF_F_TSO6; 4748 netdev->vlan_features |= NETIF_F_RXCSUM; 4749 netdev->vlan_features |= NETIF_F_RXHASH; 4750 4751 netdev->mpls_features |= NETIF_F_SG; 4752 netdev->mpls_features |= NETIF_F_HW_CSUM; 4753 netdev->mpls_features |= NETIF_F_TSO; 4754 netdev->mpls_features |= NETIF_F_TSO6; 4755 4756 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_TX; 4757 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_RX; 4758 4759 if (!!MLX5_CAP_ETH(mdev, lro_cap) && 4760 mlx5e_check_fragmented_striding_rq_cap(mdev)) 4761 netdev->vlan_features |= NETIF_F_LRO; 4762 4763 netdev->hw_features = netdev->vlan_features; 4764 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; 4765 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; 4766 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 4767 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX; 4768 4769 if (mlx5e_tunnel_any_tx_proto_supported(mdev)) { 4770 netdev->hw_enc_features |= NETIF_F_HW_CSUM; 4771 netdev->hw_enc_features |= NETIF_F_TSO; 4772 netdev->hw_enc_features |= NETIF_F_TSO6; 4773 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL; 4774 } 4775 4776 if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) { 4777 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL | 4778 NETIF_F_GSO_UDP_TUNNEL_CSUM; 4779 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL | 4780 NETIF_F_GSO_UDP_TUNNEL_CSUM; 4781 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM; 4782 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL | 4783 NETIF_F_GSO_UDP_TUNNEL_CSUM; 4784 } 4785 4786 if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_GRE)) { 4787 netdev->hw_features |= NETIF_F_GSO_GRE | 4788 NETIF_F_GSO_GRE_CSUM; 4789 netdev->hw_enc_features |= NETIF_F_GSO_GRE | 4790 NETIF_F_GSO_GRE_CSUM; 4791 netdev->gso_partial_features |= NETIF_F_GSO_GRE | 4792 NETIF_F_GSO_GRE_CSUM; 4793 } 4794 4795 if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_IPIP)) { 4796 netdev->hw_features |= NETIF_F_GSO_IPXIP4 | 4797 NETIF_F_GSO_IPXIP6; 4798 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 | 4799 NETIF_F_GSO_IPXIP6; 4800 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 | 4801 NETIF_F_GSO_IPXIP6; 4802 } 4803 4804 netdev->hw_features |= NETIF_F_GSO_PARTIAL; 4805 netdev->gso_partial_features |= NETIF_F_GSO_UDP_L4; 4806 netdev->hw_features |= NETIF_F_GSO_UDP_L4; 4807 netdev->features |= NETIF_F_GSO_UDP_L4; 4808 4809 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled); 4810 4811 if (fcs_supported) 4812 netdev->hw_features |= NETIF_F_RXALL; 4813 4814 if (MLX5_CAP_ETH(mdev, scatter_fcs)) 4815 netdev->hw_features |= NETIF_F_RXFCS; 4816 4817 netdev->features = netdev->hw_features; 4818 4819 /* Defaults */ 4820 if (fcs_enabled) 4821 netdev->features &= ~NETIF_F_RXALL; 4822 netdev->features &= ~NETIF_F_LRO; 4823 netdev->features &= ~NETIF_F_RXFCS; 4824 4825 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f) 4826 if (FT_CAP(flow_modify_en) && 4827 FT_CAP(modify_root) && 4828 FT_CAP(identified_miss_table_mode) && 4829 FT_CAP(flow_table_modify)) { 4830 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT) 4831 netdev->hw_features |= NETIF_F_HW_TC; 4832 #endif 4833 #ifdef CONFIG_MLX5_EN_ARFS 4834 netdev->hw_features |= NETIF_F_NTUPLE; 4835 #endif 4836 } 4837 if (mlx5_qos_is_supported(mdev)) 4838 netdev->features |= NETIF_F_HW_TC; 4839 4840 netdev->features |= NETIF_F_HIGHDMA; 4841 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER; 4842 4843 netdev->priv_flags |= IFF_UNICAST_FLT; 4844 4845 mlx5e_set_netdev_dev_addr(netdev); 4846 mlx5e_ipsec_build_netdev(priv); 4847 mlx5e_tls_build_netdev(priv); 4848 } 4849 4850 void mlx5e_create_q_counters(struct mlx5e_priv *priv) 4851 { 4852 u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {}; 4853 u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {}; 4854 struct mlx5_core_dev *mdev = priv->mdev; 4855 int err; 4856 4857 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 4858 err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out); 4859 if (!err) 4860 priv->q_counter = 4861 MLX5_GET(alloc_q_counter_out, out, counter_set_id); 4862 4863 err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out); 4864 if (!err) 4865 priv->drop_rq_q_counter = 4866 MLX5_GET(alloc_q_counter_out, out, counter_set_id); 4867 } 4868 4869 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv) 4870 { 4871 u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {}; 4872 4873 MLX5_SET(dealloc_q_counter_in, in, opcode, 4874 MLX5_CMD_OP_DEALLOC_Q_COUNTER); 4875 if (priv->q_counter) { 4876 MLX5_SET(dealloc_q_counter_in, in, counter_set_id, 4877 priv->q_counter); 4878 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in); 4879 } 4880 4881 if (priv->drop_rq_q_counter) { 4882 MLX5_SET(dealloc_q_counter_in, in, counter_set_id, 4883 priv->drop_rq_q_counter); 4884 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in); 4885 } 4886 } 4887 4888 static int mlx5e_nic_init(struct mlx5_core_dev *mdev, 4889 struct net_device *netdev) 4890 { 4891 struct mlx5e_priv *priv = netdev_priv(netdev); 4892 struct devlink_port *dl_port; 4893 int err; 4894 4895 mlx5e_build_nic_params(priv, &priv->xsk, netdev->mtu); 4896 mlx5e_vxlan_set_netdev_info(priv); 4897 4898 mlx5e_timestamp_init(priv); 4899 4900 err = mlx5e_ipsec_init(priv); 4901 if (err) 4902 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err); 4903 4904 err = mlx5e_tls_init(priv); 4905 if (err) 4906 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err); 4907 4908 dl_port = mlx5e_devlink_get_dl_port(priv); 4909 if (dl_port->registered) 4910 mlx5e_health_create_reporters(priv); 4911 4912 return 0; 4913 } 4914 4915 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv) 4916 { 4917 struct devlink_port *dl_port = mlx5e_devlink_get_dl_port(priv); 4918 4919 if (dl_port->registered) 4920 mlx5e_health_destroy_reporters(priv); 4921 mlx5e_tls_cleanup(priv); 4922 mlx5e_ipsec_cleanup(priv); 4923 } 4924 4925 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv) 4926 { 4927 struct mlx5_core_dev *mdev = priv->mdev; 4928 u16 max_nch = priv->max_nch; 4929 int err; 4930 4931 mlx5e_create_q_counters(priv); 4932 4933 err = mlx5e_open_drop_rq(priv, &priv->drop_rq); 4934 if (err) { 4935 mlx5_core_err(mdev, "open drop rq failed, %d\n", err); 4936 goto err_destroy_q_counters; 4937 } 4938 4939 err = mlx5e_create_indirect_rqt(priv); 4940 if (err) 4941 goto err_close_drop_rq; 4942 4943 err = mlx5e_create_direct_rqts(priv, priv->direct_tir, max_nch); 4944 if (err) 4945 goto err_destroy_indirect_rqts; 4946 4947 err = mlx5e_create_indirect_tirs(priv, true); 4948 if (err) 4949 goto err_destroy_direct_rqts; 4950 4951 err = mlx5e_create_direct_tirs(priv, priv->direct_tir, max_nch); 4952 if (err) 4953 goto err_destroy_indirect_tirs; 4954 4955 err = mlx5e_create_direct_rqts(priv, priv->xsk_tir, max_nch); 4956 if (unlikely(err)) 4957 goto err_destroy_direct_tirs; 4958 4959 err = mlx5e_create_direct_tirs(priv, priv->xsk_tir, max_nch); 4960 if (unlikely(err)) 4961 goto err_destroy_xsk_rqts; 4962 4963 err = mlx5e_create_direct_rqts(priv, &priv->ptp_tir, 1); 4964 if (err) 4965 goto err_destroy_xsk_tirs; 4966 4967 err = mlx5e_create_direct_tirs(priv, &priv->ptp_tir, 1); 4968 if (err) 4969 goto err_destroy_ptp_rqt; 4970 4971 err = mlx5e_create_flow_steering(priv); 4972 if (err) { 4973 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err); 4974 goto err_destroy_ptp_direct_tir; 4975 } 4976 4977 err = mlx5e_tc_nic_init(priv); 4978 if (err) 4979 goto err_destroy_flow_steering; 4980 4981 err = mlx5e_accel_init_rx(priv); 4982 if (err) 4983 goto err_tc_nic_cleanup; 4984 4985 #ifdef CONFIG_MLX5_EN_ARFS 4986 priv->netdev->rx_cpu_rmap = mlx5_eq_table_get_rmap(priv->mdev); 4987 #endif 4988 4989 return 0; 4990 4991 err_tc_nic_cleanup: 4992 mlx5e_tc_nic_cleanup(priv); 4993 err_destroy_flow_steering: 4994 mlx5e_destroy_flow_steering(priv); 4995 err_destroy_ptp_direct_tir: 4996 mlx5e_destroy_direct_tirs(priv, &priv->ptp_tir, 1); 4997 err_destroy_ptp_rqt: 4998 mlx5e_destroy_direct_rqts(priv, &priv->ptp_tir, 1); 4999 err_destroy_xsk_tirs: 5000 mlx5e_destroy_direct_tirs(priv, priv->xsk_tir, max_nch); 5001 err_destroy_xsk_rqts: 5002 mlx5e_destroy_direct_rqts(priv, priv->xsk_tir, max_nch); 5003 err_destroy_direct_tirs: 5004 mlx5e_destroy_direct_tirs(priv, priv->direct_tir, max_nch); 5005 err_destroy_indirect_tirs: 5006 mlx5e_destroy_indirect_tirs(priv); 5007 err_destroy_direct_rqts: 5008 mlx5e_destroy_direct_rqts(priv, priv->direct_tir, max_nch); 5009 err_destroy_indirect_rqts: 5010 mlx5e_destroy_rqt(priv, &priv->indir_rqt); 5011 err_close_drop_rq: 5012 mlx5e_close_drop_rq(&priv->drop_rq); 5013 err_destroy_q_counters: 5014 mlx5e_destroy_q_counters(priv); 5015 return err; 5016 } 5017 5018 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv) 5019 { 5020 u16 max_nch = priv->max_nch; 5021 5022 mlx5e_accel_cleanup_rx(priv); 5023 mlx5e_tc_nic_cleanup(priv); 5024 mlx5e_destroy_flow_steering(priv); 5025 mlx5e_destroy_direct_tirs(priv, &priv->ptp_tir, 1); 5026 mlx5e_destroy_direct_rqts(priv, &priv->ptp_tir, 1); 5027 mlx5e_destroy_direct_tirs(priv, priv->xsk_tir, max_nch); 5028 mlx5e_destroy_direct_rqts(priv, priv->xsk_tir, max_nch); 5029 mlx5e_destroy_direct_tirs(priv, priv->direct_tir, max_nch); 5030 mlx5e_destroy_indirect_tirs(priv); 5031 mlx5e_destroy_direct_rqts(priv, priv->direct_tir, max_nch); 5032 mlx5e_destroy_rqt(priv, &priv->indir_rqt); 5033 mlx5e_close_drop_rq(&priv->drop_rq); 5034 mlx5e_destroy_q_counters(priv); 5035 } 5036 5037 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv) 5038 { 5039 int err; 5040 5041 err = mlx5e_create_tises(priv); 5042 if (err) { 5043 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err); 5044 return err; 5045 } 5046 5047 mlx5e_dcbnl_initialize(priv); 5048 return 0; 5049 } 5050 5051 static void mlx5e_nic_enable(struct mlx5e_priv *priv) 5052 { 5053 struct net_device *netdev = priv->netdev; 5054 struct mlx5_core_dev *mdev = priv->mdev; 5055 5056 mlx5e_init_l2_addr(priv); 5057 5058 /* Marking the link as currently not needed by the Driver */ 5059 if (!netif_running(netdev)) 5060 mlx5e_modify_admin_state(mdev, MLX5_PORT_DOWN); 5061 5062 mlx5e_set_netdev_mtu_boundaries(priv); 5063 mlx5e_set_dev_port_mtu(priv); 5064 5065 mlx5_lag_add(mdev, netdev); 5066 5067 mlx5e_enable_async_events(priv); 5068 mlx5e_enable_blocking_events(priv); 5069 if (mlx5e_monitor_counter_supported(priv)) 5070 mlx5e_monitor_counter_init(priv); 5071 5072 mlx5e_hv_vhca_stats_create(priv); 5073 if (netdev->reg_state != NETREG_REGISTERED) 5074 return; 5075 mlx5e_dcbnl_init_app(priv); 5076 5077 mlx5e_nic_set_rx_mode(priv); 5078 5079 rtnl_lock(); 5080 if (netif_running(netdev)) 5081 mlx5e_open(netdev); 5082 udp_tunnel_nic_reset_ntf(priv->netdev); 5083 netif_device_attach(netdev); 5084 rtnl_unlock(); 5085 } 5086 5087 static void mlx5e_nic_disable(struct mlx5e_priv *priv) 5088 { 5089 struct mlx5_core_dev *mdev = priv->mdev; 5090 5091 if (priv->netdev->reg_state == NETREG_REGISTERED) 5092 mlx5e_dcbnl_delete_app(priv); 5093 5094 rtnl_lock(); 5095 if (netif_running(priv->netdev)) 5096 mlx5e_close(priv->netdev); 5097 netif_device_detach(priv->netdev); 5098 rtnl_unlock(); 5099 5100 mlx5e_nic_set_rx_mode(priv); 5101 5102 mlx5e_hv_vhca_stats_destroy(priv); 5103 if (mlx5e_monitor_counter_supported(priv)) 5104 mlx5e_monitor_counter_cleanup(priv); 5105 5106 mlx5e_disable_blocking_events(priv); 5107 if (priv->en_trap) { 5108 mlx5e_deactivate_trap(priv); 5109 mlx5e_close_trap(priv->en_trap); 5110 priv->en_trap = NULL; 5111 } 5112 mlx5e_disable_async_events(priv); 5113 mlx5_lag_remove(mdev); 5114 mlx5_vxlan_reset_to_default(mdev->vxlan); 5115 } 5116 5117 int mlx5e_update_nic_rx(struct mlx5e_priv *priv) 5118 { 5119 return mlx5e_refresh_tirs(priv, false, false); 5120 } 5121 5122 static const struct mlx5e_profile mlx5e_nic_profile = { 5123 .init = mlx5e_nic_init, 5124 .cleanup = mlx5e_nic_cleanup, 5125 .init_rx = mlx5e_init_nic_rx, 5126 .cleanup_rx = mlx5e_cleanup_nic_rx, 5127 .init_tx = mlx5e_init_nic_tx, 5128 .cleanup_tx = mlx5e_cleanup_nic_tx, 5129 .enable = mlx5e_nic_enable, 5130 .disable = mlx5e_nic_disable, 5131 .update_rx = mlx5e_update_nic_rx, 5132 .update_stats = mlx5e_stats_update_ndo_stats, 5133 .update_carrier = mlx5e_update_carrier, 5134 .rx_handlers = &mlx5e_rx_handlers_nic, 5135 .max_tc = MLX5E_MAX_NUM_TC, 5136 .rq_groups = MLX5E_NUM_RQ_GROUPS(XSK), 5137 .stats_grps = mlx5e_nic_stats_grps, 5138 .stats_grps_num = mlx5e_nic_stats_grps_num, 5139 .rx_ptp_support = true, 5140 }; 5141 5142 /* mlx5e generic netdev management API (move to en_common.c) */ 5143 int mlx5e_priv_init(struct mlx5e_priv *priv, 5144 struct net_device *netdev, 5145 struct mlx5_core_dev *mdev) 5146 { 5147 /* priv init */ 5148 priv->mdev = mdev; 5149 priv->netdev = netdev; 5150 priv->msglevel = MLX5E_MSG_LEVEL; 5151 priv->max_opened_tc = 1; 5152 5153 if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL)) 5154 return -ENOMEM; 5155 5156 mutex_init(&priv->state_lock); 5157 hash_init(priv->htb.qos_tc2node); 5158 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work); 5159 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work); 5160 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work); 5161 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work); 5162 5163 priv->wq = create_singlethread_workqueue("mlx5e"); 5164 if (!priv->wq) 5165 goto err_free_cpumask; 5166 5167 return 0; 5168 5169 err_free_cpumask: 5170 free_cpumask_var(priv->scratchpad.cpumask); 5171 5172 return -ENOMEM; 5173 } 5174 5175 void mlx5e_priv_cleanup(struct mlx5e_priv *priv) 5176 { 5177 int i; 5178 5179 /* bail if change profile failed and also rollback failed */ 5180 if (!priv->mdev) 5181 return; 5182 5183 destroy_workqueue(priv->wq); 5184 free_cpumask_var(priv->scratchpad.cpumask); 5185 5186 for (i = 0; i < priv->htb.max_qos_sqs; i++) 5187 kfree(priv->htb.qos_sq_stats[i]); 5188 kvfree(priv->htb.qos_sq_stats); 5189 5190 memset(priv, 0, sizeof(*priv)); 5191 } 5192 5193 struct net_device * 5194 mlx5e_create_netdev(struct mlx5_core_dev *mdev, unsigned int txqs, unsigned int rxqs) 5195 { 5196 struct net_device *netdev; 5197 int err; 5198 5199 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), txqs, rxqs); 5200 if (!netdev) { 5201 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n"); 5202 return NULL; 5203 } 5204 5205 err = mlx5e_priv_init(netdev_priv(netdev), netdev, mdev); 5206 if (err) { 5207 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err); 5208 goto err_free_netdev; 5209 } 5210 5211 netif_carrier_off(netdev); 5212 dev_net_set(netdev, mlx5_core_net(mdev)); 5213 5214 return netdev; 5215 5216 err_free_netdev: 5217 free_netdev(netdev); 5218 5219 return NULL; 5220 } 5221 5222 static void mlx5e_update_features(struct net_device *netdev) 5223 { 5224 if (netdev->reg_state != NETREG_REGISTERED) 5225 return; /* features will be updated on netdev registration */ 5226 5227 rtnl_lock(); 5228 netdev_update_features(netdev); 5229 rtnl_unlock(); 5230 } 5231 5232 int mlx5e_attach_netdev(struct mlx5e_priv *priv) 5233 { 5234 const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED; 5235 const struct mlx5e_profile *profile = priv->profile; 5236 int max_nch; 5237 int err; 5238 5239 clear_bit(MLX5E_STATE_DESTROYING, &priv->state); 5240 5241 /* max number of channels may have changed */ 5242 max_nch = mlx5e_get_max_num_channels(priv->mdev); 5243 if (priv->channels.params.num_channels > max_nch) { 5244 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch); 5245 /* Reducing the number of channels - RXFH has to be reset, and 5246 * mlx5e_num_channels_changed below will build the RQT. 5247 */ 5248 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED; 5249 priv->channels.params.num_channels = max_nch; 5250 } 5251 /* 1. Set the real number of queues in the kernel the first time. 5252 * 2. Set our default XPS cpumask. 5253 * 3. Build the RQT. 5254 * 5255 * rtnl_lock is required by netif_set_real_num_*_queues in case the 5256 * netdev has been registered by this point (if this function was called 5257 * in the reload or resume flow). 5258 */ 5259 if (take_rtnl) 5260 rtnl_lock(); 5261 err = mlx5e_num_channels_changed(priv); 5262 if (take_rtnl) 5263 rtnl_unlock(); 5264 if (err) 5265 goto out; 5266 5267 err = profile->init_tx(priv); 5268 if (err) 5269 goto out; 5270 5271 err = profile->init_rx(priv); 5272 if (err) 5273 goto err_cleanup_tx; 5274 5275 if (profile->enable) 5276 profile->enable(priv); 5277 5278 mlx5e_update_features(priv->netdev); 5279 5280 return 0; 5281 5282 err_cleanup_tx: 5283 profile->cleanup_tx(priv); 5284 5285 out: 5286 set_bit(MLX5E_STATE_DESTROYING, &priv->state); 5287 cancel_work_sync(&priv->update_stats_work); 5288 return err; 5289 } 5290 5291 void mlx5e_detach_netdev(struct mlx5e_priv *priv) 5292 { 5293 const struct mlx5e_profile *profile = priv->profile; 5294 5295 set_bit(MLX5E_STATE_DESTROYING, &priv->state); 5296 5297 if (profile->disable) 5298 profile->disable(priv); 5299 flush_workqueue(priv->wq); 5300 5301 profile->cleanup_rx(priv); 5302 profile->cleanup_tx(priv); 5303 cancel_work_sync(&priv->update_stats_work); 5304 } 5305 5306 static int 5307 mlx5e_netdev_attach_profile(struct net_device *netdev, struct mlx5_core_dev *mdev, 5308 const struct mlx5e_profile *new_profile, void *new_ppriv) 5309 { 5310 struct mlx5e_priv *priv = netdev_priv(netdev); 5311 int err; 5312 5313 err = mlx5e_priv_init(priv, netdev, mdev); 5314 if (err) { 5315 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err); 5316 return err; 5317 } 5318 netif_carrier_off(netdev); 5319 priv->profile = new_profile; 5320 priv->ppriv = new_ppriv; 5321 err = new_profile->init(priv->mdev, priv->netdev); 5322 if (err) 5323 goto priv_cleanup; 5324 err = mlx5e_attach_netdev(priv); 5325 if (err) 5326 goto profile_cleanup; 5327 return err; 5328 5329 profile_cleanup: 5330 new_profile->cleanup(priv); 5331 priv_cleanup: 5332 mlx5e_priv_cleanup(priv); 5333 return err; 5334 } 5335 5336 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv, 5337 const struct mlx5e_profile *new_profile, void *new_ppriv) 5338 { 5339 unsigned int new_max_nch = mlx5e_calc_max_nch(priv, new_profile); 5340 const struct mlx5e_profile *orig_profile = priv->profile; 5341 struct net_device *netdev = priv->netdev; 5342 struct mlx5_core_dev *mdev = priv->mdev; 5343 void *orig_ppriv = priv->ppriv; 5344 int err, rollback_err; 5345 5346 /* sanity */ 5347 if (new_max_nch != priv->max_nch) { 5348 netdev_warn(netdev, "%s: Replacing profile with different max channels\n", 5349 __func__); 5350 return -EINVAL; 5351 } 5352 5353 /* cleanup old profile */ 5354 mlx5e_detach_netdev(priv); 5355 priv->profile->cleanup(priv); 5356 mlx5e_priv_cleanup(priv); 5357 5358 err = mlx5e_netdev_attach_profile(netdev, mdev, new_profile, new_ppriv); 5359 if (err) { /* roll back to original profile */ 5360 netdev_warn(netdev, "%s: new profile init failed, %d\n", __func__, err); 5361 goto rollback; 5362 } 5363 5364 return 0; 5365 5366 rollback: 5367 rollback_err = mlx5e_netdev_attach_profile(netdev, mdev, orig_profile, orig_ppriv); 5368 if (rollback_err) 5369 netdev_err(netdev, "%s: failed to rollback to orig profile, %d\n", 5370 __func__, rollback_err); 5371 return err; 5372 } 5373 5374 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv) 5375 { 5376 mlx5e_netdev_change_profile(priv, &mlx5e_nic_profile, NULL); 5377 } 5378 5379 void mlx5e_destroy_netdev(struct mlx5e_priv *priv) 5380 { 5381 struct net_device *netdev = priv->netdev; 5382 5383 mlx5e_priv_cleanup(priv); 5384 free_netdev(netdev); 5385 } 5386 5387 static int mlx5e_resume(struct auxiliary_device *adev) 5388 { 5389 struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev); 5390 struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev); 5391 struct net_device *netdev = priv->netdev; 5392 struct mlx5_core_dev *mdev = edev->mdev; 5393 int err; 5394 5395 if (netif_device_present(netdev)) 5396 return 0; 5397 5398 err = mlx5e_create_mdev_resources(mdev); 5399 if (err) 5400 return err; 5401 5402 err = mlx5e_attach_netdev(priv); 5403 if (err) { 5404 mlx5e_destroy_mdev_resources(mdev); 5405 return err; 5406 } 5407 5408 return 0; 5409 } 5410 5411 static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state) 5412 { 5413 struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev); 5414 struct net_device *netdev = priv->netdev; 5415 struct mlx5_core_dev *mdev = priv->mdev; 5416 5417 if (!netif_device_present(netdev)) 5418 return -ENODEV; 5419 5420 mlx5e_detach_netdev(priv); 5421 mlx5e_destroy_mdev_resources(mdev); 5422 return 0; 5423 } 5424 5425 static int mlx5e_probe(struct auxiliary_device *adev, 5426 const struct auxiliary_device_id *id) 5427 { 5428 struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev); 5429 const struct mlx5e_profile *profile = &mlx5e_nic_profile; 5430 struct mlx5_core_dev *mdev = edev->mdev; 5431 struct net_device *netdev; 5432 pm_message_t state = {}; 5433 unsigned int txqs, rxqs, ptp_txqs = 0; 5434 struct mlx5e_priv *priv; 5435 int qos_sqs = 0; 5436 int err; 5437 int nch; 5438 5439 if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn)) 5440 ptp_txqs = profile->max_tc; 5441 5442 if (mlx5_qos_is_supported(mdev)) 5443 qos_sqs = mlx5e_qos_max_leaf_nodes(mdev); 5444 5445 nch = mlx5e_get_max_num_channels(mdev); 5446 txqs = nch * profile->max_tc + ptp_txqs + qos_sqs; 5447 rxqs = nch * profile->rq_groups; 5448 netdev = mlx5e_create_netdev(mdev, txqs, rxqs); 5449 if (!netdev) { 5450 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n"); 5451 return -ENOMEM; 5452 } 5453 5454 mlx5e_build_nic_netdev(netdev); 5455 5456 priv = netdev_priv(netdev); 5457 dev_set_drvdata(&adev->dev, priv); 5458 5459 priv->profile = profile; 5460 priv->ppriv = NULL; 5461 5462 err = mlx5e_devlink_port_register(priv); 5463 if (err) { 5464 mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err); 5465 goto err_destroy_netdev; 5466 } 5467 5468 err = profile->init(mdev, netdev); 5469 if (err) { 5470 mlx5_core_err(mdev, "mlx5e_nic_profile init failed, %d\n", err); 5471 goto err_devlink_cleanup; 5472 } 5473 5474 err = mlx5e_resume(adev); 5475 if (err) { 5476 mlx5_core_err(mdev, "mlx5e_resume failed, %d\n", err); 5477 goto err_profile_cleanup; 5478 } 5479 5480 err = register_netdev(netdev); 5481 if (err) { 5482 mlx5_core_err(mdev, "register_netdev failed, %d\n", err); 5483 goto err_resume; 5484 } 5485 5486 mlx5e_devlink_port_type_eth_set(priv); 5487 5488 mlx5e_dcbnl_init_app(priv); 5489 mlx5_uplink_netdev_set(mdev, netdev); 5490 return 0; 5491 5492 err_resume: 5493 mlx5e_suspend(adev, state); 5494 err_profile_cleanup: 5495 profile->cleanup(priv); 5496 err_devlink_cleanup: 5497 mlx5e_devlink_port_unregister(priv); 5498 err_destroy_netdev: 5499 mlx5e_destroy_netdev(priv); 5500 return err; 5501 } 5502 5503 static void mlx5e_remove(struct auxiliary_device *adev) 5504 { 5505 struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev); 5506 pm_message_t state = {}; 5507 5508 mlx5e_dcbnl_delete_app(priv); 5509 unregister_netdev(priv->netdev); 5510 mlx5e_suspend(adev, state); 5511 priv->profile->cleanup(priv); 5512 mlx5e_devlink_port_unregister(priv); 5513 mlx5e_destroy_netdev(priv); 5514 } 5515 5516 static const struct auxiliary_device_id mlx5e_id_table[] = { 5517 { .name = MLX5_ADEV_NAME ".eth", }, 5518 {}, 5519 }; 5520 5521 MODULE_DEVICE_TABLE(auxiliary, mlx5e_id_table); 5522 5523 static struct auxiliary_driver mlx5e_driver = { 5524 .name = "eth", 5525 .probe = mlx5e_probe, 5526 .remove = mlx5e_remove, 5527 .suspend = mlx5e_suspend, 5528 .resume = mlx5e_resume, 5529 .id_table = mlx5e_id_table, 5530 }; 5531 5532 int mlx5e_init(void) 5533 { 5534 int ret; 5535 5536 mlx5e_ipsec_build_inverse_table(); 5537 mlx5e_build_ptys2ethtool_map(); 5538 ret = auxiliary_driver_register(&mlx5e_driver); 5539 if (ret) 5540 return ret; 5541 5542 ret = mlx5e_rep_init(); 5543 if (ret) 5544 auxiliary_driver_unregister(&mlx5e_driver); 5545 return ret; 5546 } 5547 5548 void mlx5e_cleanup(void) 5549 { 5550 mlx5e_rep_cleanup(); 5551 auxiliary_driver_unregister(&mlx5e_driver); 5552 } 5553