1 /* 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <net/tc_act/tc_gact.h> 34 #include <linux/mlx5/fs.h> 35 #include <net/vxlan.h> 36 #include <net/geneve.h> 37 #include <linux/bpf.h> 38 #include <linux/if_bridge.h> 39 #include <linux/filter.h> 40 #include <net/page_pool.h> 41 #include <net/xdp_sock_drv.h> 42 #include "eswitch.h" 43 #include "en.h" 44 #include "en/txrx.h" 45 #include "en_tc.h" 46 #include "en_rep.h" 47 #include "en_accel/ipsec.h" 48 #include "en_accel/macsec.h" 49 #include "en_accel/en_accel.h" 50 #include "en_accel/ktls.h" 51 #include "lib/vxlan.h" 52 #include "lib/clock.h" 53 #include "en/port.h" 54 #include "en/xdp.h" 55 #include "lib/eq.h" 56 #include "en/monitor_stats.h" 57 #include "en/health.h" 58 #include "en/params.h" 59 #include "en/xsk/pool.h" 60 #include "en/xsk/setup.h" 61 #include "en/xsk/rx.h" 62 #include "en/xsk/tx.h" 63 #include "en/hv_vhca_stats.h" 64 #include "en/devlink.h" 65 #include "lib/mlx5.h" 66 #include "en/ptp.h" 67 #include "en/htb.h" 68 #include "qos.h" 69 #include "en/trap.h" 70 71 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev, u8 page_shift, 72 enum mlx5e_mpwrq_umr_mode umr_mode) 73 { 74 u16 umr_wqebbs, max_wqebbs; 75 bool striding_rq_umr; 76 77 striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) && MLX5_CAP_GEN(mdev, umr_ptr_rlky) && 78 MLX5_CAP_ETH(mdev, reg_umr_sq); 79 if (!striding_rq_umr) 80 return false; 81 82 umr_wqebbs = mlx5e_mpwrq_umr_wqebbs(mdev, page_shift, umr_mode); 83 max_wqebbs = mlx5e_get_max_sq_aligned_wqebbs(mdev); 84 /* Sanity check; should never happen, because mlx5e_mpwrq_umr_wqebbs is 85 * calculated from mlx5e_get_max_sq_aligned_wqebbs. 86 */ 87 if (WARN_ON(umr_wqebbs > max_wqebbs)) 88 return false; 89 90 return true; 91 } 92 93 void mlx5e_update_carrier(struct mlx5e_priv *priv) 94 { 95 struct mlx5_core_dev *mdev = priv->mdev; 96 u8 port_state; 97 bool up; 98 99 port_state = mlx5_query_vport_state(mdev, 100 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT, 101 0); 102 103 up = port_state == VPORT_STATE_UP; 104 if (up == netif_carrier_ok(priv->netdev)) 105 netif_carrier_event(priv->netdev); 106 if (up) { 107 netdev_info(priv->netdev, "Link up\n"); 108 netif_carrier_on(priv->netdev); 109 } else { 110 netdev_info(priv->netdev, "Link down\n"); 111 netif_carrier_off(priv->netdev); 112 } 113 } 114 115 static void mlx5e_update_carrier_work(struct work_struct *work) 116 { 117 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, 118 update_carrier_work); 119 120 mutex_lock(&priv->state_lock); 121 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) 122 if (priv->profile->update_carrier) 123 priv->profile->update_carrier(priv); 124 mutex_unlock(&priv->state_lock); 125 } 126 127 static void mlx5e_update_stats_work(struct work_struct *work) 128 { 129 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, 130 update_stats_work); 131 132 mutex_lock(&priv->state_lock); 133 priv->profile->update_stats(priv); 134 mutex_unlock(&priv->state_lock); 135 } 136 137 void mlx5e_queue_update_stats(struct mlx5e_priv *priv) 138 { 139 if (!priv->profile->update_stats) 140 return; 141 142 if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state))) 143 return; 144 145 queue_work(priv->wq, &priv->update_stats_work); 146 } 147 148 static int async_event(struct notifier_block *nb, unsigned long event, void *data) 149 { 150 struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb); 151 struct mlx5_eqe *eqe = data; 152 153 if (event != MLX5_EVENT_TYPE_PORT_CHANGE) 154 return NOTIFY_DONE; 155 156 switch (eqe->sub_type) { 157 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 158 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 159 queue_work(priv->wq, &priv->update_carrier_work); 160 break; 161 default: 162 return NOTIFY_DONE; 163 } 164 165 return NOTIFY_OK; 166 } 167 168 static void mlx5e_enable_async_events(struct mlx5e_priv *priv) 169 { 170 priv->events_nb.notifier_call = async_event; 171 mlx5_notifier_register(priv->mdev, &priv->events_nb); 172 } 173 174 static void mlx5e_disable_async_events(struct mlx5e_priv *priv) 175 { 176 mlx5_notifier_unregister(priv->mdev, &priv->events_nb); 177 } 178 179 static int blocking_event(struct notifier_block *nb, unsigned long event, void *data) 180 { 181 struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, blocking_events_nb); 182 int err; 183 184 switch (event) { 185 case MLX5_DRIVER_EVENT_TYPE_TRAP: 186 err = mlx5e_handle_trap_event(priv, data); 187 break; 188 default: 189 netdev_warn(priv->netdev, "Sync event: Unknown event %ld\n", event); 190 err = -EINVAL; 191 } 192 return err; 193 } 194 195 static void mlx5e_enable_blocking_events(struct mlx5e_priv *priv) 196 { 197 priv->blocking_events_nb.notifier_call = blocking_event; 198 mlx5_blocking_notifier_register(priv->mdev, &priv->blocking_events_nb); 199 } 200 201 static void mlx5e_disable_blocking_events(struct mlx5e_priv *priv) 202 { 203 mlx5_blocking_notifier_unregister(priv->mdev, &priv->blocking_events_nb); 204 } 205 206 static u16 mlx5e_mpwrq_umr_octowords(u32 entries, enum mlx5e_mpwrq_umr_mode umr_mode) 207 { 208 u8 umr_entry_size = mlx5e_mpwrq_umr_entry_size(umr_mode); 209 210 WARN_ON_ONCE(entries * umr_entry_size % MLX5_OCTWORD); 211 212 return entries * umr_entry_size / MLX5_OCTWORD; 213 } 214 215 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, 216 struct mlx5e_icosq *sq, 217 struct mlx5e_umr_wqe *wqe) 218 { 219 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; 220 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl; 221 u16 octowords; 222 u8 ds_cnt; 223 224 ds_cnt = DIV_ROUND_UP(mlx5e_mpwrq_umr_wqe_sz(rq->mdev, rq->mpwqe.page_shift, 225 rq->mpwqe.umr_mode), 226 MLX5_SEND_WQE_DS); 227 228 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) | 229 ds_cnt); 230 cseg->umr_mkey = rq->mpwqe.umr_mkey_be; 231 232 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE; 233 octowords = mlx5e_mpwrq_umr_octowords(rq->mpwqe.pages_per_wqe, rq->mpwqe.umr_mode); 234 ucseg->xlt_octowords = cpu_to_be16(octowords); 235 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 236 } 237 238 static int mlx5e_rq_shampo_hd_alloc(struct mlx5e_rq *rq, int node) 239 { 240 rq->mpwqe.shampo = kvzalloc_node(sizeof(*rq->mpwqe.shampo), 241 GFP_KERNEL, node); 242 if (!rq->mpwqe.shampo) 243 return -ENOMEM; 244 return 0; 245 } 246 247 static void mlx5e_rq_shampo_hd_free(struct mlx5e_rq *rq) 248 { 249 kvfree(rq->mpwqe.shampo); 250 } 251 252 static int mlx5e_rq_shampo_hd_info_alloc(struct mlx5e_rq *rq, int node) 253 { 254 struct mlx5e_shampo_hd *shampo = rq->mpwqe.shampo; 255 256 shampo->bitmap = bitmap_zalloc_node(shampo->hd_per_wq, GFP_KERNEL, 257 node); 258 if (!shampo->bitmap) 259 return -ENOMEM; 260 261 shampo->info = kvzalloc_node(array_size(shampo->hd_per_wq, 262 sizeof(*shampo->info)), 263 GFP_KERNEL, node); 264 if (!shampo->info) { 265 kvfree(shampo->bitmap); 266 return -ENOMEM; 267 } 268 return 0; 269 } 270 271 static void mlx5e_rq_shampo_hd_info_free(struct mlx5e_rq *rq) 272 { 273 kvfree(rq->mpwqe.shampo->bitmap); 274 kvfree(rq->mpwqe.shampo->info); 275 } 276 277 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, int node) 278 { 279 int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq); 280 size_t alloc_size; 281 282 alloc_size = array_size(wq_sz, struct_size(rq->mpwqe.info, alloc_units, 283 rq->mpwqe.pages_per_wqe)); 284 285 rq->mpwqe.info = kvzalloc_node(alloc_size, GFP_KERNEL, node); 286 if (!rq->mpwqe.info) 287 return -ENOMEM; 288 289 mlx5e_build_umr_wqe(rq, rq->icosq, &rq->mpwqe.umr_wqe); 290 291 return 0; 292 } 293 294 295 static u8 mlx5e_mpwrq_access_mode(enum mlx5e_mpwrq_umr_mode umr_mode) 296 { 297 switch (umr_mode) { 298 case MLX5E_MPWRQ_UMR_MODE_ALIGNED: 299 return MLX5_MKC_ACCESS_MODE_MTT; 300 case MLX5E_MPWRQ_UMR_MODE_UNALIGNED: 301 return MLX5_MKC_ACCESS_MODE_KSM; 302 case MLX5E_MPWRQ_UMR_MODE_OVERSIZED: 303 return MLX5_MKC_ACCESS_MODE_KLMS; 304 case MLX5E_MPWRQ_UMR_MODE_TRIPLE: 305 return MLX5_MKC_ACCESS_MODE_KSM; 306 } 307 WARN_ONCE(1, "MPWRQ UMR mode %d is not known\n", umr_mode); 308 return 0; 309 } 310 311 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev, 312 u32 npages, u8 page_shift, u32 *umr_mkey, 313 dma_addr_t filler_addr, 314 enum mlx5e_mpwrq_umr_mode umr_mode, 315 u32 xsk_chunk_size) 316 { 317 struct mlx5_mtt *mtt; 318 struct mlx5_ksm *ksm; 319 struct mlx5_klm *klm; 320 u32 octwords; 321 int inlen; 322 void *mkc; 323 u32 *in; 324 int err; 325 int i; 326 327 if ((umr_mode == MLX5E_MPWRQ_UMR_MODE_UNALIGNED || 328 umr_mode == MLX5E_MPWRQ_UMR_MODE_TRIPLE) && 329 !MLX5_CAP_GEN(mdev, fixed_buffer_size)) { 330 mlx5_core_warn(mdev, "Unaligned AF_XDP requires fixed_buffer_size capability\n"); 331 return -EINVAL; 332 } 333 334 octwords = mlx5e_mpwrq_umr_octowords(npages, umr_mode); 335 336 inlen = MLX5_FLEXIBLE_INLEN(mdev, MLX5_ST_SZ_BYTES(create_mkey_in), 337 MLX5_OCTWORD, octwords); 338 if (inlen < 0) 339 return inlen; 340 341 in = kvzalloc(inlen, GFP_KERNEL); 342 if (!in) 343 return -ENOMEM; 344 345 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 346 347 MLX5_SET(mkc, mkc, free, 1); 348 MLX5_SET(mkc, mkc, umr_en, 1); 349 MLX5_SET(mkc, mkc, lw, 1); 350 MLX5_SET(mkc, mkc, lr, 1); 351 MLX5_SET(mkc, mkc, access_mode_1_0, mlx5e_mpwrq_access_mode(umr_mode)); 352 mlx5e_mkey_set_relaxed_ordering(mdev, mkc); 353 MLX5_SET(mkc, mkc, qpn, 0xffffff); 354 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn); 355 MLX5_SET64(mkc, mkc, len, npages << page_shift); 356 MLX5_SET(mkc, mkc, translations_octword_size, octwords); 357 if (umr_mode == MLX5E_MPWRQ_UMR_MODE_TRIPLE) 358 MLX5_SET(mkc, mkc, log_page_size, page_shift - 2); 359 else if (umr_mode != MLX5E_MPWRQ_UMR_MODE_OVERSIZED) 360 MLX5_SET(mkc, mkc, log_page_size, page_shift); 361 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, octwords); 362 363 /* Initialize the mkey with all MTTs pointing to a default 364 * page (filler_addr). When the channels are activated, UMR 365 * WQEs will redirect the RX WQEs to the actual memory from 366 * the RQ's pool, while the gaps (wqe_overflow) remain mapped 367 * to the default page. 368 */ 369 switch (umr_mode) { 370 case MLX5E_MPWRQ_UMR_MODE_OVERSIZED: 371 klm = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt); 372 for (i = 0; i < npages; i++) { 373 klm[i << 1] = (struct mlx5_klm) { 374 .va = cpu_to_be64(filler_addr), 375 .bcount = cpu_to_be32(xsk_chunk_size), 376 .key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey), 377 }; 378 klm[(i << 1) + 1] = (struct mlx5_klm) { 379 .va = cpu_to_be64(filler_addr), 380 .bcount = cpu_to_be32((1 << page_shift) - xsk_chunk_size), 381 .key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey), 382 }; 383 } 384 break; 385 case MLX5E_MPWRQ_UMR_MODE_UNALIGNED: 386 ksm = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt); 387 for (i = 0; i < npages; i++) 388 ksm[i] = (struct mlx5_ksm) { 389 .key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey), 390 .va = cpu_to_be64(filler_addr), 391 }; 392 break; 393 case MLX5E_MPWRQ_UMR_MODE_ALIGNED: 394 mtt = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt); 395 for (i = 0; i < npages; i++) 396 mtt[i] = (struct mlx5_mtt) { 397 .ptag = cpu_to_be64(filler_addr), 398 }; 399 break; 400 case MLX5E_MPWRQ_UMR_MODE_TRIPLE: 401 ksm = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt); 402 for (i = 0; i < npages * 4; i++) { 403 ksm[i] = (struct mlx5_ksm) { 404 .key = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey), 405 .va = cpu_to_be64(filler_addr), 406 }; 407 } 408 break; 409 } 410 411 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen); 412 413 kvfree(in); 414 return err; 415 } 416 417 static int mlx5e_create_umr_klm_mkey(struct mlx5_core_dev *mdev, 418 u64 nentries, 419 u32 *umr_mkey) 420 { 421 int inlen; 422 void *mkc; 423 u32 *in; 424 int err; 425 426 inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 427 428 in = kvzalloc(inlen, GFP_KERNEL); 429 if (!in) 430 return -ENOMEM; 431 432 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 433 434 MLX5_SET(mkc, mkc, free, 1); 435 MLX5_SET(mkc, mkc, umr_en, 1); 436 MLX5_SET(mkc, mkc, lw, 1); 437 MLX5_SET(mkc, mkc, lr, 1); 438 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_KLMS); 439 mlx5e_mkey_set_relaxed_ordering(mdev, mkc); 440 MLX5_SET(mkc, mkc, qpn, 0xffffff); 441 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.hw_objs.pdn); 442 MLX5_SET(mkc, mkc, translations_octword_size, nentries); 443 MLX5_SET(mkc, mkc, length64, 1); 444 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen); 445 446 kvfree(in); 447 return err; 448 } 449 450 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq) 451 { 452 u32 xsk_chunk_size = rq->xsk_pool ? rq->xsk_pool->chunk_size : 0; 453 u32 wq_size = mlx5_wq_ll_get_size(&rq->mpwqe.wq); 454 u32 num_entries, max_num_entries; 455 u32 umr_mkey; 456 int err; 457 458 max_num_entries = mlx5e_mpwrq_max_num_entries(mdev, rq->mpwqe.umr_mode); 459 460 /* Shouldn't overflow, the result is at most MLX5E_MAX_RQ_NUM_MTTS. */ 461 if (WARN_ON_ONCE(check_mul_overflow(wq_size, (u32)rq->mpwqe.mtts_per_wqe, 462 &num_entries) || 463 num_entries > max_num_entries)) 464 mlx5_core_err(mdev, "%s: multiplication overflow: %u * %u > %u\n", 465 __func__, wq_size, rq->mpwqe.mtts_per_wqe, 466 max_num_entries); 467 468 err = mlx5e_create_umr_mkey(mdev, num_entries, rq->mpwqe.page_shift, 469 &umr_mkey, rq->wqe_overflow.addr, 470 rq->mpwqe.umr_mode, xsk_chunk_size); 471 rq->mpwqe.umr_mkey_be = cpu_to_be32(umr_mkey); 472 return err; 473 } 474 475 static int mlx5e_create_rq_hd_umr_mkey(struct mlx5_core_dev *mdev, 476 struct mlx5e_rq *rq) 477 { 478 u32 max_klm_size = BIT(MLX5_CAP_GEN(mdev, log_max_klm_list_size)); 479 480 if (max_klm_size < rq->mpwqe.shampo->hd_per_wq) { 481 mlx5_core_err(mdev, "max klm list size 0x%x is smaller than shampo header buffer list size 0x%x\n", 482 max_klm_size, rq->mpwqe.shampo->hd_per_wq); 483 return -EINVAL; 484 } 485 return mlx5e_create_umr_klm_mkey(mdev, rq->mpwqe.shampo->hd_per_wq, 486 &rq->mpwqe.shampo->mkey); 487 } 488 489 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq) 490 { 491 struct mlx5e_wqe_frag_info next_frag = {}; 492 struct mlx5e_wqe_frag_info *prev = NULL; 493 int i; 494 495 if (rq->xsk_pool) { 496 /* Assumptions used by XSK batched allocator. */ 497 WARN_ON(rq->wqe.info.num_frags != 1); 498 WARN_ON(rq->wqe.info.log_num_frags != 0); 499 WARN_ON(rq->wqe.info.arr[0].frag_stride != PAGE_SIZE); 500 } 501 502 next_frag.au = &rq->wqe.alloc_units[0]; 503 504 for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) { 505 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0]; 506 struct mlx5e_wqe_frag_info *frag = 507 &rq->wqe.frags[i << rq->wqe.info.log_num_frags]; 508 int f; 509 510 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) { 511 if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) { 512 next_frag.au++; 513 next_frag.offset = 0; 514 if (prev) 515 prev->last_in_page = true; 516 } 517 *frag = next_frag; 518 519 /* prepare next */ 520 next_frag.offset += frag_info[f].frag_stride; 521 prev = frag; 522 } 523 } 524 525 if (prev) 526 prev->last_in_page = true; 527 } 528 529 static int mlx5e_init_au_list(struct mlx5e_rq *rq, int wq_sz, int node) 530 { 531 int len = wq_sz << rq->wqe.info.log_num_frags; 532 533 rq->wqe.alloc_units = kvzalloc_node(array_size(len, sizeof(*rq->wqe.alloc_units)), 534 GFP_KERNEL, node); 535 if (!rq->wqe.alloc_units) 536 return -ENOMEM; 537 538 mlx5e_init_frags_partition(rq); 539 540 return 0; 541 } 542 543 static void mlx5e_free_au_list(struct mlx5e_rq *rq) 544 { 545 kvfree(rq->wqe.alloc_units); 546 } 547 548 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work) 549 { 550 struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work); 551 552 mlx5e_reporter_rq_cqe_err(rq); 553 } 554 555 static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq *rq) 556 { 557 rq->wqe_overflow.page = alloc_page(GFP_KERNEL); 558 if (!rq->wqe_overflow.page) 559 return -ENOMEM; 560 561 rq->wqe_overflow.addr = dma_map_page(rq->pdev, rq->wqe_overflow.page, 0, 562 PAGE_SIZE, rq->buff.map_dir); 563 if (dma_mapping_error(rq->pdev, rq->wqe_overflow.addr)) { 564 __free_page(rq->wqe_overflow.page); 565 return -ENOMEM; 566 } 567 return 0; 568 } 569 570 static void mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq *rq) 571 { 572 dma_unmap_page(rq->pdev, rq->wqe_overflow.addr, PAGE_SIZE, 573 rq->buff.map_dir); 574 __free_page(rq->wqe_overflow.page); 575 } 576 577 static int mlx5e_init_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params, 578 struct mlx5e_rq *rq) 579 { 580 struct mlx5_core_dev *mdev = c->mdev; 581 int err; 582 583 rq->wq_type = params->rq_wq_type; 584 rq->pdev = c->pdev; 585 rq->netdev = c->netdev; 586 rq->priv = c->priv; 587 rq->tstamp = c->tstamp; 588 rq->clock = &mdev->clock; 589 rq->icosq = &c->icosq; 590 rq->ix = c->ix; 591 rq->channel = c; 592 rq->mdev = mdev; 593 rq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu); 594 rq->xdpsq = &c->rq_xdpsq; 595 rq->stats = &c->priv->channel_stats[c->ix]->rq; 596 rq->ptp_cyc2time = mlx5_rq_ts_translator(mdev); 597 err = mlx5e_rq_set_handlers(rq, params, NULL); 598 if (err) 599 return err; 600 601 return xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix, c->napi.napi_id); 602 } 603 604 static int mlx5_rq_shampo_alloc(struct mlx5_core_dev *mdev, 605 struct mlx5e_params *params, 606 struct mlx5e_rq_param *rqp, 607 struct mlx5e_rq *rq, 608 u32 *pool_size, 609 int node) 610 { 611 void *wqc = MLX5_ADDR_OF(rqc, rqp->rqc, wq); 612 int wq_size; 613 int err; 614 615 if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) 616 return 0; 617 err = mlx5e_rq_shampo_hd_alloc(rq, node); 618 if (err) 619 goto out; 620 rq->mpwqe.shampo->hd_per_wq = 621 mlx5e_shampo_hd_per_wq(mdev, params, rqp); 622 err = mlx5e_create_rq_hd_umr_mkey(mdev, rq); 623 if (err) 624 goto err_shampo_hd; 625 err = mlx5e_rq_shampo_hd_info_alloc(rq, node); 626 if (err) 627 goto err_shampo_info; 628 rq->hw_gro_data = kvzalloc_node(sizeof(*rq->hw_gro_data), GFP_KERNEL, node); 629 if (!rq->hw_gro_data) { 630 err = -ENOMEM; 631 goto err_hw_gro_data; 632 } 633 rq->mpwqe.shampo->key = 634 cpu_to_be32(rq->mpwqe.shampo->mkey); 635 rq->mpwqe.shampo->hd_per_wqe = 636 mlx5e_shampo_hd_per_wqe(mdev, params, rqp); 637 wq_size = BIT(MLX5_GET(wq, wqc, log_wq_sz)); 638 *pool_size += (rq->mpwqe.shampo->hd_per_wqe * wq_size) / 639 MLX5E_SHAMPO_WQ_HEADER_PER_PAGE; 640 return 0; 641 642 err_hw_gro_data: 643 mlx5e_rq_shampo_hd_info_free(rq); 644 err_shampo_info: 645 mlx5_core_destroy_mkey(mdev, rq->mpwqe.shampo->mkey); 646 err_shampo_hd: 647 mlx5e_rq_shampo_hd_free(rq); 648 out: 649 return err; 650 } 651 652 static void mlx5e_rq_free_shampo(struct mlx5e_rq *rq) 653 { 654 if (!test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) 655 return; 656 657 kvfree(rq->hw_gro_data); 658 mlx5e_rq_shampo_hd_info_free(rq); 659 mlx5_core_destroy_mkey(rq->mdev, rq->mpwqe.shampo->mkey); 660 mlx5e_rq_shampo_hd_free(rq); 661 } 662 663 static int mlx5e_alloc_rq(struct mlx5e_params *params, 664 struct mlx5e_xsk_param *xsk, 665 struct mlx5e_rq_param *rqp, 666 int node, struct mlx5e_rq *rq) 667 { 668 struct page_pool_params pp_params = { 0 }; 669 struct mlx5_core_dev *mdev = rq->mdev; 670 void *rqc = rqp->rqc; 671 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); 672 u32 pool_size; 673 int wq_sz; 674 int err; 675 int i; 676 677 rqp->wq.db_numa_node = node; 678 INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work); 679 680 if (params->xdp_prog) 681 bpf_prog_inc(params->xdp_prog); 682 RCU_INIT_POINTER(rq->xdp_prog, params->xdp_prog); 683 684 rq->buff.map_dir = params->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; 685 rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk); 686 pool_size = 1 << params->log_rq_mtu_frames; 687 688 rq->mkey_be = cpu_to_be32(mdev->mlx5e_res.hw_objs.mkey); 689 690 switch (rq->wq_type) { 691 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 692 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq, 693 &rq->wq_ctrl); 694 if (err) 695 goto err_rq_xdp_prog; 696 697 err = mlx5e_alloc_mpwqe_rq_drop_page(rq); 698 if (err) 699 goto err_rq_wq_destroy; 700 701 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR]; 702 703 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq); 704 705 rq->mpwqe.page_shift = mlx5e_mpwrq_page_shift(mdev, xsk); 706 rq->mpwqe.umr_mode = mlx5e_mpwrq_umr_mode(mdev, xsk); 707 rq->mpwqe.pages_per_wqe = 708 mlx5e_mpwrq_pages_per_wqe(mdev, rq->mpwqe.page_shift, 709 rq->mpwqe.umr_mode); 710 rq->mpwqe.umr_wqebbs = 711 mlx5e_mpwrq_umr_wqebbs(mdev, rq->mpwqe.page_shift, 712 rq->mpwqe.umr_mode); 713 rq->mpwqe.mtts_per_wqe = 714 mlx5e_mpwrq_mtts_per_wqe(mdev, rq->mpwqe.page_shift, 715 rq->mpwqe.umr_mode); 716 717 pool_size = rq->mpwqe.pages_per_wqe << 718 mlx5e_mpwqe_get_log_rq_size(mdev, params, xsk); 719 720 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk); 721 rq->mpwqe.num_strides = 722 BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk)); 723 rq->mpwqe.min_wqe_bulk = mlx5e_mpwqe_get_min_wqe_bulk(wq_sz); 724 725 rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz); 726 727 err = mlx5e_create_rq_umr_mkey(mdev, rq); 728 if (err) 729 goto err_rq_drop_page; 730 731 err = mlx5e_rq_alloc_mpwqe_info(rq, node); 732 if (err) 733 goto err_rq_mkey; 734 735 err = mlx5_rq_shampo_alloc(mdev, params, rqp, rq, &pool_size, node); 736 if (err) 737 goto err_free_mpwqe_info; 738 739 break; 740 default: /* MLX5_WQ_TYPE_CYCLIC */ 741 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq, 742 &rq->wq_ctrl); 743 if (err) 744 goto err_rq_xdp_prog; 745 746 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR]; 747 748 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq); 749 750 rq->wqe.info = rqp->frags_info; 751 rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride; 752 753 rq->wqe.frags = 754 kvzalloc_node(array_size(sizeof(*rq->wqe.frags), 755 (wq_sz << rq->wqe.info.log_num_frags)), 756 GFP_KERNEL, node); 757 if (!rq->wqe.frags) { 758 err = -ENOMEM; 759 goto err_rq_wq_destroy; 760 } 761 762 err = mlx5e_init_au_list(rq, wq_sz, node); 763 if (err) 764 goto err_rq_frags; 765 } 766 767 if (xsk) { 768 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq, 769 MEM_TYPE_XSK_BUFF_POOL, NULL); 770 xsk_pool_set_rxq_info(rq->xsk_pool, &rq->xdp_rxq); 771 } else { 772 /* Create a page_pool and register it with rxq */ 773 pp_params.order = 0; 774 pp_params.flags = 0; /* No-internal DMA mapping in page_pool */ 775 pp_params.pool_size = pool_size; 776 pp_params.nid = node; 777 pp_params.dev = rq->pdev; 778 pp_params.dma_dir = rq->buff.map_dir; 779 780 /* page_pool can be used even when there is no rq->xdp_prog, 781 * given page_pool does not handle DMA mapping there is no 782 * required state to clear. And page_pool gracefully handle 783 * elevated refcnt. 784 */ 785 rq->page_pool = page_pool_create(&pp_params); 786 if (IS_ERR(rq->page_pool)) { 787 err = PTR_ERR(rq->page_pool); 788 rq->page_pool = NULL; 789 goto err_free_by_rq_type; 790 } 791 if (xdp_rxq_info_is_reg(&rq->xdp_rxq)) 792 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq, 793 MEM_TYPE_PAGE_POOL, rq->page_pool); 794 } 795 if (err) 796 goto err_destroy_page_pool; 797 798 for (i = 0; i < wq_sz; i++) { 799 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) { 800 struct mlx5e_rx_wqe_ll *wqe = 801 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i); 802 u32 byte_count = 803 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz; 804 u64 dma_offset = mul_u32_u32(i, rq->mpwqe.mtts_per_wqe) << 805 rq->mpwqe.page_shift; 806 u16 headroom = test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state) ? 807 0 : rq->buff.headroom; 808 809 wqe->data[0].addr = cpu_to_be64(dma_offset + headroom); 810 wqe->data[0].byte_count = cpu_to_be32(byte_count); 811 wqe->data[0].lkey = rq->mpwqe.umr_mkey_be; 812 } else { 813 struct mlx5e_rx_wqe_cyc *wqe = 814 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i); 815 int f; 816 817 for (f = 0; f < rq->wqe.info.num_frags; f++) { 818 u32 frag_size = rq->wqe.info.arr[f].frag_size | 819 MLX5_HW_START_PADDING; 820 821 wqe->data[f].byte_count = cpu_to_be32(frag_size); 822 wqe->data[f].lkey = rq->mkey_be; 823 } 824 /* check if num_frags is not a pow of two */ 825 if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) { 826 wqe->data[f].byte_count = 0; 827 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 828 wqe->data[f].addr = 0; 829 } 830 } 831 } 832 833 INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work); 834 835 switch (params->rx_cq_moderation.cq_period_mode) { 836 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE: 837 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE; 838 break; 839 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE: 840 default: 841 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 842 } 843 844 rq->page_cache.head = 0; 845 rq->page_cache.tail = 0; 846 847 return 0; 848 849 err_destroy_page_pool: 850 page_pool_destroy(rq->page_pool); 851 err_free_by_rq_type: 852 switch (rq->wq_type) { 853 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 854 mlx5e_rq_free_shampo(rq); 855 err_free_mpwqe_info: 856 kvfree(rq->mpwqe.info); 857 err_rq_mkey: 858 mlx5_core_destroy_mkey(mdev, be32_to_cpu(rq->mpwqe.umr_mkey_be)); 859 err_rq_drop_page: 860 mlx5e_free_mpwqe_rq_drop_page(rq); 861 break; 862 default: /* MLX5_WQ_TYPE_CYCLIC */ 863 mlx5e_free_au_list(rq); 864 err_rq_frags: 865 kvfree(rq->wqe.frags); 866 } 867 err_rq_wq_destroy: 868 mlx5_wq_destroy(&rq->wq_ctrl); 869 err_rq_xdp_prog: 870 if (params->xdp_prog) 871 bpf_prog_put(params->xdp_prog); 872 873 return err; 874 } 875 876 static void mlx5e_free_rq(struct mlx5e_rq *rq) 877 { 878 struct bpf_prog *old_prog; 879 int i; 880 881 if (xdp_rxq_info_is_reg(&rq->xdp_rxq)) { 882 old_prog = rcu_dereference_protected(rq->xdp_prog, 883 lockdep_is_held(&rq->priv->state_lock)); 884 if (old_prog) 885 bpf_prog_put(old_prog); 886 } 887 888 switch (rq->wq_type) { 889 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 890 kvfree(rq->mpwqe.info); 891 mlx5_core_destroy_mkey(rq->mdev, be32_to_cpu(rq->mpwqe.umr_mkey_be)); 892 mlx5e_free_mpwqe_rq_drop_page(rq); 893 mlx5e_rq_free_shampo(rq); 894 break; 895 default: /* MLX5_WQ_TYPE_CYCLIC */ 896 kvfree(rq->wqe.frags); 897 mlx5e_free_au_list(rq); 898 } 899 900 for (i = rq->page_cache.head; i != rq->page_cache.tail; 901 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) { 902 /* With AF_XDP, page_cache is not used, so this loop is not 903 * entered, and it's safe to call mlx5e_page_release_dynamic 904 * directly. 905 */ 906 mlx5e_page_release_dynamic(rq, rq->page_cache.page_cache[i], false); 907 } 908 909 xdp_rxq_info_unreg(&rq->xdp_rxq); 910 page_pool_destroy(rq->page_pool); 911 mlx5_wq_destroy(&rq->wq_ctrl); 912 } 913 914 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param) 915 { 916 struct mlx5_core_dev *mdev = rq->mdev; 917 u8 ts_format; 918 void *in; 919 void *rqc; 920 void *wq; 921 int inlen; 922 int err; 923 924 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + 925 sizeof(u64) * rq->wq_ctrl.buf.npages; 926 in = kvzalloc(inlen, GFP_KERNEL); 927 if (!in) 928 return -ENOMEM; 929 930 ts_format = mlx5_is_real_time_rq(mdev) ? 931 MLX5_TIMESTAMP_FORMAT_REAL_TIME : 932 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING; 933 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 934 wq = MLX5_ADDR_OF(rqc, rqc, wq); 935 936 memcpy(rqc, param->rqc, sizeof(param->rqc)); 937 938 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn); 939 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 940 MLX5_SET(rqc, rqc, ts_format, ts_format); 941 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift - 942 MLX5_ADAPTER_PAGE_SHIFT); 943 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma); 944 945 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) { 946 MLX5_SET(wq, wq, log_headers_buffer_entry_num, 947 order_base_2(rq->mpwqe.shampo->hd_per_wq)); 948 MLX5_SET(wq, wq, headers_mkey, rq->mpwqe.shampo->mkey); 949 } 950 951 mlx5_fill_page_frag_array(&rq->wq_ctrl.buf, 952 (__be64 *)MLX5_ADDR_OF(wq, wq, pas)); 953 954 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn); 955 956 kvfree(in); 957 958 return err; 959 } 960 961 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state) 962 { 963 struct mlx5_core_dev *mdev = rq->mdev; 964 965 void *in; 966 void *rqc; 967 int inlen; 968 int err; 969 970 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 971 in = kvzalloc(inlen, GFP_KERNEL); 972 if (!in) 973 return -ENOMEM; 974 975 if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY) 976 mlx5e_rqwq_reset(rq); 977 978 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 979 980 MLX5_SET(modify_rq_in, in, rq_state, curr_state); 981 MLX5_SET(rqc, rqc, state, next_state); 982 983 err = mlx5_core_modify_rq(mdev, rq->rqn, in); 984 985 kvfree(in); 986 987 return err; 988 } 989 990 static int mlx5e_rq_to_ready(struct mlx5e_rq *rq, int curr_state) 991 { 992 struct net_device *dev = rq->netdev; 993 int err; 994 995 err = mlx5e_modify_rq_state(rq, curr_state, MLX5_RQC_STATE_RST); 996 if (err) { 997 netdev_err(dev, "Failed to move rq 0x%x to reset\n", rq->rqn); 998 return err; 999 } 1000 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 1001 if (err) { 1002 netdev_err(dev, "Failed to move rq 0x%x to ready\n", rq->rqn); 1003 return err; 1004 } 1005 1006 return 0; 1007 } 1008 1009 int mlx5e_flush_rq(struct mlx5e_rq *rq, int curr_state) 1010 { 1011 mlx5e_free_rx_descs(rq); 1012 1013 return mlx5e_rq_to_ready(rq, curr_state); 1014 } 1015 1016 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable) 1017 { 1018 struct mlx5_core_dev *mdev = rq->mdev; 1019 1020 void *in; 1021 void *rqc; 1022 int inlen; 1023 int err; 1024 1025 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 1026 in = kvzalloc(inlen, GFP_KERNEL); 1027 if (!in) 1028 return -ENOMEM; 1029 1030 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1031 1032 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY); 1033 MLX5_SET64(modify_rq_in, in, modify_bitmask, 1034 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS); 1035 MLX5_SET(rqc, rqc, scatter_fcs, enable); 1036 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY); 1037 1038 err = mlx5_core_modify_rq(mdev, rq->rqn, in); 1039 1040 kvfree(in); 1041 1042 return err; 1043 } 1044 1045 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd) 1046 { 1047 struct mlx5_core_dev *mdev = rq->mdev; 1048 void *in; 1049 void *rqc; 1050 int inlen; 1051 int err; 1052 1053 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 1054 in = kvzalloc(inlen, GFP_KERNEL); 1055 if (!in) 1056 return -ENOMEM; 1057 1058 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1059 1060 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY); 1061 MLX5_SET64(modify_rq_in, in, modify_bitmask, 1062 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); 1063 MLX5_SET(rqc, rqc, vsd, vsd); 1064 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY); 1065 1066 err = mlx5_core_modify_rq(mdev, rq->rqn, in); 1067 1068 kvfree(in); 1069 1070 return err; 1071 } 1072 1073 void mlx5e_destroy_rq(struct mlx5e_rq *rq) 1074 { 1075 mlx5_core_destroy_rq(rq->mdev, rq->rqn); 1076 } 1077 1078 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time) 1079 { 1080 unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time); 1081 1082 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq)); 1083 1084 do { 1085 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes) 1086 return 0; 1087 1088 msleep(20); 1089 } while (time_before(jiffies, exp_time)); 1090 1091 netdev_warn(rq->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n", 1092 rq->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes); 1093 1094 mlx5e_reporter_rx_timeout(rq); 1095 return -ETIMEDOUT; 1096 } 1097 1098 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq *rq) 1099 { 1100 struct mlx5_wq_ll *wq; 1101 u16 head; 1102 int i; 1103 1104 if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) 1105 return; 1106 1107 wq = &rq->mpwqe.wq; 1108 head = wq->head; 1109 1110 /* Outstanding UMR WQEs (in progress) start at wq->head */ 1111 for (i = 0; i < rq->mpwqe.umr_in_progress; i++) { 1112 rq->dealloc_wqe(rq, head); 1113 head = mlx5_wq_ll_get_wqe_next_ix(wq, head); 1114 } 1115 1116 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) { 1117 u16 len; 1118 1119 len = (rq->mpwqe.shampo->pi - rq->mpwqe.shampo->ci) & 1120 (rq->mpwqe.shampo->hd_per_wq - 1); 1121 mlx5e_shampo_dealloc_hd(rq, len, rq->mpwqe.shampo->ci, false); 1122 rq->mpwqe.shampo->pi = rq->mpwqe.shampo->ci; 1123 } 1124 1125 rq->mpwqe.actual_wq_head = wq->head; 1126 rq->mpwqe.umr_in_progress = 0; 1127 rq->mpwqe.umr_completed = 0; 1128 } 1129 1130 void mlx5e_free_rx_descs(struct mlx5e_rq *rq) 1131 { 1132 __be16 wqe_ix_be; 1133 u16 wqe_ix; 1134 1135 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) { 1136 struct mlx5_wq_ll *wq = &rq->mpwqe.wq; 1137 1138 mlx5e_free_rx_in_progress_descs(rq); 1139 1140 while (!mlx5_wq_ll_is_empty(wq)) { 1141 struct mlx5e_rx_wqe_ll *wqe; 1142 1143 wqe_ix_be = *wq->tail_next; 1144 wqe_ix = be16_to_cpu(wqe_ix_be); 1145 wqe = mlx5_wq_ll_get_wqe(wq, wqe_ix); 1146 rq->dealloc_wqe(rq, wqe_ix); 1147 mlx5_wq_ll_pop(wq, wqe_ix_be, 1148 &wqe->next.next_wqe_index); 1149 } 1150 1151 if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) 1152 mlx5e_shampo_dealloc_hd(rq, rq->mpwqe.shampo->hd_per_wq, 1153 0, true); 1154 } else { 1155 struct mlx5_wq_cyc *wq = &rq->wqe.wq; 1156 1157 while (!mlx5_wq_cyc_is_empty(wq)) { 1158 wqe_ix = mlx5_wq_cyc_get_tail(wq); 1159 rq->dealloc_wqe(rq, wqe_ix); 1160 mlx5_wq_cyc_pop(wq); 1161 } 1162 } 1163 1164 } 1165 1166 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param, 1167 struct mlx5e_xsk_param *xsk, int node, 1168 struct mlx5e_rq *rq) 1169 { 1170 struct mlx5_core_dev *mdev = rq->mdev; 1171 int err; 1172 1173 if (params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) 1174 __set_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state); 1175 1176 err = mlx5e_alloc_rq(params, xsk, param, node, rq); 1177 if (err) 1178 return err; 1179 1180 err = mlx5e_create_rq(rq, param); 1181 if (err) 1182 goto err_free_rq; 1183 1184 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 1185 if (err) 1186 goto err_destroy_rq; 1187 1188 if (MLX5_CAP_ETH(mdev, cqe_checksum_full)) 1189 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state); 1190 1191 if (params->rx_dim_enabled) 1192 __set_bit(MLX5E_RQ_STATE_AM, &rq->state); 1193 1194 /* We disable csum_complete when XDP is enabled since 1195 * XDP programs might manipulate packets which will render 1196 * skb->checksum incorrect. 1197 */ 1198 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || params->xdp_prog) 1199 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state); 1200 1201 /* For CQE compression on striding RQ, use stride index provided by 1202 * HW if capability is supported. 1203 */ 1204 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) && 1205 MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index)) 1206 __set_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &rq->state); 1207 1208 return 0; 1209 1210 err_destroy_rq: 1211 mlx5e_destroy_rq(rq); 1212 err_free_rq: 1213 mlx5e_free_rq(rq); 1214 1215 return err; 1216 } 1217 1218 void mlx5e_activate_rq(struct mlx5e_rq *rq) 1219 { 1220 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state); 1221 } 1222 1223 void mlx5e_deactivate_rq(struct mlx5e_rq *rq) 1224 { 1225 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state); 1226 synchronize_net(); /* Sync with NAPI to prevent mlx5e_post_rx_wqes. */ 1227 } 1228 1229 void mlx5e_close_rq(struct mlx5e_rq *rq) 1230 { 1231 cancel_work_sync(&rq->dim.work); 1232 cancel_work_sync(&rq->recover_work); 1233 mlx5e_destroy_rq(rq); 1234 mlx5e_free_rx_descs(rq); 1235 mlx5e_free_rq(rq); 1236 } 1237 1238 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq) 1239 { 1240 kvfree(sq->db.xdpi_fifo.xi); 1241 kvfree(sq->db.wqe_info); 1242 } 1243 1244 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa) 1245 { 1246 struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo; 1247 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1248 int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS; 1249 size_t size; 1250 1251 size = array_size(sizeof(*xdpi_fifo->xi), dsegs_per_wq); 1252 xdpi_fifo->xi = kvzalloc_node(size, GFP_KERNEL, numa); 1253 if (!xdpi_fifo->xi) 1254 return -ENOMEM; 1255 1256 xdpi_fifo->pc = &sq->xdpi_fifo_pc; 1257 xdpi_fifo->cc = &sq->xdpi_fifo_cc; 1258 xdpi_fifo->mask = dsegs_per_wq - 1; 1259 1260 return 0; 1261 } 1262 1263 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa) 1264 { 1265 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1266 size_t size; 1267 int err; 1268 1269 size = array_size(sizeof(*sq->db.wqe_info), wq_sz); 1270 sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa); 1271 if (!sq->db.wqe_info) 1272 return -ENOMEM; 1273 1274 err = mlx5e_alloc_xdpsq_fifo(sq, numa); 1275 if (err) { 1276 mlx5e_free_xdpsq_db(sq); 1277 return err; 1278 } 1279 1280 return 0; 1281 } 1282 1283 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c, 1284 struct mlx5e_params *params, 1285 struct xsk_buff_pool *xsk_pool, 1286 struct mlx5e_sq_param *param, 1287 struct mlx5e_xdpsq *sq, 1288 bool is_redirect) 1289 { 1290 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq); 1291 struct mlx5_core_dev *mdev = c->mdev; 1292 struct mlx5_wq_cyc *wq = &sq->wq; 1293 int err; 1294 1295 sq->pdev = c->pdev; 1296 sq->mkey_be = c->mkey_be; 1297 sq->channel = c; 1298 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map; 1299 sq->min_inline_mode = params->tx_min_inline_mode; 1300 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu); 1301 sq->xsk_pool = xsk_pool; 1302 1303 sq->stats = sq->xsk_pool ? 1304 &c->priv->channel_stats[c->ix]->xsksq : 1305 is_redirect ? 1306 &c->priv->channel_stats[c->ix]->xdpsq : 1307 &c->priv->channel_stats[c->ix]->rq_xdpsq; 1308 sq->stop_room = param->is_mpw ? mlx5e_stop_room_for_mpwqe(mdev) : 1309 mlx5e_stop_room_for_max_wqe(mdev); 1310 sq->max_sq_mpw_wqebbs = mlx5e_get_max_sq_aligned_wqebbs(mdev); 1311 1312 param->wq.db_numa_node = cpu_to_node(c->cpu); 1313 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl); 1314 if (err) 1315 return err; 1316 wq->db = &wq->db[MLX5_SND_DBR]; 1317 1318 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu)); 1319 if (err) 1320 goto err_sq_wq_destroy; 1321 1322 return 0; 1323 1324 err_sq_wq_destroy: 1325 mlx5_wq_destroy(&sq->wq_ctrl); 1326 1327 return err; 1328 } 1329 1330 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq) 1331 { 1332 mlx5e_free_xdpsq_db(sq); 1333 mlx5_wq_destroy(&sq->wq_ctrl); 1334 } 1335 1336 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq) 1337 { 1338 kvfree(sq->db.wqe_info); 1339 } 1340 1341 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa) 1342 { 1343 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1344 size_t size; 1345 1346 size = array_size(wq_sz, sizeof(*sq->db.wqe_info)); 1347 sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa); 1348 if (!sq->db.wqe_info) 1349 return -ENOMEM; 1350 1351 return 0; 1352 } 1353 1354 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work) 1355 { 1356 struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq, 1357 recover_work); 1358 1359 mlx5e_reporter_icosq_cqe_err(sq); 1360 } 1361 1362 static void mlx5e_async_icosq_err_cqe_work(struct work_struct *recover_work) 1363 { 1364 struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq, 1365 recover_work); 1366 1367 /* Not implemented yet. */ 1368 1369 netdev_warn(sq->channel->netdev, "async_icosq recovery is not implemented\n"); 1370 } 1371 1372 static int mlx5e_alloc_icosq(struct mlx5e_channel *c, 1373 struct mlx5e_sq_param *param, 1374 struct mlx5e_icosq *sq, 1375 work_func_t recover_work_func) 1376 { 1377 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq); 1378 struct mlx5_core_dev *mdev = c->mdev; 1379 struct mlx5_wq_cyc *wq = &sq->wq; 1380 int err; 1381 1382 sq->channel = c; 1383 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map; 1384 sq->reserved_room = param->stop_room; 1385 1386 param->wq.db_numa_node = cpu_to_node(c->cpu); 1387 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl); 1388 if (err) 1389 return err; 1390 wq->db = &wq->db[MLX5_SND_DBR]; 1391 1392 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu)); 1393 if (err) 1394 goto err_sq_wq_destroy; 1395 1396 INIT_WORK(&sq->recover_work, recover_work_func); 1397 1398 return 0; 1399 1400 err_sq_wq_destroy: 1401 mlx5_wq_destroy(&sq->wq_ctrl); 1402 1403 return err; 1404 } 1405 1406 static void mlx5e_free_icosq(struct mlx5e_icosq *sq) 1407 { 1408 mlx5e_free_icosq_db(sq); 1409 mlx5_wq_destroy(&sq->wq_ctrl); 1410 } 1411 1412 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq) 1413 { 1414 kvfree(sq->db.wqe_info); 1415 kvfree(sq->db.skb_fifo.fifo); 1416 kvfree(sq->db.dma_fifo); 1417 } 1418 1419 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa) 1420 { 1421 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1422 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS; 1423 1424 sq->db.dma_fifo = kvzalloc_node(array_size(df_sz, 1425 sizeof(*sq->db.dma_fifo)), 1426 GFP_KERNEL, numa); 1427 sq->db.skb_fifo.fifo = kvzalloc_node(array_size(df_sz, 1428 sizeof(*sq->db.skb_fifo.fifo)), 1429 GFP_KERNEL, numa); 1430 sq->db.wqe_info = kvzalloc_node(array_size(wq_sz, 1431 sizeof(*sq->db.wqe_info)), 1432 GFP_KERNEL, numa); 1433 if (!sq->db.dma_fifo || !sq->db.skb_fifo.fifo || !sq->db.wqe_info) { 1434 mlx5e_free_txqsq_db(sq); 1435 return -ENOMEM; 1436 } 1437 1438 sq->dma_fifo_mask = df_sz - 1; 1439 1440 sq->db.skb_fifo.pc = &sq->skb_fifo_pc; 1441 sq->db.skb_fifo.cc = &sq->skb_fifo_cc; 1442 sq->db.skb_fifo.mask = df_sz - 1; 1443 1444 return 0; 1445 } 1446 1447 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c, 1448 int txq_ix, 1449 struct mlx5e_params *params, 1450 struct mlx5e_sq_param *param, 1451 struct mlx5e_txqsq *sq, 1452 int tc) 1453 { 1454 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq); 1455 struct mlx5_core_dev *mdev = c->mdev; 1456 struct mlx5_wq_cyc *wq = &sq->wq; 1457 int err; 1458 1459 sq->pdev = c->pdev; 1460 sq->clock = &mdev->clock; 1461 sq->mkey_be = c->mkey_be; 1462 sq->netdev = c->netdev; 1463 sq->mdev = c->mdev; 1464 sq->priv = c->priv; 1465 sq->ch_ix = c->ix; 1466 sq->txq_ix = txq_ix; 1467 sq->uar_map = mdev->mlx5e_res.hw_objs.bfreg.map; 1468 sq->min_inline_mode = params->tx_min_inline_mode; 1469 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu); 1470 sq->max_sq_mpw_wqebbs = mlx5e_get_max_sq_aligned_wqebbs(mdev); 1471 INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work); 1472 if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert)) 1473 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state); 1474 if (mlx5_ipsec_device_caps(c->priv->mdev)) 1475 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state); 1476 if (param->is_mpw) 1477 set_bit(MLX5E_SQ_STATE_MPWQE, &sq->state); 1478 sq->stop_room = param->stop_room; 1479 sq->ptp_cyc2time = mlx5_sq_ts_translator(mdev); 1480 1481 param->wq.db_numa_node = cpu_to_node(c->cpu); 1482 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl); 1483 if (err) 1484 return err; 1485 wq->db = &wq->db[MLX5_SND_DBR]; 1486 1487 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu)); 1488 if (err) 1489 goto err_sq_wq_destroy; 1490 1491 INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work); 1492 sq->dim.mode = params->tx_cq_moderation.cq_period_mode; 1493 1494 return 0; 1495 1496 err_sq_wq_destroy: 1497 mlx5_wq_destroy(&sq->wq_ctrl); 1498 1499 return err; 1500 } 1501 1502 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq) 1503 { 1504 mlx5e_free_txqsq_db(sq); 1505 mlx5_wq_destroy(&sq->wq_ctrl); 1506 } 1507 1508 static int mlx5e_create_sq(struct mlx5_core_dev *mdev, 1509 struct mlx5e_sq_param *param, 1510 struct mlx5e_create_sq_param *csp, 1511 u32 *sqn) 1512 { 1513 u8 ts_format; 1514 void *in; 1515 void *sqc; 1516 void *wq; 1517 int inlen; 1518 int err; 1519 1520 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + 1521 sizeof(u64) * csp->wq_ctrl->buf.npages; 1522 in = kvzalloc(inlen, GFP_KERNEL); 1523 if (!in) 1524 return -ENOMEM; 1525 1526 ts_format = mlx5_is_real_time_sq(mdev) ? 1527 MLX5_TIMESTAMP_FORMAT_REAL_TIME : 1528 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING; 1529 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1530 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1531 1532 memcpy(sqc, param->sqc, sizeof(param->sqc)); 1533 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz); 1534 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn); 1535 MLX5_SET(sqc, sqc, cqn, csp->cqn); 1536 MLX5_SET(sqc, sqc, ts_cqe_to_dest_cqn, csp->ts_cqe_to_dest_cqn); 1537 MLX5_SET(sqc, sqc, ts_format, ts_format); 1538 1539 1540 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) 1541 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode); 1542 1543 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1544 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1545 1546 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1547 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.hw_objs.bfreg.index); 1548 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift - 1549 MLX5_ADAPTER_PAGE_SHIFT); 1550 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma); 1551 1552 mlx5_fill_page_frag_array(&csp->wq_ctrl->buf, 1553 (__be64 *)MLX5_ADDR_OF(wq, wq, pas)); 1554 1555 err = mlx5_core_create_sq(mdev, in, inlen, sqn); 1556 1557 kvfree(in); 1558 1559 return err; 1560 } 1561 1562 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn, 1563 struct mlx5e_modify_sq_param *p) 1564 { 1565 u64 bitmask = 0; 1566 void *in; 1567 void *sqc; 1568 int inlen; 1569 int err; 1570 1571 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 1572 in = kvzalloc(inlen, GFP_KERNEL); 1573 if (!in) 1574 return -ENOMEM; 1575 1576 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1577 1578 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state); 1579 MLX5_SET(sqc, sqc, state, p->next_state); 1580 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) { 1581 bitmask |= 1; 1582 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index); 1583 } 1584 if (p->qos_update && p->next_state == MLX5_SQC_STATE_RDY) { 1585 bitmask |= 1 << 2; 1586 MLX5_SET(sqc, sqc, qos_queue_group_id, p->qos_queue_group_id); 1587 } 1588 MLX5_SET64(modify_sq_in, in, modify_bitmask, bitmask); 1589 1590 err = mlx5_core_modify_sq(mdev, sqn, in); 1591 1592 kvfree(in); 1593 1594 return err; 1595 } 1596 1597 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn) 1598 { 1599 mlx5_core_destroy_sq(mdev, sqn); 1600 } 1601 1602 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev, 1603 struct mlx5e_sq_param *param, 1604 struct mlx5e_create_sq_param *csp, 1605 u16 qos_queue_group_id, 1606 u32 *sqn) 1607 { 1608 struct mlx5e_modify_sq_param msp = {0}; 1609 int err; 1610 1611 err = mlx5e_create_sq(mdev, param, csp, sqn); 1612 if (err) 1613 return err; 1614 1615 msp.curr_state = MLX5_SQC_STATE_RST; 1616 msp.next_state = MLX5_SQC_STATE_RDY; 1617 if (qos_queue_group_id) { 1618 msp.qos_update = true; 1619 msp.qos_queue_group_id = qos_queue_group_id; 1620 } 1621 err = mlx5e_modify_sq(mdev, *sqn, &msp); 1622 if (err) 1623 mlx5e_destroy_sq(mdev, *sqn); 1624 1625 return err; 1626 } 1627 1628 static int mlx5e_set_sq_maxrate(struct net_device *dev, 1629 struct mlx5e_txqsq *sq, u32 rate); 1630 1631 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix, 1632 struct mlx5e_params *params, struct mlx5e_sq_param *param, 1633 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id, 1634 struct mlx5e_sq_stats *sq_stats) 1635 { 1636 struct mlx5e_create_sq_param csp = {}; 1637 u32 tx_rate; 1638 int err; 1639 1640 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc); 1641 if (err) 1642 return err; 1643 1644 sq->stats = sq_stats; 1645 1646 csp.tisn = tisn; 1647 csp.tis_lst_sz = 1; 1648 csp.cqn = sq->cq.mcq.cqn; 1649 csp.wq_ctrl = &sq->wq_ctrl; 1650 csp.min_inline_mode = sq->min_inline_mode; 1651 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, qos_queue_group_id, &sq->sqn); 1652 if (err) 1653 goto err_free_txqsq; 1654 1655 tx_rate = c->priv->tx_rates[sq->txq_ix]; 1656 if (tx_rate) 1657 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate); 1658 1659 if (params->tx_dim_enabled) 1660 sq->state |= BIT(MLX5E_SQ_STATE_AM); 1661 1662 return 0; 1663 1664 err_free_txqsq: 1665 mlx5e_free_txqsq(sq); 1666 1667 return err; 1668 } 1669 1670 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq) 1671 { 1672 sq->txq = netdev_get_tx_queue(sq->netdev, sq->txq_ix); 1673 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); 1674 netdev_tx_reset_queue(sq->txq); 1675 netif_tx_start_queue(sq->txq); 1676 } 1677 1678 void mlx5e_tx_disable_queue(struct netdev_queue *txq) 1679 { 1680 __netif_tx_lock_bh(txq); 1681 netif_tx_stop_queue(txq); 1682 __netif_tx_unlock_bh(txq); 1683 } 1684 1685 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq) 1686 { 1687 struct mlx5_wq_cyc *wq = &sq->wq; 1688 1689 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); 1690 synchronize_net(); /* Sync with NAPI to prevent netif_tx_wake_queue. */ 1691 1692 mlx5e_tx_disable_queue(sq->txq); 1693 1694 /* last doorbell out, godspeed .. */ 1695 if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) { 1696 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc); 1697 struct mlx5e_tx_wqe *nop; 1698 1699 sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) { 1700 .num_wqebbs = 1, 1701 }; 1702 1703 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc); 1704 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl); 1705 } 1706 } 1707 1708 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq) 1709 { 1710 struct mlx5_core_dev *mdev = sq->mdev; 1711 struct mlx5_rate_limit rl = {0}; 1712 1713 cancel_work_sync(&sq->dim.work); 1714 cancel_work_sync(&sq->recover_work); 1715 mlx5e_destroy_sq(mdev, sq->sqn); 1716 if (sq->rate_limit) { 1717 rl.rate = sq->rate_limit; 1718 mlx5_rl_remove_rate(mdev, &rl); 1719 } 1720 mlx5e_free_txqsq_descs(sq); 1721 mlx5e_free_txqsq(sq); 1722 } 1723 1724 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work) 1725 { 1726 struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq, 1727 recover_work); 1728 1729 mlx5e_reporter_tx_err_cqe(sq); 1730 } 1731 1732 static int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params, 1733 struct mlx5e_sq_param *param, struct mlx5e_icosq *sq, 1734 work_func_t recover_work_func) 1735 { 1736 struct mlx5e_create_sq_param csp = {}; 1737 int err; 1738 1739 err = mlx5e_alloc_icosq(c, param, sq, recover_work_func); 1740 if (err) 1741 return err; 1742 1743 csp.cqn = sq->cq.mcq.cqn; 1744 csp.wq_ctrl = &sq->wq_ctrl; 1745 csp.min_inline_mode = params->tx_min_inline_mode; 1746 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn); 1747 if (err) 1748 goto err_free_icosq; 1749 1750 if (param->is_tls) { 1751 sq->ktls_resync = mlx5e_ktls_rx_resync_create_resp_list(); 1752 if (IS_ERR(sq->ktls_resync)) { 1753 err = PTR_ERR(sq->ktls_resync); 1754 goto err_destroy_icosq; 1755 } 1756 } 1757 return 0; 1758 1759 err_destroy_icosq: 1760 mlx5e_destroy_sq(c->mdev, sq->sqn); 1761 err_free_icosq: 1762 mlx5e_free_icosq(sq); 1763 1764 return err; 1765 } 1766 1767 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq) 1768 { 1769 set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state); 1770 } 1771 1772 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq) 1773 { 1774 clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state); 1775 synchronize_net(); /* Sync with NAPI. */ 1776 } 1777 1778 static void mlx5e_close_icosq(struct mlx5e_icosq *sq) 1779 { 1780 struct mlx5e_channel *c = sq->channel; 1781 1782 if (sq->ktls_resync) 1783 mlx5e_ktls_rx_resync_destroy_resp_list(sq->ktls_resync); 1784 mlx5e_destroy_sq(c->mdev, sq->sqn); 1785 mlx5e_free_icosq_descs(sq); 1786 mlx5e_free_icosq(sq); 1787 } 1788 1789 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params, 1790 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool, 1791 struct mlx5e_xdpsq *sq, bool is_redirect) 1792 { 1793 struct mlx5e_create_sq_param csp = {}; 1794 int err; 1795 1796 err = mlx5e_alloc_xdpsq(c, params, xsk_pool, param, sq, is_redirect); 1797 if (err) 1798 return err; 1799 1800 csp.tis_lst_sz = 1; 1801 csp.tisn = c->priv->tisn[c->lag_port][0]; /* tc = 0 */ 1802 csp.cqn = sq->cq.mcq.cqn; 1803 csp.wq_ctrl = &sq->wq_ctrl; 1804 csp.min_inline_mode = sq->min_inline_mode; 1805 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); 1806 1807 /* Don't enable multi buffer on XDP_REDIRECT SQ, as it's not yet 1808 * supported by upstream, and there is no defined trigger to allow 1809 * transmitting redirected multi-buffer frames. 1810 */ 1811 if (param->is_xdp_mb && !is_redirect) 1812 set_bit(MLX5E_SQ_STATE_XDP_MULTIBUF, &sq->state); 1813 1814 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn); 1815 if (err) 1816 goto err_free_xdpsq; 1817 1818 mlx5e_set_xmit_fp(sq, param->is_mpw); 1819 1820 if (!param->is_mpw && !test_bit(MLX5E_SQ_STATE_XDP_MULTIBUF, &sq->state)) { 1821 unsigned int ds_cnt = MLX5E_TX_WQE_EMPTY_DS_COUNT + 1; 1822 unsigned int inline_hdr_sz = 0; 1823 int i; 1824 1825 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) { 1826 inline_hdr_sz = MLX5E_XDP_MIN_INLINE; 1827 ds_cnt++; 1828 } 1829 1830 /* Pre initialize fixed WQE fields */ 1831 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) { 1832 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i); 1833 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; 1834 struct mlx5_wqe_eth_seg *eseg = &wqe->eth; 1835 struct mlx5_wqe_data_seg *dseg; 1836 1837 sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) { 1838 .num_wqebbs = 1, 1839 .num_pkts = 1, 1840 }; 1841 1842 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt); 1843 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz); 1844 1845 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1); 1846 dseg->lkey = sq->mkey_be; 1847 } 1848 } 1849 1850 return 0; 1851 1852 err_free_xdpsq: 1853 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); 1854 mlx5e_free_xdpsq(sq); 1855 1856 return err; 1857 } 1858 1859 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq) 1860 { 1861 struct mlx5e_channel *c = sq->channel; 1862 1863 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); 1864 synchronize_net(); /* Sync with NAPI. */ 1865 1866 mlx5e_destroy_sq(c->mdev, sq->sqn); 1867 mlx5e_free_xdpsq_descs(sq); 1868 mlx5e_free_xdpsq(sq); 1869 } 1870 1871 static int mlx5e_alloc_cq_common(struct mlx5e_priv *priv, 1872 struct mlx5e_cq_param *param, 1873 struct mlx5e_cq *cq) 1874 { 1875 struct mlx5_core_dev *mdev = priv->mdev; 1876 struct mlx5_core_cq *mcq = &cq->mcq; 1877 int err; 1878 u32 i; 1879 1880 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, 1881 &cq->wq_ctrl); 1882 if (err) 1883 return err; 1884 1885 mcq->cqe_sz = 64; 1886 mcq->set_ci_db = cq->wq_ctrl.db.db; 1887 mcq->arm_db = cq->wq_ctrl.db.db + 1; 1888 *mcq->set_ci_db = 0; 1889 *mcq->arm_db = 0; 1890 mcq->vector = param->eq_ix; 1891 mcq->comp = mlx5e_completion_event; 1892 mcq->event = mlx5e_cq_error_event; 1893 1894 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) { 1895 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i); 1896 1897 cqe->op_own = 0xf1; 1898 } 1899 1900 cq->mdev = mdev; 1901 cq->netdev = priv->netdev; 1902 cq->priv = priv; 1903 1904 return 0; 1905 } 1906 1907 static int mlx5e_alloc_cq(struct mlx5e_priv *priv, 1908 struct mlx5e_cq_param *param, 1909 struct mlx5e_create_cq_param *ccp, 1910 struct mlx5e_cq *cq) 1911 { 1912 int err; 1913 1914 param->wq.buf_numa_node = ccp->node; 1915 param->wq.db_numa_node = ccp->node; 1916 param->eq_ix = ccp->ix; 1917 1918 err = mlx5e_alloc_cq_common(priv, param, cq); 1919 1920 cq->napi = ccp->napi; 1921 cq->ch_stats = ccp->ch_stats; 1922 1923 return err; 1924 } 1925 1926 static void mlx5e_free_cq(struct mlx5e_cq *cq) 1927 { 1928 mlx5_wq_destroy(&cq->wq_ctrl); 1929 } 1930 1931 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param) 1932 { 1933 u32 out[MLX5_ST_SZ_DW(create_cq_out)]; 1934 struct mlx5_core_dev *mdev = cq->mdev; 1935 struct mlx5_core_cq *mcq = &cq->mcq; 1936 1937 void *in; 1938 void *cqc; 1939 int inlen; 1940 int eqn; 1941 int err; 1942 1943 err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn); 1944 if (err) 1945 return err; 1946 1947 inlen = MLX5_ST_SZ_BYTES(create_cq_in) + 1948 sizeof(u64) * cq->wq_ctrl.buf.npages; 1949 in = kvzalloc(inlen, GFP_KERNEL); 1950 if (!in) 1951 return -ENOMEM; 1952 1953 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1954 1955 memcpy(cqc, param->cqc, sizeof(param->cqc)); 1956 1957 mlx5_fill_page_frag_array(&cq->wq_ctrl.buf, 1958 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas)); 1959 1960 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode); 1961 MLX5_SET(cqc, cqc, c_eqn_or_apu_element, eqn); 1962 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index); 1963 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - 1964 MLX5_ADAPTER_PAGE_SHIFT); 1965 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); 1966 1967 err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out)); 1968 1969 kvfree(in); 1970 1971 if (err) 1972 return err; 1973 1974 mlx5e_cq_arm(cq); 1975 1976 return 0; 1977 } 1978 1979 static void mlx5e_destroy_cq(struct mlx5e_cq *cq) 1980 { 1981 mlx5_core_destroy_cq(cq->mdev, &cq->mcq); 1982 } 1983 1984 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder, 1985 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp, 1986 struct mlx5e_cq *cq) 1987 { 1988 struct mlx5_core_dev *mdev = priv->mdev; 1989 int err; 1990 1991 err = mlx5e_alloc_cq(priv, param, ccp, cq); 1992 if (err) 1993 return err; 1994 1995 err = mlx5e_create_cq(cq, param); 1996 if (err) 1997 goto err_free_cq; 1998 1999 if (MLX5_CAP_GEN(mdev, cq_moderation)) 2000 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts); 2001 return 0; 2002 2003 err_free_cq: 2004 mlx5e_free_cq(cq); 2005 2006 return err; 2007 } 2008 2009 void mlx5e_close_cq(struct mlx5e_cq *cq) 2010 { 2011 mlx5e_destroy_cq(cq); 2012 mlx5e_free_cq(cq); 2013 } 2014 2015 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c, 2016 struct mlx5e_params *params, 2017 struct mlx5e_create_cq_param *ccp, 2018 struct mlx5e_channel_param *cparam) 2019 { 2020 int err; 2021 int tc; 2022 2023 for (tc = 0; tc < c->num_tc; tc++) { 2024 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->txq_sq.cqp, 2025 ccp, &c->sq[tc].cq); 2026 if (err) 2027 goto err_close_tx_cqs; 2028 } 2029 2030 return 0; 2031 2032 err_close_tx_cqs: 2033 for (tc--; tc >= 0; tc--) 2034 mlx5e_close_cq(&c->sq[tc].cq); 2035 2036 return err; 2037 } 2038 2039 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c) 2040 { 2041 int tc; 2042 2043 for (tc = 0; tc < c->num_tc; tc++) 2044 mlx5e_close_cq(&c->sq[tc].cq); 2045 } 2046 2047 static int mlx5e_mqprio_txq_to_tc(struct netdev_tc_txq *tc_to_txq, unsigned int txq) 2048 { 2049 int tc; 2050 2051 for (tc = 0; tc < TC_MAX_QUEUE; tc++) 2052 if (txq - tc_to_txq[tc].offset < tc_to_txq[tc].count) 2053 return tc; 2054 2055 WARN(1, "Unexpected TCs configuration. No match found for txq %u", txq); 2056 return -ENOENT; 2057 } 2058 2059 static int mlx5e_txq_get_qos_node_hw_id(struct mlx5e_params *params, int txq_ix, 2060 u32 *hw_id) 2061 { 2062 int tc; 2063 2064 if (params->mqprio.mode != TC_MQPRIO_MODE_CHANNEL) { 2065 *hw_id = 0; 2066 return 0; 2067 } 2068 2069 tc = mlx5e_mqprio_txq_to_tc(params->mqprio.tc_to_txq, txq_ix); 2070 if (tc < 0) 2071 return tc; 2072 2073 if (tc >= params->mqprio.num_tc) { 2074 WARN(1, "Unexpected TCs configuration. tc %d is out of range of %u", 2075 tc, params->mqprio.num_tc); 2076 return -EINVAL; 2077 } 2078 2079 *hw_id = params->mqprio.channel.hw_id[tc]; 2080 return 0; 2081 } 2082 2083 static int mlx5e_open_sqs(struct mlx5e_channel *c, 2084 struct mlx5e_params *params, 2085 struct mlx5e_channel_param *cparam) 2086 { 2087 int err, tc; 2088 2089 for (tc = 0; tc < mlx5e_get_dcb_num_tc(params); tc++) { 2090 int txq_ix = c->ix + tc * params->num_channels; 2091 u32 qos_queue_group_id; 2092 2093 err = mlx5e_txq_get_qos_node_hw_id(params, txq_ix, &qos_queue_group_id); 2094 if (err) 2095 goto err_close_sqs; 2096 2097 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix, 2098 params, &cparam->txq_sq, &c->sq[tc], tc, 2099 qos_queue_group_id, 2100 &c->priv->channel_stats[c->ix]->sq[tc]); 2101 if (err) 2102 goto err_close_sqs; 2103 } 2104 2105 return 0; 2106 2107 err_close_sqs: 2108 for (tc--; tc >= 0; tc--) 2109 mlx5e_close_txqsq(&c->sq[tc]); 2110 2111 return err; 2112 } 2113 2114 static void mlx5e_close_sqs(struct mlx5e_channel *c) 2115 { 2116 int tc; 2117 2118 for (tc = 0; tc < c->num_tc; tc++) 2119 mlx5e_close_txqsq(&c->sq[tc]); 2120 } 2121 2122 static int mlx5e_set_sq_maxrate(struct net_device *dev, 2123 struct mlx5e_txqsq *sq, u32 rate) 2124 { 2125 struct mlx5e_priv *priv = netdev_priv(dev); 2126 struct mlx5_core_dev *mdev = priv->mdev; 2127 struct mlx5e_modify_sq_param msp = {0}; 2128 struct mlx5_rate_limit rl = {0}; 2129 u16 rl_index = 0; 2130 int err; 2131 2132 if (rate == sq->rate_limit) 2133 /* nothing to do */ 2134 return 0; 2135 2136 if (sq->rate_limit) { 2137 rl.rate = sq->rate_limit; 2138 /* remove current rl index to free space to next ones */ 2139 mlx5_rl_remove_rate(mdev, &rl); 2140 } 2141 2142 sq->rate_limit = 0; 2143 2144 if (rate) { 2145 rl.rate = rate; 2146 err = mlx5_rl_add_rate(mdev, &rl_index, &rl); 2147 if (err) { 2148 netdev_err(dev, "Failed configuring rate %u: %d\n", 2149 rate, err); 2150 return err; 2151 } 2152 } 2153 2154 msp.curr_state = MLX5_SQC_STATE_RDY; 2155 msp.next_state = MLX5_SQC_STATE_RDY; 2156 msp.rl_index = rl_index; 2157 msp.rl_update = true; 2158 err = mlx5e_modify_sq(mdev, sq->sqn, &msp); 2159 if (err) { 2160 netdev_err(dev, "Failed configuring rate %u: %d\n", 2161 rate, err); 2162 /* remove the rate from the table */ 2163 if (rate) 2164 mlx5_rl_remove_rate(mdev, &rl); 2165 return err; 2166 } 2167 2168 sq->rate_limit = rate; 2169 return 0; 2170 } 2171 2172 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate) 2173 { 2174 struct mlx5e_priv *priv = netdev_priv(dev); 2175 struct mlx5_core_dev *mdev = priv->mdev; 2176 struct mlx5e_txqsq *sq = priv->txq2sq[index]; 2177 int err = 0; 2178 2179 if (!mlx5_rl_is_supported(mdev)) { 2180 netdev_err(dev, "Rate limiting is not supported on this device\n"); 2181 return -EINVAL; 2182 } 2183 2184 /* rate is given in Mb/sec, HW config is in Kb/sec */ 2185 rate = rate << 10; 2186 2187 /* Check whether rate in valid range, 0 is always valid */ 2188 if (rate && !mlx5_rl_is_in_range(mdev, rate)) { 2189 netdev_err(dev, "TX rate %u, is not in range\n", rate); 2190 return -ERANGE; 2191 } 2192 2193 mutex_lock(&priv->state_lock); 2194 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) 2195 err = mlx5e_set_sq_maxrate(dev, sq, rate); 2196 if (!err) 2197 priv->tx_rates[index] = rate; 2198 mutex_unlock(&priv->state_lock); 2199 2200 return err; 2201 } 2202 2203 static int mlx5e_open_rxq_rq(struct mlx5e_channel *c, struct mlx5e_params *params, 2204 struct mlx5e_rq_param *rq_params) 2205 { 2206 int err; 2207 2208 err = mlx5e_init_rxq_rq(c, params, &c->rq); 2209 if (err) 2210 return err; 2211 2212 return mlx5e_open_rq(params, rq_params, NULL, cpu_to_node(c->cpu), &c->rq); 2213 } 2214 2215 static int mlx5e_open_queues(struct mlx5e_channel *c, 2216 struct mlx5e_params *params, 2217 struct mlx5e_channel_param *cparam) 2218 { 2219 struct dim_cq_moder icocq_moder = {0, 0}; 2220 struct mlx5e_create_cq_param ccp; 2221 int err; 2222 2223 mlx5e_build_create_cq_param(&ccp, c); 2224 2225 err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->async_icosq.cqp, &ccp, 2226 &c->async_icosq.cq); 2227 if (err) 2228 return err; 2229 2230 err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->icosq.cqp, &ccp, 2231 &c->icosq.cq); 2232 if (err) 2233 goto err_close_async_icosq_cq; 2234 2235 err = mlx5e_open_tx_cqs(c, params, &ccp, cparam); 2236 if (err) 2237 goto err_close_icosq_cq; 2238 2239 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp, &ccp, 2240 &c->xdpsq.cq); 2241 if (err) 2242 goto err_close_tx_cqs; 2243 2244 err = mlx5e_open_cq(c->priv, params->rx_cq_moderation, &cparam->rq.cqp, &ccp, 2245 &c->rq.cq); 2246 if (err) 2247 goto err_close_xdp_tx_cqs; 2248 2249 err = c->xdp ? mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp, 2250 &ccp, &c->rq_xdpsq.cq) : 0; 2251 if (err) 2252 goto err_close_rx_cq; 2253 2254 spin_lock_init(&c->async_icosq_lock); 2255 2256 err = mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq, 2257 mlx5e_async_icosq_err_cqe_work); 2258 if (err) 2259 goto err_close_xdpsq_cq; 2260 2261 mutex_init(&c->icosq_recovery_lock); 2262 2263 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq, 2264 mlx5e_icosq_err_cqe_work); 2265 if (err) 2266 goto err_close_async_icosq; 2267 2268 err = mlx5e_open_sqs(c, params, cparam); 2269 if (err) 2270 goto err_close_icosq; 2271 2272 err = mlx5e_open_rxq_rq(c, params, &cparam->rq); 2273 if (err) 2274 goto err_close_sqs; 2275 2276 if (c->xdp) { 2277 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, 2278 &c->rq_xdpsq, false); 2279 if (err) 2280 goto err_close_rq; 2281 } 2282 2283 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true); 2284 if (err) 2285 goto err_close_xdp_sq; 2286 2287 return 0; 2288 2289 err_close_xdp_sq: 2290 if (c->xdp) 2291 mlx5e_close_xdpsq(&c->rq_xdpsq); 2292 2293 err_close_rq: 2294 mlx5e_close_rq(&c->rq); 2295 2296 err_close_sqs: 2297 mlx5e_close_sqs(c); 2298 2299 err_close_icosq: 2300 mlx5e_close_icosq(&c->icosq); 2301 2302 err_close_async_icosq: 2303 mlx5e_close_icosq(&c->async_icosq); 2304 2305 err_close_xdpsq_cq: 2306 if (c->xdp) 2307 mlx5e_close_cq(&c->rq_xdpsq.cq); 2308 2309 err_close_rx_cq: 2310 mlx5e_close_cq(&c->rq.cq); 2311 2312 err_close_xdp_tx_cqs: 2313 mlx5e_close_cq(&c->xdpsq.cq); 2314 2315 err_close_tx_cqs: 2316 mlx5e_close_tx_cqs(c); 2317 2318 err_close_icosq_cq: 2319 mlx5e_close_cq(&c->icosq.cq); 2320 2321 err_close_async_icosq_cq: 2322 mlx5e_close_cq(&c->async_icosq.cq); 2323 2324 return err; 2325 } 2326 2327 static void mlx5e_close_queues(struct mlx5e_channel *c) 2328 { 2329 mlx5e_close_xdpsq(&c->xdpsq); 2330 if (c->xdp) 2331 mlx5e_close_xdpsq(&c->rq_xdpsq); 2332 /* The same ICOSQ is used for UMRs for both RQ and XSKRQ. */ 2333 cancel_work_sync(&c->icosq.recover_work); 2334 mlx5e_close_rq(&c->rq); 2335 mlx5e_close_sqs(c); 2336 mlx5e_close_icosq(&c->icosq); 2337 mutex_destroy(&c->icosq_recovery_lock); 2338 mlx5e_close_icosq(&c->async_icosq); 2339 if (c->xdp) 2340 mlx5e_close_cq(&c->rq_xdpsq.cq); 2341 mlx5e_close_cq(&c->rq.cq); 2342 mlx5e_close_cq(&c->xdpsq.cq); 2343 mlx5e_close_tx_cqs(c); 2344 mlx5e_close_cq(&c->icosq.cq); 2345 mlx5e_close_cq(&c->async_icosq.cq); 2346 } 2347 2348 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix) 2349 { 2350 u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id); 2351 2352 return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev); 2353 } 2354 2355 static int mlx5e_channel_stats_alloc(struct mlx5e_priv *priv, int ix, int cpu) 2356 { 2357 if (ix > priv->stats_nch) { 2358 netdev_warn(priv->netdev, "Unexpected channel stats index %d > %d\n", ix, 2359 priv->stats_nch); 2360 return -EINVAL; 2361 } 2362 2363 if (priv->channel_stats[ix]) 2364 return 0; 2365 2366 /* Asymmetric dynamic memory allocation. 2367 * Freed in mlx5e_priv_arrays_free, not on channel closure. 2368 */ 2369 mlx5e_dbg(DRV, priv, "Creating channel stats %d\n", ix); 2370 priv->channel_stats[ix] = kvzalloc_node(sizeof(**priv->channel_stats), 2371 GFP_KERNEL, cpu_to_node(cpu)); 2372 if (!priv->channel_stats[ix]) 2373 return -ENOMEM; 2374 priv->stats_nch++; 2375 2376 return 0; 2377 } 2378 2379 void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c) 2380 { 2381 spin_lock_bh(&c->async_icosq_lock); 2382 mlx5e_trigger_irq(&c->async_icosq); 2383 spin_unlock_bh(&c->async_icosq_lock); 2384 } 2385 2386 void mlx5e_trigger_napi_sched(struct napi_struct *napi) 2387 { 2388 local_bh_disable(); 2389 napi_schedule(napi); 2390 local_bh_enable(); 2391 } 2392 2393 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix, 2394 struct mlx5e_params *params, 2395 struct mlx5e_channel_param *cparam, 2396 struct xsk_buff_pool *xsk_pool, 2397 struct mlx5e_channel **cp) 2398 { 2399 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix)); 2400 struct net_device *netdev = priv->netdev; 2401 struct mlx5e_xsk_param xsk; 2402 struct mlx5e_channel *c; 2403 unsigned int irq; 2404 int err; 2405 2406 err = mlx5_vector2irqn(priv->mdev, ix, &irq); 2407 if (err) 2408 return err; 2409 2410 err = mlx5e_channel_stats_alloc(priv, ix, cpu); 2411 if (err) 2412 return err; 2413 2414 c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu)); 2415 if (!c) 2416 return -ENOMEM; 2417 2418 c->priv = priv; 2419 c->mdev = priv->mdev; 2420 c->tstamp = &priv->tstamp; 2421 c->ix = ix; 2422 c->cpu = cpu; 2423 c->pdev = mlx5_core_dma_dev(priv->mdev); 2424 c->netdev = priv->netdev; 2425 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.hw_objs.mkey); 2426 c->num_tc = mlx5e_get_dcb_num_tc(params); 2427 c->xdp = !!params->xdp_prog; 2428 c->stats = &priv->channel_stats[ix]->ch; 2429 c->aff_mask = irq_get_effective_affinity_mask(irq); 2430 c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix); 2431 2432 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll); 2433 2434 err = mlx5e_open_queues(c, params, cparam); 2435 if (unlikely(err)) 2436 goto err_napi_del; 2437 2438 if (xsk_pool) { 2439 mlx5e_build_xsk_param(xsk_pool, &xsk); 2440 err = mlx5e_open_xsk(priv, params, &xsk, xsk_pool, c); 2441 if (unlikely(err)) 2442 goto err_close_queues; 2443 } 2444 2445 *cp = c; 2446 2447 return 0; 2448 2449 err_close_queues: 2450 mlx5e_close_queues(c); 2451 2452 err_napi_del: 2453 netif_napi_del(&c->napi); 2454 2455 kvfree(c); 2456 2457 return err; 2458 } 2459 2460 static void mlx5e_activate_channel(struct mlx5e_channel *c) 2461 { 2462 int tc; 2463 2464 napi_enable(&c->napi); 2465 2466 for (tc = 0; tc < c->num_tc; tc++) 2467 mlx5e_activate_txqsq(&c->sq[tc]); 2468 mlx5e_activate_icosq(&c->icosq); 2469 mlx5e_activate_icosq(&c->async_icosq); 2470 2471 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) 2472 mlx5e_activate_xsk(c); 2473 else 2474 mlx5e_activate_rq(&c->rq); 2475 2476 mlx5e_trigger_napi_icosq(c); 2477 } 2478 2479 static void mlx5e_deactivate_channel(struct mlx5e_channel *c) 2480 { 2481 int tc; 2482 2483 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) 2484 mlx5e_deactivate_xsk(c); 2485 else 2486 mlx5e_deactivate_rq(&c->rq); 2487 2488 mlx5e_deactivate_icosq(&c->async_icosq); 2489 mlx5e_deactivate_icosq(&c->icosq); 2490 for (tc = 0; tc < c->num_tc; tc++) 2491 mlx5e_deactivate_txqsq(&c->sq[tc]); 2492 mlx5e_qos_deactivate_queues(c); 2493 2494 napi_disable(&c->napi); 2495 } 2496 2497 static void mlx5e_close_channel(struct mlx5e_channel *c) 2498 { 2499 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) 2500 mlx5e_close_xsk(c); 2501 mlx5e_close_queues(c); 2502 mlx5e_qos_close_queues(c); 2503 netif_napi_del(&c->napi); 2504 2505 kvfree(c); 2506 } 2507 2508 int mlx5e_open_channels(struct mlx5e_priv *priv, 2509 struct mlx5e_channels *chs) 2510 { 2511 struct mlx5e_channel_param *cparam; 2512 int err = -ENOMEM; 2513 int i; 2514 2515 chs->num = chs->params.num_channels; 2516 2517 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL); 2518 cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL); 2519 if (!chs->c || !cparam) 2520 goto err_free; 2521 2522 err = mlx5e_build_channel_param(priv->mdev, &chs->params, priv->q_counter, cparam); 2523 if (err) 2524 goto err_free; 2525 2526 for (i = 0; i < chs->num; i++) { 2527 struct xsk_buff_pool *xsk_pool = NULL; 2528 2529 if (chs->params.xdp_prog) 2530 xsk_pool = mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, i); 2531 2532 err = mlx5e_open_channel(priv, i, &chs->params, cparam, xsk_pool, &chs->c[i]); 2533 if (err) 2534 goto err_close_channels; 2535 } 2536 2537 if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS) || chs->params.ptp_rx) { 2538 err = mlx5e_ptp_open(priv, &chs->params, chs->c[0]->lag_port, &chs->ptp); 2539 if (err) 2540 goto err_close_channels; 2541 } 2542 2543 if (priv->htb) { 2544 err = mlx5e_qos_open_queues(priv, chs); 2545 if (err) 2546 goto err_close_ptp; 2547 } 2548 2549 mlx5e_health_channels_update(priv); 2550 kvfree(cparam); 2551 return 0; 2552 2553 err_close_ptp: 2554 if (chs->ptp) 2555 mlx5e_ptp_close(chs->ptp); 2556 2557 err_close_channels: 2558 for (i--; i >= 0; i--) 2559 mlx5e_close_channel(chs->c[i]); 2560 2561 err_free: 2562 kfree(chs->c); 2563 kvfree(cparam); 2564 chs->num = 0; 2565 return err; 2566 } 2567 2568 static void mlx5e_activate_channels(struct mlx5e_channels *chs) 2569 { 2570 int i; 2571 2572 for (i = 0; i < chs->num; i++) 2573 mlx5e_activate_channel(chs->c[i]); 2574 2575 if (chs->ptp) 2576 mlx5e_ptp_activate_channel(chs->ptp); 2577 } 2578 2579 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs) 2580 { 2581 int err = 0; 2582 int i; 2583 2584 for (i = 0; i < chs->num; i++) { 2585 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT; 2586 struct mlx5e_channel *c = chs->c[i]; 2587 2588 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) 2589 continue; 2590 2591 err |= mlx5e_wait_for_min_rx_wqes(&c->rq, timeout); 2592 2593 /* Don't wait on the XSK RQ, because the newer xdpsock sample 2594 * doesn't provide any Fill Ring entries at the setup stage. 2595 */ 2596 } 2597 2598 return err ? -ETIMEDOUT : 0; 2599 } 2600 2601 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs) 2602 { 2603 int i; 2604 2605 if (chs->ptp) 2606 mlx5e_ptp_deactivate_channel(chs->ptp); 2607 2608 for (i = 0; i < chs->num; i++) 2609 mlx5e_deactivate_channel(chs->c[i]); 2610 } 2611 2612 void mlx5e_close_channels(struct mlx5e_channels *chs) 2613 { 2614 int i; 2615 2616 if (chs->ptp) { 2617 mlx5e_ptp_close(chs->ptp); 2618 chs->ptp = NULL; 2619 } 2620 for (i = 0; i < chs->num; i++) 2621 mlx5e_close_channel(chs->c[i]); 2622 2623 kfree(chs->c); 2624 chs->num = 0; 2625 } 2626 2627 static int mlx5e_modify_tirs_packet_merge(struct mlx5e_priv *priv) 2628 { 2629 struct mlx5e_rx_res *res = priv->rx_res; 2630 2631 return mlx5e_rx_res_packet_merge_set_param(res, &priv->channels.params.packet_merge); 2632 } 2633 2634 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_packet_merge); 2635 2636 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev, 2637 struct mlx5e_params *params, u16 mtu) 2638 { 2639 u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu); 2640 int err; 2641 2642 err = mlx5_set_port_mtu(mdev, hw_mtu, 1); 2643 if (err) 2644 return err; 2645 2646 /* Update vport context MTU */ 2647 mlx5_modify_nic_vport_mtu(mdev, hw_mtu); 2648 return 0; 2649 } 2650 2651 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev, 2652 struct mlx5e_params *params, u16 *mtu) 2653 { 2654 u16 hw_mtu = 0; 2655 int err; 2656 2657 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu); 2658 if (err || !hw_mtu) /* fallback to port oper mtu */ 2659 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1); 2660 2661 *mtu = MLX5E_HW2SW_MTU(params, hw_mtu); 2662 } 2663 2664 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv) 2665 { 2666 struct mlx5e_params *params = &priv->channels.params; 2667 struct net_device *netdev = priv->netdev; 2668 struct mlx5_core_dev *mdev = priv->mdev; 2669 u16 mtu; 2670 int err; 2671 2672 err = mlx5e_set_mtu(mdev, params, params->sw_mtu); 2673 if (err) 2674 return err; 2675 2676 mlx5e_query_mtu(mdev, params, &mtu); 2677 if (mtu != params->sw_mtu) 2678 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n", 2679 __func__, mtu, params->sw_mtu); 2680 2681 params->sw_mtu = mtu; 2682 return 0; 2683 } 2684 2685 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu); 2686 2687 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv) 2688 { 2689 struct mlx5e_params *params = &priv->channels.params; 2690 struct net_device *netdev = priv->netdev; 2691 struct mlx5_core_dev *mdev = priv->mdev; 2692 u16 max_mtu; 2693 2694 /* MTU range: 68 - hw-specific max */ 2695 netdev->min_mtu = ETH_MIN_MTU; 2696 2697 mlx5_query_port_max_mtu(mdev, &max_mtu, 1); 2698 netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu), 2699 ETH_MAX_MTU); 2700 } 2701 2702 static int mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc, 2703 struct netdev_tc_txq *tc_to_txq) 2704 { 2705 int tc, err; 2706 2707 netdev_reset_tc(netdev); 2708 2709 if (ntc == 1) 2710 return 0; 2711 2712 err = netdev_set_num_tc(netdev, ntc); 2713 if (err) { 2714 netdev_WARN(netdev, "netdev_set_num_tc failed (%d), ntc = %d\n", err, ntc); 2715 return err; 2716 } 2717 2718 for (tc = 0; tc < ntc; tc++) { 2719 u16 count, offset; 2720 2721 count = tc_to_txq[tc].count; 2722 offset = tc_to_txq[tc].offset; 2723 netdev_set_tc_queue(netdev, tc, count, offset); 2724 } 2725 2726 return 0; 2727 } 2728 2729 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv) 2730 { 2731 int nch, ntc, num_txqs, err; 2732 int qos_queues = 0; 2733 2734 if (priv->htb) 2735 qos_queues = mlx5e_htb_cur_leaf_nodes(priv->htb); 2736 2737 nch = priv->channels.params.num_channels; 2738 ntc = mlx5e_get_dcb_num_tc(&priv->channels.params); 2739 num_txqs = nch * ntc + qos_queues; 2740 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_PORT_TS)) 2741 num_txqs += ntc; 2742 2743 mlx5e_dbg(DRV, priv, "Setting num_txqs %d\n", num_txqs); 2744 err = netif_set_real_num_tx_queues(priv->netdev, num_txqs); 2745 if (err) 2746 netdev_warn(priv->netdev, "netif_set_real_num_tx_queues failed, %d\n", err); 2747 2748 return err; 2749 } 2750 2751 static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv) 2752 { 2753 struct netdev_tc_txq old_tc_to_txq[TC_MAX_QUEUE], *tc_to_txq; 2754 struct net_device *netdev = priv->netdev; 2755 int old_num_txqs, old_ntc; 2756 int nch, ntc; 2757 int err; 2758 int i; 2759 2760 old_num_txqs = netdev->real_num_tx_queues; 2761 old_ntc = netdev->num_tc ? : 1; 2762 for (i = 0; i < ARRAY_SIZE(old_tc_to_txq); i++) 2763 old_tc_to_txq[i] = netdev->tc_to_txq[i]; 2764 2765 nch = priv->channels.params.num_channels; 2766 ntc = priv->channels.params.mqprio.num_tc; 2767 tc_to_txq = priv->channels.params.mqprio.tc_to_txq; 2768 2769 err = mlx5e_netdev_set_tcs(netdev, nch, ntc, tc_to_txq); 2770 if (err) 2771 goto err_out; 2772 err = mlx5e_update_tx_netdev_queues(priv); 2773 if (err) 2774 goto err_tcs; 2775 err = netif_set_real_num_rx_queues(netdev, nch); 2776 if (err) { 2777 netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err); 2778 goto err_txqs; 2779 } 2780 2781 return 0; 2782 2783 err_txqs: 2784 /* netif_set_real_num_rx_queues could fail only when nch increased. Only 2785 * one of nch and ntc is changed in this function. That means, the call 2786 * to netif_set_real_num_tx_queues below should not fail, because it 2787 * decreases the number of TX queues. 2788 */ 2789 WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs)); 2790 2791 err_tcs: 2792 WARN_ON_ONCE(mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc, 2793 old_tc_to_txq)); 2794 err_out: 2795 return err; 2796 } 2797 2798 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_update_netdev_queues); 2799 2800 static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv, 2801 struct mlx5e_params *params) 2802 { 2803 struct mlx5_core_dev *mdev = priv->mdev; 2804 int num_comp_vectors, ix, irq; 2805 2806 num_comp_vectors = mlx5_comp_vectors_count(mdev); 2807 2808 for (ix = 0; ix < params->num_channels; ix++) { 2809 cpumask_clear(priv->scratchpad.cpumask); 2810 2811 for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) { 2812 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(mdev, irq)); 2813 2814 cpumask_set_cpu(cpu, priv->scratchpad.cpumask); 2815 } 2816 2817 netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix); 2818 } 2819 } 2820 2821 static int mlx5e_num_channels_changed(struct mlx5e_priv *priv) 2822 { 2823 u16 count = priv->channels.params.num_channels; 2824 int err; 2825 2826 err = mlx5e_update_netdev_queues(priv); 2827 if (err) 2828 return err; 2829 2830 mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params); 2831 2832 /* This function may be called on attach, before priv->rx_res is created. */ 2833 if (!netif_is_rxfh_configured(priv->netdev) && priv->rx_res) 2834 mlx5e_rx_res_rss_set_indir_uniform(priv->rx_res, count); 2835 2836 return 0; 2837 } 2838 2839 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed); 2840 2841 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv) 2842 { 2843 int i, ch, tc, num_tc; 2844 2845 ch = priv->channels.num; 2846 num_tc = mlx5e_get_dcb_num_tc(&priv->channels.params); 2847 2848 for (i = 0; i < ch; i++) { 2849 for (tc = 0; tc < num_tc; tc++) { 2850 struct mlx5e_channel *c = priv->channels.c[i]; 2851 struct mlx5e_txqsq *sq = &c->sq[tc]; 2852 2853 priv->txq2sq[sq->txq_ix] = sq; 2854 } 2855 } 2856 2857 if (!priv->channels.ptp) 2858 goto out; 2859 2860 if (!test_bit(MLX5E_PTP_STATE_TX, priv->channels.ptp->state)) 2861 goto out; 2862 2863 for (tc = 0; tc < num_tc; tc++) { 2864 struct mlx5e_ptp *c = priv->channels.ptp; 2865 struct mlx5e_txqsq *sq = &c->ptpsq[tc].txqsq; 2866 2867 priv->txq2sq[sq->txq_ix] = sq; 2868 } 2869 2870 out: 2871 /* Make the change to txq2sq visible before the queue is started. 2872 * As mlx5e_xmit runs under a spinlock, there is an implicit ACQUIRE, 2873 * which pairs with this barrier. 2874 */ 2875 smp_wmb(); 2876 } 2877 2878 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv) 2879 { 2880 mlx5e_build_txq_maps(priv); 2881 mlx5e_activate_channels(&priv->channels); 2882 if (priv->htb) 2883 mlx5e_qos_activate_queues(priv); 2884 mlx5e_xdp_tx_enable(priv); 2885 2886 /* dev_watchdog() wants all TX queues to be started when the carrier is 2887 * OK, including the ones in range real_num_tx_queues..num_tx_queues-1. 2888 * Make it happy to avoid TX timeout false alarms. 2889 */ 2890 netif_tx_start_all_queues(priv->netdev); 2891 2892 if (mlx5e_is_vport_rep(priv)) 2893 mlx5e_rep_activate_channels(priv); 2894 2895 mlx5e_wait_channels_min_rx_wqes(&priv->channels); 2896 2897 if (priv->rx_res) 2898 mlx5e_rx_res_channels_activate(priv->rx_res, &priv->channels); 2899 } 2900 2901 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv) 2902 { 2903 if (priv->rx_res) 2904 mlx5e_rx_res_channels_deactivate(priv->rx_res); 2905 2906 if (mlx5e_is_vport_rep(priv)) 2907 mlx5e_rep_deactivate_channels(priv); 2908 2909 /* The results of ndo_select_queue are unreliable, while netdev config 2910 * is being changed (real_num_tx_queues, num_tc). Stop all queues to 2911 * prevent ndo_start_xmit from being called, so that it can assume that 2912 * the selected queue is always valid. 2913 */ 2914 netif_tx_disable(priv->netdev); 2915 2916 mlx5e_xdp_tx_disable(priv); 2917 mlx5e_deactivate_channels(&priv->channels); 2918 } 2919 2920 static int mlx5e_switch_priv_params(struct mlx5e_priv *priv, 2921 struct mlx5e_params *new_params, 2922 mlx5e_fp_preactivate preactivate, 2923 void *context) 2924 { 2925 struct mlx5e_params old_params; 2926 2927 old_params = priv->channels.params; 2928 priv->channels.params = *new_params; 2929 2930 if (preactivate) { 2931 int err; 2932 2933 err = preactivate(priv, context); 2934 if (err) { 2935 priv->channels.params = old_params; 2936 return err; 2937 } 2938 } 2939 2940 return 0; 2941 } 2942 2943 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv, 2944 struct mlx5e_channels *new_chs, 2945 mlx5e_fp_preactivate preactivate, 2946 void *context) 2947 { 2948 struct net_device *netdev = priv->netdev; 2949 struct mlx5e_channels old_chs; 2950 int carrier_ok; 2951 int err = 0; 2952 2953 carrier_ok = netif_carrier_ok(netdev); 2954 netif_carrier_off(netdev); 2955 2956 mlx5e_deactivate_priv_channels(priv); 2957 2958 old_chs = priv->channels; 2959 priv->channels = *new_chs; 2960 2961 /* New channels are ready to roll, call the preactivate hook if needed 2962 * to modify HW settings or update kernel parameters. 2963 */ 2964 if (preactivate) { 2965 err = preactivate(priv, context); 2966 if (err) { 2967 priv->channels = old_chs; 2968 goto out; 2969 } 2970 } 2971 2972 mlx5e_close_channels(&old_chs); 2973 priv->profile->update_rx(priv); 2974 2975 mlx5e_selq_apply(&priv->selq); 2976 out: 2977 mlx5e_activate_priv_channels(priv); 2978 2979 /* return carrier back if needed */ 2980 if (carrier_ok) 2981 netif_carrier_on(netdev); 2982 2983 return err; 2984 } 2985 2986 int mlx5e_safe_switch_params(struct mlx5e_priv *priv, 2987 struct mlx5e_params *params, 2988 mlx5e_fp_preactivate preactivate, 2989 void *context, bool reset) 2990 { 2991 struct mlx5e_channels new_chs = {}; 2992 int err; 2993 2994 reset &= test_bit(MLX5E_STATE_OPENED, &priv->state); 2995 if (!reset) 2996 return mlx5e_switch_priv_params(priv, params, preactivate, context); 2997 2998 new_chs.params = *params; 2999 3000 mlx5e_selq_prepare_params(&priv->selq, &new_chs.params); 3001 3002 err = mlx5e_open_channels(priv, &new_chs); 3003 if (err) 3004 goto err_cancel_selq; 3005 3006 err = mlx5e_switch_priv_channels(priv, &new_chs, preactivate, context); 3007 if (err) 3008 goto err_close; 3009 3010 return 0; 3011 3012 err_close: 3013 mlx5e_close_channels(&new_chs); 3014 3015 err_cancel_selq: 3016 mlx5e_selq_cancel(&priv->selq); 3017 return err; 3018 } 3019 3020 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv) 3021 { 3022 return mlx5e_safe_switch_params(priv, &priv->channels.params, NULL, NULL, true); 3023 } 3024 3025 void mlx5e_timestamp_init(struct mlx5e_priv *priv) 3026 { 3027 priv->tstamp.tx_type = HWTSTAMP_TX_OFF; 3028 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE; 3029 } 3030 3031 static void mlx5e_modify_admin_state(struct mlx5_core_dev *mdev, 3032 enum mlx5_port_status state) 3033 { 3034 struct mlx5_eswitch *esw = mdev->priv.eswitch; 3035 int vport_admin_state; 3036 3037 mlx5_set_port_admin_status(mdev, state); 3038 3039 if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS || 3040 !MLX5_CAP_GEN(mdev, uplink_follow)) 3041 return; 3042 3043 if (state == MLX5_PORT_UP) 3044 vport_admin_state = MLX5_VPORT_ADMIN_STATE_AUTO; 3045 else 3046 vport_admin_state = MLX5_VPORT_ADMIN_STATE_DOWN; 3047 3048 mlx5_eswitch_set_vport_state(esw, MLX5_VPORT_UPLINK, vport_admin_state); 3049 } 3050 3051 int mlx5e_open_locked(struct net_device *netdev) 3052 { 3053 struct mlx5e_priv *priv = netdev_priv(netdev); 3054 int err; 3055 3056 mlx5e_selq_prepare_params(&priv->selq, &priv->channels.params); 3057 3058 set_bit(MLX5E_STATE_OPENED, &priv->state); 3059 3060 err = mlx5e_open_channels(priv, &priv->channels); 3061 if (err) 3062 goto err_clear_state_opened_flag; 3063 3064 priv->profile->update_rx(priv); 3065 mlx5e_selq_apply(&priv->selq); 3066 mlx5e_activate_priv_channels(priv); 3067 mlx5e_apply_traps(priv, true); 3068 if (priv->profile->update_carrier) 3069 priv->profile->update_carrier(priv); 3070 3071 mlx5e_queue_update_stats(priv); 3072 return 0; 3073 3074 err_clear_state_opened_flag: 3075 clear_bit(MLX5E_STATE_OPENED, &priv->state); 3076 mlx5e_selq_cancel(&priv->selq); 3077 return err; 3078 } 3079 3080 int mlx5e_open(struct net_device *netdev) 3081 { 3082 struct mlx5e_priv *priv = netdev_priv(netdev); 3083 int err; 3084 3085 mutex_lock(&priv->state_lock); 3086 err = mlx5e_open_locked(netdev); 3087 if (!err) 3088 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_UP); 3089 mutex_unlock(&priv->state_lock); 3090 3091 return err; 3092 } 3093 3094 int mlx5e_close_locked(struct net_device *netdev) 3095 { 3096 struct mlx5e_priv *priv = netdev_priv(netdev); 3097 3098 /* May already be CLOSED in case a previous configuration operation 3099 * (e.g RX/TX queue size change) that involves close&open failed. 3100 */ 3101 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) 3102 return 0; 3103 3104 mlx5e_apply_traps(priv, false); 3105 clear_bit(MLX5E_STATE_OPENED, &priv->state); 3106 3107 netif_carrier_off(priv->netdev); 3108 mlx5e_deactivate_priv_channels(priv); 3109 mlx5e_close_channels(&priv->channels); 3110 3111 return 0; 3112 } 3113 3114 int mlx5e_close(struct net_device *netdev) 3115 { 3116 struct mlx5e_priv *priv = netdev_priv(netdev); 3117 int err; 3118 3119 if (!netif_device_present(netdev)) 3120 return -ENODEV; 3121 3122 mutex_lock(&priv->state_lock); 3123 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_DOWN); 3124 err = mlx5e_close_locked(netdev); 3125 mutex_unlock(&priv->state_lock); 3126 3127 return err; 3128 } 3129 3130 static void mlx5e_free_drop_rq(struct mlx5e_rq *rq) 3131 { 3132 mlx5_wq_destroy(&rq->wq_ctrl); 3133 } 3134 3135 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev, 3136 struct mlx5e_rq *rq, 3137 struct mlx5e_rq_param *param) 3138 { 3139 void *rqc = param->rqc; 3140 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); 3141 int err; 3142 3143 param->wq.db_numa_node = param->wq.buf_numa_node; 3144 3145 err = mlx5_wq_cyc_create(mdev, ¶m->wq, rqc_wq, &rq->wqe.wq, 3146 &rq->wq_ctrl); 3147 if (err) 3148 return err; 3149 3150 /* Mark as unused given "Drop-RQ" packets never reach XDP */ 3151 xdp_rxq_info_unused(&rq->xdp_rxq); 3152 3153 rq->mdev = mdev; 3154 3155 return 0; 3156 } 3157 3158 static int mlx5e_alloc_drop_cq(struct mlx5e_priv *priv, 3159 struct mlx5e_cq *cq, 3160 struct mlx5e_cq_param *param) 3161 { 3162 struct mlx5_core_dev *mdev = priv->mdev; 3163 3164 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev)); 3165 param->wq.db_numa_node = dev_to_node(mlx5_core_dma_dev(mdev)); 3166 3167 return mlx5e_alloc_cq_common(priv, param, cq); 3168 } 3169 3170 int mlx5e_open_drop_rq(struct mlx5e_priv *priv, 3171 struct mlx5e_rq *drop_rq) 3172 { 3173 struct mlx5_core_dev *mdev = priv->mdev; 3174 struct mlx5e_cq_param cq_param = {}; 3175 struct mlx5e_rq_param rq_param = {}; 3176 struct mlx5e_cq *cq = &drop_rq->cq; 3177 int err; 3178 3179 mlx5e_build_drop_rq_param(mdev, priv->drop_rq_q_counter, &rq_param); 3180 3181 err = mlx5e_alloc_drop_cq(priv, cq, &cq_param); 3182 if (err) 3183 return err; 3184 3185 err = mlx5e_create_cq(cq, &cq_param); 3186 if (err) 3187 goto err_free_cq; 3188 3189 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param); 3190 if (err) 3191 goto err_destroy_cq; 3192 3193 err = mlx5e_create_rq(drop_rq, &rq_param); 3194 if (err) 3195 goto err_free_rq; 3196 3197 err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 3198 if (err) 3199 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err); 3200 3201 return 0; 3202 3203 err_free_rq: 3204 mlx5e_free_drop_rq(drop_rq); 3205 3206 err_destroy_cq: 3207 mlx5e_destroy_cq(cq); 3208 3209 err_free_cq: 3210 mlx5e_free_cq(cq); 3211 3212 return err; 3213 } 3214 3215 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq) 3216 { 3217 mlx5e_destroy_rq(drop_rq); 3218 mlx5e_free_drop_rq(drop_rq); 3219 mlx5e_destroy_cq(&drop_rq->cq); 3220 mlx5e_free_cq(&drop_rq->cq); 3221 } 3222 3223 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn) 3224 { 3225 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 3226 3227 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.hw_objs.td.tdn); 3228 3229 if (MLX5_GET(tisc, tisc, tls_en)) 3230 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.hw_objs.pdn); 3231 3232 if (mlx5_lag_is_lacp_owner(mdev)) 3233 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1); 3234 3235 return mlx5_core_create_tis(mdev, in, tisn); 3236 } 3237 3238 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn) 3239 { 3240 mlx5_core_destroy_tis(mdev, tisn); 3241 } 3242 3243 void mlx5e_destroy_tises(struct mlx5e_priv *priv) 3244 { 3245 int tc, i; 3246 3247 for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) 3248 for (tc = 0; tc < priv->profile->max_tc; tc++) 3249 mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]); 3250 } 3251 3252 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev) 3253 { 3254 return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1; 3255 } 3256 3257 int mlx5e_create_tises(struct mlx5e_priv *priv) 3258 { 3259 int tc, i; 3260 int err; 3261 3262 for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) { 3263 for (tc = 0; tc < priv->profile->max_tc; tc++) { 3264 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {}; 3265 void *tisc; 3266 3267 tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 3268 3269 MLX5_SET(tisc, tisc, prio, tc << 1); 3270 3271 if (mlx5e_lag_should_assign_affinity(priv->mdev)) 3272 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1); 3273 3274 err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]); 3275 if (err) 3276 goto err_close_tises; 3277 } 3278 } 3279 3280 return 0; 3281 3282 err_close_tises: 3283 for (; i >= 0; i--) { 3284 for (tc--; tc >= 0; tc--) 3285 mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]); 3286 tc = priv->profile->max_tc; 3287 } 3288 3289 return err; 3290 } 3291 3292 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv) 3293 { 3294 if (priv->mqprio_rl) { 3295 mlx5e_mqprio_rl_cleanup(priv->mqprio_rl); 3296 mlx5e_mqprio_rl_free(priv->mqprio_rl); 3297 priv->mqprio_rl = NULL; 3298 } 3299 mlx5e_accel_cleanup_tx(priv); 3300 mlx5e_destroy_tises(priv); 3301 } 3302 3303 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable) 3304 { 3305 int err = 0; 3306 int i; 3307 3308 for (i = 0; i < chs->num; i++) { 3309 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable); 3310 if (err) 3311 return err; 3312 } 3313 3314 return 0; 3315 } 3316 3317 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd) 3318 { 3319 int err; 3320 int i; 3321 3322 for (i = 0; i < chs->num; i++) { 3323 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd); 3324 if (err) 3325 return err; 3326 } 3327 if (chs->ptp && test_bit(MLX5E_PTP_STATE_RX, chs->ptp->state)) 3328 return mlx5e_modify_rq_vsd(&chs->ptp->rq, vsd); 3329 3330 return 0; 3331 } 3332 3333 static void mlx5e_mqprio_build_default_tc_to_txq(struct netdev_tc_txq *tc_to_txq, 3334 int ntc, int nch) 3335 { 3336 int tc; 3337 3338 memset(tc_to_txq, 0, sizeof(*tc_to_txq) * TC_MAX_QUEUE); 3339 3340 /* Map netdev TCs to offset 0. 3341 * We have our own UP to TXQ mapping for DCB mode of QoS 3342 */ 3343 for (tc = 0; tc < ntc; tc++) { 3344 tc_to_txq[tc] = (struct netdev_tc_txq) { 3345 .count = nch, 3346 .offset = 0, 3347 }; 3348 } 3349 } 3350 3351 static void mlx5e_mqprio_build_tc_to_txq(struct netdev_tc_txq *tc_to_txq, 3352 struct tc_mqprio_qopt *qopt) 3353 { 3354 int tc; 3355 3356 for (tc = 0; tc < TC_MAX_QUEUE; tc++) { 3357 tc_to_txq[tc] = (struct netdev_tc_txq) { 3358 .count = qopt->count[tc], 3359 .offset = qopt->offset[tc], 3360 }; 3361 } 3362 } 3363 3364 static void mlx5e_params_mqprio_dcb_set(struct mlx5e_params *params, u8 num_tc) 3365 { 3366 params->mqprio.mode = TC_MQPRIO_MODE_DCB; 3367 params->mqprio.num_tc = num_tc; 3368 mlx5e_mqprio_build_default_tc_to_txq(params->mqprio.tc_to_txq, num_tc, 3369 params->num_channels); 3370 } 3371 3372 static void mlx5e_mqprio_rl_update_params(struct mlx5e_params *params, 3373 struct mlx5e_mqprio_rl *rl) 3374 { 3375 int tc; 3376 3377 for (tc = 0; tc < TC_MAX_QUEUE; tc++) { 3378 u32 hw_id = 0; 3379 3380 if (rl) 3381 mlx5e_mqprio_rl_get_node_hw_id(rl, tc, &hw_id); 3382 params->mqprio.channel.hw_id[tc] = hw_id; 3383 } 3384 } 3385 3386 static void mlx5e_params_mqprio_channel_set(struct mlx5e_params *params, 3387 struct tc_mqprio_qopt_offload *mqprio, 3388 struct mlx5e_mqprio_rl *rl) 3389 { 3390 int tc; 3391 3392 params->mqprio.mode = TC_MQPRIO_MODE_CHANNEL; 3393 params->mqprio.num_tc = mqprio->qopt.num_tc; 3394 3395 for (tc = 0; tc < TC_MAX_QUEUE; tc++) 3396 params->mqprio.channel.max_rate[tc] = mqprio->max_rate[tc]; 3397 3398 mlx5e_mqprio_rl_update_params(params, rl); 3399 mlx5e_mqprio_build_tc_to_txq(params->mqprio.tc_to_txq, &mqprio->qopt); 3400 } 3401 3402 static void mlx5e_params_mqprio_reset(struct mlx5e_params *params) 3403 { 3404 mlx5e_params_mqprio_dcb_set(params, 1); 3405 } 3406 3407 static int mlx5e_setup_tc_mqprio_dcb(struct mlx5e_priv *priv, 3408 struct tc_mqprio_qopt *mqprio) 3409 { 3410 struct mlx5e_params new_params; 3411 u8 tc = mqprio->num_tc; 3412 int err; 3413 3414 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 3415 3416 if (tc && tc != MLX5E_MAX_NUM_TC) 3417 return -EINVAL; 3418 3419 new_params = priv->channels.params; 3420 mlx5e_params_mqprio_dcb_set(&new_params, tc ? tc : 1); 3421 3422 err = mlx5e_safe_switch_params(priv, &new_params, 3423 mlx5e_num_channels_changed_ctx, NULL, true); 3424 3425 if (!err && priv->mqprio_rl) { 3426 mlx5e_mqprio_rl_cleanup(priv->mqprio_rl); 3427 mlx5e_mqprio_rl_free(priv->mqprio_rl); 3428 priv->mqprio_rl = NULL; 3429 } 3430 3431 priv->max_opened_tc = max_t(u8, priv->max_opened_tc, 3432 mlx5e_get_dcb_num_tc(&priv->channels.params)); 3433 return err; 3434 } 3435 3436 static int mlx5e_mqprio_channel_validate(struct mlx5e_priv *priv, 3437 struct tc_mqprio_qopt_offload *mqprio) 3438 { 3439 struct net_device *netdev = priv->netdev; 3440 struct mlx5e_ptp *ptp_channel; 3441 int agg_count = 0; 3442 int i; 3443 3444 ptp_channel = priv->channels.ptp; 3445 if (ptp_channel && test_bit(MLX5E_PTP_STATE_TX, ptp_channel->state)) { 3446 netdev_err(netdev, 3447 "Cannot activate MQPRIO mode channel since it conflicts with TX port TS\n"); 3448 return -EINVAL; 3449 } 3450 3451 if (mqprio->qopt.offset[0] != 0 || mqprio->qopt.num_tc < 1 || 3452 mqprio->qopt.num_tc > MLX5E_MAX_NUM_MQPRIO_CH_TC) 3453 return -EINVAL; 3454 3455 for (i = 0; i < mqprio->qopt.num_tc; i++) { 3456 if (!mqprio->qopt.count[i]) { 3457 netdev_err(netdev, "Zero size for queue-group (%d) is not supported\n", i); 3458 return -EINVAL; 3459 } 3460 if (mqprio->min_rate[i]) { 3461 netdev_err(netdev, "Min tx rate is not supported\n"); 3462 return -EINVAL; 3463 } 3464 3465 if (mqprio->max_rate[i]) { 3466 int err; 3467 3468 err = mlx5e_qos_bytes_rate_check(priv->mdev, mqprio->max_rate[i]); 3469 if (err) 3470 return err; 3471 } 3472 3473 if (mqprio->qopt.offset[i] != agg_count) { 3474 netdev_err(netdev, "Discontinuous queues config is not supported\n"); 3475 return -EINVAL; 3476 } 3477 agg_count += mqprio->qopt.count[i]; 3478 } 3479 3480 if (priv->channels.params.num_channels != agg_count) { 3481 netdev_err(netdev, "Num of queues (%d) does not match available (%d)\n", 3482 agg_count, priv->channels.params.num_channels); 3483 return -EINVAL; 3484 } 3485 3486 return 0; 3487 } 3488 3489 static bool mlx5e_mqprio_rate_limit(u8 num_tc, u64 max_rate[]) 3490 { 3491 int tc; 3492 3493 for (tc = 0; tc < num_tc; tc++) 3494 if (max_rate[tc]) 3495 return true; 3496 return false; 3497 } 3498 3499 static struct mlx5e_mqprio_rl *mlx5e_mqprio_rl_create(struct mlx5_core_dev *mdev, 3500 u8 num_tc, u64 max_rate[]) 3501 { 3502 struct mlx5e_mqprio_rl *rl; 3503 int err; 3504 3505 if (!mlx5e_mqprio_rate_limit(num_tc, max_rate)) 3506 return NULL; 3507 3508 rl = mlx5e_mqprio_rl_alloc(); 3509 if (!rl) 3510 return ERR_PTR(-ENOMEM); 3511 3512 err = mlx5e_mqprio_rl_init(rl, mdev, num_tc, max_rate); 3513 if (err) { 3514 mlx5e_mqprio_rl_free(rl); 3515 return ERR_PTR(err); 3516 } 3517 3518 return rl; 3519 } 3520 3521 static int mlx5e_setup_tc_mqprio_channel(struct mlx5e_priv *priv, 3522 struct tc_mqprio_qopt_offload *mqprio) 3523 { 3524 mlx5e_fp_preactivate preactivate; 3525 struct mlx5e_params new_params; 3526 struct mlx5e_mqprio_rl *rl; 3527 bool nch_changed; 3528 int err; 3529 3530 err = mlx5e_mqprio_channel_validate(priv, mqprio); 3531 if (err) 3532 return err; 3533 3534 rl = mlx5e_mqprio_rl_create(priv->mdev, mqprio->qopt.num_tc, mqprio->max_rate); 3535 if (IS_ERR(rl)) 3536 return PTR_ERR(rl); 3537 3538 new_params = priv->channels.params; 3539 mlx5e_params_mqprio_channel_set(&new_params, mqprio, rl); 3540 3541 nch_changed = mlx5e_get_dcb_num_tc(&priv->channels.params) > 1; 3542 preactivate = nch_changed ? mlx5e_num_channels_changed_ctx : 3543 mlx5e_update_netdev_queues_ctx; 3544 err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, true); 3545 if (err) { 3546 if (rl) { 3547 mlx5e_mqprio_rl_cleanup(rl); 3548 mlx5e_mqprio_rl_free(rl); 3549 } 3550 return err; 3551 } 3552 3553 if (priv->mqprio_rl) { 3554 mlx5e_mqprio_rl_cleanup(priv->mqprio_rl); 3555 mlx5e_mqprio_rl_free(priv->mqprio_rl); 3556 } 3557 priv->mqprio_rl = rl; 3558 3559 return 0; 3560 } 3561 3562 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv, 3563 struct tc_mqprio_qopt_offload *mqprio) 3564 { 3565 /* MQPRIO is another toplevel qdisc that can't be attached 3566 * simultaneously with the offloaded HTB. 3567 */ 3568 if (WARN_ON(mlx5e_selq_is_htb_enabled(&priv->selq))) 3569 return -EINVAL; 3570 3571 switch (mqprio->mode) { 3572 case TC_MQPRIO_MODE_DCB: 3573 return mlx5e_setup_tc_mqprio_dcb(priv, &mqprio->qopt); 3574 case TC_MQPRIO_MODE_CHANNEL: 3575 return mlx5e_setup_tc_mqprio_channel(priv, mqprio); 3576 default: 3577 return -EOPNOTSUPP; 3578 } 3579 } 3580 3581 static LIST_HEAD(mlx5e_block_cb_list); 3582 3583 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type, 3584 void *type_data) 3585 { 3586 struct mlx5e_priv *priv = netdev_priv(dev); 3587 bool tc_unbind = false; 3588 int err; 3589 3590 if (type == TC_SETUP_BLOCK && 3591 ((struct flow_block_offload *)type_data)->command == FLOW_BLOCK_UNBIND) 3592 tc_unbind = true; 3593 3594 if (!netif_device_present(dev) && !tc_unbind) 3595 return -ENODEV; 3596 3597 switch (type) { 3598 case TC_SETUP_BLOCK: { 3599 struct flow_block_offload *f = type_data; 3600 3601 f->unlocked_driver_cb = true; 3602 return flow_block_cb_setup_simple(type_data, 3603 &mlx5e_block_cb_list, 3604 mlx5e_setup_tc_block_cb, 3605 priv, priv, true); 3606 } 3607 case TC_SETUP_QDISC_MQPRIO: 3608 mutex_lock(&priv->state_lock); 3609 err = mlx5e_setup_tc_mqprio(priv, type_data); 3610 mutex_unlock(&priv->state_lock); 3611 return err; 3612 case TC_SETUP_QDISC_HTB: 3613 mutex_lock(&priv->state_lock); 3614 err = mlx5e_htb_setup_tc(priv, type_data); 3615 mutex_unlock(&priv->state_lock); 3616 return err; 3617 default: 3618 return -EOPNOTSUPP; 3619 } 3620 } 3621 3622 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s) 3623 { 3624 int i; 3625 3626 for (i = 0; i < priv->stats_nch; i++) { 3627 struct mlx5e_channel_stats *channel_stats = priv->channel_stats[i]; 3628 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq; 3629 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq; 3630 int j; 3631 3632 s->rx_packets += rq_stats->packets + xskrq_stats->packets; 3633 s->rx_bytes += rq_stats->bytes + xskrq_stats->bytes; 3634 s->multicast += rq_stats->mcast_packets + xskrq_stats->mcast_packets; 3635 3636 for (j = 0; j < priv->max_opened_tc; j++) { 3637 struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j]; 3638 3639 s->tx_packets += sq_stats->packets; 3640 s->tx_bytes += sq_stats->bytes; 3641 s->tx_dropped += sq_stats->dropped; 3642 } 3643 } 3644 if (priv->tx_ptp_opened) { 3645 for (i = 0; i < priv->max_opened_tc; i++) { 3646 struct mlx5e_sq_stats *sq_stats = &priv->ptp_stats.sq[i]; 3647 3648 s->tx_packets += sq_stats->packets; 3649 s->tx_bytes += sq_stats->bytes; 3650 s->tx_dropped += sq_stats->dropped; 3651 } 3652 } 3653 if (priv->rx_ptp_opened) { 3654 struct mlx5e_rq_stats *rq_stats = &priv->ptp_stats.rq; 3655 3656 s->rx_packets += rq_stats->packets; 3657 s->rx_bytes += rq_stats->bytes; 3658 s->multicast += rq_stats->mcast_packets; 3659 } 3660 } 3661 3662 void 3663 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats) 3664 { 3665 struct mlx5e_priv *priv = netdev_priv(dev); 3666 struct mlx5e_pport_stats *pstats = &priv->stats.pport; 3667 3668 if (!netif_device_present(dev)) 3669 return; 3670 3671 /* In switchdev mode, monitor counters doesn't monitor 3672 * rx/tx stats of 802_3. The update stats mechanism 3673 * should keep the 802_3 layout counters updated 3674 */ 3675 if (!mlx5e_monitor_counter_supported(priv) || 3676 mlx5e_is_uplink_rep(priv)) { 3677 /* update HW stats in background for next time */ 3678 mlx5e_queue_update_stats(priv); 3679 } 3680 3681 if (mlx5e_is_uplink_rep(priv)) { 3682 struct mlx5e_vport_stats *vstats = &priv->stats.vport; 3683 3684 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok); 3685 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok); 3686 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok); 3687 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok); 3688 3689 /* vport multicast also counts packets that are dropped due to steering 3690 * or rx out of buffer 3691 */ 3692 stats->multicast = VPORT_COUNTER_GET(vstats, received_eth_multicast.packets); 3693 } else { 3694 mlx5e_fold_sw_stats64(priv, stats); 3695 } 3696 3697 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer; 3698 3699 stats->rx_length_errors = 3700 PPORT_802_3_GET(pstats, a_in_range_length_errors) + 3701 PPORT_802_3_GET(pstats, a_out_of_range_length_field) + 3702 PPORT_802_3_GET(pstats, a_frame_too_long_errors) + 3703 VNIC_ENV_GET(&priv->stats.vnic, eth_wqe_too_small); 3704 stats->rx_crc_errors = 3705 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors); 3706 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors); 3707 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards); 3708 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 3709 stats->rx_frame_errors; 3710 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors; 3711 } 3712 3713 static void mlx5e_nic_set_rx_mode(struct mlx5e_priv *priv) 3714 { 3715 if (mlx5e_is_uplink_rep(priv)) 3716 return; /* no rx mode for uplink rep */ 3717 3718 queue_work(priv->wq, &priv->set_rx_mode_work); 3719 } 3720 3721 static void mlx5e_set_rx_mode(struct net_device *dev) 3722 { 3723 struct mlx5e_priv *priv = netdev_priv(dev); 3724 3725 mlx5e_nic_set_rx_mode(priv); 3726 } 3727 3728 static int mlx5e_set_mac(struct net_device *netdev, void *addr) 3729 { 3730 struct mlx5e_priv *priv = netdev_priv(netdev); 3731 struct sockaddr *saddr = addr; 3732 3733 if (!is_valid_ether_addr(saddr->sa_data)) 3734 return -EADDRNOTAVAIL; 3735 3736 netif_addr_lock_bh(netdev); 3737 eth_hw_addr_set(netdev, saddr->sa_data); 3738 netif_addr_unlock_bh(netdev); 3739 3740 mlx5e_nic_set_rx_mode(priv); 3741 3742 return 0; 3743 } 3744 3745 #define MLX5E_SET_FEATURE(features, feature, enable) \ 3746 do { \ 3747 if (enable) \ 3748 *features |= feature; \ 3749 else \ 3750 *features &= ~feature; \ 3751 } while (0) 3752 3753 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable); 3754 3755 static int set_feature_lro(struct net_device *netdev, bool enable) 3756 { 3757 struct mlx5e_priv *priv = netdev_priv(netdev); 3758 struct mlx5_core_dev *mdev = priv->mdev; 3759 struct mlx5e_params *cur_params; 3760 struct mlx5e_params new_params; 3761 bool reset = true; 3762 int err = 0; 3763 3764 mutex_lock(&priv->state_lock); 3765 3766 cur_params = &priv->channels.params; 3767 new_params = *cur_params; 3768 3769 if (enable) 3770 new_params.packet_merge.type = MLX5E_PACKET_MERGE_LRO; 3771 else if (new_params.packet_merge.type == MLX5E_PACKET_MERGE_LRO) 3772 new_params.packet_merge.type = MLX5E_PACKET_MERGE_NONE; 3773 else 3774 goto out; 3775 3776 if (!(cur_params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO && 3777 new_params.packet_merge.type == MLX5E_PACKET_MERGE_LRO)) { 3778 if (cur_params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) { 3779 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, cur_params, NULL) == 3780 mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_params, NULL)) 3781 reset = false; 3782 } 3783 } 3784 3785 err = mlx5e_safe_switch_params(priv, &new_params, 3786 mlx5e_modify_tirs_packet_merge_ctx, NULL, reset); 3787 out: 3788 mutex_unlock(&priv->state_lock); 3789 return err; 3790 } 3791 3792 static int set_feature_hw_gro(struct net_device *netdev, bool enable) 3793 { 3794 struct mlx5e_priv *priv = netdev_priv(netdev); 3795 struct mlx5e_params new_params; 3796 bool reset = true; 3797 int err = 0; 3798 3799 mutex_lock(&priv->state_lock); 3800 new_params = priv->channels.params; 3801 3802 if (enable) { 3803 new_params.packet_merge.type = MLX5E_PACKET_MERGE_SHAMPO; 3804 new_params.packet_merge.shampo.match_criteria_type = 3805 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED; 3806 new_params.packet_merge.shampo.alignment_granularity = 3807 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE; 3808 } else if (new_params.packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) { 3809 new_params.packet_merge.type = MLX5E_PACKET_MERGE_NONE; 3810 } else { 3811 goto out; 3812 } 3813 3814 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset); 3815 out: 3816 mutex_unlock(&priv->state_lock); 3817 return err; 3818 } 3819 3820 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable) 3821 { 3822 struct mlx5e_priv *priv = netdev_priv(netdev); 3823 3824 if (enable) 3825 mlx5e_enable_cvlan_filter(priv->fs, 3826 !!(priv->netdev->flags & IFF_PROMISC)); 3827 else 3828 mlx5e_disable_cvlan_filter(priv->fs, 3829 !!(priv->netdev->flags & IFF_PROMISC)); 3830 3831 return 0; 3832 } 3833 3834 static int set_feature_hw_tc(struct net_device *netdev, bool enable) 3835 { 3836 struct mlx5e_priv *priv = netdev_priv(netdev); 3837 int err = 0; 3838 3839 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT) 3840 int tc_flag = mlx5e_is_uplink_rep(priv) ? MLX5_TC_FLAG(ESW_OFFLOAD) : 3841 MLX5_TC_FLAG(NIC_OFFLOAD); 3842 if (!enable && mlx5e_tc_num_filters(priv, tc_flag)) { 3843 netdev_err(netdev, 3844 "Active offloaded tc filters, can't turn hw_tc_offload off\n"); 3845 return -EINVAL; 3846 } 3847 #endif 3848 3849 mutex_lock(&priv->state_lock); 3850 if (!enable && mlx5e_selq_is_htb_enabled(&priv->selq)) { 3851 netdev_err(netdev, "Active HTB offload, can't turn hw_tc_offload off\n"); 3852 err = -EINVAL; 3853 } 3854 mutex_unlock(&priv->state_lock); 3855 3856 return err; 3857 } 3858 3859 static int set_feature_rx_all(struct net_device *netdev, bool enable) 3860 { 3861 struct mlx5e_priv *priv = netdev_priv(netdev); 3862 struct mlx5_core_dev *mdev = priv->mdev; 3863 3864 return mlx5_set_port_fcs(mdev, !enable); 3865 } 3866 3867 static int mlx5e_set_rx_port_ts(struct mlx5_core_dev *mdev, bool enable) 3868 { 3869 u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {}; 3870 bool supported, curr_state; 3871 int err; 3872 3873 if (!MLX5_CAP_GEN(mdev, ports_check)) 3874 return 0; 3875 3876 err = mlx5_query_ports_check(mdev, in, sizeof(in)); 3877 if (err) 3878 return err; 3879 3880 supported = MLX5_GET(pcmr_reg, in, rx_ts_over_crc_cap); 3881 curr_state = MLX5_GET(pcmr_reg, in, rx_ts_over_crc); 3882 3883 if (!supported || enable == curr_state) 3884 return 0; 3885 3886 MLX5_SET(pcmr_reg, in, local_port, 1); 3887 MLX5_SET(pcmr_reg, in, rx_ts_over_crc, enable); 3888 3889 return mlx5_set_ports_check(mdev, in, sizeof(in)); 3890 } 3891 3892 static int set_feature_rx_fcs(struct net_device *netdev, bool enable) 3893 { 3894 struct mlx5e_priv *priv = netdev_priv(netdev); 3895 struct mlx5e_channels *chs = &priv->channels; 3896 struct mlx5_core_dev *mdev = priv->mdev; 3897 int err; 3898 3899 mutex_lock(&priv->state_lock); 3900 3901 if (enable) { 3902 err = mlx5e_set_rx_port_ts(mdev, false); 3903 if (err) 3904 goto out; 3905 3906 chs->params.scatter_fcs_en = true; 3907 err = mlx5e_modify_channels_scatter_fcs(chs, true); 3908 if (err) { 3909 chs->params.scatter_fcs_en = false; 3910 mlx5e_set_rx_port_ts(mdev, true); 3911 } 3912 } else { 3913 chs->params.scatter_fcs_en = false; 3914 err = mlx5e_modify_channels_scatter_fcs(chs, false); 3915 if (err) { 3916 chs->params.scatter_fcs_en = true; 3917 goto out; 3918 } 3919 err = mlx5e_set_rx_port_ts(mdev, true); 3920 if (err) { 3921 mlx5_core_warn(mdev, "Failed to set RX port timestamp %d\n", err); 3922 err = 0; 3923 } 3924 } 3925 3926 out: 3927 mutex_unlock(&priv->state_lock); 3928 return err; 3929 } 3930 3931 static int set_feature_rx_vlan(struct net_device *netdev, bool enable) 3932 { 3933 struct mlx5e_priv *priv = netdev_priv(netdev); 3934 int err = 0; 3935 3936 mutex_lock(&priv->state_lock); 3937 3938 mlx5e_fs_set_vlan_strip_disable(priv->fs, !enable); 3939 priv->channels.params.vlan_strip_disable = !enable; 3940 3941 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) 3942 goto unlock; 3943 3944 err = mlx5e_modify_channels_vsd(&priv->channels, !enable); 3945 if (err) { 3946 mlx5e_fs_set_vlan_strip_disable(priv->fs, enable); 3947 priv->channels.params.vlan_strip_disable = enable; 3948 } 3949 unlock: 3950 mutex_unlock(&priv->state_lock); 3951 3952 return err; 3953 } 3954 3955 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid) 3956 { 3957 struct mlx5e_priv *priv = netdev_priv(dev); 3958 struct mlx5e_flow_steering *fs = priv->fs; 3959 3960 if (mlx5e_is_uplink_rep(priv)) 3961 return 0; /* no vlan table for uplink rep */ 3962 3963 return mlx5e_fs_vlan_rx_add_vid(fs, dev, proto, vid); 3964 } 3965 3966 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid) 3967 { 3968 struct mlx5e_priv *priv = netdev_priv(dev); 3969 struct mlx5e_flow_steering *fs = priv->fs; 3970 3971 if (mlx5e_is_uplink_rep(priv)) 3972 return 0; /* no vlan table for uplink rep */ 3973 3974 return mlx5e_fs_vlan_rx_kill_vid(fs, dev, proto, vid); 3975 } 3976 3977 #ifdef CONFIG_MLX5_EN_ARFS 3978 static int set_feature_arfs(struct net_device *netdev, bool enable) 3979 { 3980 struct mlx5e_priv *priv = netdev_priv(netdev); 3981 int err; 3982 3983 if (enable) 3984 err = mlx5e_arfs_enable(priv->fs); 3985 else 3986 err = mlx5e_arfs_disable(priv->fs); 3987 3988 return err; 3989 } 3990 #endif 3991 3992 static int mlx5e_handle_feature(struct net_device *netdev, 3993 netdev_features_t *features, 3994 netdev_features_t feature, 3995 mlx5e_feature_handler feature_handler) 3996 { 3997 netdev_features_t changes = *features ^ netdev->features; 3998 bool enable = !!(*features & feature); 3999 int err; 4000 4001 if (!(changes & feature)) 4002 return 0; 4003 4004 err = feature_handler(netdev, enable); 4005 if (err) { 4006 MLX5E_SET_FEATURE(features, feature, !enable); 4007 netdev_err(netdev, "%s feature %pNF failed, err %d\n", 4008 enable ? "Enable" : "Disable", &feature, err); 4009 return err; 4010 } 4011 4012 return 0; 4013 } 4014 4015 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features) 4016 { 4017 netdev_features_t oper_features = features; 4018 int err = 0; 4019 4020 #define MLX5E_HANDLE_FEATURE(feature, handler) \ 4021 mlx5e_handle_feature(netdev, &oper_features, feature, handler) 4022 4023 err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro); 4024 err |= MLX5E_HANDLE_FEATURE(NETIF_F_GRO_HW, set_feature_hw_gro); 4025 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER, 4026 set_feature_cvlan_filter); 4027 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_hw_tc); 4028 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all); 4029 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs); 4030 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan); 4031 #ifdef CONFIG_MLX5_EN_ARFS 4032 err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs); 4033 #endif 4034 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TLS_RX, mlx5e_ktls_set_feature_rx); 4035 4036 if (err) { 4037 netdev->features = oper_features; 4038 return -EINVAL; 4039 } 4040 4041 return 0; 4042 } 4043 4044 static netdev_features_t mlx5e_fix_uplink_rep_features(struct net_device *netdev, 4045 netdev_features_t features) 4046 { 4047 features &= ~NETIF_F_HW_TLS_RX; 4048 if (netdev->features & NETIF_F_HW_TLS_RX) 4049 netdev_warn(netdev, "Disabling hw_tls_rx, not supported in switchdev mode\n"); 4050 4051 features &= ~NETIF_F_HW_TLS_TX; 4052 if (netdev->features & NETIF_F_HW_TLS_TX) 4053 netdev_warn(netdev, "Disabling hw_tls_tx, not supported in switchdev mode\n"); 4054 4055 features &= ~NETIF_F_NTUPLE; 4056 if (netdev->features & NETIF_F_NTUPLE) 4057 netdev_warn(netdev, "Disabling ntuple, not supported in switchdev mode\n"); 4058 4059 features &= ~NETIF_F_GRO_HW; 4060 if (netdev->features & NETIF_F_GRO_HW) 4061 netdev_warn(netdev, "Disabling HW_GRO, not supported in switchdev mode\n"); 4062 4063 return features; 4064 } 4065 4066 static netdev_features_t mlx5e_fix_features(struct net_device *netdev, 4067 netdev_features_t features) 4068 { 4069 struct mlx5e_priv *priv = netdev_priv(netdev); 4070 struct mlx5e_vlan_table *vlan; 4071 struct mlx5e_params *params; 4072 4073 vlan = mlx5e_fs_get_vlan(priv->fs); 4074 mutex_lock(&priv->state_lock); 4075 params = &priv->channels.params; 4076 if (!vlan || 4077 !bitmap_empty(mlx5e_vlan_get_active_svlans(vlan), VLAN_N_VID)) { 4078 /* HW strips the outer C-tag header, this is a problem 4079 * for S-tag traffic. 4080 */ 4081 features &= ~NETIF_F_HW_VLAN_CTAG_RX; 4082 if (!params->vlan_strip_disable) 4083 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n"); 4084 } 4085 4086 if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) { 4087 if (features & NETIF_F_LRO) { 4088 netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n"); 4089 features &= ~NETIF_F_LRO; 4090 } 4091 if (features & NETIF_F_GRO_HW) { 4092 netdev_warn(netdev, "Disabling HW-GRO, not supported in legacy RQ\n"); 4093 features &= ~NETIF_F_GRO_HW; 4094 } 4095 } 4096 4097 if (params->xdp_prog) { 4098 if (features & NETIF_F_LRO) { 4099 netdev_warn(netdev, "LRO is incompatible with XDP\n"); 4100 features &= ~NETIF_F_LRO; 4101 } 4102 if (features & NETIF_F_GRO_HW) { 4103 netdev_warn(netdev, "HW GRO is incompatible with XDP\n"); 4104 features &= ~NETIF_F_GRO_HW; 4105 } 4106 } 4107 4108 if (priv->xsk.refcnt) { 4109 if (features & NETIF_F_LRO) { 4110 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%u XSKs are active)\n", 4111 priv->xsk.refcnt); 4112 features &= ~NETIF_F_LRO; 4113 } 4114 if (features & NETIF_F_GRO_HW) { 4115 netdev_warn(netdev, "HW GRO is incompatible with AF_XDP (%u XSKs are active)\n", 4116 priv->xsk.refcnt); 4117 features &= ~NETIF_F_GRO_HW; 4118 } 4119 } 4120 4121 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) { 4122 features &= ~NETIF_F_RXHASH; 4123 if (netdev->features & NETIF_F_RXHASH) 4124 netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n"); 4125 4126 if (features & NETIF_F_GRO_HW) { 4127 netdev_warn(netdev, "Disabling HW-GRO, not supported when CQE compress is active\n"); 4128 features &= ~NETIF_F_GRO_HW; 4129 } 4130 } 4131 4132 if (mlx5e_is_uplink_rep(priv)) 4133 features = mlx5e_fix_uplink_rep_features(netdev, features); 4134 4135 mutex_unlock(&priv->state_lock); 4136 4137 return features; 4138 } 4139 4140 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev, 4141 struct mlx5e_channels *chs, 4142 struct mlx5e_params *new_params, 4143 struct mlx5_core_dev *mdev) 4144 { 4145 u16 ix; 4146 4147 for (ix = 0; ix < chs->params.num_channels; ix++) { 4148 struct xsk_buff_pool *xsk_pool = 4149 mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, ix); 4150 struct mlx5e_xsk_param xsk; 4151 4152 if (!xsk_pool) 4153 continue; 4154 4155 mlx5e_build_xsk_param(xsk_pool, &xsk); 4156 4157 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) { 4158 u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk); 4159 int max_mtu_frame, max_mtu_page, max_mtu; 4160 4161 /* Two criteria must be met: 4162 * 1. HW MTU + all headrooms <= XSK frame size. 4163 * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE. 4164 */ 4165 max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr); 4166 max_mtu_page = MLX5E_HW2SW_MTU(new_params, SKB_MAX_HEAD(0)); 4167 max_mtu = min(max_mtu_frame, max_mtu_page); 4168 4169 netdev_err(netdev, "MTU %d is too big for an XSK running on channel %u. Try MTU <= %d\n", 4170 new_params->sw_mtu, ix, max_mtu); 4171 return false; 4172 } 4173 } 4174 4175 return true; 4176 } 4177 4178 static bool mlx5e_params_validate_xdp(struct net_device *netdev, 4179 struct mlx5_core_dev *mdev, 4180 struct mlx5e_params *params) 4181 { 4182 bool is_linear; 4183 4184 /* No XSK params: AF_XDP can't be enabled yet at the point of setting 4185 * the XDP program. 4186 */ 4187 is_linear = mlx5e_rx_is_linear_skb(mdev, params, NULL); 4188 4189 if (!is_linear && params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) { 4190 netdev_warn(netdev, "XDP is not allowed with striding RQ and MTU(%d) > %d\n", 4191 params->sw_mtu, 4192 mlx5e_xdp_max_mtu(params, NULL)); 4193 return false; 4194 } 4195 if (!is_linear && !params->xdp_prog->aux->xdp_has_frags) { 4196 netdev_warn(netdev, "MTU(%d) > %d, too big for an XDP program not aware of multi buffer\n", 4197 params->sw_mtu, 4198 mlx5e_xdp_max_mtu(params, NULL)); 4199 return false; 4200 } 4201 4202 return true; 4203 } 4204 4205 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu, 4206 mlx5e_fp_preactivate preactivate) 4207 { 4208 struct mlx5e_priv *priv = netdev_priv(netdev); 4209 struct mlx5e_params new_params; 4210 struct mlx5e_params *params; 4211 bool reset = true; 4212 int err = 0; 4213 4214 mutex_lock(&priv->state_lock); 4215 4216 params = &priv->channels.params; 4217 4218 new_params = *params; 4219 new_params.sw_mtu = new_mtu; 4220 err = mlx5e_validate_params(priv->mdev, &new_params); 4221 if (err) 4222 goto out; 4223 4224 if (new_params.xdp_prog && !mlx5e_params_validate_xdp(netdev, priv->mdev, 4225 &new_params)) { 4226 err = -EINVAL; 4227 goto out; 4228 } 4229 4230 if (priv->xsk.refcnt && 4231 !mlx5e_xsk_validate_mtu(netdev, &priv->channels, 4232 &new_params, priv->mdev)) { 4233 err = -EINVAL; 4234 goto out; 4235 } 4236 4237 if (params->packet_merge.type == MLX5E_PACKET_MERGE_LRO) 4238 reset = false; 4239 4240 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ && 4241 params->packet_merge.type != MLX5E_PACKET_MERGE_SHAMPO) { 4242 bool is_linear_old = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, params, NULL); 4243 bool is_linear_new = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, 4244 &new_params, NULL); 4245 u8 sz_old = mlx5e_mpwqe_get_log_rq_size(priv->mdev, params, NULL); 4246 u8 sz_new = mlx5e_mpwqe_get_log_rq_size(priv->mdev, &new_params, NULL); 4247 4248 /* Always reset in linear mode - hw_mtu is used in data path. 4249 * Check that the mode was non-linear and didn't change. 4250 * If XSK is active, XSK RQs are linear. 4251 * Reset if the RQ size changed, even if it's non-linear. 4252 */ 4253 if (!is_linear_old && !is_linear_new && !priv->xsk.refcnt && 4254 sz_old == sz_new) 4255 reset = false; 4256 } 4257 4258 err = mlx5e_safe_switch_params(priv, &new_params, preactivate, NULL, reset); 4259 4260 out: 4261 netdev->mtu = params->sw_mtu; 4262 mutex_unlock(&priv->state_lock); 4263 return err; 4264 } 4265 4266 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu) 4267 { 4268 return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx); 4269 } 4270 4271 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx) 4272 { 4273 bool set = *(bool *)ctx; 4274 4275 return mlx5e_ptp_rx_manage_fs(priv, set); 4276 } 4277 4278 static int mlx5e_hwstamp_config_no_ptp_rx(struct mlx5e_priv *priv, bool rx_filter) 4279 { 4280 bool rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def; 4281 int err; 4282 4283 if (!rx_filter) 4284 /* Reset CQE compression to Admin default */ 4285 return mlx5e_modify_rx_cqe_compression_locked(priv, rx_cqe_compress_def, false); 4286 4287 if (!MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS)) 4288 return 0; 4289 4290 /* Disable CQE compression */ 4291 netdev_warn(priv->netdev, "Disabling RX cqe compression\n"); 4292 err = mlx5e_modify_rx_cqe_compression_locked(priv, false, true); 4293 if (err) 4294 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err); 4295 4296 return err; 4297 } 4298 4299 static int mlx5e_hwstamp_config_ptp_rx(struct mlx5e_priv *priv, bool ptp_rx) 4300 { 4301 struct mlx5e_params new_params; 4302 4303 if (ptp_rx == priv->channels.params.ptp_rx) 4304 return 0; 4305 4306 new_params = priv->channels.params; 4307 new_params.ptp_rx = ptp_rx; 4308 return mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx, 4309 &new_params.ptp_rx, true); 4310 } 4311 4312 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr) 4313 { 4314 struct hwtstamp_config config; 4315 bool rx_cqe_compress_def; 4316 bool ptp_rx; 4317 int err; 4318 4319 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) || 4320 (mlx5_clock_get_ptp_index(priv->mdev) == -1)) 4321 return -EOPNOTSUPP; 4322 4323 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 4324 return -EFAULT; 4325 4326 /* TX HW timestamp */ 4327 switch (config.tx_type) { 4328 case HWTSTAMP_TX_OFF: 4329 case HWTSTAMP_TX_ON: 4330 break; 4331 default: 4332 return -ERANGE; 4333 } 4334 4335 mutex_lock(&priv->state_lock); 4336 rx_cqe_compress_def = priv->channels.params.rx_cqe_compress_def; 4337 4338 /* RX HW timestamp */ 4339 switch (config.rx_filter) { 4340 case HWTSTAMP_FILTER_NONE: 4341 ptp_rx = false; 4342 break; 4343 case HWTSTAMP_FILTER_ALL: 4344 case HWTSTAMP_FILTER_SOME: 4345 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 4346 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 4347 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 4348 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 4349 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 4350 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 4351 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 4352 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 4353 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 4354 case HWTSTAMP_FILTER_PTP_V2_EVENT: 4355 case HWTSTAMP_FILTER_PTP_V2_SYNC: 4356 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 4357 case HWTSTAMP_FILTER_NTP_ALL: 4358 config.rx_filter = HWTSTAMP_FILTER_ALL; 4359 /* ptp_rx is set if both HW TS is set and CQE 4360 * compression is set 4361 */ 4362 ptp_rx = rx_cqe_compress_def; 4363 break; 4364 default: 4365 err = -ERANGE; 4366 goto err_unlock; 4367 } 4368 4369 if (!mlx5e_profile_feature_cap(priv->profile, PTP_RX)) 4370 err = mlx5e_hwstamp_config_no_ptp_rx(priv, 4371 config.rx_filter != HWTSTAMP_FILTER_NONE); 4372 else 4373 err = mlx5e_hwstamp_config_ptp_rx(priv, ptp_rx); 4374 if (err) 4375 goto err_unlock; 4376 4377 memcpy(&priv->tstamp, &config, sizeof(config)); 4378 mutex_unlock(&priv->state_lock); 4379 4380 /* might need to fix some features */ 4381 netdev_update_features(priv->netdev); 4382 4383 return copy_to_user(ifr->ifr_data, &config, 4384 sizeof(config)) ? -EFAULT : 0; 4385 err_unlock: 4386 mutex_unlock(&priv->state_lock); 4387 return err; 4388 } 4389 4390 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr) 4391 { 4392 struct hwtstamp_config *cfg = &priv->tstamp; 4393 4394 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz)) 4395 return -EOPNOTSUPP; 4396 4397 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0; 4398 } 4399 4400 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 4401 { 4402 struct mlx5e_priv *priv = netdev_priv(dev); 4403 4404 switch (cmd) { 4405 case SIOCSHWTSTAMP: 4406 return mlx5e_hwstamp_set(priv, ifr); 4407 case SIOCGHWTSTAMP: 4408 return mlx5e_hwstamp_get(priv, ifr); 4409 default: 4410 return -EOPNOTSUPP; 4411 } 4412 } 4413 4414 #ifdef CONFIG_MLX5_ESWITCH 4415 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac) 4416 { 4417 struct mlx5e_priv *priv = netdev_priv(dev); 4418 struct mlx5_core_dev *mdev = priv->mdev; 4419 4420 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac); 4421 } 4422 4423 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos, 4424 __be16 vlan_proto) 4425 { 4426 struct mlx5e_priv *priv = netdev_priv(dev); 4427 struct mlx5_core_dev *mdev = priv->mdev; 4428 4429 if (vlan_proto != htons(ETH_P_8021Q)) 4430 return -EPROTONOSUPPORT; 4431 4432 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1, 4433 vlan, qos); 4434 } 4435 4436 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting) 4437 { 4438 struct mlx5e_priv *priv = netdev_priv(dev); 4439 struct mlx5_core_dev *mdev = priv->mdev; 4440 4441 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting); 4442 } 4443 4444 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting) 4445 { 4446 struct mlx5e_priv *priv = netdev_priv(dev); 4447 struct mlx5_core_dev *mdev = priv->mdev; 4448 4449 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting); 4450 } 4451 4452 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, 4453 int max_tx_rate) 4454 { 4455 struct mlx5e_priv *priv = netdev_priv(dev); 4456 struct mlx5_core_dev *mdev = priv->mdev; 4457 4458 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1, 4459 max_tx_rate, min_tx_rate); 4460 } 4461 4462 static int mlx5_vport_link2ifla(u8 esw_link) 4463 { 4464 switch (esw_link) { 4465 case MLX5_VPORT_ADMIN_STATE_DOWN: 4466 return IFLA_VF_LINK_STATE_DISABLE; 4467 case MLX5_VPORT_ADMIN_STATE_UP: 4468 return IFLA_VF_LINK_STATE_ENABLE; 4469 } 4470 return IFLA_VF_LINK_STATE_AUTO; 4471 } 4472 4473 static int mlx5_ifla_link2vport(u8 ifla_link) 4474 { 4475 switch (ifla_link) { 4476 case IFLA_VF_LINK_STATE_DISABLE: 4477 return MLX5_VPORT_ADMIN_STATE_DOWN; 4478 case IFLA_VF_LINK_STATE_ENABLE: 4479 return MLX5_VPORT_ADMIN_STATE_UP; 4480 } 4481 return MLX5_VPORT_ADMIN_STATE_AUTO; 4482 } 4483 4484 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf, 4485 int link_state) 4486 { 4487 struct mlx5e_priv *priv = netdev_priv(dev); 4488 struct mlx5_core_dev *mdev = priv->mdev; 4489 4490 if (mlx5e_is_uplink_rep(priv)) 4491 return -EOPNOTSUPP; 4492 4493 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1, 4494 mlx5_ifla_link2vport(link_state)); 4495 } 4496 4497 int mlx5e_get_vf_config(struct net_device *dev, 4498 int vf, struct ifla_vf_info *ivi) 4499 { 4500 struct mlx5e_priv *priv = netdev_priv(dev); 4501 struct mlx5_core_dev *mdev = priv->mdev; 4502 int err; 4503 4504 if (!netif_device_present(dev)) 4505 return -EOPNOTSUPP; 4506 4507 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi); 4508 if (err) 4509 return err; 4510 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate); 4511 return 0; 4512 } 4513 4514 int mlx5e_get_vf_stats(struct net_device *dev, 4515 int vf, struct ifla_vf_stats *vf_stats) 4516 { 4517 struct mlx5e_priv *priv = netdev_priv(dev); 4518 struct mlx5_core_dev *mdev = priv->mdev; 4519 4520 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1, 4521 vf_stats); 4522 } 4523 4524 static bool 4525 mlx5e_has_offload_stats(const struct net_device *dev, int attr_id) 4526 { 4527 struct mlx5e_priv *priv = netdev_priv(dev); 4528 4529 if (!netif_device_present(dev)) 4530 return false; 4531 4532 if (!mlx5e_is_uplink_rep(priv)) 4533 return false; 4534 4535 return mlx5e_rep_has_offload_stats(dev, attr_id); 4536 } 4537 4538 static int 4539 mlx5e_get_offload_stats(int attr_id, const struct net_device *dev, 4540 void *sp) 4541 { 4542 struct mlx5e_priv *priv = netdev_priv(dev); 4543 4544 if (!mlx5e_is_uplink_rep(priv)) 4545 return -EOPNOTSUPP; 4546 4547 return mlx5e_rep_get_offload_stats(attr_id, dev, sp); 4548 } 4549 #endif 4550 4551 static bool mlx5e_tunnel_proto_supported_tx(struct mlx5_core_dev *mdev, u8 proto_type) 4552 { 4553 switch (proto_type) { 4554 case IPPROTO_GRE: 4555 return MLX5_CAP_ETH(mdev, tunnel_stateless_gre); 4556 case IPPROTO_IPIP: 4557 case IPPROTO_IPV6: 4558 return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) || 4559 MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_tx)); 4560 default: 4561 return false; 4562 } 4563 } 4564 4565 static bool mlx5e_gre_tunnel_inner_proto_offload_supported(struct mlx5_core_dev *mdev, 4566 struct sk_buff *skb) 4567 { 4568 switch (skb->inner_protocol) { 4569 case htons(ETH_P_IP): 4570 case htons(ETH_P_IPV6): 4571 case htons(ETH_P_TEB): 4572 return true; 4573 case htons(ETH_P_MPLS_UC): 4574 case htons(ETH_P_MPLS_MC): 4575 return MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre); 4576 } 4577 return false; 4578 } 4579 4580 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv, 4581 struct sk_buff *skb, 4582 netdev_features_t features) 4583 { 4584 unsigned int offset = 0; 4585 struct udphdr *udph; 4586 u8 proto; 4587 u16 port; 4588 4589 switch (vlan_get_protocol(skb)) { 4590 case htons(ETH_P_IP): 4591 proto = ip_hdr(skb)->protocol; 4592 break; 4593 case htons(ETH_P_IPV6): 4594 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL); 4595 break; 4596 default: 4597 goto out; 4598 } 4599 4600 switch (proto) { 4601 case IPPROTO_GRE: 4602 if (mlx5e_gre_tunnel_inner_proto_offload_supported(priv->mdev, skb)) 4603 return features; 4604 break; 4605 case IPPROTO_IPIP: 4606 case IPPROTO_IPV6: 4607 if (mlx5e_tunnel_proto_supported_tx(priv->mdev, IPPROTO_IPIP)) 4608 return features; 4609 break; 4610 case IPPROTO_UDP: 4611 udph = udp_hdr(skb); 4612 port = be16_to_cpu(udph->dest); 4613 4614 /* Verify if UDP port is being offloaded by HW */ 4615 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port)) 4616 return features; 4617 4618 #if IS_ENABLED(CONFIG_GENEVE) 4619 /* Support Geneve offload for default UDP port */ 4620 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev)) 4621 return features; 4622 #endif 4623 break; 4624 #ifdef CONFIG_MLX5_EN_IPSEC 4625 case IPPROTO_ESP: 4626 return mlx5e_ipsec_feature_check(skb, features); 4627 #endif 4628 } 4629 4630 out: 4631 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */ 4632 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 4633 } 4634 4635 netdev_features_t mlx5e_features_check(struct sk_buff *skb, 4636 struct net_device *netdev, 4637 netdev_features_t features) 4638 { 4639 struct mlx5e_priv *priv = netdev_priv(netdev); 4640 4641 features = vlan_features_check(skb, features); 4642 features = vxlan_features_check(skb, features); 4643 4644 /* Validate if the tunneled packet is being offloaded by HW */ 4645 if (skb->encapsulation && 4646 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK)) 4647 return mlx5e_tunnel_features_check(priv, skb, features); 4648 4649 return features; 4650 } 4651 4652 static void mlx5e_tx_timeout_work(struct work_struct *work) 4653 { 4654 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, 4655 tx_timeout_work); 4656 struct net_device *netdev = priv->netdev; 4657 int i; 4658 4659 rtnl_lock(); 4660 mutex_lock(&priv->state_lock); 4661 4662 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) 4663 goto unlock; 4664 4665 for (i = 0; i < netdev->real_num_tx_queues; i++) { 4666 struct netdev_queue *dev_queue = 4667 netdev_get_tx_queue(netdev, i); 4668 struct mlx5e_txqsq *sq = priv->txq2sq[i]; 4669 4670 if (!netif_xmit_stopped(dev_queue)) 4671 continue; 4672 4673 if (mlx5e_reporter_tx_timeout(sq)) 4674 /* break if tried to reopened channels */ 4675 break; 4676 } 4677 4678 unlock: 4679 mutex_unlock(&priv->state_lock); 4680 rtnl_unlock(); 4681 } 4682 4683 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue) 4684 { 4685 struct mlx5e_priv *priv = netdev_priv(dev); 4686 4687 netdev_err(dev, "TX timeout detected\n"); 4688 queue_work(priv->wq, &priv->tx_timeout_work); 4689 } 4690 4691 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog) 4692 { 4693 struct net_device *netdev = priv->netdev; 4694 struct mlx5e_params new_params; 4695 4696 if (priv->channels.params.packet_merge.type != MLX5E_PACKET_MERGE_NONE) { 4697 netdev_warn(netdev, "can't set XDP while HW-GRO/LRO is on, disable them first\n"); 4698 return -EINVAL; 4699 } 4700 4701 new_params = priv->channels.params; 4702 new_params.xdp_prog = prog; 4703 4704 if (!mlx5e_params_validate_xdp(netdev, priv->mdev, &new_params)) 4705 return -EINVAL; 4706 4707 return 0; 4708 } 4709 4710 static void mlx5e_rq_replace_xdp_prog(struct mlx5e_rq *rq, struct bpf_prog *prog) 4711 { 4712 struct bpf_prog *old_prog; 4713 4714 old_prog = rcu_replace_pointer(rq->xdp_prog, prog, 4715 lockdep_is_held(&rq->priv->state_lock)); 4716 if (old_prog) 4717 bpf_prog_put(old_prog); 4718 } 4719 4720 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog) 4721 { 4722 struct mlx5e_priv *priv = netdev_priv(netdev); 4723 struct mlx5e_params new_params; 4724 struct bpf_prog *old_prog; 4725 int err = 0; 4726 bool reset; 4727 int i; 4728 4729 mutex_lock(&priv->state_lock); 4730 4731 if (prog) { 4732 err = mlx5e_xdp_allowed(priv, prog); 4733 if (err) 4734 goto unlock; 4735 } 4736 4737 /* no need for full reset when exchanging programs */ 4738 reset = (!priv->channels.params.xdp_prog || !prog); 4739 4740 new_params = priv->channels.params; 4741 new_params.xdp_prog = prog; 4742 4743 /* XDP affects striding RQ parameters. Block XDP if striding RQ won't be 4744 * supported with the new parameters: if PAGE_SIZE is bigger than 4745 * MLX5_MPWQE_LOG_STRIDE_SZ_MAX, striding RQ can't be used, even though 4746 * the MTU is small enough for the linear mode, because XDP uses strides 4747 * of PAGE_SIZE on regular RQs. 4748 */ 4749 if (reset && MLX5E_GET_PFLAG(&new_params, MLX5E_PFLAG_RX_STRIDING_RQ)) { 4750 /* Checking for regular RQs here; XSK RQs were checked on XSK bind. */ 4751 err = mlx5e_mpwrq_validate_regular(priv->mdev, &new_params); 4752 if (err) 4753 goto unlock; 4754 } 4755 4756 old_prog = priv->channels.params.xdp_prog; 4757 4758 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset); 4759 if (err) 4760 goto unlock; 4761 4762 if (old_prog) 4763 bpf_prog_put(old_prog); 4764 4765 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset) 4766 goto unlock; 4767 4768 /* exchanging programs w/o reset, we update ref counts on behalf 4769 * of the channels RQs here. 4770 */ 4771 bpf_prog_add(prog, priv->channels.num); 4772 for (i = 0; i < priv->channels.num; i++) { 4773 struct mlx5e_channel *c = priv->channels.c[i]; 4774 4775 mlx5e_rq_replace_xdp_prog(&c->rq, prog); 4776 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) { 4777 bpf_prog_inc(prog); 4778 mlx5e_rq_replace_xdp_prog(&c->xskrq, prog); 4779 } 4780 } 4781 4782 unlock: 4783 mutex_unlock(&priv->state_lock); 4784 4785 /* Need to fix some features. */ 4786 if (!err) 4787 netdev_update_features(netdev); 4788 4789 return err; 4790 } 4791 4792 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp) 4793 { 4794 switch (xdp->command) { 4795 case XDP_SETUP_PROG: 4796 return mlx5e_xdp_set(dev, xdp->prog); 4797 case XDP_SETUP_XSK_POOL: 4798 return mlx5e_xsk_setup_pool(dev, xdp->xsk.pool, 4799 xdp->xsk.queue_id); 4800 default: 4801 return -EINVAL; 4802 } 4803 } 4804 4805 #ifdef CONFIG_MLX5_ESWITCH 4806 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 4807 struct net_device *dev, u32 filter_mask, 4808 int nlflags) 4809 { 4810 struct mlx5e_priv *priv = netdev_priv(dev); 4811 struct mlx5_core_dev *mdev = priv->mdev; 4812 u8 mode, setting; 4813 int err; 4814 4815 err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting); 4816 if (err) 4817 return err; 4818 mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB; 4819 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, 4820 mode, 4821 0, 0, nlflags, filter_mask, NULL); 4822 } 4823 4824 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh, 4825 u16 flags, struct netlink_ext_ack *extack) 4826 { 4827 struct mlx5e_priv *priv = netdev_priv(dev); 4828 struct mlx5_core_dev *mdev = priv->mdev; 4829 struct nlattr *attr, *br_spec; 4830 u16 mode = BRIDGE_MODE_UNDEF; 4831 u8 setting; 4832 int rem; 4833 4834 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 4835 if (!br_spec) 4836 return -EINVAL; 4837 4838 nla_for_each_nested(attr, br_spec, rem) { 4839 if (nla_type(attr) != IFLA_BRIDGE_MODE) 4840 continue; 4841 4842 if (nla_len(attr) < sizeof(mode)) 4843 return -EINVAL; 4844 4845 mode = nla_get_u16(attr); 4846 if (mode > BRIDGE_MODE_VEPA) 4847 return -EINVAL; 4848 4849 break; 4850 } 4851 4852 if (mode == BRIDGE_MODE_UNDEF) 4853 return -EINVAL; 4854 4855 setting = (mode == BRIDGE_MODE_VEPA) ? 1 : 0; 4856 return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting); 4857 } 4858 #endif 4859 4860 const struct net_device_ops mlx5e_netdev_ops = { 4861 .ndo_open = mlx5e_open, 4862 .ndo_stop = mlx5e_close, 4863 .ndo_start_xmit = mlx5e_xmit, 4864 .ndo_setup_tc = mlx5e_setup_tc, 4865 .ndo_select_queue = mlx5e_select_queue, 4866 .ndo_get_stats64 = mlx5e_get_stats, 4867 .ndo_set_rx_mode = mlx5e_set_rx_mode, 4868 .ndo_set_mac_address = mlx5e_set_mac, 4869 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid, 4870 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid, 4871 .ndo_set_features = mlx5e_set_features, 4872 .ndo_fix_features = mlx5e_fix_features, 4873 .ndo_change_mtu = mlx5e_change_nic_mtu, 4874 .ndo_eth_ioctl = mlx5e_ioctl, 4875 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate, 4876 .ndo_features_check = mlx5e_features_check, 4877 .ndo_tx_timeout = mlx5e_tx_timeout, 4878 .ndo_bpf = mlx5e_xdp, 4879 .ndo_xdp_xmit = mlx5e_xdp_xmit, 4880 .ndo_xsk_wakeup = mlx5e_xsk_wakeup, 4881 #ifdef CONFIG_MLX5_EN_ARFS 4882 .ndo_rx_flow_steer = mlx5e_rx_flow_steer, 4883 #endif 4884 #ifdef CONFIG_MLX5_ESWITCH 4885 .ndo_bridge_setlink = mlx5e_bridge_setlink, 4886 .ndo_bridge_getlink = mlx5e_bridge_getlink, 4887 4888 /* SRIOV E-Switch NDOs */ 4889 .ndo_set_vf_mac = mlx5e_set_vf_mac, 4890 .ndo_set_vf_vlan = mlx5e_set_vf_vlan, 4891 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk, 4892 .ndo_set_vf_trust = mlx5e_set_vf_trust, 4893 .ndo_set_vf_rate = mlx5e_set_vf_rate, 4894 .ndo_get_vf_config = mlx5e_get_vf_config, 4895 .ndo_set_vf_link_state = mlx5e_set_vf_link_state, 4896 .ndo_get_vf_stats = mlx5e_get_vf_stats, 4897 .ndo_has_offload_stats = mlx5e_has_offload_stats, 4898 .ndo_get_offload_stats = mlx5e_get_offload_stats, 4899 #endif 4900 .ndo_get_devlink_port = mlx5e_get_devlink_port, 4901 }; 4902 4903 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout) 4904 { 4905 int i; 4906 4907 /* The supported periods are organized in ascending order */ 4908 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++) 4909 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout) 4910 break; 4911 4912 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]); 4913 } 4914 4915 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu) 4916 { 4917 struct mlx5e_params *params = &priv->channels.params; 4918 struct mlx5_core_dev *mdev = priv->mdev; 4919 u8 rx_cq_period_mode; 4920 4921 params->sw_mtu = mtu; 4922 params->hard_mtu = MLX5E_ETH_HARD_MTU; 4923 params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2, 4924 priv->max_nch); 4925 mlx5e_params_mqprio_reset(params); 4926 4927 /* SQ */ 4928 params->log_sq_size = is_kdump_kernel() ? 4929 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE : 4930 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; 4931 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev)); 4932 4933 /* XDP SQ */ 4934 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE, mlx5e_tx_mpwqe_supported(mdev)); 4935 4936 /* set CQE compression */ 4937 params->rx_cqe_compress_def = false; 4938 if (MLX5_CAP_GEN(mdev, cqe_compression) && 4939 MLX5_CAP_GEN(mdev, vport_group_manager)) 4940 params->rx_cqe_compress_def = slow_pci_heuristic(mdev); 4941 4942 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def); 4943 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false); 4944 4945 /* RQ */ 4946 mlx5e_build_rq_params(mdev, params); 4947 4948 params->packet_merge.timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT); 4949 4950 /* CQ moderation params */ 4951 rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 4952 MLX5_CQ_PERIOD_MODE_START_FROM_CQE : 4953 MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 4954 params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation); 4955 params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation); 4956 mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode); 4957 mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 4958 4959 /* TX inline */ 4960 mlx5_query_min_inline(mdev, ¶ms->tx_min_inline_mode); 4961 4962 params->tunneled_offload_en = mlx5_tunnel_inner_ft_supported(mdev); 4963 4964 /* AF_XDP */ 4965 params->xsk = xsk; 4966 4967 /* Do not update netdev->features directly in here 4968 * on mlx5e_attach_netdev() we will call mlx5e_update_features() 4969 * To update netdev->features please modify mlx5e_fix_features() 4970 */ 4971 } 4972 4973 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev) 4974 { 4975 struct mlx5e_priv *priv = netdev_priv(netdev); 4976 u8 addr[ETH_ALEN]; 4977 4978 mlx5_query_mac_address(priv->mdev, addr); 4979 if (is_zero_ether_addr(addr) && 4980 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) { 4981 eth_hw_addr_random(netdev); 4982 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr); 4983 return; 4984 } 4985 4986 eth_hw_addr_set(netdev, addr); 4987 } 4988 4989 static int mlx5e_vxlan_set_port(struct net_device *netdev, unsigned int table, 4990 unsigned int entry, struct udp_tunnel_info *ti) 4991 { 4992 struct mlx5e_priv *priv = netdev_priv(netdev); 4993 4994 return mlx5_vxlan_add_port(priv->mdev->vxlan, ntohs(ti->port)); 4995 } 4996 4997 static int mlx5e_vxlan_unset_port(struct net_device *netdev, unsigned int table, 4998 unsigned int entry, struct udp_tunnel_info *ti) 4999 { 5000 struct mlx5e_priv *priv = netdev_priv(netdev); 5001 5002 return mlx5_vxlan_del_port(priv->mdev->vxlan, ntohs(ti->port)); 5003 } 5004 5005 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv) 5006 { 5007 if (!mlx5_vxlan_allowed(priv->mdev->vxlan)) 5008 return; 5009 5010 priv->nic_info.set_port = mlx5e_vxlan_set_port; 5011 priv->nic_info.unset_port = mlx5e_vxlan_unset_port; 5012 priv->nic_info.flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP | 5013 UDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN; 5014 priv->nic_info.tables[0].tunnel_types = UDP_TUNNEL_TYPE_VXLAN; 5015 /* Don't count the space hard-coded to the IANA port */ 5016 priv->nic_info.tables[0].n_entries = 5017 mlx5_vxlan_max_udp_ports(priv->mdev) - 1; 5018 5019 priv->netdev->udp_tunnel_nic_info = &priv->nic_info; 5020 } 5021 5022 static bool mlx5e_tunnel_any_tx_proto_supported(struct mlx5_core_dev *mdev) 5023 { 5024 int tt; 5025 5026 for (tt = 0; tt < MLX5_NUM_TUNNEL_TT; tt++) { 5027 if (mlx5e_tunnel_proto_supported_tx(mdev, mlx5_get_proto_by_tunnel_type(tt))) 5028 return true; 5029 } 5030 return (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)); 5031 } 5032 5033 static void mlx5e_build_nic_netdev(struct net_device *netdev) 5034 { 5035 struct mlx5e_priv *priv = netdev_priv(netdev); 5036 struct mlx5_core_dev *mdev = priv->mdev; 5037 bool fcs_supported; 5038 bool fcs_enabled; 5039 5040 SET_NETDEV_DEV(netdev, mdev->device); 5041 5042 netdev->netdev_ops = &mlx5e_netdev_ops; 5043 5044 mlx5e_dcbnl_build_netdev(netdev); 5045 5046 netdev->watchdog_timeo = 15 * HZ; 5047 5048 netdev->ethtool_ops = &mlx5e_ethtool_ops; 5049 5050 netdev->vlan_features |= NETIF_F_SG; 5051 netdev->vlan_features |= NETIF_F_HW_CSUM; 5052 netdev->vlan_features |= NETIF_F_GRO; 5053 netdev->vlan_features |= NETIF_F_TSO; 5054 netdev->vlan_features |= NETIF_F_TSO6; 5055 netdev->vlan_features |= NETIF_F_RXCSUM; 5056 netdev->vlan_features |= NETIF_F_RXHASH; 5057 netdev->vlan_features |= NETIF_F_GSO_PARTIAL; 5058 5059 netdev->mpls_features |= NETIF_F_SG; 5060 netdev->mpls_features |= NETIF_F_HW_CSUM; 5061 netdev->mpls_features |= NETIF_F_TSO; 5062 netdev->mpls_features |= NETIF_F_TSO6; 5063 5064 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_TX; 5065 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_RX; 5066 5067 /* Tunneled LRO is not supported in the driver, and the same RQs are 5068 * shared between inner and outer TIRs, so the driver can't disable LRO 5069 * for inner TIRs while having it enabled for outer TIRs. Due to this, 5070 * block LRO altogether if the firmware declares tunneled LRO support. 5071 */ 5072 if (!!MLX5_CAP_ETH(mdev, lro_cap) && 5073 !MLX5_CAP_ETH(mdev, tunnel_lro_vxlan) && 5074 !MLX5_CAP_ETH(mdev, tunnel_lro_gre) && 5075 mlx5e_check_fragmented_striding_rq_cap(mdev, PAGE_SHIFT, 5076 MLX5E_MPWRQ_UMR_MODE_ALIGNED)) 5077 netdev->vlan_features |= NETIF_F_LRO; 5078 5079 netdev->hw_features = netdev->vlan_features; 5080 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; 5081 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; 5082 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 5083 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX; 5084 5085 if (mlx5e_tunnel_any_tx_proto_supported(mdev)) { 5086 netdev->hw_enc_features |= NETIF_F_HW_CSUM; 5087 netdev->hw_enc_features |= NETIF_F_TSO; 5088 netdev->hw_enc_features |= NETIF_F_TSO6; 5089 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL; 5090 } 5091 5092 if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) { 5093 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL | 5094 NETIF_F_GSO_UDP_TUNNEL_CSUM; 5095 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL | 5096 NETIF_F_GSO_UDP_TUNNEL_CSUM; 5097 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM; 5098 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL | 5099 NETIF_F_GSO_UDP_TUNNEL_CSUM; 5100 } 5101 5102 if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_GRE)) { 5103 netdev->hw_features |= NETIF_F_GSO_GRE | 5104 NETIF_F_GSO_GRE_CSUM; 5105 netdev->hw_enc_features |= NETIF_F_GSO_GRE | 5106 NETIF_F_GSO_GRE_CSUM; 5107 netdev->gso_partial_features |= NETIF_F_GSO_GRE | 5108 NETIF_F_GSO_GRE_CSUM; 5109 } 5110 5111 if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_IPIP)) { 5112 netdev->hw_features |= NETIF_F_GSO_IPXIP4 | 5113 NETIF_F_GSO_IPXIP6; 5114 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 | 5115 NETIF_F_GSO_IPXIP6; 5116 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 | 5117 NETIF_F_GSO_IPXIP6; 5118 } 5119 5120 netdev->gso_partial_features |= NETIF_F_GSO_UDP_L4; 5121 netdev->hw_features |= NETIF_F_GSO_UDP_L4; 5122 netdev->features |= NETIF_F_GSO_UDP_L4; 5123 5124 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled); 5125 5126 if (fcs_supported) 5127 netdev->hw_features |= NETIF_F_RXALL; 5128 5129 if (MLX5_CAP_ETH(mdev, scatter_fcs)) 5130 netdev->hw_features |= NETIF_F_RXFCS; 5131 5132 if (mlx5_qos_is_supported(mdev)) 5133 netdev->hw_features |= NETIF_F_HW_TC; 5134 5135 netdev->features = netdev->hw_features; 5136 5137 /* Defaults */ 5138 if (fcs_enabled) 5139 netdev->features &= ~NETIF_F_RXALL; 5140 netdev->features &= ~NETIF_F_LRO; 5141 netdev->features &= ~NETIF_F_GRO_HW; 5142 netdev->features &= ~NETIF_F_RXFCS; 5143 5144 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f) 5145 if (FT_CAP(flow_modify_en) && 5146 FT_CAP(modify_root) && 5147 FT_CAP(identified_miss_table_mode) && 5148 FT_CAP(flow_table_modify)) { 5149 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT) 5150 netdev->hw_features |= NETIF_F_HW_TC; 5151 #endif 5152 #ifdef CONFIG_MLX5_EN_ARFS 5153 netdev->hw_features |= NETIF_F_NTUPLE; 5154 #endif 5155 } 5156 5157 netdev->features |= NETIF_F_HIGHDMA; 5158 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER; 5159 5160 netdev->priv_flags |= IFF_UNICAST_FLT; 5161 5162 netif_set_tso_max_size(netdev, GSO_MAX_SIZE); 5163 mlx5e_set_netdev_dev_addr(netdev); 5164 mlx5e_macsec_build_netdev(priv); 5165 mlx5e_ipsec_build_netdev(priv); 5166 mlx5e_ktls_build_netdev(priv); 5167 } 5168 5169 void mlx5e_create_q_counters(struct mlx5e_priv *priv) 5170 { 5171 u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {}; 5172 u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {}; 5173 struct mlx5_core_dev *mdev = priv->mdev; 5174 int err; 5175 5176 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 5177 err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out); 5178 if (!err) 5179 priv->q_counter = 5180 MLX5_GET(alloc_q_counter_out, out, counter_set_id); 5181 5182 err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out); 5183 if (!err) 5184 priv->drop_rq_q_counter = 5185 MLX5_GET(alloc_q_counter_out, out, counter_set_id); 5186 } 5187 5188 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv) 5189 { 5190 u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {}; 5191 5192 MLX5_SET(dealloc_q_counter_in, in, opcode, 5193 MLX5_CMD_OP_DEALLOC_Q_COUNTER); 5194 if (priv->q_counter) { 5195 MLX5_SET(dealloc_q_counter_in, in, counter_set_id, 5196 priv->q_counter); 5197 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in); 5198 } 5199 5200 if (priv->drop_rq_q_counter) { 5201 MLX5_SET(dealloc_q_counter_in, in, counter_set_id, 5202 priv->drop_rq_q_counter); 5203 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in); 5204 } 5205 } 5206 5207 static int mlx5e_nic_init(struct mlx5_core_dev *mdev, 5208 struct net_device *netdev) 5209 { 5210 struct mlx5e_priv *priv = netdev_priv(netdev); 5211 struct mlx5e_flow_steering *fs; 5212 int err; 5213 5214 mlx5e_build_nic_params(priv, &priv->xsk, netdev->mtu); 5215 mlx5e_vxlan_set_netdev_info(priv); 5216 5217 mlx5e_timestamp_init(priv); 5218 5219 fs = mlx5e_fs_init(priv->profile, mdev, 5220 !test_bit(MLX5E_STATE_DESTROYING, &priv->state)); 5221 if (!fs) { 5222 err = -ENOMEM; 5223 mlx5_core_err(mdev, "FS initialization failed, %d\n", err); 5224 return err; 5225 } 5226 priv->fs = fs; 5227 5228 err = mlx5e_ipsec_init(priv); 5229 if (err) 5230 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err); 5231 5232 err = mlx5e_ktls_init(priv); 5233 if (err) 5234 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err); 5235 5236 mlx5e_health_create_reporters(priv); 5237 return 0; 5238 } 5239 5240 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv) 5241 { 5242 mlx5e_health_destroy_reporters(priv); 5243 mlx5e_ktls_cleanup(priv); 5244 mlx5e_ipsec_cleanup(priv); 5245 mlx5e_fs_cleanup(priv->fs); 5246 } 5247 5248 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv) 5249 { 5250 struct mlx5_core_dev *mdev = priv->mdev; 5251 enum mlx5e_rx_res_features features; 5252 int err; 5253 5254 priv->rx_res = mlx5e_rx_res_alloc(); 5255 if (!priv->rx_res) 5256 return -ENOMEM; 5257 5258 mlx5e_create_q_counters(priv); 5259 5260 err = mlx5e_open_drop_rq(priv, &priv->drop_rq); 5261 if (err) { 5262 mlx5_core_err(mdev, "open drop rq failed, %d\n", err); 5263 goto err_destroy_q_counters; 5264 } 5265 5266 features = MLX5E_RX_RES_FEATURE_PTP; 5267 if (priv->channels.params.tunneled_offload_en) 5268 features |= MLX5E_RX_RES_FEATURE_INNER_FT; 5269 err = mlx5e_rx_res_init(priv->rx_res, priv->mdev, features, 5270 priv->max_nch, priv->drop_rq.rqn, 5271 &priv->channels.params.packet_merge, 5272 priv->channels.params.num_channels); 5273 if (err) 5274 goto err_close_drop_rq; 5275 5276 err = mlx5e_create_flow_steering(priv->fs, priv->rx_res, priv->profile, 5277 priv->netdev); 5278 if (err) { 5279 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err); 5280 goto err_destroy_rx_res; 5281 } 5282 5283 err = mlx5e_tc_nic_init(priv); 5284 if (err) 5285 goto err_destroy_flow_steering; 5286 5287 err = mlx5e_accel_init_rx(priv); 5288 if (err) 5289 goto err_tc_nic_cleanup; 5290 5291 #ifdef CONFIG_MLX5_EN_ARFS 5292 priv->netdev->rx_cpu_rmap = mlx5_eq_table_get_rmap(priv->mdev); 5293 #endif 5294 5295 return 0; 5296 5297 err_tc_nic_cleanup: 5298 mlx5e_tc_nic_cleanup(priv); 5299 err_destroy_flow_steering: 5300 mlx5e_destroy_flow_steering(priv->fs, !!(priv->netdev->hw_features & NETIF_F_NTUPLE), 5301 priv->profile); 5302 err_destroy_rx_res: 5303 mlx5e_rx_res_destroy(priv->rx_res); 5304 err_close_drop_rq: 5305 mlx5e_close_drop_rq(&priv->drop_rq); 5306 err_destroy_q_counters: 5307 mlx5e_destroy_q_counters(priv); 5308 mlx5e_rx_res_free(priv->rx_res); 5309 priv->rx_res = NULL; 5310 return err; 5311 } 5312 5313 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv) 5314 { 5315 mlx5e_accel_cleanup_rx(priv); 5316 mlx5e_tc_nic_cleanup(priv); 5317 mlx5e_destroy_flow_steering(priv->fs, !!(priv->netdev->hw_features & NETIF_F_NTUPLE), 5318 priv->profile); 5319 mlx5e_rx_res_destroy(priv->rx_res); 5320 mlx5e_close_drop_rq(&priv->drop_rq); 5321 mlx5e_destroy_q_counters(priv); 5322 mlx5e_rx_res_free(priv->rx_res); 5323 priv->rx_res = NULL; 5324 } 5325 5326 static void mlx5e_set_mqprio_rl(struct mlx5e_priv *priv) 5327 { 5328 struct mlx5e_params *params; 5329 struct mlx5e_mqprio_rl *rl; 5330 5331 params = &priv->channels.params; 5332 if (params->mqprio.mode != TC_MQPRIO_MODE_CHANNEL) 5333 return; 5334 5335 rl = mlx5e_mqprio_rl_create(priv->mdev, params->mqprio.num_tc, 5336 params->mqprio.channel.max_rate); 5337 if (IS_ERR(rl)) 5338 rl = NULL; 5339 priv->mqprio_rl = rl; 5340 mlx5e_mqprio_rl_update_params(params, rl); 5341 } 5342 5343 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv) 5344 { 5345 int err; 5346 5347 err = mlx5e_create_tises(priv); 5348 if (err) { 5349 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err); 5350 return err; 5351 } 5352 5353 err = mlx5e_accel_init_tx(priv); 5354 if (err) 5355 goto err_destroy_tises; 5356 5357 mlx5e_set_mqprio_rl(priv); 5358 mlx5e_dcbnl_initialize(priv); 5359 return 0; 5360 5361 err_destroy_tises: 5362 mlx5e_destroy_tises(priv); 5363 return err; 5364 } 5365 5366 static void mlx5e_nic_enable(struct mlx5e_priv *priv) 5367 { 5368 struct net_device *netdev = priv->netdev; 5369 struct mlx5_core_dev *mdev = priv->mdev; 5370 int err; 5371 5372 mlx5e_fs_init_l2_addr(priv->fs, netdev); 5373 5374 err = mlx5e_macsec_init(priv); 5375 if (err) 5376 mlx5_core_err(mdev, "MACsec initialization failed, %d\n", err); 5377 5378 /* Marking the link as currently not needed by the Driver */ 5379 if (!netif_running(netdev)) 5380 mlx5e_modify_admin_state(mdev, MLX5_PORT_DOWN); 5381 5382 mlx5e_set_netdev_mtu_boundaries(priv); 5383 mlx5e_set_dev_port_mtu(priv); 5384 5385 mlx5_lag_add_netdev(mdev, netdev); 5386 5387 mlx5e_enable_async_events(priv); 5388 mlx5e_enable_blocking_events(priv); 5389 if (mlx5e_monitor_counter_supported(priv)) 5390 mlx5e_monitor_counter_init(priv); 5391 5392 mlx5e_hv_vhca_stats_create(priv); 5393 if (netdev->reg_state != NETREG_REGISTERED) 5394 return; 5395 mlx5e_dcbnl_init_app(priv); 5396 5397 mlx5e_nic_set_rx_mode(priv); 5398 5399 rtnl_lock(); 5400 if (netif_running(netdev)) 5401 mlx5e_open(netdev); 5402 udp_tunnel_nic_reset_ntf(priv->netdev); 5403 netif_device_attach(netdev); 5404 rtnl_unlock(); 5405 } 5406 5407 static void mlx5e_nic_disable(struct mlx5e_priv *priv) 5408 { 5409 struct mlx5_core_dev *mdev = priv->mdev; 5410 5411 if (priv->netdev->reg_state == NETREG_REGISTERED) 5412 mlx5e_dcbnl_delete_app(priv); 5413 5414 rtnl_lock(); 5415 if (netif_running(priv->netdev)) 5416 mlx5e_close(priv->netdev); 5417 netif_device_detach(priv->netdev); 5418 rtnl_unlock(); 5419 5420 mlx5e_nic_set_rx_mode(priv); 5421 5422 mlx5e_hv_vhca_stats_destroy(priv); 5423 if (mlx5e_monitor_counter_supported(priv)) 5424 mlx5e_monitor_counter_cleanup(priv); 5425 5426 mlx5e_disable_blocking_events(priv); 5427 if (priv->en_trap) { 5428 mlx5e_deactivate_trap(priv); 5429 mlx5e_close_trap(priv->en_trap); 5430 priv->en_trap = NULL; 5431 } 5432 mlx5e_disable_async_events(priv); 5433 mlx5_lag_remove_netdev(mdev, priv->netdev); 5434 mlx5_vxlan_reset_to_default(mdev->vxlan); 5435 mlx5e_macsec_cleanup(priv); 5436 } 5437 5438 int mlx5e_update_nic_rx(struct mlx5e_priv *priv) 5439 { 5440 return mlx5e_refresh_tirs(priv, false, false); 5441 } 5442 5443 static const struct mlx5e_profile mlx5e_nic_profile = { 5444 .init = mlx5e_nic_init, 5445 .cleanup = mlx5e_nic_cleanup, 5446 .init_rx = mlx5e_init_nic_rx, 5447 .cleanup_rx = mlx5e_cleanup_nic_rx, 5448 .init_tx = mlx5e_init_nic_tx, 5449 .cleanup_tx = mlx5e_cleanup_nic_tx, 5450 .enable = mlx5e_nic_enable, 5451 .disable = mlx5e_nic_disable, 5452 .update_rx = mlx5e_update_nic_rx, 5453 .update_stats = mlx5e_stats_update_ndo_stats, 5454 .update_carrier = mlx5e_update_carrier, 5455 .rx_handlers = &mlx5e_rx_handlers_nic, 5456 .max_tc = MLX5E_MAX_NUM_TC, 5457 .stats_grps = mlx5e_nic_stats_grps, 5458 .stats_grps_num = mlx5e_nic_stats_grps_num, 5459 .features = BIT(MLX5E_PROFILE_FEATURE_PTP_RX) | 5460 BIT(MLX5E_PROFILE_FEATURE_PTP_TX) | 5461 BIT(MLX5E_PROFILE_FEATURE_QOS_HTB) | 5462 BIT(MLX5E_PROFILE_FEATURE_FS_VLAN) | 5463 BIT(MLX5E_PROFILE_FEATURE_FS_TC), 5464 }; 5465 5466 static int mlx5e_profile_max_num_channels(struct mlx5_core_dev *mdev, 5467 const struct mlx5e_profile *profile) 5468 { 5469 int nch; 5470 5471 nch = mlx5e_get_max_num_channels(mdev); 5472 5473 if (profile->max_nch_limit) 5474 nch = min_t(int, nch, profile->max_nch_limit(mdev)); 5475 return nch; 5476 } 5477 5478 static unsigned int 5479 mlx5e_calc_max_nch(struct mlx5_core_dev *mdev, struct net_device *netdev, 5480 const struct mlx5e_profile *profile) 5481 5482 { 5483 unsigned int max_nch, tmp; 5484 5485 /* core resources */ 5486 max_nch = mlx5e_profile_max_num_channels(mdev, profile); 5487 5488 /* netdev rx queues */ 5489 max_nch = min_t(unsigned int, max_nch, netdev->num_rx_queues); 5490 5491 /* netdev tx queues */ 5492 tmp = netdev->num_tx_queues; 5493 if (mlx5_qos_is_supported(mdev)) 5494 tmp -= mlx5e_qos_max_leaf_nodes(mdev); 5495 if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn)) 5496 tmp -= profile->max_tc; 5497 tmp = tmp / profile->max_tc; 5498 max_nch = min_t(unsigned int, max_nch, tmp); 5499 5500 return max_nch; 5501 } 5502 5503 int mlx5e_get_pf_num_tirs(struct mlx5_core_dev *mdev) 5504 { 5505 /* Indirect TIRS: 2 sets of TTCs (inner + outer steering) 5506 * and 1 set of direct TIRS 5507 */ 5508 return 2 * MLX5E_NUM_INDIR_TIRS 5509 + mlx5e_profile_max_num_channels(mdev, &mlx5e_nic_profile); 5510 } 5511 5512 void mlx5e_set_rx_mode_work(struct work_struct *work) 5513 { 5514 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, 5515 set_rx_mode_work); 5516 5517 return mlx5e_fs_set_rx_mode_work(priv->fs, priv->netdev); 5518 } 5519 5520 /* mlx5e generic netdev management API (move to en_common.c) */ 5521 int mlx5e_priv_init(struct mlx5e_priv *priv, 5522 const struct mlx5e_profile *profile, 5523 struct net_device *netdev, 5524 struct mlx5_core_dev *mdev) 5525 { 5526 int nch, num_txqs, node; 5527 int err; 5528 5529 num_txqs = netdev->num_tx_queues; 5530 nch = mlx5e_calc_max_nch(mdev, netdev, profile); 5531 node = dev_to_node(mlx5_core_dma_dev(mdev)); 5532 5533 /* priv init */ 5534 priv->mdev = mdev; 5535 priv->netdev = netdev; 5536 priv->msglevel = MLX5E_MSG_LEVEL; 5537 priv->max_nch = nch; 5538 priv->max_opened_tc = 1; 5539 5540 if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL)) 5541 return -ENOMEM; 5542 5543 mutex_init(&priv->state_lock); 5544 5545 err = mlx5e_selq_init(&priv->selq, &priv->state_lock); 5546 if (err) 5547 goto err_free_cpumask; 5548 5549 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work); 5550 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work); 5551 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work); 5552 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work); 5553 5554 priv->wq = create_singlethread_workqueue("mlx5e"); 5555 if (!priv->wq) 5556 goto err_free_selq; 5557 5558 priv->txq2sq = kcalloc_node(num_txqs, sizeof(*priv->txq2sq), GFP_KERNEL, node); 5559 if (!priv->txq2sq) 5560 goto err_destroy_workqueue; 5561 5562 priv->tx_rates = kcalloc_node(num_txqs, sizeof(*priv->tx_rates), GFP_KERNEL, node); 5563 if (!priv->tx_rates) 5564 goto err_free_txq2sq; 5565 5566 priv->channel_stats = 5567 kcalloc_node(nch, sizeof(*priv->channel_stats), GFP_KERNEL, node); 5568 if (!priv->channel_stats) 5569 goto err_free_tx_rates; 5570 5571 return 0; 5572 5573 err_free_tx_rates: 5574 kfree(priv->tx_rates); 5575 err_free_txq2sq: 5576 kfree(priv->txq2sq); 5577 err_destroy_workqueue: 5578 destroy_workqueue(priv->wq); 5579 err_free_selq: 5580 mlx5e_selq_cleanup(&priv->selq); 5581 err_free_cpumask: 5582 free_cpumask_var(priv->scratchpad.cpumask); 5583 return -ENOMEM; 5584 } 5585 5586 void mlx5e_priv_cleanup(struct mlx5e_priv *priv) 5587 { 5588 int i; 5589 5590 /* bail if change profile failed and also rollback failed */ 5591 if (!priv->mdev) 5592 return; 5593 5594 for (i = 0; i < priv->stats_nch; i++) 5595 kvfree(priv->channel_stats[i]); 5596 kfree(priv->channel_stats); 5597 kfree(priv->tx_rates); 5598 kfree(priv->txq2sq); 5599 destroy_workqueue(priv->wq); 5600 mutex_lock(&priv->state_lock); 5601 mlx5e_selq_cleanup(&priv->selq); 5602 mutex_unlock(&priv->state_lock); 5603 free_cpumask_var(priv->scratchpad.cpumask); 5604 5605 for (i = 0; i < priv->htb_max_qos_sqs; i++) 5606 kfree(priv->htb_qos_sq_stats[i]); 5607 kvfree(priv->htb_qos_sq_stats); 5608 5609 memset(priv, 0, sizeof(*priv)); 5610 } 5611 5612 static unsigned int mlx5e_get_max_num_txqs(struct mlx5_core_dev *mdev, 5613 const struct mlx5e_profile *profile) 5614 { 5615 unsigned int nch, ptp_txqs, qos_txqs; 5616 5617 nch = mlx5e_profile_max_num_channels(mdev, profile); 5618 5619 ptp_txqs = MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn) && 5620 mlx5e_profile_feature_cap(profile, PTP_TX) ? 5621 profile->max_tc : 0; 5622 5623 qos_txqs = mlx5_qos_is_supported(mdev) && 5624 mlx5e_profile_feature_cap(profile, QOS_HTB) ? 5625 mlx5e_qos_max_leaf_nodes(mdev) : 0; 5626 5627 return nch * profile->max_tc + ptp_txqs + qos_txqs; 5628 } 5629 5630 static unsigned int mlx5e_get_max_num_rxqs(struct mlx5_core_dev *mdev, 5631 const struct mlx5e_profile *profile) 5632 { 5633 return mlx5e_profile_max_num_channels(mdev, profile); 5634 } 5635 5636 struct net_device * 5637 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile) 5638 { 5639 struct net_device *netdev; 5640 unsigned int txqs, rxqs; 5641 int err; 5642 5643 txqs = mlx5e_get_max_num_txqs(mdev, profile); 5644 rxqs = mlx5e_get_max_num_rxqs(mdev, profile); 5645 5646 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), txqs, rxqs); 5647 if (!netdev) { 5648 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n"); 5649 return NULL; 5650 } 5651 5652 err = mlx5e_priv_init(netdev_priv(netdev), profile, netdev, mdev); 5653 if (err) { 5654 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err); 5655 goto err_free_netdev; 5656 } 5657 5658 netif_carrier_off(netdev); 5659 netif_tx_disable(netdev); 5660 dev_net_set(netdev, mlx5_core_net(mdev)); 5661 5662 return netdev; 5663 5664 err_free_netdev: 5665 free_netdev(netdev); 5666 5667 return NULL; 5668 } 5669 5670 static void mlx5e_update_features(struct net_device *netdev) 5671 { 5672 if (netdev->reg_state != NETREG_REGISTERED) 5673 return; /* features will be updated on netdev registration */ 5674 5675 rtnl_lock(); 5676 netdev_update_features(netdev); 5677 rtnl_unlock(); 5678 } 5679 5680 static void mlx5e_reset_channels(struct net_device *netdev) 5681 { 5682 netdev_reset_tc(netdev); 5683 } 5684 5685 int mlx5e_attach_netdev(struct mlx5e_priv *priv) 5686 { 5687 const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED; 5688 const struct mlx5e_profile *profile = priv->profile; 5689 int max_nch; 5690 int err; 5691 5692 clear_bit(MLX5E_STATE_DESTROYING, &priv->state); 5693 if (priv->fs) 5694 mlx5e_fs_set_state_destroy(priv->fs, 5695 !test_bit(MLX5E_STATE_DESTROYING, &priv->state)); 5696 5697 /* Validate the max_wqe_size_sq capability. */ 5698 if (WARN_ON_ONCE(mlx5e_get_max_sq_wqebbs(priv->mdev) < MLX5E_MAX_TX_WQEBBS)) { 5699 mlx5_core_warn(priv->mdev, "MLX5E: Max SQ WQEBBs firmware capability: %u, needed %lu\n", 5700 mlx5e_get_max_sq_wqebbs(priv->mdev), MLX5E_MAX_TX_WQEBBS); 5701 return -EIO; 5702 } 5703 5704 /* max number of channels may have changed */ 5705 max_nch = mlx5e_calc_max_nch(priv->mdev, priv->netdev, profile); 5706 if (priv->channels.params.num_channels > max_nch) { 5707 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch); 5708 /* Reducing the number of channels - RXFH has to be reset, and 5709 * mlx5e_num_channels_changed below will build the RQT. 5710 */ 5711 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED; 5712 priv->channels.params.num_channels = max_nch; 5713 if (priv->channels.params.mqprio.mode == TC_MQPRIO_MODE_CHANNEL) { 5714 mlx5_core_warn(priv->mdev, "MLX5E: Disabling MQPRIO channel mode\n"); 5715 mlx5e_params_mqprio_reset(&priv->channels.params); 5716 } 5717 } 5718 if (max_nch != priv->max_nch) { 5719 mlx5_core_warn(priv->mdev, 5720 "MLX5E: Updating max number of channels from %u to %u\n", 5721 priv->max_nch, max_nch); 5722 priv->max_nch = max_nch; 5723 } 5724 5725 /* 1. Set the real number of queues in the kernel the first time. 5726 * 2. Set our default XPS cpumask. 5727 * 3. Build the RQT. 5728 * 5729 * rtnl_lock is required by netif_set_real_num_*_queues in case the 5730 * netdev has been registered by this point (if this function was called 5731 * in the reload or resume flow). 5732 */ 5733 if (take_rtnl) 5734 rtnl_lock(); 5735 err = mlx5e_num_channels_changed(priv); 5736 if (take_rtnl) 5737 rtnl_unlock(); 5738 if (err) 5739 goto out; 5740 5741 err = profile->init_tx(priv); 5742 if (err) 5743 goto out; 5744 5745 err = profile->init_rx(priv); 5746 if (err) 5747 goto err_cleanup_tx; 5748 5749 if (profile->enable) 5750 profile->enable(priv); 5751 5752 mlx5e_update_features(priv->netdev); 5753 5754 return 0; 5755 5756 err_cleanup_tx: 5757 profile->cleanup_tx(priv); 5758 5759 out: 5760 mlx5e_reset_channels(priv->netdev); 5761 set_bit(MLX5E_STATE_DESTROYING, &priv->state); 5762 if (priv->fs) 5763 mlx5e_fs_set_state_destroy(priv->fs, 5764 !test_bit(MLX5E_STATE_DESTROYING, &priv->state)); 5765 cancel_work_sync(&priv->update_stats_work); 5766 return err; 5767 } 5768 5769 void mlx5e_detach_netdev(struct mlx5e_priv *priv) 5770 { 5771 const struct mlx5e_profile *profile = priv->profile; 5772 5773 set_bit(MLX5E_STATE_DESTROYING, &priv->state); 5774 if (priv->fs) 5775 mlx5e_fs_set_state_destroy(priv->fs, 5776 !test_bit(MLX5E_STATE_DESTROYING, &priv->state)); 5777 5778 if (profile->disable) 5779 profile->disable(priv); 5780 flush_workqueue(priv->wq); 5781 5782 profile->cleanup_rx(priv); 5783 profile->cleanup_tx(priv); 5784 mlx5e_reset_channels(priv->netdev); 5785 cancel_work_sync(&priv->update_stats_work); 5786 } 5787 5788 static int 5789 mlx5e_netdev_attach_profile(struct net_device *netdev, struct mlx5_core_dev *mdev, 5790 const struct mlx5e_profile *new_profile, void *new_ppriv) 5791 { 5792 struct mlx5e_priv *priv = netdev_priv(netdev); 5793 int err; 5794 5795 err = mlx5e_priv_init(priv, new_profile, netdev, mdev); 5796 if (err) { 5797 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err); 5798 return err; 5799 } 5800 netif_carrier_off(netdev); 5801 priv->profile = new_profile; 5802 priv->ppriv = new_ppriv; 5803 err = new_profile->init(priv->mdev, priv->netdev); 5804 if (err) 5805 goto priv_cleanup; 5806 err = mlx5e_attach_netdev(priv); 5807 if (err) 5808 goto profile_cleanup; 5809 return err; 5810 5811 profile_cleanup: 5812 new_profile->cleanup(priv); 5813 priv_cleanup: 5814 mlx5e_priv_cleanup(priv); 5815 return err; 5816 } 5817 5818 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv, 5819 const struct mlx5e_profile *new_profile, void *new_ppriv) 5820 { 5821 const struct mlx5e_profile *orig_profile = priv->profile; 5822 struct net_device *netdev = priv->netdev; 5823 struct mlx5_core_dev *mdev = priv->mdev; 5824 void *orig_ppriv = priv->ppriv; 5825 int err, rollback_err; 5826 5827 /* cleanup old profile */ 5828 mlx5e_detach_netdev(priv); 5829 priv->profile->cleanup(priv); 5830 mlx5e_priv_cleanup(priv); 5831 5832 err = mlx5e_netdev_attach_profile(netdev, mdev, new_profile, new_ppriv); 5833 if (err) { /* roll back to original profile */ 5834 netdev_warn(netdev, "%s: new profile init failed, %d\n", __func__, err); 5835 goto rollback; 5836 } 5837 5838 return 0; 5839 5840 rollback: 5841 rollback_err = mlx5e_netdev_attach_profile(netdev, mdev, orig_profile, orig_ppriv); 5842 if (rollback_err) 5843 netdev_err(netdev, "%s: failed to rollback to orig profile, %d\n", 5844 __func__, rollback_err); 5845 return err; 5846 } 5847 5848 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv) 5849 { 5850 mlx5e_netdev_change_profile(priv, &mlx5e_nic_profile, NULL); 5851 } 5852 5853 void mlx5e_destroy_netdev(struct mlx5e_priv *priv) 5854 { 5855 struct net_device *netdev = priv->netdev; 5856 5857 mlx5e_priv_cleanup(priv); 5858 free_netdev(netdev); 5859 } 5860 5861 static int mlx5e_resume(struct auxiliary_device *adev) 5862 { 5863 struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev); 5864 struct mlx5e_priv *priv = auxiliary_get_drvdata(adev); 5865 struct net_device *netdev = priv->netdev; 5866 struct mlx5_core_dev *mdev = edev->mdev; 5867 int err; 5868 5869 if (netif_device_present(netdev)) 5870 return 0; 5871 5872 err = mlx5e_create_mdev_resources(mdev); 5873 if (err) 5874 return err; 5875 5876 err = mlx5e_attach_netdev(priv); 5877 if (err) { 5878 mlx5e_destroy_mdev_resources(mdev); 5879 return err; 5880 } 5881 5882 return 0; 5883 } 5884 5885 static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state) 5886 { 5887 struct mlx5e_priv *priv = auxiliary_get_drvdata(adev); 5888 struct net_device *netdev = priv->netdev; 5889 struct mlx5_core_dev *mdev = priv->mdev; 5890 5891 if (!netif_device_present(netdev)) 5892 return -ENODEV; 5893 5894 mlx5e_detach_netdev(priv); 5895 mlx5e_destroy_mdev_resources(mdev); 5896 return 0; 5897 } 5898 5899 static int mlx5e_probe(struct auxiliary_device *adev, 5900 const struct auxiliary_device_id *id) 5901 { 5902 struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev); 5903 const struct mlx5e_profile *profile = &mlx5e_nic_profile; 5904 struct mlx5_core_dev *mdev = edev->mdev; 5905 struct net_device *netdev; 5906 pm_message_t state = {}; 5907 struct mlx5e_priv *priv; 5908 int err; 5909 5910 netdev = mlx5e_create_netdev(mdev, profile); 5911 if (!netdev) { 5912 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n"); 5913 return -ENOMEM; 5914 } 5915 5916 mlx5e_build_nic_netdev(netdev); 5917 5918 priv = netdev_priv(netdev); 5919 auxiliary_set_drvdata(adev, priv); 5920 5921 priv->profile = profile; 5922 priv->ppriv = NULL; 5923 5924 err = mlx5e_devlink_port_register(priv); 5925 if (err) { 5926 mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err); 5927 goto err_destroy_netdev; 5928 } 5929 5930 err = profile->init(mdev, netdev); 5931 if (err) { 5932 mlx5_core_err(mdev, "mlx5e_nic_profile init failed, %d\n", err); 5933 goto err_devlink_cleanup; 5934 } 5935 5936 err = mlx5e_resume(adev); 5937 if (err) { 5938 mlx5_core_err(mdev, "mlx5e_resume failed, %d\n", err); 5939 goto err_profile_cleanup; 5940 } 5941 5942 err = register_netdev(netdev); 5943 if (err) { 5944 mlx5_core_err(mdev, "register_netdev failed, %d\n", err); 5945 goto err_resume; 5946 } 5947 5948 mlx5e_devlink_port_type_eth_set(priv); 5949 5950 mlx5e_dcbnl_init_app(priv); 5951 mlx5_uplink_netdev_set(mdev, netdev); 5952 return 0; 5953 5954 err_resume: 5955 mlx5e_suspend(adev, state); 5956 err_profile_cleanup: 5957 profile->cleanup(priv); 5958 err_devlink_cleanup: 5959 mlx5e_devlink_port_unregister(priv); 5960 err_destroy_netdev: 5961 mlx5e_destroy_netdev(priv); 5962 return err; 5963 } 5964 5965 static void mlx5e_remove(struct auxiliary_device *adev) 5966 { 5967 struct mlx5e_priv *priv = auxiliary_get_drvdata(adev); 5968 pm_message_t state = {}; 5969 5970 mlx5e_dcbnl_delete_app(priv); 5971 unregister_netdev(priv->netdev); 5972 mlx5e_suspend(adev, state); 5973 priv->profile->cleanup(priv); 5974 mlx5e_devlink_port_unregister(priv); 5975 mlx5e_destroy_netdev(priv); 5976 } 5977 5978 static const struct auxiliary_device_id mlx5e_id_table[] = { 5979 { .name = MLX5_ADEV_NAME ".eth", }, 5980 {}, 5981 }; 5982 5983 MODULE_DEVICE_TABLE(auxiliary, mlx5e_id_table); 5984 5985 static struct auxiliary_driver mlx5e_driver = { 5986 .name = "eth", 5987 .probe = mlx5e_probe, 5988 .remove = mlx5e_remove, 5989 .suspend = mlx5e_suspend, 5990 .resume = mlx5e_resume, 5991 .id_table = mlx5e_id_table, 5992 }; 5993 5994 int mlx5e_init(void) 5995 { 5996 int ret; 5997 5998 mlx5e_build_ptys2ethtool_map(); 5999 ret = auxiliary_driver_register(&mlx5e_driver); 6000 if (ret) 6001 return ret; 6002 6003 ret = mlx5e_rep_init(); 6004 if (ret) 6005 auxiliary_driver_unregister(&mlx5e_driver); 6006 return ret; 6007 } 6008 6009 void mlx5e_cleanup(void) 6010 { 6011 mlx5e_rep_cleanup(); 6012 auxiliary_driver_unregister(&mlx5e_driver); 6013 } 6014