1 /* 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <net/tc_act/tc_gact.h> 34 #include <net/pkt_cls.h> 35 #include <linux/mlx5/fs.h> 36 #include <net/vxlan.h> 37 #include <net/geneve.h> 38 #include <linux/bpf.h> 39 #include <linux/if_bridge.h> 40 #include <net/page_pool.h> 41 #include <net/xdp_sock_drv.h> 42 #include "eswitch.h" 43 #include "en.h" 44 #include "en/txrx.h" 45 #include "en_tc.h" 46 #include "en_rep.h" 47 #include "en_accel/ipsec.h" 48 #include "en_accel/en_accel.h" 49 #include "en_accel/tls.h" 50 #include "accel/ipsec.h" 51 #include "accel/tls.h" 52 #include "lib/vxlan.h" 53 #include "lib/clock.h" 54 #include "en/port.h" 55 #include "en/xdp.h" 56 #include "lib/eq.h" 57 #include "en/monitor_stats.h" 58 #include "en/health.h" 59 #include "en/params.h" 60 #include "en/xsk/pool.h" 61 #include "en/xsk/setup.h" 62 #include "en/xsk/rx.h" 63 #include "en/xsk/tx.h" 64 #include "en/hv_vhca_stats.h" 65 #include "en/devlink.h" 66 #include "lib/mlx5.h" 67 #include "en/ptp.h" 68 #include "qos.h" 69 #include "en/trap.h" 70 #include "fpga/ipsec.h" 71 72 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev) 73 { 74 bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) && 75 MLX5_CAP_GEN(mdev, umr_ptr_rlky) && 76 MLX5_CAP_ETH(mdev, reg_umr_sq); 77 u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq); 78 bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap; 79 80 if (!striding_rq_umr) 81 return false; 82 if (!inline_umr) { 83 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n", 84 (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap); 85 return false; 86 } 87 return true; 88 } 89 90 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev, 91 struct mlx5e_params *params) 92 { 93 params->log_rq_mtu_frames = is_kdump_kernel() ? 94 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE : 95 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE; 96 97 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n", 98 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ, 99 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ? 100 BIT(mlx5e_mpwqe_get_log_rq_size(params, NULL)) : 101 BIT(params->log_rq_mtu_frames), 102 BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL)), 103 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)); 104 } 105 106 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev, 107 struct mlx5e_params *params) 108 { 109 if (!mlx5e_check_fragmented_striding_rq_cap(mdev)) 110 return false; 111 112 if (mlx5_fpga_is_ipsec_device(mdev)) 113 return false; 114 115 if (params->xdp_prog) { 116 /* XSK params are not considered here. If striding RQ is in use, 117 * and an XSK is being opened, mlx5e_rx_mpwqe_is_linear_skb will 118 * be called with the known XSK params. 119 */ 120 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL)) 121 return false; 122 } 123 124 return true; 125 } 126 127 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params) 128 { 129 params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) && 130 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ? 131 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ : 132 MLX5_WQ_TYPE_CYCLIC; 133 } 134 135 void mlx5e_update_carrier(struct mlx5e_priv *priv) 136 { 137 struct mlx5_core_dev *mdev = priv->mdev; 138 u8 port_state; 139 140 port_state = mlx5_query_vport_state(mdev, 141 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT, 142 0); 143 144 if (port_state == VPORT_STATE_UP) { 145 netdev_info(priv->netdev, "Link up\n"); 146 netif_carrier_on(priv->netdev); 147 } else { 148 netdev_info(priv->netdev, "Link down\n"); 149 netif_carrier_off(priv->netdev); 150 } 151 } 152 153 static void mlx5e_update_carrier_work(struct work_struct *work) 154 { 155 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, 156 update_carrier_work); 157 158 mutex_lock(&priv->state_lock); 159 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) 160 if (priv->profile->update_carrier) 161 priv->profile->update_carrier(priv); 162 mutex_unlock(&priv->state_lock); 163 } 164 165 static void mlx5e_update_stats_work(struct work_struct *work) 166 { 167 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, 168 update_stats_work); 169 170 mutex_lock(&priv->state_lock); 171 priv->profile->update_stats(priv); 172 mutex_unlock(&priv->state_lock); 173 } 174 175 void mlx5e_queue_update_stats(struct mlx5e_priv *priv) 176 { 177 if (!priv->profile->update_stats) 178 return; 179 180 if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state))) 181 return; 182 183 queue_work(priv->wq, &priv->update_stats_work); 184 } 185 186 static int async_event(struct notifier_block *nb, unsigned long event, void *data) 187 { 188 struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb); 189 struct mlx5_eqe *eqe = data; 190 191 if (event != MLX5_EVENT_TYPE_PORT_CHANGE) 192 return NOTIFY_DONE; 193 194 switch (eqe->sub_type) { 195 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 196 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 197 queue_work(priv->wq, &priv->update_carrier_work); 198 break; 199 default: 200 return NOTIFY_DONE; 201 } 202 203 return NOTIFY_OK; 204 } 205 206 static void mlx5e_enable_async_events(struct mlx5e_priv *priv) 207 { 208 priv->events_nb.notifier_call = async_event; 209 mlx5_notifier_register(priv->mdev, &priv->events_nb); 210 } 211 212 static void mlx5e_disable_async_events(struct mlx5e_priv *priv) 213 { 214 mlx5_notifier_unregister(priv->mdev, &priv->events_nb); 215 } 216 217 static int blocking_event(struct notifier_block *nb, unsigned long event, void *data) 218 { 219 struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, blocking_events_nb); 220 int err; 221 222 switch (event) { 223 case MLX5_DRIVER_EVENT_TYPE_TRAP: 224 err = mlx5e_handle_trap_event(priv, data); 225 break; 226 default: 227 netdev_warn(priv->netdev, "Sync event: Unknown event %ld\n", event); 228 err = -EINVAL; 229 } 230 return err; 231 } 232 233 static void mlx5e_enable_blocking_events(struct mlx5e_priv *priv) 234 { 235 priv->blocking_events_nb.notifier_call = blocking_event; 236 mlx5_blocking_notifier_register(priv->mdev, &priv->blocking_events_nb); 237 } 238 239 static void mlx5e_disable_blocking_events(struct mlx5e_priv *priv) 240 { 241 mlx5_blocking_notifier_unregister(priv->mdev, &priv->blocking_events_nb); 242 } 243 244 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, 245 struct mlx5e_icosq *sq, 246 struct mlx5e_umr_wqe *wqe) 247 { 248 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; 249 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl; 250 u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS); 251 252 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) | 253 ds_cnt); 254 cseg->umr_mkey = rq->mkey_be; 255 256 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE; 257 ucseg->xlt_octowords = 258 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE)); 259 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); 260 } 261 262 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, 263 struct mlx5e_channel *c) 264 { 265 int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq); 266 267 rq->mpwqe.info = kvzalloc_node(array_size(wq_sz, 268 sizeof(*rq->mpwqe.info)), 269 GFP_KERNEL, cpu_to_node(c->cpu)); 270 if (!rq->mpwqe.info) 271 return -ENOMEM; 272 273 mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe); 274 275 return 0; 276 } 277 278 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev, 279 u64 npages, u8 page_shift, 280 struct mlx5_core_mkey *umr_mkey, 281 dma_addr_t filler_addr) 282 { 283 struct mlx5_mtt *mtt; 284 int inlen; 285 void *mkc; 286 u32 *in; 287 int err; 288 int i; 289 290 inlen = MLX5_ST_SZ_BYTES(create_mkey_in) + sizeof(*mtt) * npages; 291 292 in = kvzalloc(inlen, GFP_KERNEL); 293 if (!in) 294 return -ENOMEM; 295 296 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 297 298 MLX5_SET(mkc, mkc, free, 1); 299 MLX5_SET(mkc, mkc, umr_en, 1); 300 MLX5_SET(mkc, mkc, lw, 1); 301 MLX5_SET(mkc, mkc, lr, 1); 302 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 303 mlx5e_mkey_set_relaxed_ordering(mdev, mkc); 304 MLX5_SET(mkc, mkc, qpn, 0xffffff); 305 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn); 306 MLX5_SET64(mkc, mkc, len, npages << page_shift); 307 MLX5_SET(mkc, mkc, translations_octword_size, 308 MLX5_MTT_OCTW(npages)); 309 MLX5_SET(mkc, mkc, log_page_size, page_shift); 310 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 311 MLX5_MTT_OCTW(npages)); 312 313 /* Initialize the mkey with all MTTs pointing to a default 314 * page (filler_addr). When the channels are activated, UMR 315 * WQEs will redirect the RX WQEs to the actual memory from 316 * the RQ's pool, while the gaps (wqe_overflow) remain mapped 317 * to the default page. 318 */ 319 mtt = MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt); 320 for (i = 0 ; i < npages ; i++) 321 mtt[i].ptag = cpu_to_be64(filler_addr); 322 323 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen); 324 325 kvfree(in); 326 return err; 327 } 328 329 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq) 330 { 331 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq)); 332 333 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey, 334 rq->wqe_overflow.addr); 335 } 336 337 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix) 338 { 339 return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT; 340 } 341 342 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq) 343 { 344 struct mlx5e_wqe_frag_info next_frag = {}; 345 struct mlx5e_wqe_frag_info *prev = NULL; 346 int i; 347 348 next_frag.di = &rq->wqe.di[0]; 349 350 for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) { 351 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0]; 352 struct mlx5e_wqe_frag_info *frag = 353 &rq->wqe.frags[i << rq->wqe.info.log_num_frags]; 354 int f; 355 356 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) { 357 if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) { 358 next_frag.di++; 359 next_frag.offset = 0; 360 if (prev) 361 prev->last_in_page = true; 362 } 363 *frag = next_frag; 364 365 /* prepare next */ 366 next_frag.offset += frag_info[f].frag_stride; 367 prev = frag; 368 } 369 } 370 371 if (prev) 372 prev->last_in_page = true; 373 } 374 375 int mlx5e_init_di_list(struct mlx5e_rq *rq, int wq_sz, int node) 376 { 377 int len = wq_sz << rq->wqe.info.log_num_frags; 378 379 rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)), GFP_KERNEL, node); 380 if (!rq->wqe.di) 381 return -ENOMEM; 382 383 mlx5e_init_frags_partition(rq); 384 385 return 0; 386 } 387 388 void mlx5e_free_di_list(struct mlx5e_rq *rq) 389 { 390 kvfree(rq->wqe.di); 391 } 392 393 static void mlx5e_rq_err_cqe_work(struct work_struct *recover_work) 394 { 395 struct mlx5e_rq *rq = container_of(recover_work, struct mlx5e_rq, recover_work); 396 397 mlx5e_reporter_rq_cqe_err(rq); 398 } 399 400 static int mlx5e_alloc_mpwqe_rq_drop_page(struct mlx5e_rq *rq) 401 { 402 rq->wqe_overflow.page = alloc_page(GFP_KERNEL); 403 if (!rq->wqe_overflow.page) 404 return -ENOMEM; 405 406 rq->wqe_overflow.addr = dma_map_page(rq->pdev, rq->wqe_overflow.page, 0, 407 PAGE_SIZE, rq->buff.map_dir); 408 if (dma_mapping_error(rq->pdev, rq->wqe_overflow.addr)) { 409 __free_page(rq->wqe_overflow.page); 410 return -ENOMEM; 411 } 412 return 0; 413 } 414 415 static void mlx5e_free_mpwqe_rq_drop_page(struct mlx5e_rq *rq) 416 { 417 dma_unmap_page(rq->pdev, rq->wqe_overflow.addr, PAGE_SIZE, 418 rq->buff.map_dir); 419 __free_page(rq->wqe_overflow.page); 420 } 421 422 static int mlx5e_alloc_rq(struct mlx5e_channel *c, 423 struct mlx5e_params *params, 424 struct mlx5e_xsk_param *xsk, 425 struct xsk_buff_pool *xsk_pool, 426 struct mlx5e_rq_param *rqp, 427 struct mlx5e_rq *rq) 428 { 429 struct page_pool_params pp_params = { 0 }; 430 struct mlx5_core_dev *mdev = c->mdev; 431 void *rqc = rqp->rqc; 432 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); 433 u32 rq_xdp_ix; 434 u32 pool_size; 435 int wq_sz; 436 int err; 437 int i; 438 439 rqp->wq.db_numa_node = cpu_to_node(c->cpu); 440 441 rq->wq_type = params->rq_wq_type; 442 rq->pdev = c->pdev; 443 rq->netdev = c->netdev; 444 rq->priv = c->priv; 445 rq->tstamp = c->tstamp; 446 rq->clock = &mdev->clock; 447 rq->icosq = &c->icosq; 448 rq->ix = c->ix; 449 rq->mdev = mdev; 450 rq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu); 451 rq->xdpsq = &c->rq_xdpsq; 452 rq->xsk_pool = xsk_pool; 453 rq->ptp_cyc2time = mlx5_is_real_time_rq(mdev) ? 454 mlx5_real_time_cyc2time : 455 mlx5_timecounter_cyc2time; 456 457 if (rq->xsk_pool) 458 rq->stats = &c->priv->channel_stats[c->ix].xskrq; 459 else 460 rq->stats = &c->priv->channel_stats[c->ix].rq; 461 INIT_WORK(&rq->recover_work, mlx5e_rq_err_cqe_work); 462 463 if (params->xdp_prog) 464 bpf_prog_inc(params->xdp_prog); 465 RCU_INIT_POINTER(rq->xdp_prog, params->xdp_prog); 466 467 rq_xdp_ix = rq->ix; 468 if (xsk) 469 rq_xdp_ix += params->num_channels * MLX5E_RQ_GROUP_XSK; 470 err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq_xdp_ix, 0); 471 if (err < 0) 472 goto err_rq_xdp_prog; 473 474 rq->buff.map_dir = params->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; 475 rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params, xsk); 476 pool_size = 1 << params->log_rq_mtu_frames; 477 478 switch (rq->wq_type) { 479 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 480 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq, 481 &rq->wq_ctrl); 482 if (err) 483 goto err_rq_xdp; 484 485 err = mlx5e_alloc_mpwqe_rq_drop_page(rq); 486 if (err) 487 goto err_rq_wq_destroy; 488 489 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR]; 490 491 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq); 492 493 pool_size = MLX5_MPWRQ_PAGES_PER_WQE << 494 mlx5e_mpwqe_get_log_rq_size(params, xsk); 495 496 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk); 497 rq->mpwqe.num_strides = 498 BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk)); 499 500 rq->buff.frame0_sz = (1 << rq->mpwqe.log_stride_sz); 501 502 err = mlx5e_create_rq_umr_mkey(mdev, rq); 503 if (err) 504 goto err_rq_drop_page; 505 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key); 506 507 err = mlx5e_rq_alloc_mpwqe_info(rq, c); 508 if (err) 509 goto err_rq_mkey; 510 break; 511 default: /* MLX5_WQ_TYPE_CYCLIC */ 512 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq, 513 &rq->wq_ctrl); 514 if (err) 515 goto err_rq_xdp; 516 517 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR]; 518 519 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq); 520 521 rq->wqe.info = rqp->frags_info; 522 rq->buff.frame0_sz = rq->wqe.info.arr[0].frag_stride; 523 524 rq->wqe.frags = 525 kvzalloc_node(array_size(sizeof(*rq->wqe.frags), 526 (wq_sz << rq->wqe.info.log_num_frags)), 527 GFP_KERNEL, cpu_to_node(c->cpu)); 528 if (!rq->wqe.frags) { 529 err = -ENOMEM; 530 goto err_rq_wq_destroy; 531 } 532 533 err = mlx5e_init_di_list(rq, wq_sz, cpu_to_node(c->cpu)); 534 if (err) 535 goto err_rq_frags; 536 537 rq->mkey_be = c->mkey_be; 538 } 539 540 err = mlx5e_rq_set_handlers(rq, params, xsk); 541 if (err) 542 goto err_free_by_rq_type; 543 544 if (xsk) { 545 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq, 546 MEM_TYPE_XSK_BUFF_POOL, NULL); 547 xsk_pool_set_rxq_info(rq->xsk_pool, &rq->xdp_rxq); 548 } else { 549 /* Create a page_pool and register it with rxq */ 550 pp_params.order = 0; 551 pp_params.flags = 0; /* No-internal DMA mapping in page_pool */ 552 pp_params.pool_size = pool_size; 553 pp_params.nid = cpu_to_node(c->cpu); 554 pp_params.dev = c->pdev; 555 pp_params.dma_dir = rq->buff.map_dir; 556 557 /* page_pool can be used even when there is no rq->xdp_prog, 558 * given page_pool does not handle DMA mapping there is no 559 * required state to clear. And page_pool gracefully handle 560 * elevated refcnt. 561 */ 562 rq->page_pool = page_pool_create(&pp_params); 563 if (IS_ERR(rq->page_pool)) { 564 err = PTR_ERR(rq->page_pool); 565 rq->page_pool = NULL; 566 goto err_free_by_rq_type; 567 } 568 err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq, 569 MEM_TYPE_PAGE_POOL, rq->page_pool); 570 } 571 if (err) 572 goto err_free_by_rq_type; 573 574 for (i = 0; i < wq_sz; i++) { 575 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) { 576 struct mlx5e_rx_wqe_ll *wqe = 577 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i); 578 u32 byte_count = 579 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz; 580 u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i); 581 582 wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom); 583 wqe->data[0].byte_count = cpu_to_be32(byte_count); 584 wqe->data[0].lkey = rq->mkey_be; 585 } else { 586 struct mlx5e_rx_wqe_cyc *wqe = 587 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i); 588 int f; 589 590 for (f = 0; f < rq->wqe.info.num_frags; f++) { 591 u32 frag_size = rq->wqe.info.arr[f].frag_size | 592 MLX5_HW_START_PADDING; 593 594 wqe->data[f].byte_count = cpu_to_be32(frag_size); 595 wqe->data[f].lkey = rq->mkey_be; 596 } 597 /* check if num_frags is not a pow of two */ 598 if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) { 599 wqe->data[f].byte_count = 0; 600 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY); 601 wqe->data[f].addr = 0; 602 } 603 } 604 } 605 606 INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work); 607 608 switch (params->rx_cq_moderation.cq_period_mode) { 609 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE: 610 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE; 611 break; 612 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE: 613 default: 614 rq->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 615 } 616 617 rq->page_cache.head = 0; 618 rq->page_cache.tail = 0; 619 620 return 0; 621 622 err_free_by_rq_type: 623 switch (rq->wq_type) { 624 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 625 kvfree(rq->mpwqe.info); 626 err_rq_mkey: 627 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey); 628 err_rq_drop_page: 629 mlx5e_free_mpwqe_rq_drop_page(rq); 630 break; 631 default: /* MLX5_WQ_TYPE_CYCLIC */ 632 mlx5e_free_di_list(rq); 633 err_rq_frags: 634 kvfree(rq->wqe.frags); 635 } 636 err_rq_wq_destroy: 637 mlx5_wq_destroy(&rq->wq_ctrl); 638 err_rq_xdp: 639 xdp_rxq_info_unreg(&rq->xdp_rxq); 640 err_rq_xdp_prog: 641 if (params->xdp_prog) 642 bpf_prog_put(params->xdp_prog); 643 644 return err; 645 } 646 647 static void mlx5e_free_rq(struct mlx5e_rq *rq) 648 { 649 struct bpf_prog *old_prog; 650 int i; 651 652 old_prog = rcu_dereference_protected(rq->xdp_prog, 653 lockdep_is_held(&rq->priv->state_lock)); 654 if (old_prog) 655 bpf_prog_put(old_prog); 656 657 switch (rq->wq_type) { 658 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 659 kvfree(rq->mpwqe.info); 660 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey); 661 mlx5e_free_mpwqe_rq_drop_page(rq); 662 break; 663 default: /* MLX5_WQ_TYPE_CYCLIC */ 664 kvfree(rq->wqe.frags); 665 mlx5e_free_di_list(rq); 666 } 667 668 for (i = rq->page_cache.head; i != rq->page_cache.tail; 669 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) { 670 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i]; 671 672 /* With AF_XDP, page_cache is not used, so this loop is not 673 * entered, and it's safe to call mlx5e_page_release_dynamic 674 * directly. 675 */ 676 mlx5e_page_release_dynamic(rq, dma_info, false); 677 } 678 679 xdp_rxq_info_unreg(&rq->xdp_rxq); 680 page_pool_destroy(rq->page_pool); 681 mlx5_wq_destroy(&rq->wq_ctrl); 682 } 683 684 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param) 685 { 686 struct mlx5_core_dev *mdev = rq->mdev; 687 u8 ts_format; 688 void *in; 689 void *rqc; 690 void *wq; 691 int inlen; 692 int err; 693 694 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + 695 sizeof(u64) * rq->wq_ctrl.buf.npages; 696 in = kvzalloc(inlen, GFP_KERNEL); 697 if (!in) 698 return -ENOMEM; 699 700 ts_format = mlx5_is_real_time_rq(mdev) ? 701 MLX5_RQC_TIMESTAMP_FORMAT_REAL_TIME : 702 MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING; 703 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); 704 wq = MLX5_ADDR_OF(rqc, rqc, wq); 705 706 memcpy(rqc, param->rqc, sizeof(param->rqc)); 707 708 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn); 709 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); 710 MLX5_SET(rqc, rqc, ts_format, ts_format); 711 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift - 712 MLX5_ADAPTER_PAGE_SHIFT); 713 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma); 714 715 mlx5_fill_page_frag_array(&rq->wq_ctrl.buf, 716 (__be64 *)MLX5_ADDR_OF(wq, wq, pas)); 717 718 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn); 719 720 kvfree(in); 721 722 return err; 723 } 724 725 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state) 726 { 727 struct mlx5_core_dev *mdev = rq->mdev; 728 729 void *in; 730 void *rqc; 731 int inlen; 732 int err; 733 734 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 735 in = kvzalloc(inlen, GFP_KERNEL); 736 if (!in) 737 return -ENOMEM; 738 739 if (curr_state == MLX5_RQC_STATE_RST && next_state == MLX5_RQC_STATE_RDY) 740 mlx5e_rqwq_reset(rq); 741 742 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 743 744 MLX5_SET(modify_rq_in, in, rq_state, curr_state); 745 MLX5_SET(rqc, rqc, state, next_state); 746 747 err = mlx5_core_modify_rq(mdev, rq->rqn, in); 748 749 kvfree(in); 750 751 return err; 752 } 753 754 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable) 755 { 756 struct mlx5_core_dev *mdev = rq->mdev; 757 758 void *in; 759 void *rqc; 760 int inlen; 761 int err; 762 763 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 764 in = kvzalloc(inlen, GFP_KERNEL); 765 if (!in) 766 return -ENOMEM; 767 768 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 769 770 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY); 771 MLX5_SET64(modify_rq_in, in, modify_bitmask, 772 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS); 773 MLX5_SET(rqc, rqc, scatter_fcs, enable); 774 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY); 775 776 err = mlx5_core_modify_rq(mdev, rq->rqn, in); 777 778 kvfree(in); 779 780 return err; 781 } 782 783 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd) 784 { 785 struct mlx5_core_dev *mdev = rq->mdev; 786 void *in; 787 void *rqc; 788 int inlen; 789 int err; 790 791 inlen = MLX5_ST_SZ_BYTES(modify_rq_in); 792 in = kvzalloc(inlen, GFP_KERNEL); 793 if (!in) 794 return -ENOMEM; 795 796 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); 797 798 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY); 799 MLX5_SET64(modify_rq_in, in, modify_bitmask, 800 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); 801 MLX5_SET(rqc, rqc, vsd, vsd); 802 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY); 803 804 err = mlx5_core_modify_rq(mdev, rq->rqn, in); 805 806 kvfree(in); 807 808 return err; 809 } 810 811 void mlx5e_destroy_rq(struct mlx5e_rq *rq) 812 { 813 mlx5_core_destroy_rq(rq->mdev, rq->rqn); 814 } 815 816 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time) 817 { 818 unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time); 819 820 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq)); 821 822 do { 823 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes) 824 return 0; 825 826 msleep(20); 827 } while (time_before(jiffies, exp_time)); 828 829 netdev_warn(rq->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n", 830 rq->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes); 831 832 mlx5e_reporter_rx_timeout(rq); 833 return -ETIMEDOUT; 834 } 835 836 void mlx5e_free_rx_in_progress_descs(struct mlx5e_rq *rq) 837 { 838 struct mlx5_wq_ll *wq; 839 u16 head; 840 int i; 841 842 if (rq->wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) 843 return; 844 845 wq = &rq->mpwqe.wq; 846 head = wq->head; 847 848 /* Outstanding UMR WQEs (in progress) start at wq->head */ 849 for (i = 0; i < rq->mpwqe.umr_in_progress; i++) { 850 rq->dealloc_wqe(rq, head); 851 head = mlx5_wq_ll_get_wqe_next_ix(wq, head); 852 } 853 854 rq->mpwqe.actual_wq_head = wq->head; 855 rq->mpwqe.umr_in_progress = 0; 856 rq->mpwqe.umr_completed = 0; 857 } 858 859 void mlx5e_free_rx_descs(struct mlx5e_rq *rq) 860 { 861 __be16 wqe_ix_be; 862 u16 wqe_ix; 863 864 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) { 865 struct mlx5_wq_ll *wq = &rq->mpwqe.wq; 866 867 mlx5e_free_rx_in_progress_descs(rq); 868 869 while (!mlx5_wq_ll_is_empty(wq)) { 870 struct mlx5e_rx_wqe_ll *wqe; 871 872 wqe_ix_be = *wq->tail_next; 873 wqe_ix = be16_to_cpu(wqe_ix_be); 874 wqe = mlx5_wq_ll_get_wqe(wq, wqe_ix); 875 rq->dealloc_wqe(rq, wqe_ix); 876 mlx5_wq_ll_pop(wq, wqe_ix_be, 877 &wqe->next.next_wqe_index); 878 } 879 } else { 880 struct mlx5_wq_cyc *wq = &rq->wqe.wq; 881 882 while (!mlx5_wq_cyc_is_empty(wq)) { 883 wqe_ix = mlx5_wq_cyc_get_tail(wq); 884 rq->dealloc_wqe(rq, wqe_ix); 885 mlx5_wq_cyc_pop(wq); 886 } 887 } 888 889 } 890 891 int mlx5e_open_rq(struct mlx5e_channel *c, struct mlx5e_params *params, 892 struct mlx5e_rq_param *param, struct mlx5e_xsk_param *xsk, 893 struct xsk_buff_pool *xsk_pool, struct mlx5e_rq *rq) 894 { 895 int err; 896 897 err = mlx5e_alloc_rq(c, params, xsk, xsk_pool, param, rq); 898 if (err) 899 return err; 900 901 err = mlx5e_create_rq(rq, param); 902 if (err) 903 goto err_free_rq; 904 905 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 906 if (err) 907 goto err_destroy_rq; 908 909 if (mlx5e_is_tls_on(c->priv) && !mlx5_accel_is_ktls_device(c->mdev)) 910 __set_bit(MLX5E_RQ_STATE_FPGA_TLS, &c->rq.state); /* must be FPGA */ 911 912 if (MLX5_CAP_ETH(c->mdev, cqe_checksum_full)) 913 __set_bit(MLX5E_RQ_STATE_CSUM_FULL, &c->rq.state); 914 915 if (params->rx_dim_enabled) 916 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state); 917 918 /* We disable csum_complete when XDP is enabled since 919 * XDP programs might manipulate packets which will render 920 * skb->checksum incorrect. 921 */ 922 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || c->xdp) 923 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state); 924 925 /* For CQE compression on striding RQ, use stride index provided by 926 * HW if capability is supported. 927 */ 928 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) && 929 MLX5_CAP_GEN(c->mdev, mini_cqe_resp_stride_index)) 930 __set_bit(MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, &c->rq.state); 931 932 return 0; 933 934 err_destroy_rq: 935 mlx5e_destroy_rq(rq); 936 err_free_rq: 937 mlx5e_free_rq(rq); 938 939 return err; 940 } 941 942 void mlx5e_activate_rq(struct mlx5e_rq *rq) 943 { 944 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state); 945 mlx5e_trigger_irq(rq->icosq); 946 } 947 948 void mlx5e_deactivate_rq(struct mlx5e_rq *rq) 949 { 950 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state); 951 synchronize_net(); /* Sync with NAPI to prevent mlx5e_post_rx_wqes. */ 952 } 953 954 void mlx5e_close_rq(struct mlx5e_rq *rq) 955 { 956 cancel_work_sync(&rq->dim.work); 957 cancel_work_sync(&rq->icosq->recover_work); 958 cancel_work_sync(&rq->recover_work); 959 mlx5e_destroy_rq(rq); 960 mlx5e_free_rx_descs(rq); 961 mlx5e_free_rq(rq); 962 } 963 964 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq) 965 { 966 kvfree(sq->db.xdpi_fifo.xi); 967 kvfree(sq->db.wqe_info); 968 } 969 970 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa) 971 { 972 struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo; 973 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 974 int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS; 975 976 xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq, 977 GFP_KERNEL, numa); 978 if (!xdpi_fifo->xi) 979 return -ENOMEM; 980 981 xdpi_fifo->pc = &sq->xdpi_fifo_pc; 982 xdpi_fifo->cc = &sq->xdpi_fifo_cc; 983 xdpi_fifo->mask = dsegs_per_wq - 1; 984 985 return 0; 986 } 987 988 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa) 989 { 990 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 991 int err; 992 993 sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz, 994 GFP_KERNEL, numa); 995 if (!sq->db.wqe_info) 996 return -ENOMEM; 997 998 err = mlx5e_alloc_xdpsq_fifo(sq, numa); 999 if (err) { 1000 mlx5e_free_xdpsq_db(sq); 1001 return err; 1002 } 1003 1004 return 0; 1005 } 1006 1007 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c, 1008 struct mlx5e_params *params, 1009 struct xsk_buff_pool *xsk_pool, 1010 struct mlx5e_sq_param *param, 1011 struct mlx5e_xdpsq *sq, 1012 bool is_redirect) 1013 { 1014 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq); 1015 struct mlx5_core_dev *mdev = c->mdev; 1016 struct mlx5_wq_cyc *wq = &sq->wq; 1017 int err; 1018 1019 sq->pdev = c->pdev; 1020 sq->mkey_be = c->mkey_be; 1021 sq->channel = c; 1022 sq->uar_map = mdev->mlx5e_res.bfreg.map; 1023 sq->min_inline_mode = params->tx_min_inline_mode; 1024 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu); 1025 sq->xsk_pool = xsk_pool; 1026 1027 sq->stats = sq->xsk_pool ? 1028 &c->priv->channel_stats[c->ix].xsksq : 1029 is_redirect ? 1030 &c->priv->channel_stats[c->ix].xdpsq : 1031 &c->priv->channel_stats[c->ix].rq_xdpsq; 1032 1033 param->wq.db_numa_node = cpu_to_node(c->cpu); 1034 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl); 1035 if (err) 1036 return err; 1037 wq->db = &wq->db[MLX5_SND_DBR]; 1038 1039 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu)); 1040 if (err) 1041 goto err_sq_wq_destroy; 1042 1043 return 0; 1044 1045 err_sq_wq_destroy: 1046 mlx5_wq_destroy(&sq->wq_ctrl); 1047 1048 return err; 1049 } 1050 1051 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq) 1052 { 1053 mlx5e_free_xdpsq_db(sq); 1054 mlx5_wq_destroy(&sq->wq_ctrl); 1055 } 1056 1057 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq) 1058 { 1059 kvfree(sq->db.wqe_info); 1060 } 1061 1062 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa) 1063 { 1064 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1065 size_t size; 1066 1067 size = array_size(wq_sz, sizeof(*sq->db.wqe_info)); 1068 sq->db.wqe_info = kvzalloc_node(size, GFP_KERNEL, numa); 1069 if (!sq->db.wqe_info) 1070 return -ENOMEM; 1071 1072 return 0; 1073 } 1074 1075 static void mlx5e_icosq_err_cqe_work(struct work_struct *recover_work) 1076 { 1077 struct mlx5e_icosq *sq = container_of(recover_work, struct mlx5e_icosq, 1078 recover_work); 1079 1080 mlx5e_reporter_icosq_cqe_err(sq); 1081 } 1082 1083 static int mlx5e_alloc_icosq(struct mlx5e_channel *c, 1084 struct mlx5e_sq_param *param, 1085 struct mlx5e_icosq *sq) 1086 { 1087 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq); 1088 struct mlx5_core_dev *mdev = c->mdev; 1089 struct mlx5_wq_cyc *wq = &sq->wq; 1090 int err; 1091 1092 sq->channel = c; 1093 sq->uar_map = mdev->mlx5e_res.bfreg.map; 1094 1095 param->wq.db_numa_node = cpu_to_node(c->cpu); 1096 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl); 1097 if (err) 1098 return err; 1099 wq->db = &wq->db[MLX5_SND_DBR]; 1100 1101 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu)); 1102 if (err) 1103 goto err_sq_wq_destroy; 1104 1105 INIT_WORK(&sq->recover_work, mlx5e_icosq_err_cqe_work); 1106 1107 return 0; 1108 1109 err_sq_wq_destroy: 1110 mlx5_wq_destroy(&sq->wq_ctrl); 1111 1112 return err; 1113 } 1114 1115 static void mlx5e_free_icosq(struct mlx5e_icosq *sq) 1116 { 1117 mlx5e_free_icosq_db(sq); 1118 mlx5_wq_destroy(&sq->wq_ctrl); 1119 } 1120 1121 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq) 1122 { 1123 kvfree(sq->db.wqe_info); 1124 kvfree(sq->db.skb_fifo.fifo); 1125 kvfree(sq->db.dma_fifo); 1126 } 1127 1128 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa) 1129 { 1130 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); 1131 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS; 1132 1133 sq->db.dma_fifo = kvzalloc_node(array_size(df_sz, 1134 sizeof(*sq->db.dma_fifo)), 1135 GFP_KERNEL, numa); 1136 sq->db.skb_fifo.fifo = kvzalloc_node(array_size(df_sz, 1137 sizeof(*sq->db.skb_fifo.fifo)), 1138 GFP_KERNEL, numa); 1139 sq->db.wqe_info = kvzalloc_node(array_size(wq_sz, 1140 sizeof(*sq->db.wqe_info)), 1141 GFP_KERNEL, numa); 1142 if (!sq->db.dma_fifo || !sq->db.skb_fifo.fifo || !sq->db.wqe_info) { 1143 mlx5e_free_txqsq_db(sq); 1144 return -ENOMEM; 1145 } 1146 1147 sq->dma_fifo_mask = df_sz - 1; 1148 1149 sq->db.skb_fifo.pc = &sq->skb_fifo_pc; 1150 sq->db.skb_fifo.cc = &sq->skb_fifo_cc; 1151 sq->db.skb_fifo.mask = df_sz - 1; 1152 1153 return 0; 1154 } 1155 1156 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c, 1157 int txq_ix, 1158 struct mlx5e_params *params, 1159 struct mlx5e_sq_param *param, 1160 struct mlx5e_txqsq *sq, 1161 int tc) 1162 { 1163 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq); 1164 struct mlx5_core_dev *mdev = c->mdev; 1165 struct mlx5_wq_cyc *wq = &sq->wq; 1166 int err; 1167 1168 sq->pdev = c->pdev; 1169 sq->tstamp = c->tstamp; 1170 sq->clock = &mdev->clock; 1171 sq->mkey_be = c->mkey_be; 1172 sq->netdev = c->netdev; 1173 sq->mdev = c->mdev; 1174 sq->priv = c->priv; 1175 sq->ch_ix = c->ix; 1176 sq->txq_ix = txq_ix; 1177 sq->uar_map = mdev->mlx5e_res.bfreg.map; 1178 sq->min_inline_mode = params->tx_min_inline_mode; 1179 sq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu); 1180 INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work); 1181 if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert)) 1182 set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state); 1183 if (MLX5_IPSEC_DEV(c->priv->mdev)) 1184 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state); 1185 if (mlx5_accel_is_tls_device(c->priv->mdev)) 1186 set_bit(MLX5E_SQ_STATE_TLS, &sq->state); 1187 if (param->is_mpw) 1188 set_bit(MLX5E_SQ_STATE_MPWQE, &sq->state); 1189 sq->stop_room = param->stop_room; 1190 sq->ptp_cyc2time = mlx5_is_real_time_sq(mdev) ? 1191 mlx5_real_time_cyc2time : 1192 mlx5_timecounter_cyc2time; 1193 1194 param->wq.db_numa_node = cpu_to_node(c->cpu); 1195 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, wq, &sq->wq_ctrl); 1196 if (err) 1197 return err; 1198 wq->db = &wq->db[MLX5_SND_DBR]; 1199 1200 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu)); 1201 if (err) 1202 goto err_sq_wq_destroy; 1203 1204 INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work); 1205 sq->dim.mode = params->tx_cq_moderation.cq_period_mode; 1206 1207 return 0; 1208 1209 err_sq_wq_destroy: 1210 mlx5_wq_destroy(&sq->wq_ctrl); 1211 1212 return err; 1213 } 1214 1215 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq) 1216 { 1217 mlx5e_free_txqsq_db(sq); 1218 mlx5_wq_destroy(&sq->wq_ctrl); 1219 } 1220 1221 static int mlx5e_create_sq(struct mlx5_core_dev *mdev, 1222 struct mlx5e_sq_param *param, 1223 struct mlx5e_create_sq_param *csp, 1224 u32 *sqn) 1225 { 1226 u8 ts_format; 1227 void *in; 1228 void *sqc; 1229 void *wq; 1230 int inlen; 1231 int err; 1232 1233 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + 1234 sizeof(u64) * csp->wq_ctrl->buf.npages; 1235 in = kvzalloc(inlen, GFP_KERNEL); 1236 if (!in) 1237 return -ENOMEM; 1238 1239 ts_format = mlx5_is_real_time_sq(mdev) ? 1240 MLX5_SQC_TIMESTAMP_FORMAT_REAL_TIME : 1241 MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING; 1242 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); 1243 wq = MLX5_ADDR_OF(sqc, sqc, wq); 1244 1245 memcpy(sqc, param->sqc, sizeof(param->sqc)); 1246 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz); 1247 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn); 1248 MLX5_SET(sqc, sqc, cqn, csp->cqn); 1249 MLX5_SET(sqc, sqc, ts_cqe_to_dest_cqn, csp->ts_cqe_to_dest_cqn); 1250 MLX5_SET(sqc, sqc, ts_format, ts_format); 1251 1252 1253 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) 1254 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode); 1255 1256 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); 1257 MLX5_SET(sqc, sqc, flush_in_error_en, 1); 1258 1259 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 1260 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index); 1261 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift - 1262 MLX5_ADAPTER_PAGE_SHIFT); 1263 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma); 1264 1265 mlx5_fill_page_frag_array(&csp->wq_ctrl->buf, 1266 (__be64 *)MLX5_ADDR_OF(wq, wq, pas)); 1267 1268 err = mlx5_core_create_sq(mdev, in, inlen, sqn); 1269 1270 kvfree(in); 1271 1272 return err; 1273 } 1274 1275 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn, 1276 struct mlx5e_modify_sq_param *p) 1277 { 1278 u64 bitmask = 0; 1279 void *in; 1280 void *sqc; 1281 int inlen; 1282 int err; 1283 1284 inlen = MLX5_ST_SZ_BYTES(modify_sq_in); 1285 in = kvzalloc(inlen, GFP_KERNEL); 1286 if (!in) 1287 return -ENOMEM; 1288 1289 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1290 1291 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state); 1292 MLX5_SET(sqc, sqc, state, p->next_state); 1293 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) { 1294 bitmask |= 1; 1295 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index); 1296 } 1297 if (p->qos_update && p->next_state == MLX5_SQC_STATE_RDY) { 1298 bitmask |= 1 << 2; 1299 MLX5_SET(sqc, sqc, qos_queue_group_id, p->qos_queue_group_id); 1300 } 1301 MLX5_SET64(modify_sq_in, in, modify_bitmask, bitmask); 1302 1303 err = mlx5_core_modify_sq(mdev, sqn, in); 1304 1305 kvfree(in); 1306 1307 return err; 1308 } 1309 1310 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn) 1311 { 1312 mlx5_core_destroy_sq(mdev, sqn); 1313 } 1314 1315 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev, 1316 struct mlx5e_sq_param *param, 1317 struct mlx5e_create_sq_param *csp, 1318 u16 qos_queue_group_id, 1319 u32 *sqn) 1320 { 1321 struct mlx5e_modify_sq_param msp = {0}; 1322 int err; 1323 1324 err = mlx5e_create_sq(mdev, param, csp, sqn); 1325 if (err) 1326 return err; 1327 1328 msp.curr_state = MLX5_SQC_STATE_RST; 1329 msp.next_state = MLX5_SQC_STATE_RDY; 1330 if (qos_queue_group_id) { 1331 msp.qos_update = true; 1332 msp.qos_queue_group_id = qos_queue_group_id; 1333 } 1334 err = mlx5e_modify_sq(mdev, *sqn, &msp); 1335 if (err) 1336 mlx5e_destroy_sq(mdev, *sqn); 1337 1338 return err; 1339 } 1340 1341 static int mlx5e_set_sq_maxrate(struct net_device *dev, 1342 struct mlx5e_txqsq *sq, u32 rate); 1343 1344 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix, 1345 struct mlx5e_params *params, struct mlx5e_sq_param *param, 1346 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id, u16 qos_qid) 1347 { 1348 struct mlx5e_create_sq_param csp = {}; 1349 u32 tx_rate; 1350 int err; 1351 1352 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc); 1353 if (err) 1354 return err; 1355 1356 if (qos_queue_group_id) 1357 sq->stats = c->priv->htb.qos_sq_stats[qos_qid]; 1358 else 1359 sq->stats = &c->priv->channel_stats[c->ix].sq[tc]; 1360 1361 csp.tisn = tisn; 1362 csp.tis_lst_sz = 1; 1363 csp.cqn = sq->cq.mcq.cqn; 1364 csp.wq_ctrl = &sq->wq_ctrl; 1365 csp.min_inline_mode = sq->min_inline_mode; 1366 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, qos_queue_group_id, &sq->sqn); 1367 if (err) 1368 goto err_free_txqsq; 1369 1370 tx_rate = c->priv->tx_rates[sq->txq_ix]; 1371 if (tx_rate) 1372 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate); 1373 1374 if (params->tx_dim_enabled) 1375 sq->state |= BIT(MLX5E_SQ_STATE_AM); 1376 1377 return 0; 1378 1379 err_free_txqsq: 1380 mlx5e_free_txqsq(sq); 1381 1382 return err; 1383 } 1384 1385 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq) 1386 { 1387 sq->txq = netdev_get_tx_queue(sq->netdev, sq->txq_ix); 1388 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); 1389 netdev_tx_reset_queue(sq->txq); 1390 netif_tx_start_queue(sq->txq); 1391 } 1392 1393 void mlx5e_tx_disable_queue(struct netdev_queue *txq) 1394 { 1395 __netif_tx_lock_bh(txq); 1396 netif_tx_stop_queue(txq); 1397 __netif_tx_unlock_bh(txq); 1398 } 1399 1400 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq) 1401 { 1402 struct mlx5_wq_cyc *wq = &sq->wq; 1403 1404 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); 1405 synchronize_net(); /* Sync with NAPI to prevent netif_tx_wake_queue. */ 1406 1407 mlx5e_tx_disable_queue(sq->txq); 1408 1409 /* last doorbell out, godspeed .. */ 1410 if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) { 1411 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc); 1412 struct mlx5e_tx_wqe *nop; 1413 1414 sq->db.wqe_info[pi] = (struct mlx5e_tx_wqe_info) { 1415 .num_wqebbs = 1, 1416 }; 1417 1418 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc); 1419 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl); 1420 } 1421 } 1422 1423 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq) 1424 { 1425 struct mlx5_core_dev *mdev = sq->mdev; 1426 struct mlx5_rate_limit rl = {0}; 1427 1428 cancel_work_sync(&sq->dim.work); 1429 cancel_work_sync(&sq->recover_work); 1430 mlx5e_destroy_sq(mdev, sq->sqn); 1431 if (sq->rate_limit) { 1432 rl.rate = sq->rate_limit; 1433 mlx5_rl_remove_rate(mdev, &rl); 1434 } 1435 mlx5e_free_txqsq_descs(sq); 1436 mlx5e_free_txqsq(sq); 1437 } 1438 1439 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work) 1440 { 1441 struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq, 1442 recover_work); 1443 1444 mlx5e_reporter_tx_err_cqe(sq); 1445 } 1446 1447 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params, 1448 struct mlx5e_sq_param *param, struct mlx5e_icosq *sq) 1449 { 1450 struct mlx5e_create_sq_param csp = {}; 1451 int err; 1452 1453 err = mlx5e_alloc_icosq(c, param, sq); 1454 if (err) 1455 return err; 1456 1457 csp.cqn = sq->cq.mcq.cqn; 1458 csp.wq_ctrl = &sq->wq_ctrl; 1459 csp.min_inline_mode = params->tx_min_inline_mode; 1460 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn); 1461 if (err) 1462 goto err_free_icosq; 1463 1464 return 0; 1465 1466 err_free_icosq: 1467 mlx5e_free_icosq(sq); 1468 1469 return err; 1470 } 1471 1472 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq) 1473 { 1474 set_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state); 1475 } 1476 1477 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq) 1478 { 1479 clear_bit(MLX5E_SQ_STATE_ENABLED, &icosq->state); 1480 synchronize_net(); /* Sync with NAPI. */ 1481 } 1482 1483 void mlx5e_close_icosq(struct mlx5e_icosq *sq) 1484 { 1485 struct mlx5e_channel *c = sq->channel; 1486 1487 mlx5e_destroy_sq(c->mdev, sq->sqn); 1488 mlx5e_free_icosq_descs(sq); 1489 mlx5e_free_icosq(sq); 1490 } 1491 1492 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params, 1493 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool, 1494 struct mlx5e_xdpsq *sq, bool is_redirect) 1495 { 1496 struct mlx5e_create_sq_param csp = {}; 1497 int err; 1498 1499 err = mlx5e_alloc_xdpsq(c, params, xsk_pool, param, sq, is_redirect); 1500 if (err) 1501 return err; 1502 1503 csp.tis_lst_sz = 1; 1504 csp.tisn = c->priv->tisn[c->lag_port][0]; /* tc = 0 */ 1505 csp.cqn = sq->cq.mcq.cqn; 1506 csp.wq_ctrl = &sq->wq_ctrl; 1507 csp.min_inline_mode = sq->min_inline_mode; 1508 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); 1509 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, 0, &sq->sqn); 1510 if (err) 1511 goto err_free_xdpsq; 1512 1513 mlx5e_set_xmit_fp(sq, param->is_mpw); 1514 1515 if (!param->is_mpw) { 1516 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT; 1517 unsigned int inline_hdr_sz = 0; 1518 int i; 1519 1520 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) { 1521 inline_hdr_sz = MLX5E_XDP_MIN_INLINE; 1522 ds_cnt++; 1523 } 1524 1525 /* Pre initialize fixed WQE fields */ 1526 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) { 1527 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i); 1528 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; 1529 struct mlx5_wqe_eth_seg *eseg = &wqe->eth; 1530 struct mlx5_wqe_data_seg *dseg; 1531 1532 sq->db.wqe_info[i] = (struct mlx5e_xdp_wqe_info) { 1533 .num_wqebbs = 1, 1534 .num_pkts = 1, 1535 }; 1536 1537 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt); 1538 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz); 1539 1540 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1); 1541 dseg->lkey = sq->mkey_be; 1542 } 1543 } 1544 1545 return 0; 1546 1547 err_free_xdpsq: 1548 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); 1549 mlx5e_free_xdpsq(sq); 1550 1551 return err; 1552 } 1553 1554 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq) 1555 { 1556 struct mlx5e_channel *c = sq->channel; 1557 1558 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); 1559 synchronize_net(); /* Sync with NAPI. */ 1560 1561 mlx5e_destroy_sq(c->mdev, sq->sqn); 1562 mlx5e_free_xdpsq_descs(sq); 1563 mlx5e_free_xdpsq(sq); 1564 } 1565 1566 static int mlx5e_alloc_cq_common(struct mlx5e_priv *priv, 1567 struct mlx5e_cq_param *param, 1568 struct mlx5e_cq *cq) 1569 { 1570 struct mlx5_core_dev *mdev = priv->mdev; 1571 struct mlx5_core_cq *mcq = &cq->mcq; 1572 int eqn_not_used; 1573 unsigned int irqn; 1574 int err; 1575 u32 i; 1576 1577 err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn); 1578 if (err) 1579 return err; 1580 1581 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, 1582 &cq->wq_ctrl); 1583 if (err) 1584 return err; 1585 1586 mcq->cqe_sz = 64; 1587 mcq->set_ci_db = cq->wq_ctrl.db.db; 1588 mcq->arm_db = cq->wq_ctrl.db.db + 1; 1589 *mcq->set_ci_db = 0; 1590 *mcq->arm_db = 0; 1591 mcq->vector = param->eq_ix; 1592 mcq->comp = mlx5e_completion_event; 1593 mcq->event = mlx5e_cq_error_event; 1594 mcq->irqn = irqn; 1595 1596 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) { 1597 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i); 1598 1599 cqe->op_own = 0xf1; 1600 } 1601 1602 cq->mdev = mdev; 1603 cq->netdev = priv->netdev; 1604 cq->priv = priv; 1605 1606 return 0; 1607 } 1608 1609 static int mlx5e_alloc_cq(struct mlx5e_priv *priv, 1610 struct mlx5e_cq_param *param, 1611 struct mlx5e_create_cq_param *ccp, 1612 struct mlx5e_cq *cq) 1613 { 1614 int err; 1615 1616 param->wq.buf_numa_node = ccp->node; 1617 param->wq.db_numa_node = ccp->node; 1618 param->eq_ix = ccp->ix; 1619 1620 err = mlx5e_alloc_cq_common(priv, param, cq); 1621 1622 cq->napi = ccp->napi; 1623 cq->ch_stats = ccp->ch_stats; 1624 1625 return err; 1626 } 1627 1628 static void mlx5e_free_cq(struct mlx5e_cq *cq) 1629 { 1630 mlx5_wq_destroy(&cq->wq_ctrl); 1631 } 1632 1633 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param) 1634 { 1635 u32 out[MLX5_ST_SZ_DW(create_cq_out)]; 1636 struct mlx5_core_dev *mdev = cq->mdev; 1637 struct mlx5_core_cq *mcq = &cq->mcq; 1638 1639 void *in; 1640 void *cqc; 1641 int inlen; 1642 unsigned int irqn_not_used; 1643 int eqn; 1644 int err; 1645 1646 err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used); 1647 if (err) 1648 return err; 1649 1650 inlen = MLX5_ST_SZ_BYTES(create_cq_in) + 1651 sizeof(u64) * cq->wq_ctrl.buf.npages; 1652 in = kvzalloc(inlen, GFP_KERNEL); 1653 if (!in) 1654 return -ENOMEM; 1655 1656 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1657 1658 memcpy(cqc, param->cqc, sizeof(param->cqc)); 1659 1660 mlx5_fill_page_frag_array(&cq->wq_ctrl.buf, 1661 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas)); 1662 1663 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode); 1664 MLX5_SET(cqc, cqc, c_eqn, eqn); 1665 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index); 1666 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - 1667 MLX5_ADAPTER_PAGE_SHIFT); 1668 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); 1669 1670 err = mlx5_core_create_cq(mdev, mcq, in, inlen, out, sizeof(out)); 1671 1672 kvfree(in); 1673 1674 if (err) 1675 return err; 1676 1677 mlx5e_cq_arm(cq); 1678 1679 return 0; 1680 } 1681 1682 static void mlx5e_destroy_cq(struct mlx5e_cq *cq) 1683 { 1684 mlx5_core_destroy_cq(cq->mdev, &cq->mcq); 1685 } 1686 1687 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder, 1688 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp, 1689 struct mlx5e_cq *cq) 1690 { 1691 struct mlx5_core_dev *mdev = priv->mdev; 1692 int err; 1693 1694 err = mlx5e_alloc_cq(priv, param, ccp, cq); 1695 if (err) 1696 return err; 1697 1698 err = mlx5e_create_cq(cq, param); 1699 if (err) 1700 goto err_free_cq; 1701 1702 if (MLX5_CAP_GEN(mdev, cq_moderation)) 1703 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts); 1704 return 0; 1705 1706 err_free_cq: 1707 mlx5e_free_cq(cq); 1708 1709 return err; 1710 } 1711 1712 void mlx5e_close_cq(struct mlx5e_cq *cq) 1713 { 1714 mlx5e_destroy_cq(cq); 1715 mlx5e_free_cq(cq); 1716 } 1717 1718 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c, 1719 struct mlx5e_params *params, 1720 struct mlx5e_create_cq_param *ccp, 1721 struct mlx5e_channel_param *cparam) 1722 { 1723 int err; 1724 int tc; 1725 1726 for (tc = 0; tc < c->num_tc; tc++) { 1727 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->txq_sq.cqp, 1728 ccp, &c->sq[tc].cq); 1729 if (err) 1730 goto err_close_tx_cqs; 1731 } 1732 1733 return 0; 1734 1735 err_close_tx_cqs: 1736 for (tc--; tc >= 0; tc--) 1737 mlx5e_close_cq(&c->sq[tc].cq); 1738 1739 return err; 1740 } 1741 1742 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c) 1743 { 1744 int tc; 1745 1746 for (tc = 0; tc < c->num_tc; tc++) 1747 mlx5e_close_cq(&c->sq[tc].cq); 1748 } 1749 1750 static int mlx5e_open_sqs(struct mlx5e_channel *c, 1751 struct mlx5e_params *params, 1752 struct mlx5e_channel_param *cparam) 1753 { 1754 int err, tc; 1755 1756 for (tc = 0; tc < params->num_tc; tc++) { 1757 int txq_ix = c->ix + tc * params->num_channels; 1758 1759 err = mlx5e_open_txqsq(c, c->priv->tisn[c->lag_port][tc], txq_ix, 1760 params, &cparam->txq_sq, &c->sq[tc], tc, 0, 0); 1761 if (err) 1762 goto err_close_sqs; 1763 } 1764 1765 return 0; 1766 1767 err_close_sqs: 1768 for (tc--; tc >= 0; tc--) 1769 mlx5e_close_txqsq(&c->sq[tc]); 1770 1771 return err; 1772 } 1773 1774 static void mlx5e_close_sqs(struct mlx5e_channel *c) 1775 { 1776 int tc; 1777 1778 for (tc = 0; tc < c->num_tc; tc++) 1779 mlx5e_close_txqsq(&c->sq[tc]); 1780 } 1781 1782 static int mlx5e_set_sq_maxrate(struct net_device *dev, 1783 struct mlx5e_txqsq *sq, u32 rate) 1784 { 1785 struct mlx5e_priv *priv = netdev_priv(dev); 1786 struct mlx5_core_dev *mdev = priv->mdev; 1787 struct mlx5e_modify_sq_param msp = {0}; 1788 struct mlx5_rate_limit rl = {0}; 1789 u16 rl_index = 0; 1790 int err; 1791 1792 if (rate == sq->rate_limit) 1793 /* nothing to do */ 1794 return 0; 1795 1796 if (sq->rate_limit) { 1797 rl.rate = sq->rate_limit; 1798 /* remove current rl index to free space to next ones */ 1799 mlx5_rl_remove_rate(mdev, &rl); 1800 } 1801 1802 sq->rate_limit = 0; 1803 1804 if (rate) { 1805 rl.rate = rate; 1806 err = mlx5_rl_add_rate(mdev, &rl_index, &rl); 1807 if (err) { 1808 netdev_err(dev, "Failed configuring rate %u: %d\n", 1809 rate, err); 1810 return err; 1811 } 1812 } 1813 1814 msp.curr_state = MLX5_SQC_STATE_RDY; 1815 msp.next_state = MLX5_SQC_STATE_RDY; 1816 msp.rl_index = rl_index; 1817 msp.rl_update = true; 1818 err = mlx5e_modify_sq(mdev, sq->sqn, &msp); 1819 if (err) { 1820 netdev_err(dev, "Failed configuring rate %u: %d\n", 1821 rate, err); 1822 /* remove the rate from the table */ 1823 if (rate) 1824 mlx5_rl_remove_rate(mdev, &rl); 1825 return err; 1826 } 1827 1828 sq->rate_limit = rate; 1829 return 0; 1830 } 1831 1832 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate) 1833 { 1834 struct mlx5e_priv *priv = netdev_priv(dev); 1835 struct mlx5_core_dev *mdev = priv->mdev; 1836 struct mlx5e_txqsq *sq = priv->txq2sq[index]; 1837 int err = 0; 1838 1839 if (!mlx5_rl_is_supported(mdev)) { 1840 netdev_err(dev, "Rate limiting is not supported on this device\n"); 1841 return -EINVAL; 1842 } 1843 1844 /* rate is given in Mb/sec, HW config is in Kb/sec */ 1845 rate = rate << 10; 1846 1847 /* Check whether rate in valid range, 0 is always valid */ 1848 if (rate && !mlx5_rl_is_in_range(mdev, rate)) { 1849 netdev_err(dev, "TX rate %u, is not in range\n", rate); 1850 return -ERANGE; 1851 } 1852 1853 mutex_lock(&priv->state_lock); 1854 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) 1855 err = mlx5e_set_sq_maxrate(dev, sq, rate); 1856 if (!err) 1857 priv->tx_rates[index] = rate; 1858 mutex_unlock(&priv->state_lock); 1859 1860 return err; 1861 } 1862 1863 void mlx5e_build_create_cq_param(struct mlx5e_create_cq_param *ccp, struct mlx5e_channel *c) 1864 { 1865 *ccp = (struct mlx5e_create_cq_param) { 1866 .napi = &c->napi, 1867 .ch_stats = c->stats, 1868 .node = cpu_to_node(c->cpu), 1869 .ix = c->ix, 1870 }; 1871 } 1872 1873 static int mlx5e_open_queues(struct mlx5e_channel *c, 1874 struct mlx5e_params *params, 1875 struct mlx5e_channel_param *cparam) 1876 { 1877 struct dim_cq_moder icocq_moder = {0, 0}; 1878 struct mlx5e_create_cq_param ccp; 1879 int err; 1880 1881 mlx5e_build_create_cq_param(&ccp, c); 1882 1883 err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->async_icosq.cqp, &ccp, 1884 &c->async_icosq.cq); 1885 if (err) 1886 return err; 1887 1888 err = mlx5e_open_cq(c->priv, icocq_moder, &cparam->icosq.cqp, &ccp, 1889 &c->icosq.cq); 1890 if (err) 1891 goto err_close_async_icosq_cq; 1892 1893 err = mlx5e_open_tx_cqs(c, params, &ccp, cparam); 1894 if (err) 1895 goto err_close_icosq_cq; 1896 1897 err = mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp, &ccp, 1898 &c->xdpsq.cq); 1899 if (err) 1900 goto err_close_tx_cqs; 1901 1902 err = mlx5e_open_cq(c->priv, params->rx_cq_moderation, &cparam->rq.cqp, &ccp, 1903 &c->rq.cq); 1904 if (err) 1905 goto err_close_xdp_tx_cqs; 1906 1907 err = c->xdp ? mlx5e_open_cq(c->priv, params->tx_cq_moderation, &cparam->xdp_sq.cqp, 1908 &ccp, &c->rq_xdpsq.cq) : 0; 1909 if (err) 1910 goto err_close_rx_cq; 1911 1912 spin_lock_init(&c->async_icosq_lock); 1913 1914 err = mlx5e_open_icosq(c, params, &cparam->async_icosq, &c->async_icosq); 1915 if (err) 1916 goto err_close_xdpsq_cq; 1917 1918 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq); 1919 if (err) 1920 goto err_close_async_icosq; 1921 1922 err = mlx5e_open_sqs(c, params, cparam); 1923 if (err) 1924 goto err_close_icosq; 1925 1926 if (c->xdp) { 1927 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, 1928 &c->rq_xdpsq, false); 1929 if (err) 1930 goto err_close_sqs; 1931 } 1932 1933 err = mlx5e_open_rq(c, params, &cparam->rq, NULL, NULL, &c->rq); 1934 if (err) 1935 goto err_close_xdp_sq; 1936 1937 err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, NULL, &c->xdpsq, true); 1938 if (err) 1939 goto err_close_rq; 1940 1941 return 0; 1942 1943 err_close_rq: 1944 mlx5e_close_rq(&c->rq); 1945 1946 err_close_xdp_sq: 1947 if (c->xdp) 1948 mlx5e_close_xdpsq(&c->rq_xdpsq); 1949 1950 err_close_sqs: 1951 mlx5e_close_sqs(c); 1952 1953 err_close_icosq: 1954 mlx5e_close_icosq(&c->icosq); 1955 1956 err_close_async_icosq: 1957 mlx5e_close_icosq(&c->async_icosq); 1958 1959 err_close_xdpsq_cq: 1960 if (c->xdp) 1961 mlx5e_close_cq(&c->rq_xdpsq.cq); 1962 1963 err_close_rx_cq: 1964 mlx5e_close_cq(&c->rq.cq); 1965 1966 err_close_xdp_tx_cqs: 1967 mlx5e_close_cq(&c->xdpsq.cq); 1968 1969 err_close_tx_cqs: 1970 mlx5e_close_tx_cqs(c); 1971 1972 err_close_icosq_cq: 1973 mlx5e_close_cq(&c->icosq.cq); 1974 1975 err_close_async_icosq_cq: 1976 mlx5e_close_cq(&c->async_icosq.cq); 1977 1978 return err; 1979 } 1980 1981 static void mlx5e_close_queues(struct mlx5e_channel *c) 1982 { 1983 mlx5e_close_xdpsq(&c->xdpsq); 1984 mlx5e_close_rq(&c->rq); 1985 if (c->xdp) 1986 mlx5e_close_xdpsq(&c->rq_xdpsq); 1987 mlx5e_close_sqs(c); 1988 mlx5e_close_icosq(&c->icosq); 1989 mlx5e_close_icosq(&c->async_icosq); 1990 if (c->xdp) 1991 mlx5e_close_cq(&c->rq_xdpsq.cq); 1992 mlx5e_close_cq(&c->rq.cq); 1993 mlx5e_close_cq(&c->xdpsq.cq); 1994 mlx5e_close_tx_cqs(c); 1995 mlx5e_close_cq(&c->icosq.cq); 1996 mlx5e_close_cq(&c->async_icosq.cq); 1997 } 1998 1999 static u8 mlx5e_enumerate_lag_port(struct mlx5_core_dev *mdev, int ix) 2000 { 2001 u16 port_aff_bias = mlx5_core_is_pf(mdev) ? 0 : MLX5_CAP_GEN(mdev, vhca_id); 2002 2003 return (ix + port_aff_bias) % mlx5e_get_num_lag_ports(mdev); 2004 } 2005 2006 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix, 2007 struct mlx5e_params *params, 2008 struct mlx5e_channel_param *cparam, 2009 struct xsk_buff_pool *xsk_pool, 2010 struct mlx5e_channel **cp) 2011 { 2012 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix)); 2013 struct net_device *netdev = priv->netdev; 2014 struct mlx5e_xsk_param xsk; 2015 struct mlx5e_channel *c; 2016 unsigned int irq; 2017 int err; 2018 int eqn; 2019 2020 err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq); 2021 if (err) 2022 return err; 2023 2024 c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu)); 2025 if (!c) 2026 return -ENOMEM; 2027 2028 c->priv = priv; 2029 c->mdev = priv->mdev; 2030 c->tstamp = &priv->tstamp; 2031 c->ix = ix; 2032 c->cpu = cpu; 2033 c->pdev = mlx5_core_dma_dev(priv->mdev); 2034 c->netdev = priv->netdev; 2035 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key); 2036 c->num_tc = params->num_tc; 2037 c->xdp = !!params->xdp_prog; 2038 c->stats = &priv->channel_stats[ix].ch; 2039 c->aff_mask = irq_get_effective_affinity_mask(irq); 2040 c->lag_port = mlx5e_enumerate_lag_port(priv->mdev, ix); 2041 2042 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64); 2043 2044 err = mlx5e_open_queues(c, params, cparam); 2045 if (unlikely(err)) 2046 goto err_napi_del; 2047 2048 if (xsk_pool) { 2049 mlx5e_build_xsk_param(xsk_pool, &xsk); 2050 err = mlx5e_open_xsk(priv, params, &xsk, xsk_pool, c); 2051 if (unlikely(err)) 2052 goto err_close_queues; 2053 } 2054 2055 *cp = c; 2056 2057 return 0; 2058 2059 err_close_queues: 2060 mlx5e_close_queues(c); 2061 2062 err_napi_del: 2063 netif_napi_del(&c->napi); 2064 2065 kvfree(c); 2066 2067 return err; 2068 } 2069 2070 static void mlx5e_activate_channel(struct mlx5e_channel *c) 2071 { 2072 int tc; 2073 2074 napi_enable(&c->napi); 2075 2076 for (tc = 0; tc < c->num_tc; tc++) 2077 mlx5e_activate_txqsq(&c->sq[tc]); 2078 mlx5e_activate_icosq(&c->icosq); 2079 mlx5e_activate_icosq(&c->async_icosq); 2080 mlx5e_activate_rq(&c->rq); 2081 2082 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) 2083 mlx5e_activate_xsk(c); 2084 } 2085 2086 static void mlx5e_deactivate_channel(struct mlx5e_channel *c) 2087 { 2088 int tc; 2089 2090 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) 2091 mlx5e_deactivate_xsk(c); 2092 2093 mlx5e_deactivate_rq(&c->rq); 2094 mlx5e_deactivate_icosq(&c->async_icosq); 2095 mlx5e_deactivate_icosq(&c->icosq); 2096 for (tc = 0; tc < c->num_tc; tc++) 2097 mlx5e_deactivate_txqsq(&c->sq[tc]); 2098 mlx5e_qos_deactivate_queues(c); 2099 2100 napi_disable(&c->napi); 2101 } 2102 2103 static void mlx5e_close_channel(struct mlx5e_channel *c) 2104 { 2105 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) 2106 mlx5e_close_xsk(c); 2107 mlx5e_close_queues(c); 2108 mlx5e_qos_close_queues(c); 2109 netif_napi_del(&c->napi); 2110 2111 kvfree(c); 2112 } 2113 2114 #define DEFAULT_FRAG_SIZE (2048) 2115 2116 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev, 2117 struct mlx5e_params *params, 2118 struct mlx5e_xsk_param *xsk, 2119 struct mlx5e_rq_frags_info *info) 2120 { 2121 u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu); 2122 int frag_size_max = DEFAULT_FRAG_SIZE; 2123 u32 buf_size = 0; 2124 int i; 2125 2126 if (mlx5_fpga_is_ipsec_device(mdev)) 2127 byte_count += MLX5E_METADATA_ETHER_LEN; 2128 2129 if (mlx5e_rx_is_linear_skb(params, xsk)) { 2130 int frag_stride; 2131 2132 frag_stride = mlx5e_rx_get_linear_frag_sz(params, xsk); 2133 frag_stride = roundup_pow_of_two(frag_stride); 2134 2135 info->arr[0].frag_size = byte_count; 2136 info->arr[0].frag_stride = frag_stride; 2137 info->num_frags = 1; 2138 info->wqe_bulk = PAGE_SIZE / frag_stride; 2139 goto out; 2140 } 2141 2142 if (byte_count > PAGE_SIZE + 2143 (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max) 2144 frag_size_max = PAGE_SIZE; 2145 2146 i = 0; 2147 while (buf_size < byte_count) { 2148 int frag_size = byte_count - buf_size; 2149 2150 if (i < MLX5E_MAX_RX_FRAGS - 1) 2151 frag_size = min(frag_size, frag_size_max); 2152 2153 info->arr[i].frag_size = frag_size; 2154 info->arr[i].frag_stride = roundup_pow_of_two(frag_size); 2155 2156 buf_size += frag_size; 2157 i++; 2158 } 2159 info->num_frags = i; 2160 /* number of different wqes sharing a page */ 2161 info->wqe_bulk = 1 + (info->num_frags % 2); 2162 2163 out: 2164 info->wqe_bulk = max_t(u8, info->wqe_bulk, 8); 2165 info->log_num_frags = order_base_2(info->num_frags); 2166 } 2167 2168 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs) 2169 { 2170 int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs; 2171 2172 switch (wq_type) { 2173 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 2174 sz += sizeof(struct mlx5e_rx_wqe_ll); 2175 break; 2176 default: /* MLX5_WQ_TYPE_CYCLIC */ 2177 sz += sizeof(struct mlx5e_rx_wqe_cyc); 2178 } 2179 2180 return order_base_2(sz); 2181 } 2182 2183 static u8 mlx5e_get_rq_log_wq_sz(void *rqc) 2184 { 2185 void *wq = MLX5_ADDR_OF(rqc, rqc, wq); 2186 2187 return MLX5_GET(wq, wq, log_wq_sz); 2188 } 2189 2190 void mlx5e_build_rq_param(struct mlx5e_priv *priv, 2191 struct mlx5e_params *params, 2192 struct mlx5e_xsk_param *xsk, 2193 struct mlx5e_rq_param *param) 2194 { 2195 struct mlx5_core_dev *mdev = priv->mdev; 2196 void *rqc = param->rqc; 2197 void *wq = MLX5_ADDR_OF(rqc, rqc, wq); 2198 int ndsegs = 1; 2199 2200 switch (params->rq_wq_type) { 2201 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 2202 MLX5_SET(wq, wq, log_wqe_num_of_strides, 2203 mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk) - 2204 MLX5_MPWQE_LOG_NUM_STRIDES_BASE); 2205 MLX5_SET(wq, wq, log_wqe_stride_size, 2206 mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk) - 2207 MLX5_MPWQE_LOG_STRIDE_SZ_BASE); 2208 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params, xsk)); 2209 break; 2210 default: /* MLX5_WQ_TYPE_CYCLIC */ 2211 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames); 2212 mlx5e_build_rq_frags_info(mdev, params, xsk, ¶m->frags_info); 2213 ndsegs = param->frags_info.num_frags; 2214 } 2215 2216 MLX5_SET(wq, wq, wq_type, params->rq_wq_type); 2217 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); 2218 MLX5_SET(wq, wq, log_wq_stride, 2219 mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs)); 2220 MLX5_SET(wq, wq, pd, mdev->mlx5e_res.pdn); 2221 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter); 2222 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable); 2223 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en); 2224 2225 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev)); 2226 mlx5e_build_rx_cq_param(priv, params, xsk, ¶m->cqp); 2227 } 2228 2229 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv, 2230 struct mlx5e_rq_param *param) 2231 { 2232 struct mlx5_core_dev *mdev = priv->mdev; 2233 void *rqc = param->rqc; 2234 void *wq = MLX5_ADDR_OF(rqc, rqc, wq); 2235 2236 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 2237 MLX5_SET(wq, wq, log_wq_stride, 2238 mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1)); 2239 MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter); 2240 2241 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev)); 2242 } 2243 2244 void mlx5e_build_sq_param_common(struct mlx5e_priv *priv, 2245 struct mlx5e_sq_param *param) 2246 { 2247 void *sqc = param->sqc; 2248 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 2249 2250 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 2251 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn); 2252 2253 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(priv->mdev)); 2254 } 2255 2256 void mlx5e_build_sq_param(struct mlx5e_priv *priv, struct mlx5e_params *params, 2257 struct mlx5e_sq_param *param) 2258 { 2259 void *sqc = param->sqc; 2260 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 2261 bool allow_swp; 2262 2263 allow_swp = mlx5_geneve_tx_allowed(priv->mdev) || 2264 !!MLX5_IPSEC_DEV(priv->mdev); 2265 mlx5e_build_sq_param_common(priv, param); 2266 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size); 2267 MLX5_SET(sqc, sqc, allow_swp, allow_swp); 2268 param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE); 2269 param->stop_room = mlx5e_calc_sq_stop_room(priv->mdev, params); 2270 mlx5e_build_tx_cq_param(priv, params, ¶m->cqp); 2271 } 2272 2273 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv, 2274 struct mlx5e_cq_param *param) 2275 { 2276 void *cqc = param->cqc; 2277 2278 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index); 2279 if (MLX5_CAP_GEN(priv->mdev, cqe_128_always) && cache_line_size() >= 128) 2280 MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD); 2281 } 2282 2283 void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv, 2284 struct mlx5e_params *params, 2285 struct mlx5e_xsk_param *xsk, 2286 struct mlx5e_cq_param *param) 2287 { 2288 struct mlx5_core_dev *mdev = priv->mdev; 2289 bool hw_stridx = false; 2290 void *cqc = param->cqc; 2291 u8 log_cq_size; 2292 2293 switch (params->rq_wq_type) { 2294 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 2295 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params, xsk) + 2296 mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk); 2297 hw_stridx = MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index); 2298 break; 2299 default: /* MLX5_WQ_TYPE_CYCLIC */ 2300 log_cq_size = params->log_rq_mtu_frames; 2301 } 2302 2303 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size); 2304 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) { 2305 MLX5_SET(cqc, cqc, mini_cqe_res_format, hw_stridx ? 2306 MLX5_CQE_FORMAT_CSUM_STRIDX : MLX5_CQE_FORMAT_CSUM); 2307 MLX5_SET(cqc, cqc, cqe_comp_en, 1); 2308 } 2309 2310 mlx5e_build_common_cq_param(priv, param); 2311 param->cq_period_mode = params->rx_cq_moderation.cq_period_mode; 2312 } 2313 2314 void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv, 2315 struct mlx5e_params *params, 2316 struct mlx5e_cq_param *param) 2317 { 2318 void *cqc = param->cqc; 2319 2320 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size); 2321 2322 mlx5e_build_common_cq_param(priv, param); 2323 param->cq_period_mode = params->tx_cq_moderation.cq_period_mode; 2324 } 2325 2326 void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv, 2327 u8 log_wq_size, 2328 struct mlx5e_cq_param *param) 2329 { 2330 void *cqc = param->cqc; 2331 2332 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size); 2333 2334 mlx5e_build_common_cq_param(priv, param); 2335 2336 param->cq_period_mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 2337 } 2338 2339 void mlx5e_build_icosq_param(struct mlx5e_priv *priv, 2340 u8 log_wq_size, 2341 struct mlx5e_sq_param *param) 2342 { 2343 void *sqc = param->sqc; 2344 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 2345 2346 mlx5e_build_sq_param_common(priv, param); 2347 2348 MLX5_SET(wq, wq, log_wq_sz, log_wq_size); 2349 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq)); 2350 mlx5e_build_ico_cq_param(priv, log_wq_size, ¶m->cqp); 2351 } 2352 2353 void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv, 2354 struct mlx5e_params *params, 2355 struct mlx5e_sq_param *param) 2356 { 2357 void *sqc = param->sqc; 2358 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 2359 2360 mlx5e_build_sq_param_common(priv, param); 2361 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size); 2362 param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE); 2363 mlx5e_build_tx_cq_param(priv, params, ¶m->cqp); 2364 } 2365 2366 static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5e_params *params, 2367 struct mlx5e_rq_param *rqp) 2368 { 2369 switch (params->rq_wq_type) { 2370 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 2371 return order_base_2(MLX5E_UMR_WQEBBS) + 2372 mlx5e_get_rq_log_wq_sz(rqp->rqc); 2373 default: /* MLX5_WQ_TYPE_CYCLIC */ 2374 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE; 2375 } 2376 } 2377 2378 static u8 mlx5e_build_async_icosq_log_wq_sz(struct net_device *netdev) 2379 { 2380 if (netdev->hw_features & NETIF_F_HW_TLS_RX) 2381 return MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; 2382 2383 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE; 2384 } 2385 2386 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, 2387 struct mlx5e_params *params, 2388 struct mlx5e_channel_param *cparam) 2389 { 2390 u8 icosq_log_wq_sz, async_icosq_log_wq_sz; 2391 2392 mlx5e_build_rq_param(priv, params, NULL, &cparam->rq); 2393 2394 icosq_log_wq_sz = mlx5e_build_icosq_log_wq_sz(params, &cparam->rq); 2395 async_icosq_log_wq_sz = mlx5e_build_async_icosq_log_wq_sz(priv->netdev); 2396 2397 mlx5e_build_sq_param(priv, params, &cparam->txq_sq); 2398 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq); 2399 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq); 2400 mlx5e_build_icosq_param(priv, async_icosq_log_wq_sz, &cparam->async_icosq); 2401 } 2402 2403 int mlx5e_open_channels(struct mlx5e_priv *priv, 2404 struct mlx5e_channels *chs) 2405 { 2406 struct mlx5e_channel_param *cparam; 2407 int err = -ENOMEM; 2408 int i; 2409 2410 chs->num = chs->params.num_channels; 2411 2412 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL); 2413 cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL); 2414 if (!chs->c || !cparam) 2415 goto err_free; 2416 2417 mlx5e_build_channel_param(priv, &chs->params, cparam); 2418 for (i = 0; i < chs->num; i++) { 2419 struct xsk_buff_pool *xsk_pool = NULL; 2420 2421 if (chs->params.xdp_prog) 2422 xsk_pool = mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, i); 2423 2424 err = mlx5e_open_channel(priv, i, &chs->params, cparam, xsk_pool, &chs->c[i]); 2425 if (err) 2426 goto err_close_channels; 2427 } 2428 2429 if (MLX5E_GET_PFLAG(&chs->params, MLX5E_PFLAG_TX_PORT_TS)) { 2430 err = mlx5e_port_ptp_open(priv, &chs->params, chs->c[0]->lag_port, 2431 &chs->port_ptp); 2432 if (err) 2433 goto err_close_channels; 2434 } 2435 2436 err = mlx5e_qos_open_queues(priv, chs); 2437 if (err) 2438 goto err_close_ptp; 2439 2440 mlx5e_health_channels_update(priv); 2441 kvfree(cparam); 2442 return 0; 2443 2444 err_close_ptp: 2445 if (chs->port_ptp) 2446 mlx5e_port_ptp_close(chs->port_ptp); 2447 2448 err_close_channels: 2449 for (i--; i >= 0; i--) 2450 mlx5e_close_channel(chs->c[i]); 2451 2452 err_free: 2453 kfree(chs->c); 2454 kvfree(cparam); 2455 chs->num = 0; 2456 return err; 2457 } 2458 2459 static void mlx5e_activate_channels(struct mlx5e_channels *chs) 2460 { 2461 int i; 2462 2463 for (i = 0; i < chs->num; i++) 2464 mlx5e_activate_channel(chs->c[i]); 2465 2466 if (chs->port_ptp) 2467 mlx5e_ptp_activate_channel(chs->port_ptp); 2468 } 2469 2470 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */ 2471 2472 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs) 2473 { 2474 int err = 0; 2475 int i; 2476 2477 for (i = 0; i < chs->num; i++) { 2478 int timeout = err ? 0 : MLX5E_RQ_WQES_TIMEOUT; 2479 2480 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq, timeout); 2481 2482 /* Don't wait on the XSK RQ, because the newer xdpsock sample 2483 * doesn't provide any Fill Ring entries at the setup stage. 2484 */ 2485 } 2486 2487 return err ? -ETIMEDOUT : 0; 2488 } 2489 2490 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs) 2491 { 2492 int i; 2493 2494 if (chs->port_ptp) 2495 mlx5e_ptp_deactivate_channel(chs->port_ptp); 2496 2497 for (i = 0; i < chs->num; i++) 2498 mlx5e_deactivate_channel(chs->c[i]); 2499 } 2500 2501 void mlx5e_close_channels(struct mlx5e_channels *chs) 2502 { 2503 int i; 2504 2505 if (chs->port_ptp) 2506 mlx5e_port_ptp_close(chs->port_ptp); 2507 2508 for (i = 0; i < chs->num; i++) 2509 mlx5e_close_channel(chs->c[i]); 2510 2511 kfree(chs->c); 2512 chs->num = 0; 2513 } 2514 2515 static int 2516 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt) 2517 { 2518 struct mlx5_core_dev *mdev = priv->mdev; 2519 void *rqtc; 2520 int inlen; 2521 int err; 2522 u32 *in; 2523 int i; 2524 2525 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; 2526 in = kvzalloc(inlen, GFP_KERNEL); 2527 if (!in) 2528 return -ENOMEM; 2529 2530 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 2531 2532 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 2533 MLX5_SET(rqtc, rqtc, rqt_max_size, sz); 2534 2535 for (i = 0; i < sz; i++) 2536 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn); 2537 2538 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn); 2539 if (!err) 2540 rqt->enabled = true; 2541 2542 kvfree(in); 2543 return err; 2544 } 2545 2546 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt) 2547 { 2548 rqt->enabled = false; 2549 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn); 2550 } 2551 2552 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv) 2553 { 2554 struct mlx5e_rqt *rqt = &priv->indir_rqt; 2555 int err; 2556 2557 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt); 2558 if (err) 2559 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err); 2560 return err; 2561 } 2562 2563 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs) 2564 { 2565 int err; 2566 int ix; 2567 2568 for (ix = 0; ix < priv->max_nch; ix++) { 2569 err = mlx5e_create_rqt(priv, 1 /*size */, &tirs[ix].rqt); 2570 if (unlikely(err)) 2571 goto err_destroy_rqts; 2572 } 2573 2574 return 0; 2575 2576 err_destroy_rqts: 2577 mlx5_core_warn(priv->mdev, "create rqts failed, %d\n", err); 2578 for (ix--; ix >= 0; ix--) 2579 mlx5e_destroy_rqt(priv, &tirs[ix].rqt); 2580 2581 return err; 2582 } 2583 2584 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs) 2585 { 2586 int i; 2587 2588 for (i = 0; i < priv->max_nch; i++) 2589 mlx5e_destroy_rqt(priv, &tirs[i].rqt); 2590 } 2591 2592 static int mlx5e_rx_hash_fn(int hfunc) 2593 { 2594 return (hfunc == ETH_RSS_HASH_TOP) ? 2595 MLX5_RX_HASH_FN_TOEPLITZ : 2596 MLX5_RX_HASH_FN_INVERTED_XOR8; 2597 } 2598 2599 int mlx5e_bits_invert(unsigned long a, int size) 2600 { 2601 int inv = 0; 2602 int i; 2603 2604 for (i = 0; i < size; i++) 2605 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i; 2606 2607 return inv; 2608 } 2609 2610 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz, 2611 struct mlx5e_redirect_rqt_param rrp, void *rqtc) 2612 { 2613 int i; 2614 2615 for (i = 0; i < sz; i++) { 2616 u32 rqn; 2617 2618 if (rrp.is_rss) { 2619 int ix = i; 2620 2621 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR) 2622 ix = mlx5e_bits_invert(i, ilog2(sz)); 2623 2624 ix = priv->rss_params.indirection_rqt[ix]; 2625 rqn = rrp.rss.channels->c[ix]->rq.rqn; 2626 } else { 2627 rqn = rrp.rqn; 2628 } 2629 MLX5_SET(rqtc, rqtc, rq_num[i], rqn); 2630 } 2631 } 2632 2633 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, 2634 struct mlx5e_redirect_rqt_param rrp) 2635 { 2636 struct mlx5_core_dev *mdev = priv->mdev; 2637 void *rqtc; 2638 int inlen; 2639 u32 *in; 2640 int err; 2641 2642 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz; 2643 in = kvzalloc(inlen, GFP_KERNEL); 2644 if (!in) 2645 return -ENOMEM; 2646 2647 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx); 2648 2649 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); 2650 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1); 2651 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc); 2652 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen); 2653 2654 kvfree(in); 2655 return err; 2656 } 2657 2658 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix, 2659 struct mlx5e_redirect_rqt_param rrp) 2660 { 2661 if (!rrp.is_rss) 2662 return rrp.rqn; 2663 2664 if (ix >= rrp.rss.channels->num) 2665 return priv->drop_rq.rqn; 2666 2667 return rrp.rss.channels->c[ix]->rq.rqn; 2668 } 2669 2670 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv, 2671 struct mlx5e_redirect_rqt_param rrp) 2672 { 2673 u32 rqtn; 2674 int ix; 2675 2676 if (priv->indir_rqt.enabled) { 2677 /* RSS RQ table */ 2678 rqtn = priv->indir_rqt.rqtn; 2679 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp); 2680 } 2681 2682 for (ix = 0; ix < priv->max_nch; ix++) { 2683 struct mlx5e_redirect_rqt_param direct_rrp = { 2684 .is_rss = false, 2685 { 2686 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp) 2687 }, 2688 }; 2689 2690 /* Direct RQ Tables */ 2691 if (!priv->direct_tir[ix].rqt.enabled) 2692 continue; 2693 2694 rqtn = priv->direct_tir[ix].rqt.rqtn; 2695 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp); 2696 } 2697 } 2698 2699 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv, 2700 struct mlx5e_channels *chs) 2701 { 2702 struct mlx5e_redirect_rqt_param rrp = { 2703 .is_rss = true, 2704 { 2705 .rss = { 2706 .channels = chs, 2707 .hfunc = priv->rss_params.hfunc, 2708 } 2709 }, 2710 }; 2711 2712 mlx5e_redirect_rqts(priv, rrp); 2713 } 2714 2715 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv) 2716 { 2717 struct mlx5e_redirect_rqt_param drop_rrp = { 2718 .is_rss = false, 2719 { 2720 .rqn = priv->drop_rq.rqn, 2721 }, 2722 }; 2723 2724 mlx5e_redirect_rqts(priv, drop_rrp); 2725 } 2726 2727 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = { 2728 [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4, 2729 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP, 2730 .rx_hash_fields = MLX5_HASH_IP_L4PORTS, 2731 }, 2732 [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6, 2733 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP, 2734 .rx_hash_fields = MLX5_HASH_IP_L4PORTS, 2735 }, 2736 [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4, 2737 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP, 2738 .rx_hash_fields = MLX5_HASH_IP_L4PORTS, 2739 }, 2740 [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6, 2741 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP, 2742 .rx_hash_fields = MLX5_HASH_IP_L4PORTS, 2743 }, 2744 [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4, 2745 .l4_prot_type = 0, 2746 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI, 2747 }, 2748 [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6, 2749 .l4_prot_type = 0, 2750 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI, 2751 }, 2752 [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4, 2753 .l4_prot_type = 0, 2754 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI, 2755 }, 2756 [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6, 2757 .l4_prot_type = 0, 2758 .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI, 2759 }, 2760 [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4, 2761 .l4_prot_type = 0, 2762 .rx_hash_fields = MLX5_HASH_IP, 2763 }, 2764 [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6, 2765 .l4_prot_type = 0, 2766 .rx_hash_fields = MLX5_HASH_IP, 2767 }, 2768 }; 2769 2770 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt) 2771 { 2772 return tirc_default_config[tt]; 2773 } 2774 2775 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc) 2776 { 2777 if (!params->lro_en) 2778 return; 2779 2780 #define ROUGH_MAX_L2_L3_HDR_SZ 256 2781 2782 MLX5_SET(tirc, tirc, lro_enable_mask, 2783 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO | 2784 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO); 2785 MLX5_SET(tirc, tirc, lro_max_ip_payload_size, 2786 (MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - ROUGH_MAX_L2_L3_HDR_SZ) >> 8); 2787 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout); 2788 } 2789 2790 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params, 2791 const struct mlx5e_tirc_config *ttconfig, 2792 void *tirc, bool inner) 2793 { 2794 void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) : 2795 MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); 2796 2797 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc)); 2798 if (rss_params->hfunc == ETH_RSS_HASH_TOP) { 2799 void *rss_key = MLX5_ADDR_OF(tirc, tirc, 2800 rx_hash_toeplitz_key); 2801 size_t len = MLX5_FLD_SZ_BYTES(tirc, 2802 rx_hash_toeplitz_key); 2803 2804 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); 2805 memcpy(rss_key, rss_params->toeplitz_hash_key, len); 2806 } 2807 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, 2808 ttconfig->l3_prot_type); 2809 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, 2810 ttconfig->l4_prot_type); 2811 MLX5_SET(rx_hash_field_select, hfso, selected_fields, 2812 ttconfig->rx_hash_fields); 2813 } 2814 2815 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig, 2816 enum mlx5e_traffic_types tt, 2817 u32 rx_hash_fields) 2818 { 2819 *ttconfig = tirc_default_config[tt]; 2820 ttconfig->rx_hash_fields = rx_hash_fields; 2821 } 2822 2823 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in) 2824 { 2825 void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx); 2826 struct mlx5e_rss_params *rss = &priv->rss_params; 2827 struct mlx5_core_dev *mdev = priv->mdev; 2828 int ctxlen = MLX5_ST_SZ_BYTES(tirc); 2829 struct mlx5e_tirc_config ttconfig; 2830 int tt; 2831 2832 MLX5_SET(modify_tir_in, in, bitmask.hash, 1); 2833 2834 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { 2835 memset(tirc, 0, ctxlen); 2836 mlx5e_update_rx_hash_fields(&ttconfig, tt, 2837 rss->rx_hash_fields[tt]); 2838 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false); 2839 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in); 2840 } 2841 2842 /* Verify inner tirs resources allocated */ 2843 if (!priv->inner_indir_tir[0].tirn) 2844 return; 2845 2846 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { 2847 memset(tirc, 0, ctxlen); 2848 mlx5e_update_rx_hash_fields(&ttconfig, tt, 2849 rss->rx_hash_fields[tt]); 2850 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true); 2851 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in); 2852 } 2853 } 2854 2855 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv) 2856 { 2857 struct mlx5_core_dev *mdev = priv->mdev; 2858 2859 void *in; 2860 void *tirc; 2861 int inlen; 2862 int err; 2863 int tt; 2864 int ix; 2865 2866 inlen = MLX5_ST_SZ_BYTES(modify_tir_in); 2867 in = kvzalloc(inlen, GFP_KERNEL); 2868 if (!in) 2869 return -ENOMEM; 2870 2871 MLX5_SET(modify_tir_in, in, bitmask.lro, 1); 2872 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx); 2873 2874 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc); 2875 2876 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { 2877 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in); 2878 if (err) 2879 goto free_in; 2880 } 2881 2882 for (ix = 0; ix < priv->max_nch; ix++) { 2883 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn, in); 2884 if (err) 2885 goto free_in; 2886 } 2887 2888 free_in: 2889 kvfree(in); 2890 2891 return err; 2892 } 2893 2894 static MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_modify_tirs_lro); 2895 2896 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev, 2897 struct mlx5e_params *params, u16 mtu) 2898 { 2899 u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu); 2900 int err; 2901 2902 err = mlx5_set_port_mtu(mdev, hw_mtu, 1); 2903 if (err) 2904 return err; 2905 2906 /* Update vport context MTU */ 2907 mlx5_modify_nic_vport_mtu(mdev, hw_mtu); 2908 return 0; 2909 } 2910 2911 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev, 2912 struct mlx5e_params *params, u16 *mtu) 2913 { 2914 u16 hw_mtu = 0; 2915 int err; 2916 2917 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu); 2918 if (err || !hw_mtu) /* fallback to port oper mtu */ 2919 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1); 2920 2921 *mtu = MLX5E_HW2SW_MTU(params, hw_mtu); 2922 } 2923 2924 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv) 2925 { 2926 struct mlx5e_params *params = &priv->channels.params; 2927 struct net_device *netdev = priv->netdev; 2928 struct mlx5_core_dev *mdev = priv->mdev; 2929 u16 mtu; 2930 int err; 2931 2932 err = mlx5e_set_mtu(mdev, params, params->sw_mtu); 2933 if (err) 2934 return err; 2935 2936 mlx5e_query_mtu(mdev, params, &mtu); 2937 if (mtu != params->sw_mtu) 2938 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n", 2939 __func__, mtu, params->sw_mtu); 2940 2941 params->sw_mtu = mtu; 2942 return 0; 2943 } 2944 2945 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_set_dev_port_mtu); 2946 2947 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv) 2948 { 2949 struct mlx5e_params *params = &priv->channels.params; 2950 struct net_device *netdev = priv->netdev; 2951 struct mlx5_core_dev *mdev = priv->mdev; 2952 u16 max_mtu; 2953 2954 /* MTU range: 68 - hw-specific max */ 2955 netdev->min_mtu = ETH_MIN_MTU; 2956 2957 mlx5_query_port_max_mtu(mdev, &max_mtu, 1); 2958 netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu), 2959 ETH_MAX_MTU); 2960 } 2961 2962 static void mlx5e_netdev_set_tcs(struct net_device *netdev, u16 nch, u8 ntc) 2963 { 2964 int tc; 2965 2966 netdev_reset_tc(netdev); 2967 2968 if (ntc == 1) 2969 return; 2970 2971 netdev_set_num_tc(netdev, ntc); 2972 2973 /* Map netdev TCs to offset 0 2974 * We have our own UP to TXQ mapping for QoS 2975 */ 2976 for (tc = 0; tc < ntc; tc++) 2977 netdev_set_tc_queue(netdev, tc, nch, 0); 2978 } 2979 2980 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv) 2981 { 2982 int qos_queues, nch, ntc, num_txqs, err; 2983 2984 qos_queues = mlx5e_qos_cur_leaf_nodes(priv); 2985 2986 nch = priv->channels.params.num_channels; 2987 ntc = priv->channels.params.num_tc; 2988 num_txqs = nch * ntc + qos_queues; 2989 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_PORT_TS)) 2990 num_txqs += ntc; 2991 2992 mlx5e_dbg(DRV, priv, "Setting num_txqs %d\n", num_txqs); 2993 err = netif_set_real_num_tx_queues(priv->netdev, num_txqs); 2994 if (err) 2995 netdev_warn(priv->netdev, "netif_set_real_num_tx_queues failed, %d\n", err); 2996 2997 return err; 2998 } 2999 3000 static int mlx5e_update_netdev_queues(struct mlx5e_priv *priv) 3001 { 3002 struct net_device *netdev = priv->netdev; 3003 int old_num_txqs, old_ntc; 3004 int num_rxqs, nch, ntc; 3005 int err; 3006 3007 old_num_txqs = netdev->real_num_tx_queues; 3008 old_ntc = netdev->num_tc; 3009 3010 nch = priv->channels.params.num_channels; 3011 ntc = priv->channels.params.num_tc; 3012 num_rxqs = nch * priv->profile->rq_groups; 3013 3014 mlx5e_netdev_set_tcs(netdev, nch, ntc); 3015 3016 err = mlx5e_update_tx_netdev_queues(priv); 3017 if (err) 3018 goto err_tcs; 3019 err = netif_set_real_num_rx_queues(netdev, num_rxqs); 3020 if (err) { 3021 netdev_warn(netdev, "netif_set_real_num_rx_queues failed, %d\n", err); 3022 goto err_txqs; 3023 } 3024 3025 return 0; 3026 3027 err_txqs: 3028 /* netif_set_real_num_rx_queues could fail only when nch increased. Only 3029 * one of nch and ntc is changed in this function. That means, the call 3030 * to netif_set_real_num_tx_queues below should not fail, because it 3031 * decreases the number of TX queues. 3032 */ 3033 WARN_ON_ONCE(netif_set_real_num_tx_queues(netdev, old_num_txqs)); 3034 3035 err_tcs: 3036 mlx5e_netdev_set_tcs(netdev, old_num_txqs / old_ntc, old_ntc); 3037 return err; 3038 } 3039 3040 static void mlx5e_set_default_xps_cpumasks(struct mlx5e_priv *priv, 3041 struct mlx5e_params *params) 3042 { 3043 struct mlx5_core_dev *mdev = priv->mdev; 3044 int num_comp_vectors, ix, irq; 3045 3046 num_comp_vectors = mlx5_comp_vectors_count(mdev); 3047 3048 for (ix = 0; ix < params->num_channels; ix++) { 3049 cpumask_clear(priv->scratchpad.cpumask); 3050 3051 for (irq = ix; irq < num_comp_vectors; irq += params->num_channels) { 3052 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(mdev, irq)); 3053 3054 cpumask_set_cpu(cpu, priv->scratchpad.cpumask); 3055 } 3056 3057 netif_set_xps_queue(priv->netdev, priv->scratchpad.cpumask, ix); 3058 } 3059 } 3060 3061 int mlx5e_num_channels_changed(struct mlx5e_priv *priv) 3062 { 3063 u16 count = priv->channels.params.num_channels; 3064 int err; 3065 3066 err = mlx5e_update_netdev_queues(priv); 3067 if (err) 3068 return err; 3069 3070 mlx5e_set_default_xps_cpumasks(priv, &priv->channels.params); 3071 3072 if (!netif_is_rxfh_configured(priv->netdev)) 3073 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt, 3074 MLX5E_INDIR_RQT_SIZE, count); 3075 3076 return 0; 3077 } 3078 3079 MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(mlx5e_num_channels_changed); 3080 3081 static void mlx5e_build_txq_maps(struct mlx5e_priv *priv) 3082 { 3083 int i, ch, tc, num_tc; 3084 3085 ch = priv->channels.num; 3086 num_tc = priv->channels.params.num_tc; 3087 3088 for (i = 0; i < ch; i++) { 3089 for (tc = 0; tc < num_tc; tc++) { 3090 struct mlx5e_channel *c = priv->channels.c[i]; 3091 struct mlx5e_txqsq *sq = &c->sq[tc]; 3092 3093 priv->txq2sq[sq->txq_ix] = sq; 3094 priv->channel_tc2realtxq[i][tc] = i + tc * ch; 3095 } 3096 } 3097 3098 if (!priv->channels.port_ptp) 3099 return; 3100 3101 for (tc = 0; tc < num_tc; tc++) { 3102 struct mlx5e_port_ptp *c = priv->channels.port_ptp; 3103 struct mlx5e_txqsq *sq = &c->ptpsq[tc].txqsq; 3104 3105 priv->txq2sq[sq->txq_ix] = sq; 3106 priv->port_ptp_tc2realtxq[tc] = priv->num_tc_x_num_ch + tc; 3107 } 3108 } 3109 3110 static void mlx5e_update_num_tc_x_num_ch(struct mlx5e_priv *priv) 3111 { 3112 /* Sync with mlx5e_select_queue. */ 3113 WRITE_ONCE(priv->num_tc_x_num_ch, 3114 priv->channels.params.num_tc * priv->channels.num); 3115 } 3116 3117 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv) 3118 { 3119 mlx5e_update_num_tc_x_num_ch(priv); 3120 mlx5e_build_txq_maps(priv); 3121 mlx5e_activate_channels(&priv->channels); 3122 mlx5e_qos_activate_queues(priv); 3123 mlx5e_xdp_tx_enable(priv); 3124 netif_tx_start_all_queues(priv->netdev); 3125 3126 if (mlx5e_is_vport_rep(priv)) 3127 mlx5e_add_sqs_fwd_rules(priv); 3128 3129 mlx5e_wait_channels_min_rx_wqes(&priv->channels); 3130 mlx5e_redirect_rqts_to_channels(priv, &priv->channels); 3131 3132 mlx5e_xsk_redirect_rqts_to_channels(priv, &priv->channels); 3133 } 3134 3135 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv) 3136 { 3137 mlx5e_xsk_redirect_rqts_to_drop(priv, &priv->channels); 3138 3139 mlx5e_redirect_rqts_to_drop(priv); 3140 3141 if (mlx5e_is_vport_rep(priv)) 3142 mlx5e_remove_sqs_fwd_rules(priv); 3143 3144 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when 3145 * polling for inactive tx queues. 3146 */ 3147 netif_tx_stop_all_queues(priv->netdev); 3148 netif_tx_disable(priv->netdev); 3149 mlx5e_xdp_tx_disable(priv); 3150 mlx5e_deactivate_channels(&priv->channels); 3151 } 3152 3153 static int mlx5e_switch_priv_channels(struct mlx5e_priv *priv, 3154 struct mlx5e_channels *new_chs, 3155 mlx5e_fp_preactivate preactivate, 3156 void *context) 3157 { 3158 struct net_device *netdev = priv->netdev; 3159 struct mlx5e_channels old_chs; 3160 int carrier_ok; 3161 int err = 0; 3162 3163 carrier_ok = netif_carrier_ok(netdev); 3164 netif_carrier_off(netdev); 3165 3166 mlx5e_deactivate_priv_channels(priv); 3167 3168 old_chs = priv->channels; 3169 priv->channels = *new_chs; 3170 3171 /* New channels are ready to roll, call the preactivate hook if needed 3172 * to modify HW settings or update kernel parameters. 3173 */ 3174 if (preactivate) { 3175 err = preactivate(priv, context); 3176 if (err) { 3177 priv->channels = old_chs; 3178 goto out; 3179 } 3180 } 3181 3182 mlx5e_close_channels(&old_chs); 3183 priv->profile->update_rx(priv); 3184 3185 out: 3186 mlx5e_activate_priv_channels(priv); 3187 3188 /* return carrier back if needed */ 3189 if (carrier_ok) 3190 netif_carrier_on(netdev); 3191 3192 return err; 3193 } 3194 3195 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv, 3196 struct mlx5e_channels *new_chs, 3197 mlx5e_fp_preactivate preactivate, 3198 void *context) 3199 { 3200 int err; 3201 3202 err = mlx5e_open_channels(priv, new_chs); 3203 if (err) 3204 return err; 3205 3206 err = mlx5e_switch_priv_channels(priv, new_chs, preactivate, context); 3207 if (err) 3208 goto err_close; 3209 3210 return 0; 3211 3212 err_close: 3213 mlx5e_close_channels(new_chs); 3214 3215 return err; 3216 } 3217 3218 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv) 3219 { 3220 struct mlx5e_channels new_channels = {}; 3221 3222 new_channels.params = priv->channels.params; 3223 return mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL); 3224 } 3225 3226 void mlx5e_timestamp_init(struct mlx5e_priv *priv) 3227 { 3228 priv->tstamp.tx_type = HWTSTAMP_TX_OFF; 3229 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE; 3230 } 3231 3232 static void mlx5e_modify_admin_state(struct mlx5_core_dev *mdev, 3233 enum mlx5_port_status state) 3234 { 3235 struct mlx5_eswitch *esw = mdev->priv.eswitch; 3236 int vport_admin_state; 3237 3238 mlx5_set_port_admin_status(mdev, state); 3239 3240 if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS || 3241 !MLX5_CAP_GEN(mdev, uplink_follow)) 3242 return; 3243 3244 if (state == MLX5_PORT_UP) 3245 vport_admin_state = MLX5_VPORT_ADMIN_STATE_AUTO; 3246 else 3247 vport_admin_state = MLX5_VPORT_ADMIN_STATE_DOWN; 3248 3249 mlx5_eswitch_set_vport_state(esw, MLX5_VPORT_UPLINK, vport_admin_state); 3250 } 3251 3252 int mlx5e_open_locked(struct net_device *netdev) 3253 { 3254 struct mlx5e_priv *priv = netdev_priv(netdev); 3255 int err; 3256 3257 set_bit(MLX5E_STATE_OPENED, &priv->state); 3258 3259 err = mlx5e_open_channels(priv, &priv->channels); 3260 if (err) 3261 goto err_clear_state_opened_flag; 3262 3263 priv->profile->update_rx(priv); 3264 mlx5e_activate_priv_channels(priv); 3265 mlx5e_apply_traps(priv, true); 3266 if (priv->profile->update_carrier) 3267 priv->profile->update_carrier(priv); 3268 3269 mlx5e_queue_update_stats(priv); 3270 return 0; 3271 3272 err_clear_state_opened_flag: 3273 clear_bit(MLX5E_STATE_OPENED, &priv->state); 3274 return err; 3275 } 3276 3277 int mlx5e_open(struct net_device *netdev) 3278 { 3279 struct mlx5e_priv *priv = netdev_priv(netdev); 3280 int err; 3281 3282 mutex_lock(&priv->state_lock); 3283 err = mlx5e_open_locked(netdev); 3284 if (!err) 3285 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_UP); 3286 mutex_unlock(&priv->state_lock); 3287 3288 return err; 3289 } 3290 3291 int mlx5e_close_locked(struct net_device *netdev) 3292 { 3293 struct mlx5e_priv *priv = netdev_priv(netdev); 3294 3295 /* May already be CLOSED in case a previous configuration operation 3296 * (e.g RX/TX queue size change) that involves close&open failed. 3297 */ 3298 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) 3299 return 0; 3300 3301 mlx5e_apply_traps(priv, false); 3302 clear_bit(MLX5E_STATE_OPENED, &priv->state); 3303 3304 netif_carrier_off(priv->netdev); 3305 mlx5e_deactivate_priv_channels(priv); 3306 mlx5e_close_channels(&priv->channels); 3307 3308 return 0; 3309 } 3310 3311 int mlx5e_close(struct net_device *netdev) 3312 { 3313 struct mlx5e_priv *priv = netdev_priv(netdev); 3314 int err; 3315 3316 if (!netif_device_present(netdev)) 3317 return -ENODEV; 3318 3319 mutex_lock(&priv->state_lock); 3320 mlx5e_modify_admin_state(priv->mdev, MLX5_PORT_DOWN); 3321 err = mlx5e_close_locked(netdev); 3322 mutex_unlock(&priv->state_lock); 3323 3324 return err; 3325 } 3326 3327 static void mlx5e_free_drop_rq(struct mlx5e_rq *rq) 3328 { 3329 mlx5_wq_destroy(&rq->wq_ctrl); 3330 } 3331 3332 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev, 3333 struct mlx5e_rq *rq, 3334 struct mlx5e_rq_param *param) 3335 { 3336 void *rqc = param->rqc; 3337 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); 3338 int err; 3339 3340 param->wq.db_numa_node = param->wq.buf_numa_node; 3341 3342 err = mlx5_wq_cyc_create(mdev, ¶m->wq, rqc_wq, &rq->wqe.wq, 3343 &rq->wq_ctrl); 3344 if (err) 3345 return err; 3346 3347 /* Mark as unused given "Drop-RQ" packets never reach XDP */ 3348 xdp_rxq_info_unused(&rq->xdp_rxq); 3349 3350 rq->mdev = mdev; 3351 3352 return 0; 3353 } 3354 3355 static int mlx5e_alloc_drop_cq(struct mlx5e_priv *priv, 3356 struct mlx5e_cq *cq, 3357 struct mlx5e_cq_param *param) 3358 { 3359 struct mlx5_core_dev *mdev = priv->mdev; 3360 3361 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev)); 3362 param->wq.db_numa_node = dev_to_node(mlx5_core_dma_dev(mdev)); 3363 3364 return mlx5e_alloc_cq_common(priv, param, cq); 3365 } 3366 3367 int mlx5e_open_drop_rq(struct mlx5e_priv *priv, 3368 struct mlx5e_rq *drop_rq) 3369 { 3370 struct mlx5_core_dev *mdev = priv->mdev; 3371 struct mlx5e_cq_param cq_param = {}; 3372 struct mlx5e_rq_param rq_param = {}; 3373 struct mlx5e_cq *cq = &drop_rq->cq; 3374 int err; 3375 3376 mlx5e_build_drop_rq_param(priv, &rq_param); 3377 3378 err = mlx5e_alloc_drop_cq(priv, cq, &cq_param); 3379 if (err) 3380 return err; 3381 3382 err = mlx5e_create_cq(cq, &cq_param); 3383 if (err) 3384 goto err_free_cq; 3385 3386 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param); 3387 if (err) 3388 goto err_destroy_cq; 3389 3390 err = mlx5e_create_rq(drop_rq, &rq_param); 3391 if (err) 3392 goto err_free_rq; 3393 3394 err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); 3395 if (err) 3396 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err); 3397 3398 return 0; 3399 3400 err_free_rq: 3401 mlx5e_free_drop_rq(drop_rq); 3402 3403 err_destroy_cq: 3404 mlx5e_destroy_cq(cq); 3405 3406 err_free_cq: 3407 mlx5e_free_cq(cq); 3408 3409 return err; 3410 } 3411 3412 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq) 3413 { 3414 mlx5e_destroy_rq(drop_rq); 3415 mlx5e_free_drop_rq(drop_rq); 3416 mlx5e_destroy_cq(&drop_rq->cq); 3417 mlx5e_free_cq(&drop_rq->cq); 3418 } 3419 3420 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn) 3421 { 3422 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 3423 3424 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn); 3425 3426 if (MLX5_GET(tisc, tisc, tls_en)) 3427 MLX5_SET(tisc, tisc, pd, mdev->mlx5e_res.pdn); 3428 3429 if (mlx5_lag_is_lacp_owner(mdev)) 3430 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1); 3431 3432 return mlx5_core_create_tis(mdev, in, tisn); 3433 } 3434 3435 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn) 3436 { 3437 mlx5_core_destroy_tis(mdev, tisn); 3438 } 3439 3440 void mlx5e_destroy_tises(struct mlx5e_priv *priv) 3441 { 3442 int tc, i; 3443 3444 for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) 3445 for (tc = 0; tc < priv->profile->max_tc; tc++) 3446 mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]); 3447 } 3448 3449 static bool mlx5e_lag_should_assign_affinity(struct mlx5_core_dev *mdev) 3450 { 3451 return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1; 3452 } 3453 3454 int mlx5e_create_tises(struct mlx5e_priv *priv) 3455 { 3456 int tc, i; 3457 int err; 3458 3459 for (i = 0; i < mlx5e_get_num_lag_ports(priv->mdev); i++) { 3460 for (tc = 0; tc < priv->profile->max_tc; tc++) { 3461 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {}; 3462 void *tisc; 3463 3464 tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); 3465 3466 MLX5_SET(tisc, tisc, prio, tc << 1); 3467 3468 if (mlx5e_lag_should_assign_affinity(priv->mdev)) 3469 MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1); 3470 3471 err = mlx5e_create_tis(priv->mdev, in, &priv->tisn[i][tc]); 3472 if (err) 3473 goto err_close_tises; 3474 } 3475 } 3476 3477 return 0; 3478 3479 err_close_tises: 3480 for (; i >= 0; i--) { 3481 for (tc--; tc >= 0; tc--) 3482 mlx5e_destroy_tis(priv->mdev, priv->tisn[i][tc]); 3483 tc = priv->profile->max_tc; 3484 } 3485 3486 return err; 3487 } 3488 3489 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv) 3490 { 3491 mlx5e_destroy_tises(priv); 3492 } 3493 3494 static void mlx5e_build_indir_tir_ctx_common(struct mlx5e_priv *priv, 3495 u32 rqtn, u32 *tirc) 3496 { 3497 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn); 3498 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); 3499 MLX5_SET(tirc, tirc, indirect_table, rqtn); 3500 MLX5_SET(tirc, tirc, tunneled_offload_en, 3501 priv->channels.params.tunneled_offload_en); 3502 3503 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc); 3504 } 3505 3506 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, 3507 enum mlx5e_traffic_types tt, 3508 u32 *tirc) 3509 { 3510 mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc); 3511 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, 3512 &tirc_default_config[tt], tirc, false); 3513 } 3514 3515 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc) 3516 { 3517 mlx5e_build_indir_tir_ctx_common(priv, rqtn, tirc); 3518 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8); 3519 } 3520 3521 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv, 3522 enum mlx5e_traffic_types tt, 3523 u32 *tirc) 3524 { 3525 mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc); 3526 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, 3527 &tirc_default_config[tt], tirc, true); 3528 } 3529 3530 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc) 3531 { 3532 struct mlx5e_tir *tir; 3533 void *tirc; 3534 int inlen; 3535 int i = 0; 3536 int err; 3537 u32 *in; 3538 int tt; 3539 3540 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 3541 in = kvzalloc(inlen, GFP_KERNEL); 3542 if (!in) 3543 return -ENOMEM; 3544 3545 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { 3546 memset(in, 0, inlen); 3547 tir = &priv->indir_tir[tt]; 3548 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 3549 mlx5e_build_indir_tir_ctx(priv, tt, tirc); 3550 err = mlx5e_create_tir(priv->mdev, tir, in); 3551 if (err) { 3552 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err); 3553 goto err_destroy_inner_tirs; 3554 } 3555 } 3556 3557 if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev)) 3558 goto out; 3559 3560 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) { 3561 memset(in, 0, inlen); 3562 tir = &priv->inner_indir_tir[i]; 3563 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 3564 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc); 3565 err = mlx5e_create_tir(priv->mdev, tir, in); 3566 if (err) { 3567 mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err); 3568 goto err_destroy_inner_tirs; 3569 } 3570 } 3571 3572 out: 3573 kvfree(in); 3574 3575 return 0; 3576 3577 err_destroy_inner_tirs: 3578 for (i--; i >= 0; i--) 3579 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]); 3580 3581 for (tt--; tt >= 0; tt--) 3582 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]); 3583 3584 kvfree(in); 3585 3586 return err; 3587 } 3588 3589 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs) 3590 { 3591 struct mlx5e_tir *tir; 3592 void *tirc; 3593 int inlen; 3594 int err = 0; 3595 u32 *in; 3596 int ix; 3597 3598 inlen = MLX5_ST_SZ_BYTES(create_tir_in); 3599 in = kvzalloc(inlen, GFP_KERNEL); 3600 if (!in) 3601 return -ENOMEM; 3602 3603 for (ix = 0; ix < priv->max_nch; ix++) { 3604 memset(in, 0, inlen); 3605 tir = &tirs[ix]; 3606 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); 3607 mlx5e_build_direct_tir_ctx(priv, tir->rqt.rqtn, tirc); 3608 err = mlx5e_create_tir(priv->mdev, tir, in); 3609 if (unlikely(err)) 3610 goto err_destroy_ch_tirs; 3611 } 3612 3613 goto out; 3614 3615 err_destroy_ch_tirs: 3616 mlx5_core_warn(priv->mdev, "create tirs failed, %d\n", err); 3617 for (ix--; ix >= 0; ix--) 3618 mlx5e_destroy_tir(priv->mdev, &tirs[ix]); 3619 3620 out: 3621 kvfree(in); 3622 3623 return err; 3624 } 3625 3626 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv) 3627 { 3628 int i; 3629 3630 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) 3631 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]); 3632 3633 /* Verify inner tirs resources allocated */ 3634 if (!priv->inner_indir_tir[0].tirn) 3635 return; 3636 3637 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) 3638 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]); 3639 } 3640 3641 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs) 3642 { 3643 int i; 3644 3645 for (i = 0; i < priv->max_nch; i++) 3646 mlx5e_destroy_tir(priv->mdev, &tirs[i]); 3647 } 3648 3649 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable) 3650 { 3651 int err = 0; 3652 int i; 3653 3654 for (i = 0; i < chs->num; i++) { 3655 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable); 3656 if (err) 3657 return err; 3658 } 3659 3660 return 0; 3661 } 3662 3663 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd) 3664 { 3665 int err = 0; 3666 int i; 3667 3668 for (i = 0; i < chs->num; i++) { 3669 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd); 3670 if (err) 3671 return err; 3672 } 3673 3674 return 0; 3675 } 3676 3677 static int mlx5e_setup_tc_mqprio(struct mlx5e_priv *priv, 3678 struct tc_mqprio_qopt *mqprio) 3679 { 3680 struct mlx5e_channels new_channels = {}; 3681 u8 tc = mqprio->num_tc; 3682 int err = 0; 3683 3684 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 3685 3686 if (tc && tc != MLX5E_MAX_NUM_TC) 3687 return -EINVAL; 3688 3689 mutex_lock(&priv->state_lock); 3690 3691 /* MQPRIO is another toplevel qdisc that can't be attached 3692 * simultaneously with the offloaded HTB. 3693 */ 3694 if (WARN_ON(priv->htb.maj_id)) { 3695 err = -EINVAL; 3696 goto out; 3697 } 3698 3699 new_channels.params = priv->channels.params; 3700 new_channels.params.num_tc = tc ? tc : 1; 3701 3702 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { 3703 struct mlx5e_params old_params; 3704 3705 old_params = priv->channels.params; 3706 priv->channels.params = new_channels.params; 3707 err = mlx5e_num_channels_changed(priv); 3708 if (err) 3709 priv->channels.params = old_params; 3710 3711 goto out; 3712 } 3713 3714 err = mlx5e_safe_switch_channels(priv, &new_channels, 3715 mlx5e_num_channels_changed_ctx, NULL); 3716 3717 out: 3718 priv->max_opened_tc = max_t(u8, priv->max_opened_tc, 3719 priv->channels.params.num_tc); 3720 mutex_unlock(&priv->state_lock); 3721 return err; 3722 } 3723 3724 static int mlx5e_setup_tc_htb(struct mlx5e_priv *priv, struct tc_htb_qopt_offload *htb) 3725 { 3726 int res; 3727 3728 switch (htb->command) { 3729 case TC_HTB_CREATE: 3730 return mlx5e_htb_root_add(priv, htb->parent_classid, htb->classid, 3731 htb->extack); 3732 case TC_HTB_DESTROY: 3733 return mlx5e_htb_root_del(priv); 3734 case TC_HTB_LEAF_ALLOC_QUEUE: 3735 res = mlx5e_htb_leaf_alloc_queue(priv, htb->classid, htb->parent_classid, 3736 htb->rate, htb->ceil, htb->extack); 3737 if (res < 0) 3738 return res; 3739 htb->qid = res; 3740 return 0; 3741 case TC_HTB_LEAF_TO_INNER: 3742 return mlx5e_htb_leaf_to_inner(priv, htb->parent_classid, htb->classid, 3743 htb->rate, htb->ceil, htb->extack); 3744 case TC_HTB_LEAF_DEL: 3745 return mlx5e_htb_leaf_del(priv, htb->classid, &htb->moved_qid, &htb->qid, 3746 htb->extack); 3747 case TC_HTB_LEAF_DEL_LAST: 3748 case TC_HTB_LEAF_DEL_LAST_FORCE: 3749 return mlx5e_htb_leaf_del_last(priv, htb->classid, 3750 htb->command == TC_HTB_LEAF_DEL_LAST_FORCE, 3751 htb->extack); 3752 case TC_HTB_NODE_MODIFY: 3753 return mlx5e_htb_node_modify(priv, htb->classid, htb->rate, htb->ceil, 3754 htb->extack); 3755 case TC_HTB_LEAF_QUERY_QUEUE: 3756 res = mlx5e_get_txq_by_classid(priv, htb->classid); 3757 if (res < 0) 3758 return res; 3759 htb->qid = res; 3760 return 0; 3761 default: 3762 return -EOPNOTSUPP; 3763 } 3764 } 3765 3766 static LIST_HEAD(mlx5e_block_cb_list); 3767 3768 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type, 3769 void *type_data) 3770 { 3771 struct mlx5e_priv *priv = netdev_priv(dev); 3772 int err; 3773 3774 switch (type) { 3775 case TC_SETUP_BLOCK: { 3776 struct flow_block_offload *f = type_data; 3777 3778 f->unlocked_driver_cb = true; 3779 return flow_block_cb_setup_simple(type_data, 3780 &mlx5e_block_cb_list, 3781 mlx5e_setup_tc_block_cb, 3782 priv, priv, true); 3783 } 3784 case TC_SETUP_QDISC_MQPRIO: 3785 return mlx5e_setup_tc_mqprio(priv, type_data); 3786 case TC_SETUP_QDISC_HTB: 3787 mutex_lock(&priv->state_lock); 3788 err = mlx5e_setup_tc_htb(priv, type_data); 3789 mutex_unlock(&priv->state_lock); 3790 return err; 3791 default: 3792 return -EOPNOTSUPP; 3793 } 3794 } 3795 3796 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s) 3797 { 3798 int i; 3799 3800 for (i = 0; i < priv->max_nch; i++) { 3801 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i]; 3802 struct mlx5e_rq_stats *xskrq_stats = &channel_stats->xskrq; 3803 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq; 3804 int j; 3805 3806 s->rx_packets += rq_stats->packets + xskrq_stats->packets; 3807 s->rx_bytes += rq_stats->bytes + xskrq_stats->bytes; 3808 s->multicast += rq_stats->mcast_packets + xskrq_stats->mcast_packets; 3809 3810 for (j = 0; j < priv->max_opened_tc; j++) { 3811 struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j]; 3812 3813 s->tx_packets += sq_stats->packets; 3814 s->tx_bytes += sq_stats->bytes; 3815 s->tx_dropped += sq_stats->dropped; 3816 } 3817 } 3818 } 3819 3820 void 3821 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats) 3822 { 3823 struct mlx5e_priv *priv = netdev_priv(dev); 3824 struct mlx5e_pport_stats *pstats = &priv->stats.pport; 3825 3826 /* In switchdev mode, monitor counters doesn't monitor 3827 * rx/tx stats of 802_3. The update stats mechanism 3828 * should keep the 802_3 layout counters updated 3829 */ 3830 if (!mlx5e_monitor_counter_supported(priv) || 3831 mlx5e_is_uplink_rep(priv)) { 3832 /* update HW stats in background for next time */ 3833 mlx5e_queue_update_stats(priv); 3834 } 3835 3836 if (mlx5e_is_uplink_rep(priv)) { 3837 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok); 3838 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok); 3839 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok); 3840 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok); 3841 } else { 3842 mlx5e_fold_sw_stats64(priv, stats); 3843 } 3844 3845 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer; 3846 3847 stats->rx_length_errors = 3848 PPORT_802_3_GET(pstats, a_in_range_length_errors) + 3849 PPORT_802_3_GET(pstats, a_out_of_range_length_field) + 3850 PPORT_802_3_GET(pstats, a_frame_too_long_errors); 3851 stats->rx_crc_errors = 3852 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors); 3853 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors); 3854 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards); 3855 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 3856 stats->rx_frame_errors; 3857 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors; 3858 } 3859 3860 static void mlx5e_set_rx_mode(struct net_device *dev) 3861 { 3862 struct mlx5e_priv *priv = netdev_priv(dev); 3863 3864 queue_work(priv->wq, &priv->set_rx_mode_work); 3865 } 3866 3867 static int mlx5e_set_mac(struct net_device *netdev, void *addr) 3868 { 3869 struct mlx5e_priv *priv = netdev_priv(netdev); 3870 struct sockaddr *saddr = addr; 3871 3872 if (!is_valid_ether_addr(saddr->sa_data)) 3873 return -EADDRNOTAVAIL; 3874 3875 netif_addr_lock_bh(netdev); 3876 ether_addr_copy(netdev->dev_addr, saddr->sa_data); 3877 netif_addr_unlock_bh(netdev); 3878 3879 queue_work(priv->wq, &priv->set_rx_mode_work); 3880 3881 return 0; 3882 } 3883 3884 #define MLX5E_SET_FEATURE(features, feature, enable) \ 3885 do { \ 3886 if (enable) \ 3887 *features |= feature; \ 3888 else \ 3889 *features &= ~feature; \ 3890 } while (0) 3891 3892 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable); 3893 3894 static int set_feature_lro(struct net_device *netdev, bool enable) 3895 { 3896 struct mlx5e_priv *priv = netdev_priv(netdev); 3897 struct mlx5_core_dev *mdev = priv->mdev; 3898 struct mlx5e_channels new_channels = {}; 3899 struct mlx5e_params *cur_params; 3900 int err = 0; 3901 bool reset; 3902 3903 mutex_lock(&priv->state_lock); 3904 3905 if (enable && priv->xsk.refcnt) { 3906 netdev_warn(netdev, "LRO is incompatible with AF_XDP (%u XSKs are active)\n", 3907 priv->xsk.refcnt); 3908 err = -EINVAL; 3909 goto out; 3910 } 3911 3912 cur_params = &priv->channels.params; 3913 if (enable && !MLX5E_GET_PFLAG(cur_params, MLX5E_PFLAG_RX_STRIDING_RQ)) { 3914 netdev_warn(netdev, "can't set LRO with legacy RQ\n"); 3915 err = -EINVAL; 3916 goto out; 3917 } 3918 3919 reset = test_bit(MLX5E_STATE_OPENED, &priv->state); 3920 3921 new_channels.params = *cur_params; 3922 new_channels.params.lro_en = enable; 3923 3924 if (cur_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) { 3925 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, cur_params, NULL) == 3926 mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params, NULL)) 3927 reset = false; 3928 } 3929 3930 if (!reset) { 3931 struct mlx5e_params old_params; 3932 3933 old_params = *cur_params; 3934 *cur_params = new_channels.params; 3935 err = mlx5e_modify_tirs_lro(priv); 3936 if (err) 3937 *cur_params = old_params; 3938 goto out; 3939 } 3940 3941 err = mlx5e_safe_switch_channels(priv, &new_channels, 3942 mlx5e_modify_tirs_lro_ctx, NULL); 3943 out: 3944 mutex_unlock(&priv->state_lock); 3945 return err; 3946 } 3947 3948 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable) 3949 { 3950 struct mlx5e_priv *priv = netdev_priv(netdev); 3951 3952 if (enable) 3953 mlx5e_enable_cvlan_filter(priv); 3954 else 3955 mlx5e_disable_cvlan_filter(priv); 3956 3957 return 0; 3958 } 3959 3960 static int set_feature_hw_tc(struct net_device *netdev, bool enable) 3961 { 3962 struct mlx5e_priv *priv = netdev_priv(netdev); 3963 3964 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT) 3965 if (!enable && mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD))) { 3966 netdev_err(netdev, 3967 "Active offloaded tc filters, can't turn hw_tc_offload off\n"); 3968 return -EINVAL; 3969 } 3970 #endif 3971 3972 if (!enable && priv->htb.maj_id) { 3973 netdev_err(netdev, "Active HTB offload, can't turn hw_tc_offload off\n"); 3974 return -EINVAL; 3975 } 3976 3977 return 0; 3978 } 3979 3980 static int set_feature_rx_all(struct net_device *netdev, bool enable) 3981 { 3982 struct mlx5e_priv *priv = netdev_priv(netdev); 3983 struct mlx5_core_dev *mdev = priv->mdev; 3984 3985 return mlx5_set_port_fcs(mdev, !enable); 3986 } 3987 3988 static int set_feature_rx_fcs(struct net_device *netdev, bool enable) 3989 { 3990 struct mlx5e_priv *priv = netdev_priv(netdev); 3991 int err; 3992 3993 mutex_lock(&priv->state_lock); 3994 3995 priv->channels.params.scatter_fcs_en = enable; 3996 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable); 3997 if (err) 3998 priv->channels.params.scatter_fcs_en = !enable; 3999 4000 mutex_unlock(&priv->state_lock); 4001 4002 return err; 4003 } 4004 4005 static int set_feature_rx_vlan(struct net_device *netdev, bool enable) 4006 { 4007 struct mlx5e_priv *priv = netdev_priv(netdev); 4008 int err = 0; 4009 4010 mutex_lock(&priv->state_lock); 4011 4012 priv->channels.params.vlan_strip_disable = !enable; 4013 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) 4014 goto unlock; 4015 4016 err = mlx5e_modify_channels_vsd(&priv->channels, !enable); 4017 if (err) 4018 priv->channels.params.vlan_strip_disable = enable; 4019 4020 unlock: 4021 mutex_unlock(&priv->state_lock); 4022 4023 return err; 4024 } 4025 4026 #ifdef CONFIG_MLX5_EN_ARFS 4027 static int set_feature_arfs(struct net_device *netdev, bool enable) 4028 { 4029 struct mlx5e_priv *priv = netdev_priv(netdev); 4030 int err; 4031 4032 if (enable) 4033 err = mlx5e_arfs_enable(priv); 4034 else 4035 err = mlx5e_arfs_disable(priv); 4036 4037 return err; 4038 } 4039 #endif 4040 4041 static int mlx5e_handle_feature(struct net_device *netdev, 4042 netdev_features_t *features, 4043 netdev_features_t wanted_features, 4044 netdev_features_t feature, 4045 mlx5e_feature_handler feature_handler) 4046 { 4047 netdev_features_t changes = wanted_features ^ netdev->features; 4048 bool enable = !!(wanted_features & feature); 4049 int err; 4050 4051 if (!(changes & feature)) 4052 return 0; 4053 4054 err = feature_handler(netdev, enable); 4055 if (err) { 4056 netdev_err(netdev, "%s feature %pNF failed, err %d\n", 4057 enable ? "Enable" : "Disable", &feature, err); 4058 return err; 4059 } 4060 4061 MLX5E_SET_FEATURE(features, feature, enable); 4062 return 0; 4063 } 4064 4065 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features) 4066 { 4067 netdev_features_t oper_features = netdev->features; 4068 int err = 0; 4069 4070 #define MLX5E_HANDLE_FEATURE(feature, handler) \ 4071 mlx5e_handle_feature(netdev, &oper_features, features, feature, handler) 4072 4073 err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro); 4074 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER, 4075 set_feature_cvlan_filter); 4076 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_hw_tc); 4077 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all); 4078 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs); 4079 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan); 4080 #ifdef CONFIG_MLX5_EN_ARFS 4081 err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs); 4082 #endif 4083 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TLS_RX, mlx5e_ktls_set_feature_rx); 4084 4085 if (err) { 4086 netdev->features = oper_features; 4087 return -EINVAL; 4088 } 4089 4090 return 0; 4091 } 4092 4093 static netdev_features_t mlx5e_fix_features(struct net_device *netdev, 4094 netdev_features_t features) 4095 { 4096 struct mlx5e_priv *priv = netdev_priv(netdev); 4097 struct mlx5e_params *params; 4098 4099 mutex_lock(&priv->state_lock); 4100 params = &priv->channels.params; 4101 if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) { 4102 /* HW strips the outer C-tag header, this is a problem 4103 * for S-tag traffic. 4104 */ 4105 features &= ~NETIF_F_HW_VLAN_CTAG_RX; 4106 if (!params->vlan_strip_disable) 4107 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n"); 4108 } 4109 4110 if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) { 4111 if (features & NETIF_F_LRO) { 4112 netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n"); 4113 features &= ~NETIF_F_LRO; 4114 } 4115 } 4116 4117 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) { 4118 features &= ~NETIF_F_RXHASH; 4119 if (netdev->features & NETIF_F_RXHASH) 4120 netdev_warn(netdev, "Disabling rxhash, not supported when CQE compress is active\n"); 4121 } 4122 4123 mutex_unlock(&priv->state_lock); 4124 4125 return features; 4126 } 4127 4128 static bool mlx5e_xsk_validate_mtu(struct net_device *netdev, 4129 struct mlx5e_channels *chs, 4130 struct mlx5e_params *new_params, 4131 struct mlx5_core_dev *mdev) 4132 { 4133 u16 ix; 4134 4135 for (ix = 0; ix < chs->params.num_channels; ix++) { 4136 struct xsk_buff_pool *xsk_pool = 4137 mlx5e_xsk_get_pool(&chs->params, chs->params.xsk, ix); 4138 struct mlx5e_xsk_param xsk; 4139 4140 if (!xsk_pool) 4141 continue; 4142 4143 mlx5e_build_xsk_param(xsk_pool, &xsk); 4144 4145 if (!mlx5e_validate_xsk_param(new_params, &xsk, mdev)) { 4146 u32 hr = mlx5e_get_linear_rq_headroom(new_params, &xsk); 4147 int max_mtu_frame, max_mtu_page, max_mtu; 4148 4149 /* Two criteria must be met: 4150 * 1. HW MTU + all headrooms <= XSK frame size. 4151 * 2. Size of SKBs allocated on XDP_PASS <= PAGE_SIZE. 4152 */ 4153 max_mtu_frame = MLX5E_HW2SW_MTU(new_params, xsk.chunk_size - hr); 4154 max_mtu_page = mlx5e_xdp_max_mtu(new_params, &xsk); 4155 max_mtu = min(max_mtu_frame, max_mtu_page); 4156 4157 netdev_err(netdev, "MTU %d is too big for an XSK running on channel %u. Try MTU <= %d\n", 4158 new_params->sw_mtu, ix, max_mtu); 4159 return false; 4160 } 4161 } 4162 4163 return true; 4164 } 4165 4166 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu, 4167 mlx5e_fp_preactivate preactivate) 4168 { 4169 struct mlx5e_priv *priv = netdev_priv(netdev); 4170 struct mlx5e_channels new_channels = {}; 4171 struct mlx5e_params *params; 4172 int err = 0; 4173 bool reset; 4174 4175 mutex_lock(&priv->state_lock); 4176 4177 params = &priv->channels.params; 4178 4179 reset = !params->lro_en; 4180 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state); 4181 4182 new_channels.params = *params; 4183 new_channels.params.sw_mtu = new_mtu; 4184 err = mlx5e_validate_params(priv, &new_channels.params); 4185 if (err) 4186 goto out; 4187 4188 if (params->xdp_prog && 4189 !mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) { 4190 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n", 4191 new_mtu, mlx5e_xdp_max_mtu(params, NULL)); 4192 err = -EINVAL; 4193 goto out; 4194 } 4195 4196 if (priv->xsk.refcnt && 4197 !mlx5e_xsk_validate_mtu(netdev, &priv->channels, 4198 &new_channels.params, priv->mdev)) { 4199 err = -EINVAL; 4200 goto out; 4201 } 4202 4203 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) { 4204 bool is_linear = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, 4205 &new_channels.params, 4206 NULL); 4207 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params, NULL); 4208 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params, NULL); 4209 4210 /* If XSK is active, XSK RQs are linear. */ 4211 is_linear |= priv->xsk.refcnt; 4212 4213 /* Always reset in linear mode - hw_mtu is used in data path. */ 4214 reset = reset && (is_linear || (ppw_old != ppw_new)); 4215 } 4216 4217 if (!reset) { 4218 unsigned int old_mtu = params->sw_mtu; 4219 4220 params->sw_mtu = new_mtu; 4221 if (preactivate) { 4222 err = preactivate(priv, NULL); 4223 if (err) { 4224 params->sw_mtu = old_mtu; 4225 goto out; 4226 } 4227 } 4228 netdev->mtu = params->sw_mtu; 4229 goto out; 4230 } 4231 4232 err = mlx5e_safe_switch_channels(priv, &new_channels, preactivate, NULL); 4233 if (err) 4234 goto out; 4235 4236 netdev->mtu = new_channels.params.sw_mtu; 4237 4238 out: 4239 mutex_unlock(&priv->state_lock); 4240 return err; 4241 } 4242 4243 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu) 4244 { 4245 return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu_ctx); 4246 } 4247 4248 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr) 4249 { 4250 struct hwtstamp_config config; 4251 int err; 4252 4253 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) || 4254 (mlx5_clock_get_ptp_index(priv->mdev) == -1)) 4255 return -EOPNOTSUPP; 4256 4257 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 4258 return -EFAULT; 4259 4260 /* TX HW timestamp */ 4261 switch (config.tx_type) { 4262 case HWTSTAMP_TX_OFF: 4263 case HWTSTAMP_TX_ON: 4264 break; 4265 default: 4266 return -ERANGE; 4267 } 4268 4269 mutex_lock(&priv->state_lock); 4270 /* RX HW timestamp */ 4271 switch (config.rx_filter) { 4272 case HWTSTAMP_FILTER_NONE: 4273 /* Reset CQE compression to Admin default */ 4274 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def); 4275 break; 4276 case HWTSTAMP_FILTER_ALL: 4277 case HWTSTAMP_FILTER_SOME: 4278 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 4279 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 4280 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 4281 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 4282 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 4283 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 4284 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 4285 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 4286 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 4287 case HWTSTAMP_FILTER_PTP_V2_EVENT: 4288 case HWTSTAMP_FILTER_PTP_V2_SYNC: 4289 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 4290 case HWTSTAMP_FILTER_NTP_ALL: 4291 /* Disable CQE compression */ 4292 if (MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS)) 4293 netdev_warn(priv->netdev, "Disabling RX cqe compression\n"); 4294 err = mlx5e_modify_rx_cqe_compression_locked(priv, false); 4295 if (err) { 4296 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err); 4297 mutex_unlock(&priv->state_lock); 4298 return err; 4299 } 4300 config.rx_filter = HWTSTAMP_FILTER_ALL; 4301 break; 4302 default: 4303 mutex_unlock(&priv->state_lock); 4304 return -ERANGE; 4305 } 4306 4307 memcpy(&priv->tstamp, &config, sizeof(config)); 4308 mutex_unlock(&priv->state_lock); 4309 4310 /* might need to fix some features */ 4311 netdev_update_features(priv->netdev); 4312 4313 return copy_to_user(ifr->ifr_data, &config, 4314 sizeof(config)) ? -EFAULT : 0; 4315 } 4316 4317 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr) 4318 { 4319 struct hwtstamp_config *cfg = &priv->tstamp; 4320 4321 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz)) 4322 return -EOPNOTSUPP; 4323 4324 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0; 4325 } 4326 4327 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 4328 { 4329 struct mlx5e_priv *priv = netdev_priv(dev); 4330 4331 switch (cmd) { 4332 case SIOCSHWTSTAMP: 4333 return mlx5e_hwstamp_set(priv, ifr); 4334 case SIOCGHWTSTAMP: 4335 return mlx5e_hwstamp_get(priv, ifr); 4336 default: 4337 return -EOPNOTSUPP; 4338 } 4339 } 4340 4341 #ifdef CONFIG_MLX5_ESWITCH 4342 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac) 4343 { 4344 struct mlx5e_priv *priv = netdev_priv(dev); 4345 struct mlx5_core_dev *mdev = priv->mdev; 4346 4347 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac); 4348 } 4349 4350 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos, 4351 __be16 vlan_proto) 4352 { 4353 struct mlx5e_priv *priv = netdev_priv(dev); 4354 struct mlx5_core_dev *mdev = priv->mdev; 4355 4356 if (vlan_proto != htons(ETH_P_8021Q)) 4357 return -EPROTONOSUPPORT; 4358 4359 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1, 4360 vlan, qos); 4361 } 4362 4363 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting) 4364 { 4365 struct mlx5e_priv *priv = netdev_priv(dev); 4366 struct mlx5_core_dev *mdev = priv->mdev; 4367 4368 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting); 4369 } 4370 4371 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting) 4372 { 4373 struct mlx5e_priv *priv = netdev_priv(dev); 4374 struct mlx5_core_dev *mdev = priv->mdev; 4375 4376 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting); 4377 } 4378 4379 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, 4380 int max_tx_rate) 4381 { 4382 struct mlx5e_priv *priv = netdev_priv(dev); 4383 struct mlx5_core_dev *mdev = priv->mdev; 4384 4385 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1, 4386 max_tx_rate, min_tx_rate); 4387 } 4388 4389 static int mlx5_vport_link2ifla(u8 esw_link) 4390 { 4391 switch (esw_link) { 4392 case MLX5_VPORT_ADMIN_STATE_DOWN: 4393 return IFLA_VF_LINK_STATE_DISABLE; 4394 case MLX5_VPORT_ADMIN_STATE_UP: 4395 return IFLA_VF_LINK_STATE_ENABLE; 4396 } 4397 return IFLA_VF_LINK_STATE_AUTO; 4398 } 4399 4400 static int mlx5_ifla_link2vport(u8 ifla_link) 4401 { 4402 switch (ifla_link) { 4403 case IFLA_VF_LINK_STATE_DISABLE: 4404 return MLX5_VPORT_ADMIN_STATE_DOWN; 4405 case IFLA_VF_LINK_STATE_ENABLE: 4406 return MLX5_VPORT_ADMIN_STATE_UP; 4407 } 4408 return MLX5_VPORT_ADMIN_STATE_AUTO; 4409 } 4410 4411 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf, 4412 int link_state) 4413 { 4414 struct mlx5e_priv *priv = netdev_priv(dev); 4415 struct mlx5_core_dev *mdev = priv->mdev; 4416 4417 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1, 4418 mlx5_ifla_link2vport(link_state)); 4419 } 4420 4421 int mlx5e_get_vf_config(struct net_device *dev, 4422 int vf, struct ifla_vf_info *ivi) 4423 { 4424 struct mlx5e_priv *priv = netdev_priv(dev); 4425 struct mlx5_core_dev *mdev = priv->mdev; 4426 int err; 4427 4428 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi); 4429 if (err) 4430 return err; 4431 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate); 4432 return 0; 4433 } 4434 4435 int mlx5e_get_vf_stats(struct net_device *dev, 4436 int vf, struct ifla_vf_stats *vf_stats) 4437 { 4438 struct mlx5e_priv *priv = netdev_priv(dev); 4439 struct mlx5_core_dev *mdev = priv->mdev; 4440 4441 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1, 4442 vf_stats); 4443 } 4444 #endif 4445 4446 static bool mlx5e_tunnel_proto_supported_tx(struct mlx5_core_dev *mdev, u8 proto_type) 4447 { 4448 switch (proto_type) { 4449 case IPPROTO_GRE: 4450 return MLX5_CAP_ETH(mdev, tunnel_stateless_gre); 4451 case IPPROTO_IPIP: 4452 case IPPROTO_IPV6: 4453 return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) || 4454 MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_tx)); 4455 default: 4456 return false; 4457 } 4458 } 4459 4460 static bool mlx5e_gre_tunnel_inner_proto_offload_supported(struct mlx5_core_dev *mdev, 4461 struct sk_buff *skb) 4462 { 4463 switch (skb->inner_protocol) { 4464 case htons(ETH_P_IP): 4465 case htons(ETH_P_IPV6): 4466 case htons(ETH_P_TEB): 4467 return true; 4468 case htons(ETH_P_MPLS_UC): 4469 case htons(ETH_P_MPLS_MC): 4470 return MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre); 4471 } 4472 return false; 4473 } 4474 4475 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv, 4476 struct sk_buff *skb, 4477 netdev_features_t features) 4478 { 4479 unsigned int offset = 0; 4480 struct udphdr *udph; 4481 u8 proto; 4482 u16 port; 4483 4484 switch (vlan_get_protocol(skb)) { 4485 case htons(ETH_P_IP): 4486 proto = ip_hdr(skb)->protocol; 4487 break; 4488 case htons(ETH_P_IPV6): 4489 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL); 4490 break; 4491 default: 4492 goto out; 4493 } 4494 4495 switch (proto) { 4496 case IPPROTO_GRE: 4497 if (mlx5e_gre_tunnel_inner_proto_offload_supported(priv->mdev, skb)) 4498 return features; 4499 break; 4500 case IPPROTO_IPIP: 4501 case IPPROTO_IPV6: 4502 if (mlx5e_tunnel_proto_supported_tx(priv->mdev, IPPROTO_IPIP)) 4503 return features; 4504 break; 4505 case IPPROTO_UDP: 4506 udph = udp_hdr(skb); 4507 port = be16_to_cpu(udph->dest); 4508 4509 /* Verify if UDP port is being offloaded by HW */ 4510 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port)) 4511 return features; 4512 4513 #if IS_ENABLED(CONFIG_GENEVE) 4514 /* Support Geneve offload for default UDP port */ 4515 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev)) 4516 return features; 4517 #endif 4518 } 4519 4520 out: 4521 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */ 4522 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 4523 } 4524 4525 netdev_features_t mlx5e_features_check(struct sk_buff *skb, 4526 struct net_device *netdev, 4527 netdev_features_t features) 4528 { 4529 struct mlx5e_priv *priv = netdev_priv(netdev); 4530 4531 features = vlan_features_check(skb, features); 4532 features = vxlan_features_check(skb, features); 4533 4534 if (mlx5e_ipsec_feature_check(skb, netdev, features)) 4535 return features; 4536 4537 /* Validate if the tunneled packet is being offloaded by HW */ 4538 if (skb->encapsulation && 4539 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK)) 4540 return mlx5e_tunnel_features_check(priv, skb, features); 4541 4542 return features; 4543 } 4544 4545 static void mlx5e_tx_timeout_work(struct work_struct *work) 4546 { 4547 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, 4548 tx_timeout_work); 4549 struct net_device *netdev = priv->netdev; 4550 int i; 4551 4552 rtnl_lock(); 4553 mutex_lock(&priv->state_lock); 4554 4555 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) 4556 goto unlock; 4557 4558 for (i = 0; i < netdev->real_num_tx_queues; i++) { 4559 struct netdev_queue *dev_queue = 4560 netdev_get_tx_queue(netdev, i); 4561 struct mlx5e_txqsq *sq = priv->txq2sq[i]; 4562 4563 if (!netif_xmit_stopped(dev_queue)) 4564 continue; 4565 4566 if (mlx5e_reporter_tx_timeout(sq)) 4567 /* break if tried to reopened channels */ 4568 break; 4569 } 4570 4571 unlock: 4572 mutex_unlock(&priv->state_lock); 4573 rtnl_unlock(); 4574 } 4575 4576 static void mlx5e_tx_timeout(struct net_device *dev, unsigned int txqueue) 4577 { 4578 struct mlx5e_priv *priv = netdev_priv(dev); 4579 4580 netdev_err(dev, "TX timeout detected\n"); 4581 queue_work(priv->wq, &priv->tx_timeout_work); 4582 } 4583 4584 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog) 4585 { 4586 struct net_device *netdev = priv->netdev; 4587 struct mlx5e_channels new_channels = {}; 4588 4589 if (priv->channels.params.lro_en) { 4590 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n"); 4591 return -EINVAL; 4592 } 4593 4594 if (mlx5_fpga_is_ipsec_device(priv->mdev)) { 4595 netdev_warn(netdev, 4596 "XDP is not available on Innova cards with IPsec support\n"); 4597 return -EINVAL; 4598 } 4599 4600 new_channels.params = priv->channels.params; 4601 new_channels.params.xdp_prog = prog; 4602 4603 /* No XSK params: AF_XDP can't be enabled yet at the point of setting 4604 * the XDP program. 4605 */ 4606 if (!mlx5e_rx_is_linear_skb(&new_channels.params, NULL)) { 4607 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n", 4608 new_channels.params.sw_mtu, 4609 mlx5e_xdp_max_mtu(&new_channels.params, NULL)); 4610 return -EINVAL; 4611 } 4612 4613 return 0; 4614 } 4615 4616 static void mlx5e_rq_replace_xdp_prog(struct mlx5e_rq *rq, struct bpf_prog *prog) 4617 { 4618 struct bpf_prog *old_prog; 4619 4620 old_prog = rcu_replace_pointer(rq->xdp_prog, prog, 4621 lockdep_is_held(&rq->priv->state_lock)); 4622 if (old_prog) 4623 bpf_prog_put(old_prog); 4624 } 4625 4626 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog) 4627 { 4628 struct mlx5e_priv *priv = netdev_priv(netdev); 4629 struct bpf_prog *old_prog; 4630 bool reset, was_opened; 4631 int err = 0; 4632 int i; 4633 4634 mutex_lock(&priv->state_lock); 4635 4636 if (prog) { 4637 err = mlx5e_xdp_allowed(priv, prog); 4638 if (err) 4639 goto unlock; 4640 } 4641 4642 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 4643 /* no need for full reset when exchanging programs */ 4644 reset = (!priv->channels.params.xdp_prog || !prog); 4645 4646 if (was_opened && !reset) 4647 /* num_channels is invariant here, so we can take the 4648 * batched reference right upfront. 4649 */ 4650 bpf_prog_add(prog, priv->channels.num); 4651 4652 if (was_opened && reset) { 4653 struct mlx5e_channels new_channels = {}; 4654 4655 new_channels.params = priv->channels.params; 4656 new_channels.params.xdp_prog = prog; 4657 mlx5e_set_rq_type(priv->mdev, &new_channels.params); 4658 old_prog = priv->channels.params.xdp_prog; 4659 4660 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL); 4661 if (err) 4662 goto unlock; 4663 } else { 4664 /* exchange programs, extra prog reference we got from caller 4665 * as long as we don't fail from this point onwards. 4666 */ 4667 old_prog = xchg(&priv->channels.params.xdp_prog, prog); 4668 } 4669 4670 if (old_prog) 4671 bpf_prog_put(old_prog); 4672 4673 if (!was_opened && reset) /* change RQ type according to priv->xdp_prog */ 4674 mlx5e_set_rq_type(priv->mdev, &priv->channels.params); 4675 4676 if (!was_opened || reset) 4677 goto unlock; 4678 4679 /* exchanging programs w/o reset, we update ref counts on behalf 4680 * of the channels RQs here. 4681 */ 4682 for (i = 0; i < priv->channels.num; i++) { 4683 struct mlx5e_channel *c = priv->channels.c[i]; 4684 4685 mlx5e_rq_replace_xdp_prog(&c->rq, prog); 4686 if (test_bit(MLX5E_CHANNEL_STATE_XSK, c->state)) 4687 mlx5e_rq_replace_xdp_prog(&c->xskrq, prog); 4688 } 4689 4690 unlock: 4691 mutex_unlock(&priv->state_lock); 4692 return err; 4693 } 4694 4695 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp) 4696 { 4697 switch (xdp->command) { 4698 case XDP_SETUP_PROG: 4699 return mlx5e_xdp_set(dev, xdp->prog); 4700 case XDP_SETUP_XSK_POOL: 4701 return mlx5e_xsk_setup_pool(dev, xdp->xsk.pool, 4702 xdp->xsk.queue_id); 4703 default: 4704 return -EINVAL; 4705 } 4706 } 4707 4708 #ifdef CONFIG_MLX5_ESWITCH 4709 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, 4710 struct net_device *dev, u32 filter_mask, 4711 int nlflags) 4712 { 4713 struct mlx5e_priv *priv = netdev_priv(dev); 4714 struct mlx5_core_dev *mdev = priv->mdev; 4715 u8 mode, setting; 4716 int err; 4717 4718 err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting); 4719 if (err) 4720 return err; 4721 mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB; 4722 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, 4723 mode, 4724 0, 0, nlflags, filter_mask, NULL); 4725 } 4726 4727 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh, 4728 u16 flags, struct netlink_ext_ack *extack) 4729 { 4730 struct mlx5e_priv *priv = netdev_priv(dev); 4731 struct mlx5_core_dev *mdev = priv->mdev; 4732 struct nlattr *attr, *br_spec; 4733 u16 mode = BRIDGE_MODE_UNDEF; 4734 u8 setting; 4735 int rem; 4736 4737 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); 4738 if (!br_spec) 4739 return -EINVAL; 4740 4741 nla_for_each_nested(attr, br_spec, rem) { 4742 if (nla_type(attr) != IFLA_BRIDGE_MODE) 4743 continue; 4744 4745 if (nla_len(attr) < sizeof(mode)) 4746 return -EINVAL; 4747 4748 mode = nla_get_u16(attr); 4749 if (mode > BRIDGE_MODE_VEPA) 4750 return -EINVAL; 4751 4752 break; 4753 } 4754 4755 if (mode == BRIDGE_MODE_UNDEF) 4756 return -EINVAL; 4757 4758 setting = (mode == BRIDGE_MODE_VEPA) ? 1 : 0; 4759 return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting); 4760 } 4761 #endif 4762 4763 const struct net_device_ops mlx5e_netdev_ops = { 4764 .ndo_open = mlx5e_open, 4765 .ndo_stop = mlx5e_close, 4766 .ndo_start_xmit = mlx5e_xmit, 4767 .ndo_setup_tc = mlx5e_setup_tc, 4768 .ndo_select_queue = mlx5e_select_queue, 4769 .ndo_get_stats64 = mlx5e_get_stats, 4770 .ndo_set_rx_mode = mlx5e_set_rx_mode, 4771 .ndo_set_mac_address = mlx5e_set_mac, 4772 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid, 4773 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid, 4774 .ndo_set_features = mlx5e_set_features, 4775 .ndo_fix_features = mlx5e_fix_features, 4776 .ndo_change_mtu = mlx5e_change_nic_mtu, 4777 .ndo_do_ioctl = mlx5e_ioctl, 4778 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate, 4779 .ndo_features_check = mlx5e_features_check, 4780 .ndo_tx_timeout = mlx5e_tx_timeout, 4781 .ndo_bpf = mlx5e_xdp, 4782 .ndo_xdp_xmit = mlx5e_xdp_xmit, 4783 .ndo_xsk_wakeup = mlx5e_xsk_wakeup, 4784 #ifdef CONFIG_MLX5_EN_ARFS 4785 .ndo_rx_flow_steer = mlx5e_rx_flow_steer, 4786 #endif 4787 #ifdef CONFIG_MLX5_ESWITCH 4788 .ndo_bridge_setlink = mlx5e_bridge_setlink, 4789 .ndo_bridge_getlink = mlx5e_bridge_getlink, 4790 4791 /* SRIOV E-Switch NDOs */ 4792 .ndo_set_vf_mac = mlx5e_set_vf_mac, 4793 .ndo_set_vf_vlan = mlx5e_set_vf_vlan, 4794 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk, 4795 .ndo_set_vf_trust = mlx5e_set_vf_trust, 4796 .ndo_set_vf_rate = mlx5e_set_vf_rate, 4797 .ndo_get_vf_config = mlx5e_get_vf_config, 4798 .ndo_set_vf_link_state = mlx5e_set_vf_link_state, 4799 .ndo_get_vf_stats = mlx5e_get_vf_stats, 4800 #endif 4801 .ndo_get_devlink_port = mlx5e_get_devlink_port, 4802 }; 4803 4804 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len, 4805 int num_channels) 4806 { 4807 int i; 4808 4809 for (i = 0; i < len; i++) 4810 indirection_rqt[i] = i % num_channels; 4811 } 4812 4813 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev) 4814 { 4815 u32 link_speed = 0; 4816 u32 pci_bw = 0; 4817 4818 mlx5e_port_max_linkspeed(mdev, &link_speed); 4819 pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL); 4820 mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n", 4821 link_speed, pci_bw); 4822 4823 #define MLX5E_SLOW_PCI_RATIO (2) 4824 4825 return link_speed && pci_bw && 4826 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw; 4827 } 4828 4829 static struct dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode) 4830 { 4831 struct dim_cq_moder moder; 4832 4833 moder.cq_period_mode = cq_period_mode; 4834 moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS; 4835 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC; 4836 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE) 4837 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE; 4838 4839 return moder; 4840 } 4841 4842 static struct dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode) 4843 { 4844 struct dim_cq_moder moder; 4845 4846 moder.cq_period_mode = cq_period_mode; 4847 moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS; 4848 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC; 4849 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE) 4850 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE; 4851 4852 return moder; 4853 } 4854 4855 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode) 4856 { 4857 return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ? 4858 DIM_CQ_PERIOD_MODE_START_FROM_CQE : 4859 DIM_CQ_PERIOD_MODE_START_FROM_EQE; 4860 } 4861 4862 void mlx5e_reset_tx_moderation(struct mlx5e_params *params, u8 cq_period_mode) 4863 { 4864 if (params->tx_dim_enabled) { 4865 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode); 4866 4867 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode); 4868 } else { 4869 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode); 4870 } 4871 } 4872 4873 void mlx5e_reset_rx_moderation(struct mlx5e_params *params, u8 cq_period_mode) 4874 { 4875 if (params->rx_dim_enabled) { 4876 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode); 4877 4878 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode); 4879 } else { 4880 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode); 4881 } 4882 } 4883 4884 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode) 4885 { 4886 mlx5e_reset_tx_moderation(params, cq_period_mode); 4887 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER, 4888 params->tx_cq_moderation.cq_period_mode == 4889 MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 4890 } 4891 4892 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode) 4893 { 4894 mlx5e_reset_rx_moderation(params, cq_period_mode); 4895 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER, 4896 params->rx_cq_moderation.cq_period_mode == 4897 MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 4898 } 4899 4900 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout) 4901 { 4902 int i; 4903 4904 /* The supported periods are organized in ascending order */ 4905 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++) 4906 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout) 4907 break; 4908 4909 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]); 4910 } 4911 4912 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev, 4913 struct mlx5e_params *params) 4914 { 4915 /* Prefer Striding RQ, unless any of the following holds: 4916 * - Striding RQ configuration is not possible/supported. 4917 * - Slow PCI heuristic. 4918 * - Legacy RQ would use linear SKB while Striding RQ would use non-linear. 4919 * 4920 * No XSK params: checking the availability of striding RQ in general. 4921 */ 4922 if (!slow_pci_heuristic(mdev) && 4923 mlx5e_striding_rq_possible(mdev, params) && 4924 (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) || 4925 !mlx5e_rx_is_linear_skb(params, NULL))) 4926 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true); 4927 mlx5e_set_rq_type(mdev, params); 4928 mlx5e_init_rq_type_params(mdev, params); 4929 } 4930 4931 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params, 4932 u16 num_channels) 4933 { 4934 enum mlx5e_traffic_types tt; 4935 4936 rss_params->hfunc = ETH_RSS_HASH_TOP; 4937 netdev_rss_key_fill(rss_params->toeplitz_hash_key, 4938 sizeof(rss_params->toeplitz_hash_key)); 4939 mlx5e_build_default_indir_rqt(rss_params->indirection_rqt, 4940 MLX5E_INDIR_RQT_SIZE, num_channels); 4941 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) 4942 rss_params->rx_hash_fields[tt] = 4943 tirc_default_config[tt].rx_hash_fields; 4944 } 4945 4946 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu) 4947 { 4948 struct mlx5e_rss_params *rss_params = &priv->rss_params; 4949 struct mlx5e_params *params = &priv->channels.params; 4950 struct mlx5_core_dev *mdev = priv->mdev; 4951 u8 rx_cq_period_mode; 4952 4953 priv->max_nch = mlx5e_calc_max_nch(priv, priv->profile); 4954 4955 params->sw_mtu = mtu; 4956 params->hard_mtu = MLX5E_ETH_HARD_MTU; 4957 params->num_channels = min_t(unsigned int, MLX5E_MAX_NUM_CHANNELS / 2, 4958 priv->max_nch); 4959 params->num_tc = 1; 4960 4961 /* SQ */ 4962 params->log_sq_size = is_kdump_kernel() ? 4963 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE : 4964 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; 4965 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE, 4966 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)); 4967 4968 /* XDP SQ */ 4969 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE, 4970 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)); 4971 4972 /* set CQE compression */ 4973 params->rx_cqe_compress_def = false; 4974 if (MLX5_CAP_GEN(mdev, cqe_compression) && 4975 MLX5_CAP_GEN(mdev, vport_group_manager)) 4976 params->rx_cqe_compress_def = slow_pci_heuristic(mdev); 4977 4978 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def); 4979 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false); 4980 4981 /* RQ */ 4982 mlx5e_build_rq_params(mdev, params); 4983 4984 /* HW LRO */ 4985 if (MLX5_CAP_ETH(mdev, lro_cap) && 4986 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) { 4987 /* No XSK params: checking the availability of striding RQ in general. */ 4988 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL)) 4989 params->lro_en = !slow_pci_heuristic(mdev); 4990 } 4991 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT); 4992 4993 /* CQ moderation params */ 4994 rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 4995 MLX5_CQ_PERIOD_MODE_START_FROM_CQE : 4996 MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 4997 params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation); 4998 params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation); 4999 mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode); 5000 mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); 5001 5002 /* TX inline */ 5003 mlx5_query_min_inline(mdev, ¶ms->tx_min_inline_mode); 5004 5005 /* RSS */ 5006 mlx5e_build_rss_params(rss_params, params->num_channels); 5007 params->tunneled_offload_en = 5008 mlx5e_tunnel_inner_ft_supported(mdev); 5009 5010 /* AF_XDP */ 5011 params->xsk = xsk; 5012 5013 /* Do not update netdev->features directly in here 5014 * on mlx5e_attach_netdev() we will call mlx5e_update_features() 5015 * To update netdev->features please modify mlx5e_fix_features() 5016 */ 5017 } 5018 5019 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev) 5020 { 5021 struct mlx5e_priv *priv = netdev_priv(netdev); 5022 5023 mlx5_query_mac_address(priv->mdev, netdev->dev_addr); 5024 if (is_zero_ether_addr(netdev->dev_addr) && 5025 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) { 5026 eth_hw_addr_random(netdev); 5027 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr); 5028 } 5029 } 5030 5031 static int mlx5e_vxlan_set_port(struct net_device *netdev, unsigned int table, 5032 unsigned int entry, struct udp_tunnel_info *ti) 5033 { 5034 struct mlx5e_priv *priv = netdev_priv(netdev); 5035 5036 return mlx5_vxlan_add_port(priv->mdev->vxlan, ntohs(ti->port)); 5037 } 5038 5039 static int mlx5e_vxlan_unset_port(struct net_device *netdev, unsigned int table, 5040 unsigned int entry, struct udp_tunnel_info *ti) 5041 { 5042 struct mlx5e_priv *priv = netdev_priv(netdev); 5043 5044 return mlx5_vxlan_del_port(priv->mdev->vxlan, ntohs(ti->port)); 5045 } 5046 5047 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv) 5048 { 5049 if (!mlx5_vxlan_allowed(priv->mdev->vxlan)) 5050 return; 5051 5052 priv->nic_info.set_port = mlx5e_vxlan_set_port; 5053 priv->nic_info.unset_port = mlx5e_vxlan_unset_port; 5054 priv->nic_info.flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP | 5055 UDP_TUNNEL_NIC_INFO_STATIC_IANA_VXLAN; 5056 priv->nic_info.tables[0].tunnel_types = UDP_TUNNEL_TYPE_VXLAN; 5057 /* Don't count the space hard-coded to the IANA port */ 5058 priv->nic_info.tables[0].n_entries = 5059 mlx5_vxlan_max_udp_ports(priv->mdev) - 1; 5060 5061 priv->netdev->udp_tunnel_nic_info = &priv->nic_info; 5062 } 5063 5064 static bool mlx5e_tunnel_any_tx_proto_supported(struct mlx5_core_dev *mdev) 5065 { 5066 int tt; 5067 5068 for (tt = 0; tt < MLX5E_NUM_TUNNEL_TT; tt++) { 5069 if (mlx5e_tunnel_proto_supported_tx(mdev, mlx5e_get_proto_by_tunnel_type(tt))) 5070 return true; 5071 } 5072 return (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)); 5073 } 5074 5075 static void mlx5e_build_nic_netdev(struct net_device *netdev) 5076 { 5077 struct mlx5e_priv *priv = netdev_priv(netdev); 5078 struct mlx5_core_dev *mdev = priv->mdev; 5079 bool fcs_supported; 5080 bool fcs_enabled; 5081 5082 SET_NETDEV_DEV(netdev, mdev->device); 5083 5084 netdev->netdev_ops = &mlx5e_netdev_ops; 5085 5086 mlx5e_dcbnl_build_netdev(netdev); 5087 5088 netdev->watchdog_timeo = 15 * HZ; 5089 5090 netdev->ethtool_ops = &mlx5e_ethtool_ops; 5091 5092 netdev->vlan_features |= NETIF_F_SG; 5093 netdev->vlan_features |= NETIF_F_HW_CSUM; 5094 netdev->vlan_features |= NETIF_F_GRO; 5095 netdev->vlan_features |= NETIF_F_TSO; 5096 netdev->vlan_features |= NETIF_F_TSO6; 5097 netdev->vlan_features |= NETIF_F_RXCSUM; 5098 netdev->vlan_features |= NETIF_F_RXHASH; 5099 5100 netdev->mpls_features |= NETIF_F_SG; 5101 netdev->mpls_features |= NETIF_F_HW_CSUM; 5102 netdev->mpls_features |= NETIF_F_TSO; 5103 netdev->mpls_features |= NETIF_F_TSO6; 5104 5105 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_TX; 5106 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_RX; 5107 5108 if (!!MLX5_CAP_ETH(mdev, lro_cap) && 5109 mlx5e_check_fragmented_striding_rq_cap(mdev)) 5110 netdev->vlan_features |= NETIF_F_LRO; 5111 5112 netdev->hw_features = netdev->vlan_features; 5113 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; 5114 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; 5115 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 5116 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX; 5117 5118 if (mlx5e_tunnel_any_tx_proto_supported(mdev)) { 5119 netdev->hw_enc_features |= NETIF_F_HW_CSUM; 5120 netdev->hw_enc_features |= NETIF_F_TSO; 5121 netdev->hw_enc_features |= NETIF_F_TSO6; 5122 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL; 5123 } 5124 5125 if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) { 5126 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL | 5127 NETIF_F_GSO_UDP_TUNNEL_CSUM; 5128 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL | 5129 NETIF_F_GSO_UDP_TUNNEL_CSUM; 5130 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM; 5131 netdev->vlan_features |= NETIF_F_GSO_UDP_TUNNEL | 5132 NETIF_F_GSO_UDP_TUNNEL_CSUM; 5133 } 5134 5135 if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_GRE)) { 5136 netdev->hw_features |= NETIF_F_GSO_GRE | 5137 NETIF_F_GSO_GRE_CSUM; 5138 netdev->hw_enc_features |= NETIF_F_GSO_GRE | 5139 NETIF_F_GSO_GRE_CSUM; 5140 netdev->gso_partial_features |= NETIF_F_GSO_GRE | 5141 NETIF_F_GSO_GRE_CSUM; 5142 } 5143 5144 if (mlx5e_tunnel_proto_supported_tx(mdev, IPPROTO_IPIP)) { 5145 netdev->hw_features |= NETIF_F_GSO_IPXIP4 | 5146 NETIF_F_GSO_IPXIP6; 5147 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4 | 5148 NETIF_F_GSO_IPXIP6; 5149 netdev->gso_partial_features |= NETIF_F_GSO_IPXIP4 | 5150 NETIF_F_GSO_IPXIP6; 5151 } 5152 5153 netdev->hw_features |= NETIF_F_GSO_PARTIAL; 5154 netdev->gso_partial_features |= NETIF_F_GSO_UDP_L4; 5155 netdev->hw_features |= NETIF_F_GSO_UDP_L4; 5156 netdev->features |= NETIF_F_GSO_UDP_L4; 5157 5158 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled); 5159 5160 if (fcs_supported) 5161 netdev->hw_features |= NETIF_F_RXALL; 5162 5163 if (MLX5_CAP_ETH(mdev, scatter_fcs)) 5164 netdev->hw_features |= NETIF_F_RXFCS; 5165 5166 netdev->features = netdev->hw_features; 5167 5168 /* Defaults */ 5169 if (fcs_enabled) 5170 netdev->features &= ~NETIF_F_RXALL; 5171 netdev->features &= ~NETIF_F_LRO; 5172 netdev->features &= ~NETIF_F_RXFCS; 5173 5174 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f) 5175 if (FT_CAP(flow_modify_en) && 5176 FT_CAP(modify_root) && 5177 FT_CAP(identified_miss_table_mode) && 5178 FT_CAP(flow_table_modify)) { 5179 #if IS_ENABLED(CONFIG_MLX5_CLS_ACT) 5180 netdev->hw_features |= NETIF_F_HW_TC; 5181 #endif 5182 #ifdef CONFIG_MLX5_EN_ARFS 5183 netdev->hw_features |= NETIF_F_NTUPLE; 5184 #endif 5185 } 5186 if (mlx5_qos_is_supported(mdev)) 5187 netdev->features |= NETIF_F_HW_TC; 5188 5189 netdev->features |= NETIF_F_HIGHDMA; 5190 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER; 5191 5192 netdev->priv_flags |= IFF_UNICAST_FLT; 5193 5194 mlx5e_set_netdev_dev_addr(netdev); 5195 mlx5e_ipsec_build_netdev(priv); 5196 mlx5e_tls_build_netdev(priv); 5197 } 5198 5199 void mlx5e_create_q_counters(struct mlx5e_priv *priv) 5200 { 5201 u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {}; 5202 u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {}; 5203 struct mlx5_core_dev *mdev = priv->mdev; 5204 int err; 5205 5206 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 5207 err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out); 5208 if (!err) 5209 priv->q_counter = 5210 MLX5_GET(alloc_q_counter_out, out, counter_set_id); 5211 5212 err = mlx5_cmd_exec_inout(mdev, alloc_q_counter, in, out); 5213 if (!err) 5214 priv->drop_rq_q_counter = 5215 MLX5_GET(alloc_q_counter_out, out, counter_set_id); 5216 } 5217 5218 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv) 5219 { 5220 u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {}; 5221 5222 MLX5_SET(dealloc_q_counter_in, in, opcode, 5223 MLX5_CMD_OP_DEALLOC_Q_COUNTER); 5224 if (priv->q_counter) { 5225 MLX5_SET(dealloc_q_counter_in, in, counter_set_id, 5226 priv->q_counter); 5227 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in); 5228 } 5229 5230 if (priv->drop_rq_q_counter) { 5231 MLX5_SET(dealloc_q_counter_in, in, counter_set_id, 5232 priv->drop_rq_q_counter); 5233 mlx5_cmd_exec_in(priv->mdev, dealloc_q_counter, in); 5234 } 5235 } 5236 5237 static int mlx5e_nic_init(struct mlx5_core_dev *mdev, 5238 struct net_device *netdev) 5239 { 5240 struct mlx5e_priv *priv = netdev_priv(netdev); 5241 int err; 5242 5243 mlx5e_build_nic_params(priv, &priv->xsk, netdev->mtu); 5244 mlx5e_vxlan_set_netdev_info(priv); 5245 5246 mlx5e_timestamp_init(priv); 5247 5248 err = mlx5e_ipsec_init(priv); 5249 if (err) 5250 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err); 5251 5252 err = mlx5e_tls_init(priv); 5253 if (err) 5254 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err); 5255 5256 err = mlx5e_devlink_port_register(priv); 5257 if (err) 5258 mlx5_core_err(mdev, "mlx5e_devlink_port_register failed, %d\n", err); 5259 5260 mlx5e_health_create_reporters(priv); 5261 5262 return 0; 5263 } 5264 5265 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv) 5266 { 5267 mlx5e_health_destroy_reporters(priv); 5268 mlx5e_devlink_port_unregister(priv); 5269 mlx5e_tls_cleanup(priv); 5270 mlx5e_ipsec_cleanup(priv); 5271 } 5272 5273 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv) 5274 { 5275 struct mlx5_core_dev *mdev = priv->mdev; 5276 int err; 5277 5278 mlx5e_create_q_counters(priv); 5279 5280 err = mlx5e_open_drop_rq(priv, &priv->drop_rq); 5281 if (err) { 5282 mlx5_core_err(mdev, "open drop rq failed, %d\n", err); 5283 goto err_destroy_q_counters; 5284 } 5285 5286 err = mlx5e_create_indirect_rqt(priv); 5287 if (err) 5288 goto err_close_drop_rq; 5289 5290 err = mlx5e_create_direct_rqts(priv, priv->direct_tir); 5291 if (err) 5292 goto err_destroy_indirect_rqts; 5293 5294 err = mlx5e_create_indirect_tirs(priv, true); 5295 if (err) 5296 goto err_destroy_direct_rqts; 5297 5298 err = mlx5e_create_direct_tirs(priv, priv->direct_tir); 5299 if (err) 5300 goto err_destroy_indirect_tirs; 5301 5302 err = mlx5e_create_direct_rqts(priv, priv->xsk_tir); 5303 if (unlikely(err)) 5304 goto err_destroy_direct_tirs; 5305 5306 err = mlx5e_create_direct_tirs(priv, priv->xsk_tir); 5307 if (unlikely(err)) 5308 goto err_destroy_xsk_rqts; 5309 5310 err = mlx5e_create_flow_steering(priv); 5311 if (err) { 5312 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err); 5313 goto err_destroy_xsk_tirs; 5314 } 5315 5316 err = mlx5e_tc_nic_init(priv); 5317 if (err) 5318 goto err_destroy_flow_steering; 5319 5320 err = mlx5e_accel_init_rx(priv); 5321 if (err) 5322 goto err_tc_nic_cleanup; 5323 5324 #ifdef CONFIG_MLX5_EN_ARFS 5325 priv->netdev->rx_cpu_rmap = mlx5_eq_table_get_rmap(priv->mdev); 5326 #endif 5327 5328 return 0; 5329 5330 err_tc_nic_cleanup: 5331 mlx5e_tc_nic_cleanup(priv); 5332 err_destroy_flow_steering: 5333 mlx5e_destroy_flow_steering(priv); 5334 err_destroy_xsk_tirs: 5335 mlx5e_destroy_direct_tirs(priv, priv->xsk_tir); 5336 err_destroy_xsk_rqts: 5337 mlx5e_destroy_direct_rqts(priv, priv->xsk_tir); 5338 err_destroy_direct_tirs: 5339 mlx5e_destroy_direct_tirs(priv, priv->direct_tir); 5340 err_destroy_indirect_tirs: 5341 mlx5e_destroy_indirect_tirs(priv); 5342 err_destroy_direct_rqts: 5343 mlx5e_destroy_direct_rqts(priv, priv->direct_tir); 5344 err_destroy_indirect_rqts: 5345 mlx5e_destroy_rqt(priv, &priv->indir_rqt); 5346 err_close_drop_rq: 5347 mlx5e_close_drop_rq(&priv->drop_rq); 5348 err_destroy_q_counters: 5349 mlx5e_destroy_q_counters(priv); 5350 return err; 5351 } 5352 5353 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv) 5354 { 5355 mlx5e_accel_cleanup_rx(priv); 5356 mlx5e_tc_nic_cleanup(priv); 5357 mlx5e_destroy_flow_steering(priv); 5358 mlx5e_destroy_direct_tirs(priv, priv->xsk_tir); 5359 mlx5e_destroy_direct_rqts(priv, priv->xsk_tir); 5360 mlx5e_destroy_direct_tirs(priv, priv->direct_tir); 5361 mlx5e_destroy_indirect_tirs(priv); 5362 mlx5e_destroy_direct_rqts(priv, priv->direct_tir); 5363 mlx5e_destroy_rqt(priv, &priv->indir_rqt); 5364 mlx5e_close_drop_rq(&priv->drop_rq); 5365 mlx5e_destroy_q_counters(priv); 5366 } 5367 5368 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv) 5369 { 5370 int err; 5371 5372 err = mlx5e_create_tises(priv); 5373 if (err) { 5374 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err); 5375 return err; 5376 } 5377 5378 mlx5e_dcbnl_initialize(priv); 5379 return 0; 5380 } 5381 5382 static void mlx5e_nic_enable(struct mlx5e_priv *priv) 5383 { 5384 struct net_device *netdev = priv->netdev; 5385 struct mlx5_core_dev *mdev = priv->mdev; 5386 5387 mlx5e_init_l2_addr(priv); 5388 5389 /* Marking the link as currently not needed by the Driver */ 5390 if (!netif_running(netdev)) 5391 mlx5e_modify_admin_state(mdev, MLX5_PORT_DOWN); 5392 5393 mlx5e_set_netdev_mtu_boundaries(priv); 5394 mlx5e_set_dev_port_mtu(priv); 5395 5396 mlx5_lag_add(mdev, netdev); 5397 5398 mlx5e_enable_async_events(priv); 5399 mlx5e_enable_blocking_events(priv); 5400 if (mlx5e_monitor_counter_supported(priv)) 5401 mlx5e_monitor_counter_init(priv); 5402 5403 mlx5e_hv_vhca_stats_create(priv); 5404 if (netdev->reg_state != NETREG_REGISTERED) 5405 return; 5406 mlx5e_dcbnl_init_app(priv); 5407 5408 queue_work(priv->wq, &priv->set_rx_mode_work); 5409 5410 rtnl_lock(); 5411 if (netif_running(netdev)) 5412 mlx5e_open(netdev); 5413 udp_tunnel_nic_reset_ntf(priv->netdev); 5414 netif_device_attach(netdev); 5415 rtnl_unlock(); 5416 } 5417 5418 static void mlx5e_nic_disable(struct mlx5e_priv *priv) 5419 { 5420 struct mlx5_core_dev *mdev = priv->mdev; 5421 5422 if (priv->netdev->reg_state == NETREG_REGISTERED) 5423 mlx5e_dcbnl_delete_app(priv); 5424 5425 rtnl_lock(); 5426 if (netif_running(priv->netdev)) 5427 mlx5e_close(priv->netdev); 5428 netif_device_detach(priv->netdev); 5429 rtnl_unlock(); 5430 5431 queue_work(priv->wq, &priv->set_rx_mode_work); 5432 5433 mlx5e_hv_vhca_stats_destroy(priv); 5434 if (mlx5e_monitor_counter_supported(priv)) 5435 mlx5e_monitor_counter_cleanup(priv); 5436 5437 mlx5e_disable_blocking_events(priv); 5438 if (priv->en_trap) { 5439 mlx5e_deactivate_trap(priv); 5440 mlx5e_close_trap(priv->en_trap); 5441 priv->en_trap = NULL; 5442 } 5443 mlx5e_disable_async_events(priv); 5444 mlx5_lag_remove(mdev); 5445 mlx5_vxlan_reset_to_default(mdev->vxlan); 5446 } 5447 5448 int mlx5e_update_nic_rx(struct mlx5e_priv *priv) 5449 { 5450 return mlx5e_refresh_tirs(priv, false, false); 5451 } 5452 5453 static const struct mlx5e_profile mlx5e_nic_profile = { 5454 .init = mlx5e_nic_init, 5455 .cleanup = mlx5e_nic_cleanup, 5456 .init_rx = mlx5e_init_nic_rx, 5457 .cleanup_rx = mlx5e_cleanup_nic_rx, 5458 .init_tx = mlx5e_init_nic_tx, 5459 .cleanup_tx = mlx5e_cleanup_nic_tx, 5460 .enable = mlx5e_nic_enable, 5461 .disable = mlx5e_nic_disable, 5462 .update_rx = mlx5e_update_nic_rx, 5463 .update_stats = mlx5e_stats_update_ndo_stats, 5464 .update_carrier = mlx5e_update_carrier, 5465 .rx_handlers = &mlx5e_rx_handlers_nic, 5466 .max_tc = MLX5E_MAX_NUM_TC, 5467 .rq_groups = MLX5E_NUM_RQ_GROUPS(XSK), 5468 .stats_grps = mlx5e_nic_stats_grps, 5469 .stats_grps_num = mlx5e_nic_stats_grps_num, 5470 }; 5471 5472 /* mlx5e generic netdev management API (move to en_common.c) */ 5473 int mlx5e_priv_init(struct mlx5e_priv *priv, 5474 struct net_device *netdev, 5475 struct mlx5_core_dev *mdev) 5476 { 5477 memset(priv, 0, sizeof(*priv)); 5478 5479 /* priv init */ 5480 priv->mdev = mdev; 5481 priv->netdev = netdev; 5482 priv->msglevel = MLX5E_MSG_LEVEL; 5483 priv->max_opened_tc = 1; 5484 5485 if (!alloc_cpumask_var(&priv->scratchpad.cpumask, GFP_KERNEL)) 5486 return -ENOMEM; 5487 5488 mutex_init(&priv->state_lock); 5489 hash_init(priv->htb.qos_tc2node); 5490 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work); 5491 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work); 5492 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work); 5493 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work); 5494 5495 priv->wq = create_singlethread_workqueue("mlx5e"); 5496 if (!priv->wq) 5497 goto err_free_cpumask; 5498 5499 return 0; 5500 5501 err_free_cpumask: 5502 free_cpumask_var(priv->scratchpad.cpumask); 5503 5504 return -ENOMEM; 5505 } 5506 5507 void mlx5e_priv_cleanup(struct mlx5e_priv *priv) 5508 { 5509 int i; 5510 5511 destroy_workqueue(priv->wq); 5512 free_cpumask_var(priv->scratchpad.cpumask); 5513 5514 for (i = 0; i < priv->htb.max_qos_sqs; i++) 5515 kfree(priv->htb.qos_sq_stats[i]); 5516 kvfree(priv->htb.qos_sq_stats); 5517 } 5518 5519 struct net_device * 5520 mlx5e_create_netdev(struct mlx5_core_dev *mdev, unsigned int txqs, unsigned int rxqs) 5521 { 5522 struct net_device *netdev; 5523 int err; 5524 5525 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), txqs, rxqs); 5526 if (!netdev) { 5527 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n"); 5528 return NULL; 5529 } 5530 5531 err = mlx5e_priv_init(netdev_priv(netdev), netdev, mdev); 5532 if (err) { 5533 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err); 5534 goto err_free_netdev; 5535 } 5536 5537 netif_carrier_off(netdev); 5538 dev_net_set(netdev, mlx5_core_net(mdev)); 5539 5540 return netdev; 5541 5542 err_free_netdev: 5543 free_netdev(netdev); 5544 5545 return NULL; 5546 } 5547 5548 static void mlx5e_update_features(struct net_device *netdev) 5549 { 5550 if (netdev->reg_state != NETREG_REGISTERED) 5551 return; /* features will be updated on netdev registration */ 5552 5553 rtnl_lock(); 5554 netdev_update_features(netdev); 5555 rtnl_unlock(); 5556 } 5557 5558 int mlx5e_attach_netdev(struct mlx5e_priv *priv) 5559 { 5560 const bool take_rtnl = priv->netdev->reg_state == NETREG_REGISTERED; 5561 const struct mlx5e_profile *profile = priv->profile; 5562 int max_nch; 5563 int err; 5564 5565 clear_bit(MLX5E_STATE_DESTROYING, &priv->state); 5566 5567 /* max number of channels may have changed */ 5568 max_nch = mlx5e_get_max_num_channels(priv->mdev); 5569 if (priv->channels.params.num_channels > max_nch) { 5570 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch); 5571 /* Reducing the number of channels - RXFH has to be reset, and 5572 * mlx5e_num_channels_changed below will build the RQT. 5573 */ 5574 priv->netdev->priv_flags &= ~IFF_RXFH_CONFIGURED; 5575 priv->channels.params.num_channels = max_nch; 5576 } 5577 /* 1. Set the real number of queues in the kernel the first time. 5578 * 2. Set our default XPS cpumask. 5579 * 3. Build the RQT. 5580 * 5581 * rtnl_lock is required by netif_set_real_num_*_queues in case the 5582 * netdev has been registered by this point (if this function was called 5583 * in the reload or resume flow). 5584 */ 5585 if (take_rtnl) 5586 rtnl_lock(); 5587 err = mlx5e_num_channels_changed(priv); 5588 if (take_rtnl) 5589 rtnl_unlock(); 5590 if (err) 5591 goto out; 5592 5593 err = profile->init_tx(priv); 5594 if (err) 5595 goto out; 5596 5597 err = profile->init_rx(priv); 5598 if (err) 5599 goto err_cleanup_tx; 5600 5601 if (profile->enable) 5602 profile->enable(priv); 5603 5604 mlx5e_update_features(priv->netdev); 5605 5606 return 0; 5607 5608 err_cleanup_tx: 5609 profile->cleanup_tx(priv); 5610 5611 out: 5612 set_bit(MLX5E_STATE_DESTROYING, &priv->state); 5613 cancel_work_sync(&priv->update_stats_work); 5614 return err; 5615 } 5616 5617 void mlx5e_detach_netdev(struct mlx5e_priv *priv) 5618 { 5619 const struct mlx5e_profile *profile = priv->profile; 5620 5621 set_bit(MLX5E_STATE_DESTROYING, &priv->state); 5622 5623 if (profile->disable) 5624 profile->disable(priv); 5625 flush_workqueue(priv->wq); 5626 5627 profile->cleanup_rx(priv); 5628 profile->cleanup_tx(priv); 5629 cancel_work_sync(&priv->update_stats_work); 5630 } 5631 5632 static int 5633 mlx5e_netdev_attach_profile(struct mlx5e_priv *priv, 5634 const struct mlx5e_profile *new_profile, void *new_ppriv) 5635 { 5636 struct net_device *netdev = priv->netdev; 5637 struct mlx5_core_dev *mdev = priv->mdev; 5638 int err; 5639 5640 err = mlx5e_priv_init(priv, netdev, mdev); 5641 if (err) { 5642 mlx5_core_err(mdev, "mlx5e_priv_init failed, err=%d\n", err); 5643 return err; 5644 } 5645 netif_carrier_off(netdev); 5646 priv->profile = new_profile; 5647 priv->ppriv = new_ppriv; 5648 err = new_profile->init(priv->mdev, priv->netdev); 5649 if (err) 5650 return err; 5651 err = mlx5e_attach_netdev(priv); 5652 if (err) 5653 new_profile->cleanup(priv); 5654 return err; 5655 } 5656 5657 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv, 5658 const struct mlx5e_profile *new_profile, void *new_ppriv) 5659 { 5660 unsigned int new_max_nch = mlx5e_calc_max_nch(priv, new_profile); 5661 const struct mlx5e_profile *orig_profile = priv->profile; 5662 void *orig_ppriv = priv->ppriv; 5663 int err, rollback_err; 5664 5665 /* sanity */ 5666 if (new_max_nch != priv->max_nch) { 5667 netdev_warn(priv->netdev, 5668 "%s: Replacing profile with different max channels\n", 5669 __func__); 5670 return -EINVAL; 5671 } 5672 5673 /* cleanup old profile */ 5674 mlx5e_detach_netdev(priv); 5675 priv->profile->cleanup(priv); 5676 mlx5e_priv_cleanup(priv); 5677 5678 err = mlx5e_netdev_attach_profile(priv, new_profile, new_ppriv); 5679 if (err) { /* roll back to original profile */ 5680 netdev_warn(priv->netdev, "%s: new profile init failed, %d\n", 5681 __func__, err); 5682 goto rollback; 5683 } 5684 5685 return 0; 5686 5687 rollback: 5688 rollback_err = mlx5e_netdev_attach_profile(priv, orig_profile, orig_ppriv); 5689 if (rollback_err) { 5690 netdev_err(priv->netdev, 5691 "%s: failed to rollback to orig profile, %d\n", 5692 __func__, rollback_err); 5693 } 5694 return err; 5695 } 5696 5697 void mlx5e_destroy_netdev(struct mlx5e_priv *priv) 5698 { 5699 struct net_device *netdev = priv->netdev; 5700 5701 mlx5e_priv_cleanup(priv); 5702 free_netdev(netdev); 5703 } 5704 5705 static int mlx5e_resume(struct auxiliary_device *adev) 5706 { 5707 struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev); 5708 struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev); 5709 struct net_device *netdev = priv->netdev; 5710 struct mlx5_core_dev *mdev = edev->mdev; 5711 int err; 5712 5713 if (netif_device_present(netdev)) 5714 return 0; 5715 5716 err = mlx5e_create_mdev_resources(mdev); 5717 if (err) 5718 return err; 5719 5720 err = mlx5e_attach_netdev(priv); 5721 if (err) { 5722 mlx5e_destroy_mdev_resources(mdev); 5723 return err; 5724 } 5725 5726 return 0; 5727 } 5728 5729 static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state) 5730 { 5731 struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev); 5732 struct net_device *netdev = priv->netdev; 5733 struct mlx5_core_dev *mdev = priv->mdev; 5734 5735 if (!netif_device_present(netdev)) 5736 return -ENODEV; 5737 5738 mlx5e_detach_netdev(priv); 5739 mlx5e_destroy_mdev_resources(mdev); 5740 return 0; 5741 } 5742 5743 static int mlx5e_probe(struct auxiliary_device *adev, 5744 const struct auxiliary_device_id *id) 5745 { 5746 struct mlx5_adev *edev = container_of(adev, struct mlx5_adev, adev); 5747 const struct mlx5e_profile *profile = &mlx5e_nic_profile; 5748 struct mlx5_core_dev *mdev = edev->mdev; 5749 struct net_device *netdev; 5750 pm_message_t state = {}; 5751 unsigned int txqs, rxqs, ptp_txqs = 0; 5752 struct mlx5e_priv *priv; 5753 int qos_sqs = 0; 5754 int err; 5755 int nch; 5756 5757 if (MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn)) 5758 ptp_txqs = profile->max_tc; 5759 5760 if (mlx5_qos_is_supported(mdev)) 5761 qos_sqs = mlx5e_qos_max_leaf_nodes(mdev); 5762 5763 nch = mlx5e_get_max_num_channels(mdev); 5764 txqs = nch * profile->max_tc + ptp_txqs + qos_sqs; 5765 rxqs = nch * profile->rq_groups; 5766 netdev = mlx5e_create_netdev(mdev, txqs, rxqs); 5767 if (!netdev) { 5768 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n"); 5769 return -ENOMEM; 5770 } 5771 5772 mlx5e_build_nic_netdev(netdev); 5773 5774 priv = netdev_priv(netdev); 5775 dev_set_drvdata(&adev->dev, priv); 5776 5777 priv->profile = profile; 5778 priv->ppriv = NULL; 5779 err = profile->init(mdev, netdev); 5780 if (err) { 5781 mlx5_core_err(mdev, "mlx5e_nic_profile init failed, %d\n", err); 5782 goto err_destroy_netdev; 5783 } 5784 5785 err = mlx5e_resume(adev); 5786 if (err) { 5787 mlx5_core_err(mdev, "mlx5e_resume failed, %d\n", err); 5788 goto err_profile_cleanup; 5789 } 5790 5791 err = register_netdev(netdev); 5792 if (err) { 5793 mlx5_core_err(mdev, "register_netdev failed, %d\n", err); 5794 goto err_resume; 5795 } 5796 5797 mlx5e_devlink_port_type_eth_set(priv); 5798 5799 mlx5e_dcbnl_init_app(priv); 5800 return 0; 5801 5802 err_resume: 5803 mlx5e_suspend(adev, state); 5804 err_profile_cleanup: 5805 profile->cleanup(priv); 5806 err_destroy_netdev: 5807 mlx5e_destroy_netdev(priv); 5808 return err; 5809 } 5810 5811 static void mlx5e_remove(struct auxiliary_device *adev) 5812 { 5813 struct mlx5e_priv *priv = dev_get_drvdata(&adev->dev); 5814 pm_message_t state = {}; 5815 5816 mlx5e_dcbnl_delete_app(priv); 5817 unregister_netdev(priv->netdev); 5818 mlx5e_suspend(adev, state); 5819 priv->profile->cleanup(priv); 5820 mlx5e_destroy_netdev(priv); 5821 } 5822 5823 static const struct auxiliary_device_id mlx5e_id_table[] = { 5824 { .name = MLX5_ADEV_NAME ".eth", }, 5825 {}, 5826 }; 5827 5828 MODULE_DEVICE_TABLE(auxiliary, mlx5e_id_table); 5829 5830 static struct auxiliary_driver mlx5e_driver = { 5831 .name = "eth", 5832 .probe = mlx5e_probe, 5833 .remove = mlx5e_remove, 5834 .suspend = mlx5e_suspend, 5835 .resume = mlx5e_resume, 5836 .id_table = mlx5e_id_table, 5837 }; 5838 5839 int mlx5e_init(void) 5840 { 5841 int ret; 5842 5843 mlx5e_ipsec_build_inverse_table(); 5844 mlx5e_build_ptys2ethtool_map(); 5845 ret = mlx5e_rep_init(); 5846 if (ret) 5847 return ret; 5848 5849 ret = auxiliary_driver_register(&mlx5e_driver); 5850 if (ret) 5851 mlx5e_rep_cleanup(); 5852 return ret; 5853 } 5854 5855 void mlx5e_cleanup(void) 5856 { 5857 auxiliary_driver_unregister(&mlx5e_driver); 5858 mlx5e_rep_cleanup(); 5859 } 5860