1 /* 2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include "en.h" 34 #include "en/port.h" 35 #include "en/params.h" 36 #include "en/xsk/pool.h" 37 #include "lib/clock.h" 38 39 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv, 40 struct ethtool_drvinfo *drvinfo) 41 { 42 struct mlx5_core_dev *mdev = priv->mdev; 43 44 strlcpy(drvinfo->driver, KBUILD_MODNAME, sizeof(drvinfo->driver)); 45 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), 46 "%d.%d.%04d (%.16s)", 47 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev), 48 mdev->board_id); 49 strlcpy(drvinfo->bus_info, dev_name(mdev->device), 50 sizeof(drvinfo->bus_info)); 51 } 52 53 static void mlx5e_get_drvinfo(struct net_device *dev, 54 struct ethtool_drvinfo *drvinfo) 55 { 56 struct mlx5e_priv *priv = netdev_priv(dev); 57 58 mlx5e_ethtool_get_drvinfo(priv, drvinfo); 59 } 60 61 struct ptys2ethtool_config { 62 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); 63 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised); 64 }; 65 66 static 67 struct ptys2ethtool_config ptys2legacy_ethtool_table[MLX5E_LINK_MODES_NUMBER]; 68 static 69 struct ptys2ethtool_config ptys2ext_ethtool_table[MLX5E_EXT_LINK_MODES_NUMBER]; 70 71 #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, table, ...) \ 72 ({ \ 73 struct ptys2ethtool_config *cfg; \ 74 const unsigned int modes[] = { __VA_ARGS__ }; \ 75 unsigned int i, bit, idx; \ 76 cfg = &ptys2##table##_ethtool_table[reg_]; \ 77 bitmap_zero(cfg->supported, \ 78 __ETHTOOL_LINK_MODE_MASK_NBITS); \ 79 bitmap_zero(cfg->advertised, \ 80 __ETHTOOL_LINK_MODE_MASK_NBITS); \ 81 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \ 82 bit = modes[i] % 64; \ 83 idx = modes[i] / 64; \ 84 __set_bit(bit, &cfg->supported[idx]); \ 85 __set_bit(bit, &cfg->advertised[idx]); \ 86 } \ 87 }) 88 89 void mlx5e_build_ptys2ethtool_map(void) 90 { 91 memset(ptys2legacy_ethtool_table, 0, sizeof(ptys2legacy_ethtool_table)); 92 memset(ptys2ext_ethtool_table, 0, sizeof(ptys2ext_ethtool_table)); 93 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, legacy, 94 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT); 95 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, legacy, 96 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT); 97 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, legacy, 98 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT); 99 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, legacy, 100 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT); 101 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, legacy, 102 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); 103 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, legacy, 104 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT); 105 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, legacy, 106 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT); 107 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, legacy, 108 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT); 109 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, legacy, 110 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT); 111 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, legacy, 112 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); 113 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, legacy, 114 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); 115 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, legacy, 116 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); 117 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, legacy, 118 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT); 119 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, legacy, 120 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT); 121 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, legacy, 122 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT); 123 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, legacy, 124 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT); 125 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, legacy, 126 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT); 127 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, legacy, 128 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT); 129 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, legacy, 130 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT); 131 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, legacy, 132 ETHTOOL_LINK_MODE_10000baseT_Full_BIT); 133 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, legacy, 134 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT); 135 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, legacy, 136 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT); 137 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, legacy, 138 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT); 139 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, legacy, 140 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT); 141 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, legacy, 142 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT); 143 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_SGMII_100M, ext, 144 ETHTOOL_LINK_MODE_100baseT_Full_BIT); 145 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_X_SGMII, ext, 146 ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 147 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 148 ETHTOOL_LINK_MODE_1000baseX_Full_BIT); 149 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_5GBASE_R, ext, 150 ETHTOOL_LINK_MODE_5000baseT_Full_BIT); 151 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_XFI_XAUI_1, ext, 152 ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 153 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 154 ETHTOOL_LINK_MODE_10000baseR_FEC_BIT, 155 ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, 156 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 157 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 158 ETHTOOL_LINK_MODE_10000baseER_Full_BIT); 159 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_XLAUI_4_XLPPI_4, ext, 160 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 161 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 162 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 163 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT); 164 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GAUI_1_25GBASE_CR_KR, ext, 165 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 166 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 167 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT); 168 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2, 169 ext, 170 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 171 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 172 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT); 173 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR, ext, 174 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, 175 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, 176 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, 177 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 178 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT); 179 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_CAUI_4_100GBASE_CR4_KR4, ext, 180 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 181 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 182 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 183 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT); 184 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_2_100GBASE_CR2_KR2, ext, 185 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, 186 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, 187 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, 188 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, 189 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT); 190 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_4_200GBASE_CR4_KR4, ext, 191 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT, 192 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT, 193 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT, 194 ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT, 195 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT); 196 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_1_100GBASE_CR_KR, ext, 197 ETHTOOL_LINK_MODE_100000baseKR_Full_BIT, 198 ETHTOOL_LINK_MODE_100000baseSR_Full_BIT, 199 ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT, 200 ETHTOOL_LINK_MODE_100000baseDR_Full_BIT, 201 ETHTOOL_LINK_MODE_100000baseCR_Full_BIT); 202 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_2_200GBASE_CR2_KR2, ext, 203 ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT, 204 ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT, 205 ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT, 206 ETHTOOL_LINK_MODE_200000baseDR2_Full_BIT, 207 ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT); 208 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_4_400GBASE_CR4_KR4, ext, 209 ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT, 210 ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT, 211 ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT, 212 ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT, 213 ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT); 214 } 215 216 static void mlx5e_ethtool_get_speed_arr(struct mlx5_core_dev *mdev, 217 struct ptys2ethtool_config **arr, 218 u32 *size) 219 { 220 bool ext = mlx5e_ptys_ext_supported(mdev); 221 222 *arr = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table; 223 *size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) : 224 ARRAY_SIZE(ptys2legacy_ethtool_table); 225 } 226 227 typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable); 228 229 struct pflag_desc { 230 char name[ETH_GSTRING_LEN]; 231 mlx5e_pflag_handler handler; 232 }; 233 234 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS]; 235 236 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset) 237 { 238 switch (sset) { 239 case ETH_SS_STATS: 240 return mlx5e_stats_total_num(priv); 241 case ETH_SS_PRIV_FLAGS: 242 return MLX5E_NUM_PFLAGS; 243 case ETH_SS_TEST: 244 return mlx5e_self_test_num(priv); 245 default: 246 return -EOPNOTSUPP; 247 } 248 } 249 250 static int mlx5e_get_sset_count(struct net_device *dev, int sset) 251 { 252 struct mlx5e_priv *priv = netdev_priv(dev); 253 254 return mlx5e_ethtool_get_sset_count(priv, sset); 255 } 256 257 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, u32 stringset, u8 *data) 258 { 259 int i; 260 261 switch (stringset) { 262 case ETH_SS_PRIV_FLAGS: 263 for (i = 0; i < MLX5E_NUM_PFLAGS; i++) 264 strcpy(data + i * ETH_GSTRING_LEN, 265 mlx5e_priv_flags[i].name); 266 break; 267 268 case ETH_SS_TEST: 269 for (i = 0; i < mlx5e_self_test_num(priv); i++) 270 strcpy(data + i * ETH_GSTRING_LEN, 271 mlx5e_self_tests[i]); 272 break; 273 274 case ETH_SS_STATS: 275 mlx5e_stats_fill_strings(priv, data); 276 break; 277 } 278 } 279 280 static void mlx5e_get_strings(struct net_device *dev, u32 stringset, u8 *data) 281 { 282 struct mlx5e_priv *priv = netdev_priv(dev); 283 284 mlx5e_ethtool_get_strings(priv, stringset, data); 285 } 286 287 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv, 288 struct ethtool_stats *stats, u64 *data) 289 { 290 int idx = 0; 291 292 mutex_lock(&priv->state_lock); 293 mlx5e_stats_update(priv); 294 mutex_unlock(&priv->state_lock); 295 296 mlx5e_stats_fill(priv, data, idx); 297 } 298 299 static void mlx5e_get_ethtool_stats(struct net_device *dev, 300 struct ethtool_stats *stats, 301 u64 *data) 302 { 303 struct mlx5e_priv *priv = netdev_priv(dev); 304 305 mlx5e_ethtool_get_ethtool_stats(priv, stats, data); 306 } 307 308 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv, 309 struct ethtool_ringparam *param) 310 { 311 param->rx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE; 312 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE; 313 param->rx_pending = 1 << priv->channels.params.log_rq_mtu_frames; 314 param->tx_pending = 1 << priv->channels.params.log_sq_size; 315 } 316 317 static void mlx5e_get_ringparam(struct net_device *dev, 318 struct ethtool_ringparam *param) 319 { 320 struct mlx5e_priv *priv = netdev_priv(dev); 321 322 mlx5e_ethtool_get_ringparam(priv, param); 323 } 324 325 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, 326 struct ethtool_ringparam *param) 327 { 328 struct mlx5e_channels new_channels = {}; 329 u8 log_rq_size; 330 u8 log_sq_size; 331 int err = 0; 332 333 if (param->rx_jumbo_pending) { 334 netdev_info(priv->netdev, "%s: rx_jumbo_pending not supported\n", 335 __func__); 336 return -EINVAL; 337 } 338 if (param->rx_mini_pending) { 339 netdev_info(priv->netdev, "%s: rx_mini_pending not supported\n", 340 __func__); 341 return -EINVAL; 342 } 343 344 if (param->rx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) { 345 netdev_info(priv->netdev, "%s: rx_pending (%d) < min (%d)\n", 346 __func__, param->rx_pending, 347 1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE); 348 return -EINVAL; 349 } 350 351 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) { 352 netdev_info(priv->netdev, "%s: tx_pending (%d) < min (%d)\n", 353 __func__, param->tx_pending, 354 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE); 355 return -EINVAL; 356 } 357 358 log_rq_size = order_base_2(param->rx_pending); 359 log_sq_size = order_base_2(param->tx_pending); 360 361 if (log_rq_size == priv->channels.params.log_rq_mtu_frames && 362 log_sq_size == priv->channels.params.log_sq_size) 363 return 0; 364 365 mutex_lock(&priv->state_lock); 366 367 new_channels.params = priv->channels.params; 368 new_channels.params.log_rq_mtu_frames = log_rq_size; 369 new_channels.params.log_sq_size = log_sq_size; 370 371 err = mlx5e_validate_params(priv, &new_channels.params); 372 if (err) 373 goto unlock; 374 375 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { 376 priv->channels.params = new_channels.params; 377 goto unlock; 378 } 379 380 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL); 381 382 unlock: 383 mutex_unlock(&priv->state_lock); 384 385 return err; 386 } 387 388 static int mlx5e_set_ringparam(struct net_device *dev, 389 struct ethtool_ringparam *param) 390 { 391 struct mlx5e_priv *priv = netdev_priv(dev); 392 393 return mlx5e_ethtool_set_ringparam(priv, param); 394 } 395 396 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv, 397 struct ethtool_channels *ch) 398 { 399 mutex_lock(&priv->state_lock); 400 401 ch->max_combined = priv->max_nch; 402 ch->combined_count = priv->channels.params.num_channels; 403 if (priv->xsk.refcnt) { 404 /* The upper half are XSK queues. */ 405 ch->max_combined *= 2; 406 ch->combined_count *= 2; 407 } 408 409 mutex_unlock(&priv->state_lock); 410 } 411 412 static void mlx5e_get_channels(struct net_device *dev, 413 struct ethtool_channels *ch) 414 { 415 struct mlx5e_priv *priv = netdev_priv(dev); 416 417 mlx5e_ethtool_get_channels(priv, ch); 418 } 419 420 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, 421 struct ethtool_channels *ch) 422 { 423 struct mlx5e_params *cur_params = &priv->channels.params; 424 unsigned int count = ch->combined_count; 425 struct mlx5e_channels new_channels = {}; 426 bool arfs_enabled; 427 int err = 0; 428 429 if (!count) { 430 netdev_info(priv->netdev, "%s: combined_count=0 not supported\n", 431 __func__); 432 return -EINVAL; 433 } 434 435 if (cur_params->num_channels == count) 436 return 0; 437 438 mutex_lock(&priv->state_lock); 439 440 /* Don't allow changing the number of channels if there is an active 441 * XSK, because the numeration of the XSK and regular RQs will change. 442 */ 443 if (priv->xsk.refcnt) { 444 err = -EINVAL; 445 netdev_err(priv->netdev, "%s: AF_XDP is active, cannot change the number of channels\n", 446 __func__); 447 goto out; 448 } 449 450 new_channels.params = *cur_params; 451 new_channels.params.num_channels = count; 452 453 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { 454 struct mlx5e_params old_params; 455 456 old_params = *cur_params; 457 *cur_params = new_channels.params; 458 err = mlx5e_num_channels_changed(priv); 459 if (err) 460 *cur_params = old_params; 461 462 goto out; 463 } 464 465 arfs_enabled = priv->netdev->features & NETIF_F_NTUPLE; 466 if (arfs_enabled) 467 mlx5e_arfs_disable(priv); 468 469 /* Switch to new channels, set new parameters and close old ones */ 470 err = mlx5e_safe_switch_channels(priv, &new_channels, 471 mlx5e_num_channels_changed_ctx, NULL); 472 473 if (arfs_enabled) { 474 int err2 = mlx5e_arfs_enable(priv); 475 476 if (err2) 477 netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n", 478 __func__, err2); 479 } 480 481 out: 482 mutex_unlock(&priv->state_lock); 483 484 return err; 485 } 486 487 static int mlx5e_set_channels(struct net_device *dev, 488 struct ethtool_channels *ch) 489 { 490 struct mlx5e_priv *priv = netdev_priv(dev); 491 492 return mlx5e_ethtool_set_channels(priv, ch); 493 } 494 495 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv, 496 struct ethtool_coalesce *coal) 497 { 498 struct dim_cq_moder *rx_moder, *tx_moder; 499 500 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation)) 501 return -EOPNOTSUPP; 502 503 rx_moder = &priv->channels.params.rx_cq_moderation; 504 coal->rx_coalesce_usecs = rx_moder->usec; 505 coal->rx_max_coalesced_frames = rx_moder->pkts; 506 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_dim_enabled; 507 508 tx_moder = &priv->channels.params.tx_cq_moderation; 509 coal->tx_coalesce_usecs = tx_moder->usec; 510 coal->tx_max_coalesced_frames = tx_moder->pkts; 511 coal->use_adaptive_tx_coalesce = priv->channels.params.tx_dim_enabled; 512 513 return 0; 514 } 515 516 static int mlx5e_get_coalesce(struct net_device *netdev, 517 struct ethtool_coalesce *coal) 518 { 519 struct mlx5e_priv *priv = netdev_priv(netdev); 520 521 return mlx5e_ethtool_get_coalesce(priv, coal); 522 } 523 524 #define MLX5E_MAX_COAL_TIME MLX5_MAX_CQ_PERIOD 525 #define MLX5E_MAX_COAL_FRAMES MLX5_MAX_CQ_COUNT 526 527 static void 528 mlx5e_set_priv_channels_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal) 529 { 530 struct mlx5_core_dev *mdev = priv->mdev; 531 int tc; 532 int i; 533 534 for (i = 0; i < priv->channels.num; ++i) { 535 struct mlx5e_channel *c = priv->channels.c[i]; 536 537 for (tc = 0; tc < c->num_tc; tc++) { 538 mlx5_core_modify_cq_moderation(mdev, 539 &c->sq[tc].cq.mcq, 540 coal->tx_coalesce_usecs, 541 coal->tx_max_coalesced_frames); 542 } 543 544 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq, 545 coal->rx_coalesce_usecs, 546 coal->rx_max_coalesced_frames); 547 } 548 } 549 550 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, 551 struct ethtool_coalesce *coal) 552 { 553 struct dim_cq_moder *rx_moder, *tx_moder; 554 struct mlx5_core_dev *mdev = priv->mdev; 555 struct mlx5e_channels new_channels = {}; 556 bool reset_rx, reset_tx; 557 int err = 0; 558 559 if (!MLX5_CAP_GEN(mdev, cq_moderation)) 560 return -EOPNOTSUPP; 561 562 if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME || 563 coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) { 564 netdev_info(priv->netdev, "%s: maximum coalesce time supported is %lu usecs\n", 565 __func__, MLX5E_MAX_COAL_TIME); 566 return -ERANGE; 567 } 568 569 if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES || 570 coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) { 571 netdev_info(priv->netdev, "%s: maximum coalesced frames supported is %lu\n", 572 __func__, MLX5E_MAX_COAL_FRAMES); 573 return -ERANGE; 574 } 575 576 mutex_lock(&priv->state_lock); 577 new_channels.params = priv->channels.params; 578 579 rx_moder = &new_channels.params.rx_cq_moderation; 580 rx_moder->usec = coal->rx_coalesce_usecs; 581 rx_moder->pkts = coal->rx_max_coalesced_frames; 582 new_channels.params.rx_dim_enabled = !!coal->use_adaptive_rx_coalesce; 583 584 tx_moder = &new_channels.params.tx_cq_moderation; 585 tx_moder->usec = coal->tx_coalesce_usecs; 586 tx_moder->pkts = coal->tx_max_coalesced_frames; 587 new_channels.params.tx_dim_enabled = !!coal->use_adaptive_tx_coalesce; 588 589 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { 590 priv->channels.params = new_channels.params; 591 goto out; 592 } 593 /* we are opened */ 594 595 reset_rx = !!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_dim_enabled; 596 reset_tx = !!coal->use_adaptive_tx_coalesce != priv->channels.params.tx_dim_enabled; 597 598 if (!reset_rx && !reset_tx) { 599 mlx5e_set_priv_channels_coalesce(priv, coal); 600 priv->channels.params = new_channels.params; 601 goto out; 602 } 603 604 if (reset_rx) { 605 u8 mode = MLX5E_GET_PFLAG(&new_channels.params, 606 MLX5E_PFLAG_RX_CQE_BASED_MODER); 607 608 mlx5e_reset_rx_moderation(&new_channels.params, mode); 609 } 610 if (reset_tx) { 611 u8 mode = MLX5E_GET_PFLAG(&new_channels.params, 612 MLX5E_PFLAG_TX_CQE_BASED_MODER); 613 614 mlx5e_reset_tx_moderation(&new_channels.params, mode); 615 } 616 617 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL); 618 619 out: 620 mutex_unlock(&priv->state_lock); 621 return err; 622 } 623 624 static int mlx5e_set_coalesce(struct net_device *netdev, 625 struct ethtool_coalesce *coal) 626 { 627 struct mlx5e_priv *priv = netdev_priv(netdev); 628 629 return mlx5e_ethtool_set_coalesce(priv, coal); 630 } 631 632 static void ptys2ethtool_supported_link(struct mlx5_core_dev *mdev, 633 unsigned long *supported_modes, 634 u32 eth_proto_cap) 635 { 636 unsigned long proto_cap = eth_proto_cap; 637 struct ptys2ethtool_config *table; 638 u32 max_size; 639 int proto; 640 641 mlx5e_ethtool_get_speed_arr(mdev, &table, &max_size); 642 for_each_set_bit(proto, &proto_cap, max_size) 643 bitmap_or(supported_modes, supported_modes, 644 table[proto].supported, 645 __ETHTOOL_LINK_MODE_MASK_NBITS); 646 } 647 648 static void ptys2ethtool_adver_link(unsigned long *advertising_modes, 649 u32 eth_proto_cap, bool ext) 650 { 651 unsigned long proto_cap = eth_proto_cap; 652 struct ptys2ethtool_config *table; 653 u32 max_size; 654 int proto; 655 656 table = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table; 657 max_size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) : 658 ARRAY_SIZE(ptys2legacy_ethtool_table); 659 660 for_each_set_bit(proto, &proto_cap, max_size) 661 bitmap_or(advertising_modes, advertising_modes, 662 table[proto].advertised, 663 __ETHTOOL_LINK_MODE_MASK_NBITS); 664 } 665 666 static const u32 pplm_fec_2_ethtool[] = { 667 [MLX5E_FEC_NOFEC] = ETHTOOL_FEC_OFF, 668 [MLX5E_FEC_FIRECODE] = ETHTOOL_FEC_BASER, 669 [MLX5E_FEC_RS_528_514] = ETHTOOL_FEC_RS, 670 [MLX5E_FEC_RS_544_514] = ETHTOOL_FEC_RS, 671 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_FEC_LLRS, 672 }; 673 674 static u32 pplm2ethtool_fec(u_long fec_mode, unsigned long size) 675 { 676 int mode = 0; 677 678 if (!fec_mode) 679 return ETHTOOL_FEC_AUTO; 680 681 mode = find_first_bit(&fec_mode, size); 682 683 if (mode < ARRAY_SIZE(pplm_fec_2_ethtool)) 684 return pplm_fec_2_ethtool[mode]; 685 686 return 0; 687 } 688 689 #define MLX5E_ADVERTISE_SUPPORTED_FEC(mlx5_fec, ethtool_fec) \ 690 do { \ 691 if (mlx5e_fec_in_caps(dev, 1 << (mlx5_fec))) \ 692 __set_bit(ethtool_fec, \ 693 link_ksettings->link_modes.supported);\ 694 } while (0) 695 696 static const u32 pplm_fec_2_ethtool_linkmodes[] = { 697 [MLX5E_FEC_NOFEC] = ETHTOOL_LINK_MODE_FEC_NONE_BIT, 698 [MLX5E_FEC_FIRECODE] = ETHTOOL_LINK_MODE_FEC_BASER_BIT, 699 [MLX5E_FEC_RS_528_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT, 700 [MLX5E_FEC_RS_544_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT, 701 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 702 }; 703 704 static int get_fec_supported_advertised(struct mlx5_core_dev *dev, 705 struct ethtool_link_ksettings *link_ksettings) 706 { 707 unsigned long active_fec_long; 708 u32 active_fec; 709 u32 bitn; 710 int err; 711 712 err = mlx5e_get_fec_mode(dev, &active_fec, NULL); 713 if (err) 714 return (err == -EOPNOTSUPP) ? 0 : err; 715 716 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_NOFEC, 717 ETHTOOL_LINK_MODE_FEC_NONE_BIT); 718 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_FIRECODE, 719 ETHTOOL_LINK_MODE_FEC_BASER_BIT); 720 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_RS_528_514, 721 ETHTOOL_LINK_MODE_FEC_RS_BIT); 722 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_LLRS_272_257_1, 723 ETHTOOL_LINK_MODE_FEC_LLRS_BIT); 724 725 active_fec_long = active_fec; 726 /* active fec is a bit set, find out which bit is set and 727 * advertise the corresponding ethtool bit 728 */ 729 bitn = find_first_bit(&active_fec_long, sizeof(active_fec_long) * BITS_PER_BYTE); 730 if (bitn < ARRAY_SIZE(pplm_fec_2_ethtool_linkmodes)) 731 __set_bit(pplm_fec_2_ethtool_linkmodes[bitn], 732 link_ksettings->link_modes.advertising); 733 734 return 0; 735 } 736 737 static void ptys2ethtool_supported_advertised_port(struct ethtool_link_ksettings *link_ksettings, 738 u32 eth_proto_cap, 739 u8 connector_type, bool ext) 740 { 741 if ((!connector_type && !ext) || connector_type >= MLX5E_CONNECTOR_TYPE_NUMBER) { 742 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR) 743 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR) 744 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) 745 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) 746 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) 747 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) { 748 ethtool_link_ksettings_add_link_mode(link_ksettings, 749 supported, 750 FIBRE); 751 ethtool_link_ksettings_add_link_mode(link_ksettings, 752 advertising, 753 FIBRE); 754 } 755 756 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4) 757 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) 758 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR) 759 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) 760 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) { 761 ethtool_link_ksettings_add_link_mode(link_ksettings, 762 supported, 763 Backplane); 764 ethtool_link_ksettings_add_link_mode(link_ksettings, 765 advertising, 766 Backplane); 767 } 768 return; 769 } 770 771 switch (connector_type) { 772 case MLX5E_PORT_TP: 773 ethtool_link_ksettings_add_link_mode(link_ksettings, 774 supported, TP); 775 ethtool_link_ksettings_add_link_mode(link_ksettings, 776 advertising, TP); 777 break; 778 case MLX5E_PORT_AUI: 779 ethtool_link_ksettings_add_link_mode(link_ksettings, 780 supported, AUI); 781 ethtool_link_ksettings_add_link_mode(link_ksettings, 782 advertising, AUI); 783 break; 784 case MLX5E_PORT_BNC: 785 ethtool_link_ksettings_add_link_mode(link_ksettings, 786 supported, BNC); 787 ethtool_link_ksettings_add_link_mode(link_ksettings, 788 advertising, BNC); 789 break; 790 case MLX5E_PORT_MII: 791 ethtool_link_ksettings_add_link_mode(link_ksettings, 792 supported, MII); 793 ethtool_link_ksettings_add_link_mode(link_ksettings, 794 advertising, MII); 795 break; 796 case MLX5E_PORT_FIBRE: 797 ethtool_link_ksettings_add_link_mode(link_ksettings, 798 supported, FIBRE); 799 ethtool_link_ksettings_add_link_mode(link_ksettings, 800 advertising, FIBRE); 801 break; 802 case MLX5E_PORT_DA: 803 ethtool_link_ksettings_add_link_mode(link_ksettings, 804 supported, Backplane); 805 ethtool_link_ksettings_add_link_mode(link_ksettings, 806 advertising, Backplane); 807 break; 808 case MLX5E_PORT_NONE: 809 case MLX5E_PORT_OTHER: 810 default: 811 break; 812 } 813 } 814 815 static void get_speed_duplex(struct net_device *netdev, 816 u32 eth_proto_oper, bool force_legacy, 817 u16 data_rate_oper, 818 struct ethtool_link_ksettings *link_ksettings) 819 { 820 struct mlx5e_priv *priv = netdev_priv(netdev); 821 u32 speed = SPEED_UNKNOWN; 822 u8 duplex = DUPLEX_UNKNOWN; 823 824 if (!netif_carrier_ok(netdev)) 825 goto out; 826 827 speed = mlx5e_port_ptys2speed(priv->mdev, eth_proto_oper, force_legacy); 828 if (!speed) { 829 if (data_rate_oper) 830 speed = 100 * data_rate_oper; 831 else 832 speed = SPEED_UNKNOWN; 833 goto out; 834 } 835 836 duplex = DUPLEX_FULL; 837 838 out: 839 link_ksettings->base.speed = speed; 840 link_ksettings->base.duplex = duplex; 841 } 842 843 static void get_supported(struct mlx5_core_dev *mdev, u32 eth_proto_cap, 844 struct ethtool_link_ksettings *link_ksettings) 845 { 846 unsigned long *supported = link_ksettings->link_modes.supported; 847 ptys2ethtool_supported_link(mdev, supported, eth_proto_cap); 848 849 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause); 850 } 851 852 static void get_advertising(u32 eth_proto_cap, u8 tx_pause, u8 rx_pause, 853 struct ethtool_link_ksettings *link_ksettings, 854 bool ext) 855 { 856 unsigned long *advertising = link_ksettings->link_modes.advertising; 857 ptys2ethtool_adver_link(advertising, eth_proto_cap, ext); 858 859 if (rx_pause) 860 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause); 861 if (tx_pause ^ rx_pause) 862 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause); 863 } 864 865 static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = { 866 [MLX5E_PORT_UNKNOWN] = PORT_OTHER, 867 [MLX5E_PORT_NONE] = PORT_NONE, 868 [MLX5E_PORT_TP] = PORT_TP, 869 [MLX5E_PORT_AUI] = PORT_AUI, 870 [MLX5E_PORT_BNC] = PORT_BNC, 871 [MLX5E_PORT_MII] = PORT_MII, 872 [MLX5E_PORT_FIBRE] = PORT_FIBRE, 873 [MLX5E_PORT_DA] = PORT_DA, 874 [MLX5E_PORT_OTHER] = PORT_OTHER, 875 }; 876 877 static u8 get_connector_port(u32 eth_proto, u8 connector_type, bool ext) 878 { 879 if ((connector_type || ext) && connector_type < MLX5E_CONNECTOR_TYPE_NUMBER) 880 return ptys2connector_type[connector_type]; 881 882 if (eth_proto & 883 (MLX5E_PROT_MASK(MLX5E_10GBASE_SR) | 884 MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) | 885 MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) | 886 MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) { 887 return PORT_FIBRE; 888 } 889 890 if (eth_proto & 891 (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) | 892 MLX5E_PROT_MASK(MLX5E_10GBASE_CR) | 893 MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) { 894 return PORT_DA; 895 } 896 897 if (eth_proto & 898 (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) | 899 MLX5E_PROT_MASK(MLX5E_10GBASE_KR) | 900 MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) | 901 MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) { 902 return PORT_NONE; 903 } 904 905 return PORT_OTHER; 906 } 907 908 static void get_lp_advertising(struct mlx5_core_dev *mdev, u32 eth_proto_lp, 909 struct ethtool_link_ksettings *link_ksettings) 910 { 911 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising; 912 bool ext = mlx5e_ptys_ext_supported(mdev); 913 914 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp, ext); 915 } 916 917 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv, 918 struct ethtool_link_ksettings *link_ksettings) 919 { 920 struct mlx5_core_dev *mdev = priv->mdev; 921 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {}; 922 u32 eth_proto_admin; 923 u8 an_disable_admin; 924 u16 data_rate_oper; 925 u32 eth_proto_oper; 926 u32 eth_proto_cap; 927 u8 connector_type; 928 u32 rx_pause = 0; 929 u32 tx_pause = 0; 930 u32 eth_proto_lp; 931 bool admin_ext; 932 u8 an_status; 933 bool ext; 934 int err; 935 936 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1); 937 if (err) { 938 netdev_err(priv->netdev, "%s: query port ptys failed: %d\n", 939 __func__, err); 940 goto err_query_regs; 941 } 942 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability); 943 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 944 eth_proto_capability); 945 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 946 eth_proto_admin); 947 /* Fields: eth_proto_admin and ext_eth_proto_admin are 948 * mutually exclusive. Hence try reading legacy advertising 949 * when extended advertising is zero. 950 * admin_ext indicates which proto_admin (ext vs. legacy) 951 * should be read and interpreted 952 */ 953 admin_ext = ext; 954 if (ext && !eth_proto_admin) { 955 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, false, 956 eth_proto_admin); 957 admin_ext = false; 958 } 959 960 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, admin_ext, 961 eth_proto_oper); 962 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise); 963 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin); 964 an_status = MLX5_GET(ptys_reg, out, an_status); 965 connector_type = MLX5_GET(ptys_reg, out, connector_type); 966 data_rate_oper = MLX5_GET(ptys_reg, out, data_rate_oper); 967 968 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause); 969 970 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported); 971 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising); 972 973 get_supported(mdev, eth_proto_cap, link_ksettings); 974 get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings, 975 admin_ext); 976 get_speed_duplex(priv->netdev, eth_proto_oper, !admin_ext, 977 data_rate_oper, link_ksettings); 978 979 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap; 980 981 link_ksettings->base.port = get_connector_port(eth_proto_oper, 982 connector_type, ext); 983 ptys2ethtool_supported_advertised_port(link_ksettings, eth_proto_admin, 984 connector_type, ext); 985 get_lp_advertising(mdev, eth_proto_lp, link_ksettings); 986 987 if (an_status == MLX5_AN_COMPLETE) 988 ethtool_link_ksettings_add_link_mode(link_ksettings, 989 lp_advertising, Autoneg); 990 991 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE : 992 AUTONEG_ENABLE; 993 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, 994 Autoneg); 995 996 err = get_fec_supported_advertised(mdev, link_ksettings); 997 if (err) { 998 netdev_dbg(priv->netdev, "%s: FEC caps query failed: %d\n", 999 __func__, err); 1000 err = 0; /* don't fail caps query because of FEC error */ 1001 } 1002 1003 if (!an_disable_admin) 1004 ethtool_link_ksettings_add_link_mode(link_ksettings, 1005 advertising, Autoneg); 1006 1007 err_query_regs: 1008 return err; 1009 } 1010 1011 static int mlx5e_get_link_ksettings(struct net_device *netdev, 1012 struct ethtool_link_ksettings *link_ksettings) 1013 { 1014 struct mlx5e_priv *priv = netdev_priv(netdev); 1015 1016 return mlx5e_ethtool_get_link_ksettings(priv, link_ksettings); 1017 } 1018 1019 static int mlx5e_speed_validate(struct net_device *netdev, bool ext, 1020 const unsigned long link_modes, u8 autoneg) 1021 { 1022 /* Extended link-mode has no speed limitations. */ 1023 if (ext) 1024 return 0; 1025 1026 if ((link_modes & MLX5E_PROT_MASK(MLX5E_56GBASE_R4)) && 1027 autoneg != AUTONEG_ENABLE) { 1028 netdev_err(netdev, "%s: 56G link speed requires autoneg enabled\n", 1029 __func__); 1030 return -EINVAL; 1031 } 1032 return 0; 1033 } 1034 1035 static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes) 1036 { 1037 u32 i, ptys_modes = 0; 1038 1039 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) { 1040 if (*ptys2legacy_ethtool_table[i].advertised == 0) 1041 continue; 1042 if (bitmap_intersects(ptys2legacy_ethtool_table[i].advertised, 1043 link_modes, 1044 __ETHTOOL_LINK_MODE_MASK_NBITS)) 1045 ptys_modes |= MLX5E_PROT_MASK(i); 1046 } 1047 1048 return ptys_modes; 1049 } 1050 1051 static u32 mlx5e_ethtool2ptys_ext_adver_link(const unsigned long *link_modes) 1052 { 1053 u32 i, ptys_modes = 0; 1054 unsigned long modes[2]; 1055 1056 for (i = 0; i < MLX5E_EXT_LINK_MODES_NUMBER; ++i) { 1057 if (ptys2ext_ethtool_table[i].advertised[0] == 0 && 1058 ptys2ext_ethtool_table[i].advertised[1] == 0) 1059 continue; 1060 memset(modes, 0, sizeof(modes)); 1061 bitmap_and(modes, ptys2ext_ethtool_table[i].advertised, 1062 link_modes, __ETHTOOL_LINK_MODE_MASK_NBITS); 1063 1064 if (modes[0] == ptys2ext_ethtool_table[i].advertised[0] && 1065 modes[1] == ptys2ext_ethtool_table[i].advertised[1]) 1066 ptys_modes |= MLX5E_PROT_MASK(i); 1067 } 1068 return ptys_modes; 1069 } 1070 1071 static bool ext_link_mode_requested(const unsigned long *adver) 1072 { 1073 #define MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT ETHTOOL_LINK_MODE_50000baseKR_Full_BIT 1074 int size = __ETHTOOL_LINK_MODE_MASK_NBITS - MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT; 1075 __ETHTOOL_DECLARE_LINK_MODE_MASK(modes) = {0,}; 1076 1077 bitmap_set(modes, MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT, size); 1078 return bitmap_intersects(modes, adver, __ETHTOOL_LINK_MODE_MASK_NBITS); 1079 } 1080 1081 static bool ext_requested(u8 autoneg, const unsigned long *adver, bool ext_supported) 1082 { 1083 bool ext_link_mode = ext_link_mode_requested(adver); 1084 1085 return autoneg == AUTONEG_ENABLE ? ext_link_mode : ext_supported; 1086 } 1087 1088 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv, 1089 const struct ethtool_link_ksettings *link_ksettings) 1090 { 1091 struct mlx5_core_dev *mdev = priv->mdev; 1092 struct mlx5e_port_eth_proto eproto; 1093 const unsigned long *adver; 1094 bool an_changes = false; 1095 u8 an_disable_admin; 1096 bool ext_supported; 1097 u8 an_disable_cap; 1098 bool an_disable; 1099 u32 link_modes; 1100 u8 an_status; 1101 u8 autoneg; 1102 u32 speed; 1103 bool ext; 1104 int err; 1105 1106 u32 (*ethtool2ptys_adver_func)(const unsigned long *adver); 1107 1108 adver = link_ksettings->link_modes.advertising; 1109 autoneg = link_ksettings->base.autoneg; 1110 speed = link_ksettings->base.speed; 1111 1112 ext_supported = mlx5e_ptys_ext_supported(mdev); 1113 ext = ext_requested(autoneg, adver, ext_supported); 1114 if (!ext_supported && ext) 1115 return -EOPNOTSUPP; 1116 1117 ethtool2ptys_adver_func = ext ? mlx5e_ethtool2ptys_ext_adver_link : 1118 mlx5e_ethtool2ptys_adver_link; 1119 err = mlx5_port_query_eth_proto(mdev, 1, ext, &eproto); 1120 if (err) { 1121 netdev_err(priv->netdev, "%s: query port eth proto failed: %d\n", 1122 __func__, err); 1123 goto out; 1124 } 1125 link_modes = autoneg == AUTONEG_ENABLE ? ethtool2ptys_adver_func(adver) : 1126 mlx5e_port_speed2linkmodes(mdev, speed, !ext); 1127 1128 err = mlx5e_speed_validate(priv->netdev, ext, link_modes, autoneg); 1129 if (err) 1130 goto out; 1131 1132 link_modes = link_modes & eproto.cap; 1133 if (!link_modes) { 1134 netdev_err(priv->netdev, "%s: Not supported link mode(s) requested", 1135 __func__); 1136 err = -EINVAL; 1137 goto out; 1138 } 1139 1140 mlx5_port_query_eth_autoneg(mdev, &an_status, &an_disable_cap, 1141 &an_disable_admin); 1142 1143 an_disable = autoneg == AUTONEG_DISABLE; 1144 an_changes = ((!an_disable && an_disable_admin) || 1145 (an_disable && !an_disable_admin)); 1146 1147 if (!an_changes && link_modes == eproto.admin) 1148 goto out; 1149 1150 mlx5_port_set_eth_ptys(mdev, an_disable, link_modes, ext); 1151 mlx5_toggle_port_link(mdev); 1152 1153 out: 1154 return err; 1155 } 1156 1157 static int mlx5e_set_link_ksettings(struct net_device *netdev, 1158 const struct ethtool_link_ksettings *link_ksettings) 1159 { 1160 struct mlx5e_priv *priv = netdev_priv(netdev); 1161 1162 return mlx5e_ethtool_set_link_ksettings(priv, link_ksettings); 1163 } 1164 1165 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv) 1166 { 1167 return sizeof(priv->rss_params.toeplitz_hash_key); 1168 } 1169 1170 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev) 1171 { 1172 struct mlx5e_priv *priv = netdev_priv(netdev); 1173 1174 return mlx5e_ethtool_get_rxfh_key_size(priv); 1175 } 1176 1177 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv) 1178 { 1179 return MLX5E_INDIR_RQT_SIZE; 1180 } 1181 1182 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev) 1183 { 1184 struct mlx5e_priv *priv = netdev_priv(netdev); 1185 1186 return mlx5e_ethtool_get_rxfh_indir_size(priv); 1187 } 1188 1189 int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, 1190 u8 *hfunc) 1191 { 1192 struct mlx5e_priv *priv = netdev_priv(netdev); 1193 struct mlx5e_rss_params *rss = &priv->rss_params; 1194 1195 if (indir) 1196 memcpy(indir, rss->indirection_rqt, 1197 sizeof(rss->indirection_rqt)); 1198 1199 if (key) 1200 memcpy(key, rss->toeplitz_hash_key, 1201 sizeof(rss->toeplitz_hash_key)); 1202 1203 if (hfunc) 1204 *hfunc = rss->hfunc; 1205 1206 return 0; 1207 } 1208 1209 int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir, 1210 const u8 *key, const u8 hfunc) 1211 { 1212 struct mlx5e_priv *priv = netdev_priv(dev); 1213 struct mlx5e_rss_params *rss = &priv->rss_params; 1214 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in); 1215 bool refresh_tirs = false; 1216 bool refresh_rqt = false; 1217 void *in; 1218 1219 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) && 1220 (hfunc != ETH_RSS_HASH_XOR) && 1221 (hfunc != ETH_RSS_HASH_TOP)) 1222 return -EINVAL; 1223 1224 in = kvzalloc(inlen, GFP_KERNEL); 1225 if (!in) 1226 return -ENOMEM; 1227 1228 mutex_lock(&priv->state_lock); 1229 1230 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != rss->hfunc) { 1231 rss->hfunc = hfunc; 1232 refresh_rqt = true; 1233 refresh_tirs = true; 1234 } 1235 1236 if (indir) { 1237 memcpy(rss->indirection_rqt, indir, 1238 sizeof(rss->indirection_rqt)); 1239 refresh_rqt = true; 1240 } 1241 1242 if (key) { 1243 memcpy(rss->toeplitz_hash_key, key, 1244 sizeof(rss->toeplitz_hash_key)); 1245 refresh_tirs = refresh_tirs || rss->hfunc == ETH_RSS_HASH_TOP; 1246 } 1247 1248 if (refresh_rqt && test_bit(MLX5E_STATE_OPENED, &priv->state)) { 1249 struct mlx5e_redirect_rqt_param rrp = { 1250 .is_rss = true, 1251 { 1252 .rss = { 1253 .hfunc = rss->hfunc, 1254 .channels = &priv->channels, 1255 }, 1256 }, 1257 }; 1258 u32 rqtn = priv->indir_rqt.rqtn; 1259 1260 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp); 1261 } 1262 1263 if (refresh_tirs) 1264 mlx5e_modify_tirs_hash(priv, in); 1265 1266 mutex_unlock(&priv->state_lock); 1267 1268 kvfree(in); 1269 1270 return 0; 1271 } 1272 1273 #define MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC 100 1274 #define MLX5E_PFC_PREVEN_TOUT_MAX_MSEC 8000 1275 #define MLX5E_PFC_PREVEN_MINOR_PRECENT 85 1276 #define MLX5E_PFC_PREVEN_TOUT_MIN_MSEC 80 1277 #define MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout) \ 1278 max_t(u16, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, \ 1279 (critical_tout * MLX5E_PFC_PREVEN_MINOR_PRECENT) / 100) 1280 1281 static int mlx5e_get_pfc_prevention_tout(struct net_device *netdev, 1282 u16 *pfc_prevention_tout) 1283 { 1284 struct mlx5e_priv *priv = netdev_priv(netdev); 1285 struct mlx5_core_dev *mdev = priv->mdev; 1286 1287 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) || 1288 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect)) 1289 return -EOPNOTSUPP; 1290 1291 return mlx5_query_port_stall_watermark(mdev, pfc_prevention_tout, NULL); 1292 } 1293 1294 static int mlx5e_set_pfc_prevention_tout(struct net_device *netdev, 1295 u16 pfc_preven) 1296 { 1297 struct mlx5e_priv *priv = netdev_priv(netdev); 1298 struct mlx5_core_dev *mdev = priv->mdev; 1299 u16 critical_tout; 1300 u16 minor; 1301 1302 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) || 1303 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect)) 1304 return -EOPNOTSUPP; 1305 1306 critical_tout = (pfc_preven == PFC_STORM_PREVENTION_AUTO) ? 1307 MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC : 1308 pfc_preven; 1309 1310 if (critical_tout != PFC_STORM_PREVENTION_DISABLE && 1311 (critical_tout > MLX5E_PFC_PREVEN_TOUT_MAX_MSEC || 1312 critical_tout < MLX5E_PFC_PREVEN_TOUT_MIN_MSEC)) { 1313 netdev_info(netdev, "%s: pfc prevention tout not in range (%d-%d)\n", 1314 __func__, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, 1315 MLX5E_PFC_PREVEN_TOUT_MAX_MSEC); 1316 return -EINVAL; 1317 } 1318 1319 minor = MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout); 1320 return mlx5_set_port_stall_watermark(mdev, critical_tout, 1321 minor); 1322 } 1323 1324 static int mlx5e_get_tunable(struct net_device *dev, 1325 const struct ethtool_tunable *tuna, 1326 void *data) 1327 { 1328 int err; 1329 1330 switch (tuna->id) { 1331 case ETHTOOL_PFC_PREVENTION_TOUT: 1332 err = mlx5e_get_pfc_prevention_tout(dev, data); 1333 break; 1334 default: 1335 err = -EINVAL; 1336 break; 1337 } 1338 1339 return err; 1340 } 1341 1342 static int mlx5e_set_tunable(struct net_device *dev, 1343 const struct ethtool_tunable *tuna, 1344 const void *data) 1345 { 1346 struct mlx5e_priv *priv = netdev_priv(dev); 1347 int err; 1348 1349 mutex_lock(&priv->state_lock); 1350 1351 switch (tuna->id) { 1352 case ETHTOOL_PFC_PREVENTION_TOUT: 1353 err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data); 1354 break; 1355 default: 1356 err = -EINVAL; 1357 break; 1358 } 1359 1360 mutex_unlock(&priv->state_lock); 1361 return err; 1362 } 1363 1364 static void mlx5e_get_pause_stats(struct net_device *netdev, 1365 struct ethtool_pause_stats *pause_stats) 1366 { 1367 struct mlx5e_priv *priv = netdev_priv(netdev); 1368 1369 mlx5e_stats_pause_get(priv, pause_stats); 1370 } 1371 1372 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv, 1373 struct ethtool_pauseparam *pauseparam) 1374 { 1375 struct mlx5_core_dev *mdev = priv->mdev; 1376 int err; 1377 1378 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause, 1379 &pauseparam->tx_pause); 1380 if (err) { 1381 netdev_err(priv->netdev, "%s: mlx5_query_port_pause failed:0x%x\n", 1382 __func__, err); 1383 } 1384 } 1385 1386 static void mlx5e_get_pauseparam(struct net_device *netdev, 1387 struct ethtool_pauseparam *pauseparam) 1388 { 1389 struct mlx5e_priv *priv = netdev_priv(netdev); 1390 1391 mlx5e_ethtool_get_pauseparam(priv, pauseparam); 1392 } 1393 1394 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv, 1395 struct ethtool_pauseparam *pauseparam) 1396 { 1397 struct mlx5_core_dev *mdev = priv->mdev; 1398 int err; 1399 1400 if (!MLX5_CAP_GEN(mdev, vport_group_manager)) 1401 return -EOPNOTSUPP; 1402 1403 if (pauseparam->autoneg) 1404 return -EINVAL; 1405 1406 err = mlx5_set_port_pause(mdev, 1407 pauseparam->rx_pause ? 1 : 0, 1408 pauseparam->tx_pause ? 1 : 0); 1409 if (err) { 1410 netdev_err(priv->netdev, "%s: mlx5_set_port_pause failed:0x%x\n", 1411 __func__, err); 1412 } 1413 1414 return err; 1415 } 1416 1417 static int mlx5e_set_pauseparam(struct net_device *netdev, 1418 struct ethtool_pauseparam *pauseparam) 1419 { 1420 struct mlx5e_priv *priv = netdev_priv(netdev); 1421 1422 return mlx5e_ethtool_set_pauseparam(priv, pauseparam); 1423 } 1424 1425 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv, 1426 struct ethtool_ts_info *info) 1427 { 1428 struct mlx5_core_dev *mdev = priv->mdev; 1429 1430 info->phc_index = mlx5_clock_get_ptp_index(mdev); 1431 1432 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) || 1433 info->phc_index == -1) 1434 return 0; 1435 1436 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE | 1437 SOF_TIMESTAMPING_RX_HARDWARE | 1438 SOF_TIMESTAMPING_RAW_HARDWARE; 1439 1440 info->tx_types = BIT(HWTSTAMP_TX_OFF) | 1441 BIT(HWTSTAMP_TX_ON); 1442 1443 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | 1444 BIT(HWTSTAMP_FILTER_ALL); 1445 1446 return 0; 1447 } 1448 1449 static int mlx5e_get_ts_info(struct net_device *dev, 1450 struct ethtool_ts_info *info) 1451 { 1452 struct mlx5e_priv *priv = netdev_priv(dev); 1453 1454 return mlx5e_ethtool_get_ts_info(priv, info); 1455 } 1456 1457 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev) 1458 { 1459 __u32 ret = 0; 1460 1461 if (MLX5_CAP_GEN(mdev, wol_g)) 1462 ret |= WAKE_MAGIC; 1463 1464 if (MLX5_CAP_GEN(mdev, wol_s)) 1465 ret |= WAKE_MAGICSECURE; 1466 1467 if (MLX5_CAP_GEN(mdev, wol_a)) 1468 ret |= WAKE_ARP; 1469 1470 if (MLX5_CAP_GEN(mdev, wol_b)) 1471 ret |= WAKE_BCAST; 1472 1473 if (MLX5_CAP_GEN(mdev, wol_m)) 1474 ret |= WAKE_MCAST; 1475 1476 if (MLX5_CAP_GEN(mdev, wol_u)) 1477 ret |= WAKE_UCAST; 1478 1479 if (MLX5_CAP_GEN(mdev, wol_p)) 1480 ret |= WAKE_PHY; 1481 1482 return ret; 1483 } 1484 1485 static __u32 mlx5e_reformat_wol_mode_mlx5_to_linux(u8 mode) 1486 { 1487 __u32 ret = 0; 1488 1489 if (mode & MLX5_WOL_MAGIC) 1490 ret |= WAKE_MAGIC; 1491 1492 if (mode & MLX5_WOL_SECURED_MAGIC) 1493 ret |= WAKE_MAGICSECURE; 1494 1495 if (mode & MLX5_WOL_ARP) 1496 ret |= WAKE_ARP; 1497 1498 if (mode & MLX5_WOL_BROADCAST) 1499 ret |= WAKE_BCAST; 1500 1501 if (mode & MLX5_WOL_MULTICAST) 1502 ret |= WAKE_MCAST; 1503 1504 if (mode & MLX5_WOL_UNICAST) 1505 ret |= WAKE_UCAST; 1506 1507 if (mode & MLX5_WOL_PHY_ACTIVITY) 1508 ret |= WAKE_PHY; 1509 1510 return ret; 1511 } 1512 1513 static u8 mlx5e_reformat_wol_mode_linux_to_mlx5(__u32 mode) 1514 { 1515 u8 ret = 0; 1516 1517 if (mode & WAKE_MAGIC) 1518 ret |= MLX5_WOL_MAGIC; 1519 1520 if (mode & WAKE_MAGICSECURE) 1521 ret |= MLX5_WOL_SECURED_MAGIC; 1522 1523 if (mode & WAKE_ARP) 1524 ret |= MLX5_WOL_ARP; 1525 1526 if (mode & WAKE_BCAST) 1527 ret |= MLX5_WOL_BROADCAST; 1528 1529 if (mode & WAKE_MCAST) 1530 ret |= MLX5_WOL_MULTICAST; 1531 1532 if (mode & WAKE_UCAST) 1533 ret |= MLX5_WOL_UNICAST; 1534 1535 if (mode & WAKE_PHY) 1536 ret |= MLX5_WOL_PHY_ACTIVITY; 1537 1538 return ret; 1539 } 1540 1541 static void mlx5e_get_wol(struct net_device *netdev, 1542 struct ethtool_wolinfo *wol) 1543 { 1544 struct mlx5e_priv *priv = netdev_priv(netdev); 1545 struct mlx5_core_dev *mdev = priv->mdev; 1546 u8 mlx5_wol_mode; 1547 int err; 1548 1549 memset(wol, 0, sizeof(*wol)); 1550 1551 wol->supported = mlx5e_get_wol_supported(mdev); 1552 if (!wol->supported) 1553 return; 1554 1555 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode); 1556 if (err) 1557 return; 1558 1559 wol->wolopts = mlx5e_reformat_wol_mode_mlx5_to_linux(mlx5_wol_mode); 1560 } 1561 1562 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 1563 { 1564 struct mlx5e_priv *priv = netdev_priv(netdev); 1565 struct mlx5_core_dev *mdev = priv->mdev; 1566 __u32 wol_supported = mlx5e_get_wol_supported(mdev); 1567 u32 mlx5_wol_mode; 1568 1569 if (!wol_supported) 1570 return -EOPNOTSUPP; 1571 1572 if (wol->wolopts & ~wol_supported) 1573 return -EINVAL; 1574 1575 mlx5_wol_mode = mlx5e_reformat_wol_mode_linux_to_mlx5(wol->wolopts); 1576 1577 return mlx5_set_port_wol(mdev, mlx5_wol_mode); 1578 } 1579 1580 static int mlx5e_get_fecparam(struct net_device *netdev, 1581 struct ethtool_fecparam *fecparam) 1582 { 1583 struct mlx5e_priv *priv = netdev_priv(netdev); 1584 struct mlx5_core_dev *mdev = priv->mdev; 1585 u16 fec_configured; 1586 u32 fec_active; 1587 int err; 1588 1589 err = mlx5e_get_fec_mode(mdev, &fec_active, &fec_configured); 1590 1591 if (err) 1592 return err; 1593 1594 fecparam->active_fec = pplm2ethtool_fec((unsigned long)fec_active, 1595 sizeof(unsigned long) * BITS_PER_BYTE); 1596 1597 if (!fecparam->active_fec) 1598 return -EOPNOTSUPP; 1599 1600 fecparam->fec = pplm2ethtool_fec((unsigned long)fec_configured, 1601 sizeof(unsigned long) * BITS_PER_BYTE); 1602 1603 return 0; 1604 } 1605 1606 static int mlx5e_set_fecparam(struct net_device *netdev, 1607 struct ethtool_fecparam *fecparam) 1608 { 1609 struct mlx5e_priv *priv = netdev_priv(netdev); 1610 struct mlx5_core_dev *mdev = priv->mdev; 1611 u16 fec_policy = 0; 1612 int mode; 1613 int err; 1614 1615 if (bitmap_weight((unsigned long *)&fecparam->fec, 1616 ETHTOOL_FEC_LLRS_BIT + 1) > 1) 1617 return -EOPNOTSUPP; 1618 1619 for (mode = 0; mode < ARRAY_SIZE(pplm_fec_2_ethtool); mode++) { 1620 if (!(pplm_fec_2_ethtool[mode] & fecparam->fec)) 1621 continue; 1622 fec_policy |= (1 << mode); 1623 break; 1624 } 1625 1626 err = mlx5e_set_fec_mode(mdev, fec_policy); 1627 1628 if (err) 1629 return err; 1630 1631 mlx5_toggle_port_link(mdev); 1632 1633 return 0; 1634 } 1635 1636 static u32 mlx5e_get_msglevel(struct net_device *dev) 1637 { 1638 return ((struct mlx5e_priv *)netdev_priv(dev))->msglevel; 1639 } 1640 1641 static void mlx5e_set_msglevel(struct net_device *dev, u32 val) 1642 { 1643 ((struct mlx5e_priv *)netdev_priv(dev))->msglevel = val; 1644 } 1645 1646 static int mlx5e_set_phys_id(struct net_device *dev, 1647 enum ethtool_phys_id_state state) 1648 { 1649 struct mlx5e_priv *priv = netdev_priv(dev); 1650 struct mlx5_core_dev *mdev = priv->mdev; 1651 u16 beacon_duration; 1652 1653 if (!MLX5_CAP_GEN(mdev, beacon_led)) 1654 return -EOPNOTSUPP; 1655 1656 switch (state) { 1657 case ETHTOOL_ID_ACTIVE: 1658 beacon_duration = MLX5_BEACON_DURATION_INF; 1659 break; 1660 case ETHTOOL_ID_INACTIVE: 1661 beacon_duration = MLX5_BEACON_DURATION_OFF; 1662 break; 1663 default: 1664 return -EOPNOTSUPP; 1665 } 1666 1667 return mlx5_set_port_beacon(mdev, beacon_duration); 1668 } 1669 1670 static int mlx5e_get_module_info(struct net_device *netdev, 1671 struct ethtool_modinfo *modinfo) 1672 { 1673 struct mlx5e_priv *priv = netdev_priv(netdev); 1674 struct mlx5_core_dev *dev = priv->mdev; 1675 int size_read = 0; 1676 u8 data[4] = {0}; 1677 1678 size_read = mlx5_query_module_eeprom(dev, 0, 2, data); 1679 if (size_read < 2) 1680 return -EIO; 1681 1682 /* data[0] = identifier byte */ 1683 switch (data[0]) { 1684 case MLX5_MODULE_ID_QSFP: 1685 modinfo->type = ETH_MODULE_SFF_8436; 1686 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN; 1687 break; 1688 case MLX5_MODULE_ID_QSFP_PLUS: 1689 case MLX5_MODULE_ID_QSFP28: 1690 /* data[1] = revision id */ 1691 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) { 1692 modinfo->type = ETH_MODULE_SFF_8636; 1693 modinfo->eeprom_len = ETH_MODULE_SFF_8636_MAX_LEN; 1694 } else { 1695 modinfo->type = ETH_MODULE_SFF_8436; 1696 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN; 1697 } 1698 break; 1699 case MLX5_MODULE_ID_SFP: 1700 modinfo->type = ETH_MODULE_SFF_8472; 1701 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 1702 break; 1703 default: 1704 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n", 1705 __func__, data[0]); 1706 return -EINVAL; 1707 } 1708 1709 return 0; 1710 } 1711 1712 static int mlx5e_get_module_eeprom(struct net_device *netdev, 1713 struct ethtool_eeprom *ee, 1714 u8 *data) 1715 { 1716 struct mlx5e_priv *priv = netdev_priv(netdev); 1717 struct mlx5_core_dev *mdev = priv->mdev; 1718 int offset = ee->offset; 1719 int size_read; 1720 int i = 0; 1721 1722 if (!ee->len) 1723 return -EINVAL; 1724 1725 memset(data, 0, ee->len); 1726 1727 while (i < ee->len) { 1728 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i, 1729 data + i); 1730 1731 if (!size_read) 1732 /* Done reading */ 1733 return 0; 1734 1735 if (size_read < 0) { 1736 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n", 1737 __func__, size_read); 1738 return 0; 1739 } 1740 1741 i += size_read; 1742 offset += size_read; 1743 } 1744 1745 return 0; 1746 } 1747 1748 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv, 1749 struct ethtool_flash *flash) 1750 { 1751 struct mlx5_core_dev *mdev = priv->mdev; 1752 struct net_device *dev = priv->netdev; 1753 const struct firmware *fw; 1754 int err; 1755 1756 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS) 1757 return -EOPNOTSUPP; 1758 1759 err = request_firmware_direct(&fw, flash->data, &dev->dev); 1760 if (err) 1761 return err; 1762 1763 dev_hold(dev); 1764 rtnl_unlock(); 1765 1766 err = mlx5_firmware_flash(mdev, fw, NULL); 1767 release_firmware(fw); 1768 1769 rtnl_lock(); 1770 dev_put(dev); 1771 return err; 1772 } 1773 1774 static int mlx5e_flash_device(struct net_device *dev, 1775 struct ethtool_flash *flash) 1776 { 1777 struct mlx5e_priv *priv = netdev_priv(dev); 1778 1779 return mlx5e_ethtool_flash_device(priv, flash); 1780 } 1781 1782 static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable, 1783 bool is_rx_cq) 1784 { 1785 struct mlx5e_priv *priv = netdev_priv(netdev); 1786 struct mlx5_core_dev *mdev = priv->mdev; 1787 struct mlx5e_channels new_channels = {}; 1788 bool mode_changed; 1789 u8 cq_period_mode, current_cq_period_mode; 1790 1791 cq_period_mode = enable ? 1792 MLX5_CQ_PERIOD_MODE_START_FROM_CQE : 1793 MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 1794 current_cq_period_mode = is_rx_cq ? 1795 priv->channels.params.rx_cq_moderation.cq_period_mode : 1796 priv->channels.params.tx_cq_moderation.cq_period_mode; 1797 mode_changed = cq_period_mode != current_cq_period_mode; 1798 1799 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE && 1800 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe)) 1801 return -EOPNOTSUPP; 1802 1803 if (!mode_changed) 1804 return 0; 1805 1806 new_channels.params = priv->channels.params; 1807 if (is_rx_cq) 1808 mlx5e_set_rx_cq_mode_params(&new_channels.params, cq_period_mode); 1809 else 1810 mlx5e_set_tx_cq_mode_params(&new_channels.params, cq_period_mode); 1811 1812 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { 1813 priv->channels.params = new_channels.params; 1814 return 0; 1815 } 1816 1817 return mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL); 1818 } 1819 1820 static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable) 1821 { 1822 return set_pflag_cqe_based_moder(netdev, enable, false); 1823 } 1824 1825 static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable) 1826 { 1827 return set_pflag_cqe_based_moder(netdev, enable, true); 1828 } 1829 1830 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val) 1831 { 1832 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS); 1833 struct mlx5e_channels new_channels = {}; 1834 int err = 0; 1835 1836 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression)) 1837 return new_val ? -EOPNOTSUPP : 0; 1838 1839 if (curr_val == new_val) 1840 return 0; 1841 1842 new_channels.params = priv->channels.params; 1843 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val); 1844 1845 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { 1846 priv->channels.params = new_channels.params; 1847 return 0; 1848 } 1849 1850 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL); 1851 if (err) 1852 return err; 1853 1854 mlx5e_dbg(DRV, priv, "MLX5E: RxCqeCmprss was turned %s\n", 1855 MLX5E_GET_PFLAG(&priv->channels.params, 1856 MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF"); 1857 1858 return 0; 1859 } 1860 1861 static int set_pflag_rx_cqe_compress(struct net_device *netdev, 1862 bool enable) 1863 { 1864 struct mlx5e_priv *priv = netdev_priv(netdev); 1865 struct mlx5_core_dev *mdev = priv->mdev; 1866 1867 if (!MLX5_CAP_GEN(mdev, cqe_compression)) 1868 return -EOPNOTSUPP; 1869 1870 if (enable && priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE) { 1871 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n"); 1872 return -EINVAL; 1873 } 1874 1875 mlx5e_modify_rx_cqe_compression_locked(priv, enable); 1876 priv->channels.params.rx_cqe_compress_def = enable; 1877 1878 return 0; 1879 } 1880 1881 static int set_pflag_rx_striding_rq(struct net_device *netdev, bool enable) 1882 { 1883 struct mlx5e_priv *priv = netdev_priv(netdev); 1884 struct mlx5_core_dev *mdev = priv->mdev; 1885 struct mlx5e_channels new_channels = {}; 1886 1887 if (enable) { 1888 if (!mlx5e_check_fragmented_striding_rq_cap(mdev)) 1889 return -EOPNOTSUPP; 1890 if (!mlx5e_striding_rq_possible(mdev, &priv->channels.params)) 1891 return -EINVAL; 1892 } else if (priv->channels.params.lro_en) { 1893 netdev_warn(netdev, "Can't set legacy RQ with LRO, disable LRO first\n"); 1894 return -EINVAL; 1895 } 1896 1897 new_channels.params = priv->channels.params; 1898 1899 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_STRIDING_RQ, enable); 1900 mlx5e_set_rq_type(mdev, &new_channels.params); 1901 1902 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { 1903 priv->channels.params = new_channels.params; 1904 return 0; 1905 } 1906 1907 return mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL); 1908 } 1909 1910 static int set_pflag_rx_no_csum_complete(struct net_device *netdev, bool enable) 1911 { 1912 struct mlx5e_priv *priv = netdev_priv(netdev); 1913 struct mlx5e_channels *channels = &priv->channels; 1914 struct mlx5e_channel *c; 1915 int i; 1916 1917 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || 1918 priv->channels.params.xdp_prog) 1919 return 0; 1920 1921 for (i = 0; i < channels->num; i++) { 1922 c = channels->c[i]; 1923 if (enable) 1924 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state); 1925 else 1926 __clear_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state); 1927 } 1928 1929 return 0; 1930 } 1931 1932 static int set_pflag_tx_mpwqe_common(struct net_device *netdev, u32 flag, bool enable) 1933 { 1934 struct mlx5e_priv *priv = netdev_priv(netdev); 1935 struct mlx5_core_dev *mdev = priv->mdev; 1936 struct mlx5e_channels new_channels = {}; 1937 int err; 1938 1939 if (enable && !MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1940 return -EOPNOTSUPP; 1941 1942 new_channels.params = priv->channels.params; 1943 1944 MLX5E_SET_PFLAG(&new_channels.params, flag, enable); 1945 1946 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { 1947 priv->channels.params = new_channels.params; 1948 return 0; 1949 } 1950 1951 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL); 1952 return err; 1953 } 1954 1955 static int set_pflag_xdp_tx_mpwqe(struct net_device *netdev, bool enable) 1956 { 1957 return set_pflag_tx_mpwqe_common(netdev, MLX5E_PFLAG_XDP_TX_MPWQE, enable); 1958 } 1959 1960 static int set_pflag_skb_tx_mpwqe(struct net_device *netdev, bool enable) 1961 { 1962 return set_pflag_tx_mpwqe_common(netdev, MLX5E_PFLAG_SKB_TX_MPWQE, enable); 1963 } 1964 1965 static int set_pflag_tx_port_ts(struct net_device *netdev, bool enable) 1966 { 1967 struct mlx5e_priv *priv = netdev_priv(netdev); 1968 struct mlx5_core_dev *mdev = priv->mdev; 1969 struct mlx5e_channels new_channels = {}; 1970 int err; 1971 1972 if (!MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn)) 1973 return -EOPNOTSUPP; 1974 1975 new_channels.params = priv->channels.params; 1976 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_TX_PORT_TS, enable); 1977 /* No need to verify SQ stop room as 1978 * ptpsq.txqsq.stop_room <= generic_sq->stop_room, and both 1979 * has the same log_sq_size. 1980 */ 1981 1982 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { 1983 priv->channels.params = new_channels.params; 1984 err = mlx5e_num_channels_changed(priv); 1985 goto out; 1986 } 1987 1988 err = mlx5e_safe_switch_channels(priv, &new_channels, 1989 mlx5e_num_channels_changed_ctx, NULL); 1990 out: 1991 if (!err) 1992 priv->port_ptp_opened = true; 1993 1994 return err; 1995 } 1996 1997 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS] = { 1998 { "rx_cqe_moder", set_pflag_rx_cqe_based_moder }, 1999 { "tx_cqe_moder", set_pflag_tx_cqe_based_moder }, 2000 { "rx_cqe_compress", set_pflag_rx_cqe_compress }, 2001 { "rx_striding_rq", set_pflag_rx_striding_rq }, 2002 { "rx_no_csum_complete", set_pflag_rx_no_csum_complete }, 2003 { "xdp_tx_mpwqe", set_pflag_xdp_tx_mpwqe }, 2004 { "skb_tx_mpwqe", set_pflag_skb_tx_mpwqe }, 2005 { "tx_port_ts", set_pflag_tx_port_ts }, 2006 }; 2007 2008 static int mlx5e_handle_pflag(struct net_device *netdev, 2009 u32 wanted_flags, 2010 enum mlx5e_priv_flag flag) 2011 { 2012 struct mlx5e_priv *priv = netdev_priv(netdev); 2013 bool enable = !!(wanted_flags & BIT(flag)); 2014 u32 changes = wanted_flags ^ priv->channels.params.pflags; 2015 int err; 2016 2017 if (!(changes & BIT(flag))) 2018 return 0; 2019 2020 err = mlx5e_priv_flags[flag].handler(netdev, enable); 2021 if (err) { 2022 netdev_err(netdev, "%s private flag '%s' failed err %d\n", 2023 enable ? "Enable" : "Disable", mlx5e_priv_flags[flag].name, err); 2024 return err; 2025 } 2026 2027 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable); 2028 return 0; 2029 } 2030 2031 static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags) 2032 { 2033 struct mlx5e_priv *priv = netdev_priv(netdev); 2034 enum mlx5e_priv_flag pflag; 2035 int err; 2036 2037 mutex_lock(&priv->state_lock); 2038 2039 for (pflag = 0; pflag < MLX5E_NUM_PFLAGS; pflag++) { 2040 err = mlx5e_handle_pflag(netdev, pflags, pflag); 2041 if (err) 2042 break; 2043 } 2044 2045 mutex_unlock(&priv->state_lock); 2046 2047 /* Need to fix some features.. */ 2048 netdev_update_features(netdev); 2049 2050 return err; 2051 } 2052 2053 static u32 mlx5e_get_priv_flags(struct net_device *netdev) 2054 { 2055 struct mlx5e_priv *priv = netdev_priv(netdev); 2056 2057 return priv->channels.params.pflags; 2058 } 2059 2060 int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, 2061 u32 *rule_locs) 2062 { 2063 struct mlx5e_priv *priv = netdev_priv(dev); 2064 2065 /* ETHTOOL_GRXRINGS is needed by ethtool -x which is not part 2066 * of rxnfc. We keep this logic out of mlx5e_ethtool_get_rxnfc, 2067 * to avoid breaking "ethtool -x" when mlx5e_ethtool_get_rxnfc 2068 * is compiled out via CONFIG_MLX5_EN_RXNFC=n. 2069 */ 2070 if (info->cmd == ETHTOOL_GRXRINGS) { 2071 info->data = priv->channels.params.num_channels; 2072 return 0; 2073 } 2074 2075 return mlx5e_ethtool_get_rxnfc(dev, info, rule_locs); 2076 } 2077 2078 int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2079 { 2080 return mlx5e_ethtool_set_rxnfc(dev, cmd); 2081 } 2082 2083 const struct ethtool_ops mlx5e_ethtool_ops = { 2084 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2085 ETHTOOL_COALESCE_MAX_FRAMES | 2086 ETHTOOL_COALESCE_USE_ADAPTIVE, 2087 .get_drvinfo = mlx5e_get_drvinfo, 2088 .get_link = ethtool_op_get_link, 2089 .get_strings = mlx5e_get_strings, 2090 .get_sset_count = mlx5e_get_sset_count, 2091 .get_ethtool_stats = mlx5e_get_ethtool_stats, 2092 .get_ringparam = mlx5e_get_ringparam, 2093 .set_ringparam = mlx5e_set_ringparam, 2094 .get_channels = mlx5e_get_channels, 2095 .set_channels = mlx5e_set_channels, 2096 .get_coalesce = mlx5e_get_coalesce, 2097 .set_coalesce = mlx5e_set_coalesce, 2098 .get_link_ksettings = mlx5e_get_link_ksettings, 2099 .set_link_ksettings = mlx5e_set_link_ksettings, 2100 .get_rxfh_key_size = mlx5e_get_rxfh_key_size, 2101 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size, 2102 .get_rxfh = mlx5e_get_rxfh, 2103 .set_rxfh = mlx5e_set_rxfh, 2104 .get_rxnfc = mlx5e_get_rxnfc, 2105 .set_rxnfc = mlx5e_set_rxnfc, 2106 .get_tunable = mlx5e_get_tunable, 2107 .set_tunable = mlx5e_set_tunable, 2108 .get_pause_stats = mlx5e_get_pause_stats, 2109 .get_pauseparam = mlx5e_get_pauseparam, 2110 .set_pauseparam = mlx5e_set_pauseparam, 2111 .get_ts_info = mlx5e_get_ts_info, 2112 .set_phys_id = mlx5e_set_phys_id, 2113 .get_wol = mlx5e_get_wol, 2114 .set_wol = mlx5e_set_wol, 2115 .get_module_info = mlx5e_get_module_info, 2116 .get_module_eeprom = mlx5e_get_module_eeprom, 2117 .flash_device = mlx5e_flash_device, 2118 .get_priv_flags = mlx5e_get_priv_flags, 2119 .set_priv_flags = mlx5e_set_priv_flags, 2120 .self_test = mlx5e_self_test, 2121 .get_msglevel = mlx5e_get_msglevel, 2122 .set_msglevel = mlx5e_set_msglevel, 2123 .get_fecparam = mlx5e_get_fecparam, 2124 .set_fecparam = mlx5e_set_fecparam, 2125 }; 2126