1 /* 2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/ethtool_netlink.h> 34 35 #include "en.h" 36 #include "en/port.h" 37 #include "en/params.h" 38 #include "en/xsk/pool.h" 39 #include "en/ptp.h" 40 #include "lib/clock.h" 41 #include "en/fs_ethtool.h" 42 43 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv, 44 struct ethtool_drvinfo *drvinfo) 45 { 46 struct mlx5_core_dev *mdev = priv->mdev; 47 48 strscpy(drvinfo->driver, KBUILD_MODNAME, sizeof(drvinfo->driver)); 49 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), 50 "%d.%d.%04d (%.16s)", 51 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev), 52 mdev->board_id); 53 strscpy(drvinfo->bus_info, dev_name(mdev->device), 54 sizeof(drvinfo->bus_info)); 55 } 56 57 static void mlx5e_get_drvinfo(struct net_device *dev, 58 struct ethtool_drvinfo *drvinfo) 59 { 60 struct mlx5e_priv *priv = netdev_priv(dev); 61 62 mlx5e_ethtool_get_drvinfo(priv, drvinfo); 63 } 64 65 struct ptys2ethtool_config { 66 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); 67 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised); 68 }; 69 70 static 71 struct ptys2ethtool_config ptys2legacy_ethtool_table[MLX5E_LINK_MODES_NUMBER]; 72 static 73 struct ptys2ethtool_config ptys2ext_ethtool_table[MLX5E_EXT_LINK_MODES_NUMBER]; 74 75 #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, table, ...) \ 76 ({ \ 77 struct ptys2ethtool_config *cfg; \ 78 const unsigned int modes[] = { __VA_ARGS__ }; \ 79 unsigned int i, bit, idx; \ 80 cfg = &ptys2##table##_ethtool_table[reg_]; \ 81 bitmap_zero(cfg->supported, \ 82 __ETHTOOL_LINK_MODE_MASK_NBITS); \ 83 bitmap_zero(cfg->advertised, \ 84 __ETHTOOL_LINK_MODE_MASK_NBITS); \ 85 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \ 86 bit = modes[i] % 64; \ 87 idx = modes[i] / 64; \ 88 __set_bit(bit, &cfg->supported[idx]); \ 89 __set_bit(bit, &cfg->advertised[idx]); \ 90 } \ 91 }) 92 93 void mlx5e_build_ptys2ethtool_map(void) 94 { 95 memset(ptys2legacy_ethtool_table, 0, sizeof(ptys2legacy_ethtool_table)); 96 memset(ptys2ext_ethtool_table, 0, sizeof(ptys2ext_ethtool_table)); 97 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, legacy, 98 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT); 99 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, legacy, 100 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT); 101 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, legacy, 102 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT); 103 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, legacy, 104 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT); 105 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, legacy, 106 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); 107 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, legacy, 108 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT); 109 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, legacy, 110 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT); 111 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, legacy, 112 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT); 113 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, legacy, 114 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT); 115 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, legacy, 116 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); 117 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, legacy, 118 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); 119 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, legacy, 120 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); 121 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, legacy, 122 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT); 123 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, legacy, 124 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT); 125 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, legacy, 126 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT); 127 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, legacy, 128 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT); 129 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, legacy, 130 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT); 131 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, legacy, 132 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT); 133 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, legacy, 134 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT); 135 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, legacy, 136 ETHTOOL_LINK_MODE_10000baseT_Full_BIT); 137 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, legacy, 138 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT); 139 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, legacy, 140 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT); 141 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, legacy, 142 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT); 143 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, legacy, 144 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT); 145 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, legacy, 146 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT); 147 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_SGMII_100M, ext, 148 ETHTOOL_LINK_MODE_100baseT_Full_BIT); 149 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_X_SGMII, ext, 150 ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 151 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 152 ETHTOOL_LINK_MODE_1000baseX_Full_BIT); 153 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_5GBASE_R, ext, 154 ETHTOOL_LINK_MODE_5000baseT_Full_BIT); 155 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_XFI_XAUI_1, ext, 156 ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 157 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 158 ETHTOOL_LINK_MODE_10000baseR_FEC_BIT, 159 ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, 160 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 161 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 162 ETHTOOL_LINK_MODE_10000baseER_Full_BIT); 163 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_XLAUI_4_XLPPI_4, ext, 164 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 165 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 166 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 167 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT); 168 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GAUI_1_25GBASE_CR_KR, ext, 169 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 170 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 171 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT); 172 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2, 173 ext, 174 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 175 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 176 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT); 177 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR, ext, 178 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, 179 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, 180 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, 181 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 182 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT); 183 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_CAUI_4_100GBASE_CR4_KR4, ext, 184 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 185 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 186 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 187 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT); 188 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_2_100GBASE_CR2_KR2, ext, 189 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, 190 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, 191 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, 192 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, 193 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT); 194 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_4_200GBASE_CR4_KR4, ext, 195 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT, 196 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT, 197 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT, 198 ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT, 199 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT); 200 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_1_100GBASE_CR_KR, ext, 201 ETHTOOL_LINK_MODE_100000baseKR_Full_BIT, 202 ETHTOOL_LINK_MODE_100000baseSR_Full_BIT, 203 ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT, 204 ETHTOOL_LINK_MODE_100000baseDR_Full_BIT, 205 ETHTOOL_LINK_MODE_100000baseCR_Full_BIT); 206 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_2_200GBASE_CR2_KR2, ext, 207 ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT, 208 ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT, 209 ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT, 210 ETHTOOL_LINK_MODE_200000baseDR2_Full_BIT, 211 ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT); 212 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_4_400GBASE_CR4_KR4, ext, 213 ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT, 214 ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT, 215 ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT, 216 ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT, 217 ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT); 218 } 219 220 static void mlx5e_ethtool_get_speed_arr(struct mlx5_core_dev *mdev, 221 struct ptys2ethtool_config **arr, 222 u32 *size) 223 { 224 bool ext = mlx5e_ptys_ext_supported(mdev); 225 226 *arr = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table; 227 *size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) : 228 ARRAY_SIZE(ptys2legacy_ethtool_table); 229 } 230 231 typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable); 232 233 struct pflag_desc { 234 char name[ETH_GSTRING_LEN]; 235 mlx5e_pflag_handler handler; 236 }; 237 238 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS]; 239 240 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset) 241 { 242 switch (sset) { 243 case ETH_SS_STATS: 244 return mlx5e_stats_total_num(priv); 245 case ETH_SS_PRIV_FLAGS: 246 return MLX5E_NUM_PFLAGS; 247 case ETH_SS_TEST: 248 return mlx5e_self_test_num(priv); 249 default: 250 return -EOPNOTSUPP; 251 } 252 } 253 254 static int mlx5e_get_sset_count(struct net_device *dev, int sset) 255 { 256 struct mlx5e_priv *priv = netdev_priv(dev); 257 258 return mlx5e_ethtool_get_sset_count(priv, sset); 259 } 260 261 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, u32 stringset, u8 *data) 262 { 263 int i; 264 265 switch (stringset) { 266 case ETH_SS_PRIV_FLAGS: 267 for (i = 0; i < MLX5E_NUM_PFLAGS; i++) 268 strcpy(data + i * ETH_GSTRING_LEN, 269 mlx5e_priv_flags[i].name); 270 break; 271 272 case ETH_SS_TEST: 273 mlx5e_self_test_fill_strings(priv, data); 274 break; 275 276 case ETH_SS_STATS: 277 mlx5e_stats_fill_strings(priv, data); 278 break; 279 } 280 } 281 282 static void mlx5e_get_strings(struct net_device *dev, u32 stringset, u8 *data) 283 { 284 struct mlx5e_priv *priv = netdev_priv(dev); 285 286 mlx5e_ethtool_get_strings(priv, stringset, data); 287 } 288 289 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv, 290 struct ethtool_stats *stats, u64 *data) 291 { 292 int idx = 0; 293 294 mutex_lock(&priv->state_lock); 295 mlx5e_stats_update(priv); 296 mutex_unlock(&priv->state_lock); 297 298 mlx5e_stats_fill(priv, data, idx); 299 } 300 301 static void mlx5e_get_ethtool_stats(struct net_device *dev, 302 struct ethtool_stats *stats, 303 u64 *data) 304 { 305 struct mlx5e_priv *priv = netdev_priv(dev); 306 307 mlx5e_ethtool_get_ethtool_stats(priv, stats, data); 308 } 309 310 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv, 311 struct ethtool_ringparam *param, 312 struct kernel_ethtool_ringparam *kernel_param) 313 { 314 /* Limitation for regular RQ. XSK RQ may clamp the queue length in 315 * mlx5e_mpwqe_get_log_rq_size. 316 */ 317 u8 max_log_mpwrq_pkts = mlx5e_mpwrq_max_log_rq_pkts(priv->mdev, 318 PAGE_SHIFT, 319 MLX5E_MPWRQ_UMR_MODE_ALIGNED); 320 321 param->rx_max_pending = 1 << min_t(u8, MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE, 322 max_log_mpwrq_pkts); 323 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE; 324 param->rx_pending = 1 << priv->channels.params.log_rq_mtu_frames; 325 param->tx_pending = 1 << priv->channels.params.log_sq_size; 326 327 kernel_param->tcp_data_split = 328 (priv->channels.params.packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) ? 329 ETHTOOL_TCP_DATA_SPLIT_ENABLED : 330 ETHTOOL_TCP_DATA_SPLIT_DISABLED; 331 } 332 333 static void mlx5e_get_ringparam(struct net_device *dev, 334 struct ethtool_ringparam *param, 335 struct kernel_ethtool_ringparam *kernel_param, 336 struct netlink_ext_ack *extack) 337 { 338 struct mlx5e_priv *priv = netdev_priv(dev); 339 340 mlx5e_ethtool_get_ringparam(priv, param, kernel_param); 341 } 342 343 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, 344 struct ethtool_ringparam *param) 345 { 346 struct mlx5e_params new_params; 347 u8 log_rq_size; 348 u8 log_sq_size; 349 int err = 0; 350 351 if (param->rx_jumbo_pending) { 352 netdev_info(priv->netdev, "%s: rx_jumbo_pending not supported\n", 353 __func__); 354 return -EINVAL; 355 } 356 if (param->rx_mini_pending) { 357 netdev_info(priv->netdev, "%s: rx_mini_pending not supported\n", 358 __func__); 359 return -EINVAL; 360 } 361 362 if (param->rx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) { 363 netdev_info(priv->netdev, "%s: rx_pending (%d) < min (%d)\n", 364 __func__, param->rx_pending, 365 1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE); 366 return -EINVAL; 367 } 368 369 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) { 370 netdev_info(priv->netdev, "%s: tx_pending (%d) < min (%d)\n", 371 __func__, param->tx_pending, 372 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE); 373 return -EINVAL; 374 } 375 376 log_rq_size = order_base_2(param->rx_pending); 377 log_sq_size = order_base_2(param->tx_pending); 378 379 if (log_rq_size == priv->channels.params.log_rq_mtu_frames && 380 log_sq_size == priv->channels.params.log_sq_size) 381 return 0; 382 383 mutex_lock(&priv->state_lock); 384 385 new_params = priv->channels.params; 386 new_params.log_rq_mtu_frames = log_rq_size; 387 new_params.log_sq_size = log_sq_size; 388 389 err = mlx5e_validate_params(priv->mdev, &new_params); 390 if (err) 391 goto unlock; 392 393 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true); 394 395 unlock: 396 mutex_unlock(&priv->state_lock); 397 398 return err; 399 } 400 401 static int mlx5e_set_ringparam(struct net_device *dev, 402 struct ethtool_ringparam *param, 403 struct kernel_ethtool_ringparam *kernel_param, 404 struct netlink_ext_ack *extack) 405 { 406 struct mlx5e_priv *priv = netdev_priv(dev); 407 408 return mlx5e_ethtool_set_ringparam(priv, param); 409 } 410 411 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv, 412 struct ethtool_channels *ch) 413 { 414 mutex_lock(&priv->state_lock); 415 416 ch->max_combined = priv->max_nch; 417 ch->combined_count = priv->channels.params.num_channels; 418 if (priv->xsk.refcnt) { 419 /* The upper half are XSK queues. */ 420 ch->max_combined *= 2; 421 ch->combined_count *= 2; 422 } 423 424 mutex_unlock(&priv->state_lock); 425 } 426 427 static void mlx5e_get_channels(struct net_device *dev, 428 struct ethtool_channels *ch) 429 { 430 struct mlx5e_priv *priv = netdev_priv(dev); 431 432 mlx5e_ethtool_get_channels(priv, ch); 433 } 434 435 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, 436 struct ethtool_channels *ch) 437 { 438 struct mlx5e_params *cur_params = &priv->channels.params; 439 unsigned int count = ch->combined_count; 440 struct mlx5e_params new_params; 441 bool arfs_enabled; 442 int rss_cnt; 443 bool opened; 444 int err = 0; 445 446 if (!count) { 447 netdev_info(priv->netdev, "%s: combined_count=0 not supported\n", 448 __func__); 449 return -EINVAL; 450 } 451 452 if (cur_params->num_channels == count) 453 return 0; 454 455 mutex_lock(&priv->state_lock); 456 457 /* Don't allow changing the number of channels if there is an active 458 * XSK, because the numeration of the XSK and regular RQs will change. 459 */ 460 if (priv->xsk.refcnt) { 461 err = -EINVAL; 462 netdev_err(priv->netdev, "%s: AF_XDP is active, cannot change the number of channels\n", 463 __func__); 464 goto out; 465 } 466 467 /* Don't allow changing the number of channels if HTB offload is active, 468 * because the numeration of the QoS SQs will change, while per-queue 469 * qdiscs are attached. 470 */ 471 if (mlx5e_selq_is_htb_enabled(&priv->selq)) { 472 err = -EINVAL; 473 netdev_err(priv->netdev, "%s: HTB offload is active, cannot change the number of channels\n", 474 __func__); 475 goto out; 476 } 477 478 /* Don't allow changing the number of channels if non-default RSS contexts exist, 479 * the kernel doesn't protect against set_channels operations that break them. 480 */ 481 rss_cnt = mlx5e_rx_res_rss_cnt(priv->rx_res) - 1; 482 if (rss_cnt) { 483 err = -EINVAL; 484 netdev_err(priv->netdev, "%s: Non-default RSS contexts exist (%d), cannot change the number of channels\n", 485 __func__, rss_cnt); 486 goto out; 487 } 488 489 /* Don't allow changing the number of channels if MQPRIO mode channel offload is active, 490 * because it defines a partition over the channels queues. 491 */ 492 if (cur_params->mqprio.mode == TC_MQPRIO_MODE_CHANNEL) { 493 err = -EINVAL; 494 netdev_err(priv->netdev, "%s: MQPRIO mode channel offload is active, cannot change the number of channels\n", 495 __func__); 496 goto out; 497 } 498 499 new_params = *cur_params; 500 new_params.num_channels = count; 501 502 opened = test_bit(MLX5E_STATE_OPENED, &priv->state); 503 504 arfs_enabled = opened && (priv->netdev->features & NETIF_F_NTUPLE); 505 if (arfs_enabled) 506 mlx5e_arfs_disable(priv->fs); 507 508 /* Switch to new channels, set new parameters and close old ones */ 509 err = mlx5e_safe_switch_params(priv, &new_params, 510 mlx5e_num_channels_changed_ctx, NULL, true); 511 512 if (arfs_enabled) { 513 int err2 = mlx5e_arfs_enable(priv->fs); 514 515 if (err2) 516 netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n", 517 __func__, err2); 518 } 519 520 out: 521 mutex_unlock(&priv->state_lock); 522 523 return err; 524 } 525 526 static int mlx5e_set_channels(struct net_device *dev, 527 struct ethtool_channels *ch) 528 { 529 struct mlx5e_priv *priv = netdev_priv(dev); 530 531 return mlx5e_ethtool_set_channels(priv, ch); 532 } 533 534 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv, 535 struct ethtool_coalesce *coal, 536 struct kernel_ethtool_coalesce *kernel_coal) 537 { 538 struct dim_cq_moder *rx_moder, *tx_moder; 539 540 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation)) 541 return -EOPNOTSUPP; 542 543 rx_moder = &priv->channels.params.rx_cq_moderation; 544 coal->rx_coalesce_usecs = rx_moder->usec; 545 coal->rx_max_coalesced_frames = rx_moder->pkts; 546 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_dim_enabled; 547 548 tx_moder = &priv->channels.params.tx_cq_moderation; 549 coal->tx_coalesce_usecs = tx_moder->usec; 550 coal->tx_max_coalesced_frames = tx_moder->pkts; 551 coal->use_adaptive_tx_coalesce = priv->channels.params.tx_dim_enabled; 552 553 kernel_coal->use_cqe_mode_rx = 554 MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_BASED_MODER); 555 kernel_coal->use_cqe_mode_tx = 556 MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_TX_CQE_BASED_MODER); 557 558 return 0; 559 } 560 561 static int mlx5e_get_coalesce(struct net_device *netdev, 562 struct ethtool_coalesce *coal, 563 struct kernel_ethtool_coalesce *kernel_coal, 564 struct netlink_ext_ack *extack) 565 { 566 struct mlx5e_priv *priv = netdev_priv(netdev); 567 568 return mlx5e_ethtool_get_coalesce(priv, coal, kernel_coal); 569 } 570 571 #define MLX5E_MAX_COAL_TIME MLX5_MAX_CQ_PERIOD 572 #define MLX5E_MAX_COAL_FRAMES MLX5_MAX_CQ_COUNT 573 574 static void 575 mlx5e_set_priv_channels_tx_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal) 576 { 577 struct mlx5_core_dev *mdev = priv->mdev; 578 int tc; 579 int i; 580 581 for (i = 0; i < priv->channels.num; ++i) { 582 struct mlx5e_channel *c = priv->channels.c[i]; 583 584 for (tc = 0; tc < c->num_tc; tc++) { 585 mlx5_core_modify_cq_moderation(mdev, 586 &c->sq[tc].cq.mcq, 587 coal->tx_coalesce_usecs, 588 coal->tx_max_coalesced_frames); 589 } 590 } 591 } 592 593 static void 594 mlx5e_set_priv_channels_rx_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal) 595 { 596 struct mlx5_core_dev *mdev = priv->mdev; 597 int i; 598 599 for (i = 0; i < priv->channels.num; ++i) { 600 struct mlx5e_channel *c = priv->channels.c[i]; 601 602 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq, 603 coal->rx_coalesce_usecs, 604 coal->rx_max_coalesced_frames); 605 } 606 } 607 608 /* convert a boolean value of cq_mode to mlx5 period mode 609 * true : MLX5_CQ_PERIOD_MODE_START_FROM_CQE 610 * false : MLX5_CQ_PERIOD_MODE_START_FROM_EQE 611 */ 612 static int cqe_mode_to_period_mode(bool val) 613 { 614 return val ? MLX5_CQ_PERIOD_MODE_START_FROM_CQE : MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 615 } 616 617 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, 618 struct ethtool_coalesce *coal, 619 struct kernel_ethtool_coalesce *kernel_coal, 620 struct netlink_ext_ack *extack) 621 { 622 struct dim_cq_moder *rx_moder, *tx_moder; 623 struct mlx5_core_dev *mdev = priv->mdev; 624 struct mlx5e_params new_params; 625 bool reset_rx, reset_tx; 626 bool reset = true; 627 u8 cq_period_mode; 628 int err = 0; 629 630 if (!MLX5_CAP_GEN(mdev, cq_moderation)) 631 return -EOPNOTSUPP; 632 633 if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME || 634 coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) { 635 netdev_info(priv->netdev, "%s: maximum coalesce time supported is %lu usecs\n", 636 __func__, MLX5E_MAX_COAL_TIME); 637 return -ERANGE; 638 } 639 640 if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES || 641 coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) { 642 netdev_info(priv->netdev, "%s: maximum coalesced frames supported is %lu\n", 643 __func__, MLX5E_MAX_COAL_FRAMES); 644 return -ERANGE; 645 } 646 647 if ((kernel_coal->use_cqe_mode_rx || kernel_coal->use_cqe_mode_tx) && 648 !MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) { 649 NL_SET_ERR_MSG_MOD(extack, "cqe_mode_rx/tx is not supported on this device"); 650 return -EOPNOTSUPP; 651 } 652 653 mutex_lock(&priv->state_lock); 654 new_params = priv->channels.params; 655 656 rx_moder = &new_params.rx_cq_moderation; 657 rx_moder->usec = coal->rx_coalesce_usecs; 658 rx_moder->pkts = coal->rx_max_coalesced_frames; 659 new_params.rx_dim_enabled = !!coal->use_adaptive_rx_coalesce; 660 661 tx_moder = &new_params.tx_cq_moderation; 662 tx_moder->usec = coal->tx_coalesce_usecs; 663 tx_moder->pkts = coal->tx_max_coalesced_frames; 664 new_params.tx_dim_enabled = !!coal->use_adaptive_tx_coalesce; 665 666 reset_rx = !!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_dim_enabled; 667 reset_tx = !!coal->use_adaptive_tx_coalesce != priv->channels.params.tx_dim_enabled; 668 669 cq_period_mode = cqe_mode_to_period_mode(kernel_coal->use_cqe_mode_rx); 670 if (cq_period_mode != rx_moder->cq_period_mode) { 671 mlx5e_set_rx_cq_mode_params(&new_params, cq_period_mode); 672 reset_rx = true; 673 } 674 675 cq_period_mode = cqe_mode_to_period_mode(kernel_coal->use_cqe_mode_tx); 676 if (cq_period_mode != tx_moder->cq_period_mode) { 677 mlx5e_set_tx_cq_mode_params(&new_params, cq_period_mode); 678 reset_tx = true; 679 } 680 681 if (reset_rx) { 682 u8 mode = MLX5E_GET_PFLAG(&new_params, 683 MLX5E_PFLAG_RX_CQE_BASED_MODER); 684 685 mlx5e_reset_rx_moderation(&new_params, mode); 686 } 687 if (reset_tx) { 688 u8 mode = MLX5E_GET_PFLAG(&new_params, 689 MLX5E_PFLAG_TX_CQE_BASED_MODER); 690 691 mlx5e_reset_tx_moderation(&new_params, mode); 692 } 693 694 /* If DIM state hasn't changed, it's possible to modify interrupt 695 * moderation parameters on the fly, even if the channels are open. 696 */ 697 if (!reset_rx && !reset_tx && test_bit(MLX5E_STATE_OPENED, &priv->state)) { 698 if (!coal->use_adaptive_rx_coalesce) 699 mlx5e_set_priv_channels_rx_coalesce(priv, coal); 700 if (!coal->use_adaptive_tx_coalesce) 701 mlx5e_set_priv_channels_tx_coalesce(priv, coal); 702 reset = false; 703 } 704 705 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, reset); 706 707 mutex_unlock(&priv->state_lock); 708 return err; 709 } 710 711 static int mlx5e_set_coalesce(struct net_device *netdev, 712 struct ethtool_coalesce *coal, 713 struct kernel_ethtool_coalesce *kernel_coal, 714 struct netlink_ext_ack *extack) 715 { 716 struct mlx5e_priv *priv = netdev_priv(netdev); 717 718 return mlx5e_ethtool_set_coalesce(priv, coal, kernel_coal, extack); 719 } 720 721 static void ptys2ethtool_supported_link(struct mlx5_core_dev *mdev, 722 unsigned long *supported_modes, 723 u32 eth_proto_cap) 724 { 725 unsigned long proto_cap = eth_proto_cap; 726 struct ptys2ethtool_config *table; 727 u32 max_size; 728 int proto; 729 730 mlx5e_ethtool_get_speed_arr(mdev, &table, &max_size); 731 for_each_set_bit(proto, &proto_cap, max_size) 732 bitmap_or(supported_modes, supported_modes, 733 table[proto].supported, 734 __ETHTOOL_LINK_MODE_MASK_NBITS); 735 } 736 737 static void ptys2ethtool_adver_link(unsigned long *advertising_modes, 738 u32 eth_proto_cap, bool ext) 739 { 740 unsigned long proto_cap = eth_proto_cap; 741 struct ptys2ethtool_config *table; 742 u32 max_size; 743 int proto; 744 745 table = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table; 746 max_size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) : 747 ARRAY_SIZE(ptys2legacy_ethtool_table); 748 749 for_each_set_bit(proto, &proto_cap, max_size) 750 bitmap_or(advertising_modes, advertising_modes, 751 table[proto].advertised, 752 __ETHTOOL_LINK_MODE_MASK_NBITS); 753 } 754 755 static const u32 pplm_fec_2_ethtool[] = { 756 [MLX5E_FEC_NOFEC] = ETHTOOL_FEC_OFF, 757 [MLX5E_FEC_FIRECODE] = ETHTOOL_FEC_BASER, 758 [MLX5E_FEC_RS_528_514] = ETHTOOL_FEC_RS, 759 [MLX5E_FEC_RS_544_514] = ETHTOOL_FEC_RS, 760 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_FEC_LLRS, 761 }; 762 763 static u32 pplm2ethtool_fec(u_long fec_mode, unsigned long size) 764 { 765 int mode = 0; 766 767 if (!fec_mode) 768 return ETHTOOL_FEC_AUTO; 769 770 mode = find_first_bit(&fec_mode, size); 771 772 if (mode < ARRAY_SIZE(pplm_fec_2_ethtool)) 773 return pplm_fec_2_ethtool[mode]; 774 775 return 0; 776 } 777 778 #define MLX5E_ADVERTISE_SUPPORTED_FEC(mlx5_fec, ethtool_fec) \ 779 do { \ 780 if (mlx5e_fec_in_caps(dev, 1 << (mlx5_fec))) \ 781 __set_bit(ethtool_fec, \ 782 link_ksettings->link_modes.supported);\ 783 } while (0) 784 785 static const u32 pplm_fec_2_ethtool_linkmodes[] = { 786 [MLX5E_FEC_NOFEC] = ETHTOOL_LINK_MODE_FEC_NONE_BIT, 787 [MLX5E_FEC_FIRECODE] = ETHTOOL_LINK_MODE_FEC_BASER_BIT, 788 [MLX5E_FEC_RS_528_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT, 789 [MLX5E_FEC_RS_544_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT, 790 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 791 }; 792 793 static int get_fec_supported_advertised(struct mlx5_core_dev *dev, 794 struct ethtool_link_ksettings *link_ksettings) 795 { 796 unsigned long active_fec_long; 797 u32 active_fec; 798 u32 bitn; 799 int err; 800 801 err = mlx5e_get_fec_mode(dev, &active_fec, NULL); 802 if (err) 803 return (err == -EOPNOTSUPP) ? 0 : err; 804 805 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_NOFEC, 806 ETHTOOL_LINK_MODE_FEC_NONE_BIT); 807 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_FIRECODE, 808 ETHTOOL_LINK_MODE_FEC_BASER_BIT); 809 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_RS_528_514, 810 ETHTOOL_LINK_MODE_FEC_RS_BIT); 811 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_LLRS_272_257_1, 812 ETHTOOL_LINK_MODE_FEC_LLRS_BIT); 813 814 active_fec_long = active_fec; 815 /* active fec is a bit set, find out which bit is set and 816 * advertise the corresponding ethtool bit 817 */ 818 bitn = find_first_bit(&active_fec_long, sizeof(active_fec_long) * BITS_PER_BYTE); 819 if (bitn < ARRAY_SIZE(pplm_fec_2_ethtool_linkmodes)) 820 __set_bit(pplm_fec_2_ethtool_linkmodes[bitn], 821 link_ksettings->link_modes.advertising); 822 823 return 0; 824 } 825 826 static void ptys2ethtool_supported_advertised_port(struct mlx5_core_dev *mdev, 827 struct ethtool_link_ksettings *link_ksettings, 828 u32 eth_proto_cap, u8 connector_type) 829 { 830 if (!MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type)) { 831 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR) 832 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR) 833 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) 834 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) 835 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) 836 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) { 837 ethtool_link_ksettings_add_link_mode(link_ksettings, 838 supported, 839 FIBRE); 840 ethtool_link_ksettings_add_link_mode(link_ksettings, 841 advertising, 842 FIBRE); 843 } 844 845 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4) 846 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) 847 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR) 848 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) 849 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) { 850 ethtool_link_ksettings_add_link_mode(link_ksettings, 851 supported, 852 Backplane); 853 ethtool_link_ksettings_add_link_mode(link_ksettings, 854 advertising, 855 Backplane); 856 } 857 return; 858 } 859 860 switch (connector_type) { 861 case MLX5E_PORT_TP: 862 ethtool_link_ksettings_add_link_mode(link_ksettings, 863 supported, TP); 864 ethtool_link_ksettings_add_link_mode(link_ksettings, 865 advertising, TP); 866 break; 867 case MLX5E_PORT_AUI: 868 ethtool_link_ksettings_add_link_mode(link_ksettings, 869 supported, AUI); 870 ethtool_link_ksettings_add_link_mode(link_ksettings, 871 advertising, AUI); 872 break; 873 case MLX5E_PORT_BNC: 874 ethtool_link_ksettings_add_link_mode(link_ksettings, 875 supported, BNC); 876 ethtool_link_ksettings_add_link_mode(link_ksettings, 877 advertising, BNC); 878 break; 879 case MLX5E_PORT_MII: 880 ethtool_link_ksettings_add_link_mode(link_ksettings, 881 supported, MII); 882 ethtool_link_ksettings_add_link_mode(link_ksettings, 883 advertising, MII); 884 break; 885 case MLX5E_PORT_FIBRE: 886 ethtool_link_ksettings_add_link_mode(link_ksettings, 887 supported, FIBRE); 888 ethtool_link_ksettings_add_link_mode(link_ksettings, 889 advertising, FIBRE); 890 break; 891 case MLX5E_PORT_DA: 892 ethtool_link_ksettings_add_link_mode(link_ksettings, 893 supported, Backplane); 894 ethtool_link_ksettings_add_link_mode(link_ksettings, 895 advertising, Backplane); 896 break; 897 case MLX5E_PORT_NONE: 898 case MLX5E_PORT_OTHER: 899 default: 900 break; 901 } 902 } 903 904 static void get_speed_duplex(struct net_device *netdev, 905 u32 eth_proto_oper, bool force_legacy, 906 u16 data_rate_oper, 907 struct ethtool_link_ksettings *link_ksettings) 908 { 909 struct mlx5e_priv *priv = netdev_priv(netdev); 910 u32 speed = SPEED_UNKNOWN; 911 u8 duplex = DUPLEX_UNKNOWN; 912 913 if (!netif_carrier_ok(netdev)) 914 goto out; 915 916 speed = mlx5e_port_ptys2speed(priv->mdev, eth_proto_oper, force_legacy); 917 if (!speed) { 918 if (data_rate_oper) 919 speed = 100 * data_rate_oper; 920 else 921 speed = SPEED_UNKNOWN; 922 goto out; 923 } 924 925 duplex = DUPLEX_FULL; 926 927 out: 928 link_ksettings->base.speed = speed; 929 link_ksettings->base.duplex = duplex; 930 } 931 932 static void get_supported(struct mlx5_core_dev *mdev, u32 eth_proto_cap, 933 struct ethtool_link_ksettings *link_ksettings) 934 { 935 unsigned long *supported = link_ksettings->link_modes.supported; 936 ptys2ethtool_supported_link(mdev, supported, eth_proto_cap); 937 938 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause); 939 } 940 941 static void get_advertising(u32 eth_proto_cap, u8 tx_pause, u8 rx_pause, 942 struct ethtool_link_ksettings *link_ksettings, 943 bool ext) 944 { 945 unsigned long *advertising = link_ksettings->link_modes.advertising; 946 ptys2ethtool_adver_link(advertising, eth_proto_cap, ext); 947 948 if (rx_pause) 949 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause); 950 if (tx_pause ^ rx_pause) 951 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause); 952 } 953 954 static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = { 955 [MLX5E_PORT_UNKNOWN] = PORT_OTHER, 956 [MLX5E_PORT_NONE] = PORT_NONE, 957 [MLX5E_PORT_TP] = PORT_TP, 958 [MLX5E_PORT_AUI] = PORT_AUI, 959 [MLX5E_PORT_BNC] = PORT_BNC, 960 [MLX5E_PORT_MII] = PORT_MII, 961 [MLX5E_PORT_FIBRE] = PORT_FIBRE, 962 [MLX5E_PORT_DA] = PORT_DA, 963 [MLX5E_PORT_OTHER] = PORT_OTHER, 964 }; 965 966 static u8 get_connector_port(struct mlx5_core_dev *mdev, u32 eth_proto, u8 connector_type) 967 { 968 if (MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type)) 969 return ptys2connector_type[connector_type]; 970 971 if (eth_proto & 972 (MLX5E_PROT_MASK(MLX5E_10GBASE_SR) | 973 MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) | 974 MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) | 975 MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) { 976 return PORT_FIBRE; 977 } 978 979 if (eth_proto & 980 (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) | 981 MLX5E_PROT_MASK(MLX5E_10GBASE_CR) | 982 MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) { 983 return PORT_DA; 984 } 985 986 if (eth_proto & 987 (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) | 988 MLX5E_PROT_MASK(MLX5E_10GBASE_KR) | 989 MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) | 990 MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) { 991 return PORT_NONE; 992 } 993 994 return PORT_OTHER; 995 } 996 997 static void get_lp_advertising(struct mlx5_core_dev *mdev, u32 eth_proto_lp, 998 struct ethtool_link_ksettings *link_ksettings) 999 { 1000 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising; 1001 bool ext = mlx5e_ptys_ext_supported(mdev); 1002 1003 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp, ext); 1004 } 1005 1006 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv, 1007 struct ethtool_link_ksettings *link_ksettings) 1008 { 1009 struct mlx5_core_dev *mdev = priv->mdev; 1010 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {}; 1011 u32 eth_proto_admin; 1012 u8 an_disable_admin; 1013 u16 data_rate_oper; 1014 u32 eth_proto_oper; 1015 u32 eth_proto_cap; 1016 u8 connector_type; 1017 u32 rx_pause = 0; 1018 u32 tx_pause = 0; 1019 u32 eth_proto_lp; 1020 bool admin_ext; 1021 u8 an_status; 1022 bool ext; 1023 int err; 1024 1025 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1); 1026 if (err) { 1027 netdev_err(priv->netdev, "%s: query port ptys failed: %d\n", 1028 __func__, err); 1029 goto err_query_regs; 1030 } 1031 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability); 1032 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 1033 eth_proto_capability); 1034 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 1035 eth_proto_admin); 1036 /* Fields: eth_proto_admin and ext_eth_proto_admin are 1037 * mutually exclusive. Hence try reading legacy advertising 1038 * when extended advertising is zero. 1039 * admin_ext indicates which proto_admin (ext vs. legacy) 1040 * should be read and interpreted 1041 */ 1042 admin_ext = ext; 1043 if (ext && !eth_proto_admin) { 1044 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, false, 1045 eth_proto_admin); 1046 admin_ext = false; 1047 } 1048 1049 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, admin_ext, 1050 eth_proto_oper); 1051 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise); 1052 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin); 1053 an_status = MLX5_GET(ptys_reg, out, an_status); 1054 connector_type = MLX5_GET(ptys_reg, out, connector_type); 1055 data_rate_oper = MLX5_GET(ptys_reg, out, data_rate_oper); 1056 1057 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause); 1058 1059 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported); 1060 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising); 1061 1062 get_supported(mdev, eth_proto_cap, link_ksettings); 1063 get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings, 1064 admin_ext); 1065 get_speed_duplex(priv->netdev, eth_proto_oper, !admin_ext, 1066 data_rate_oper, link_ksettings); 1067 1068 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap; 1069 connector_type = connector_type < MLX5E_CONNECTOR_TYPE_NUMBER ? 1070 connector_type : MLX5E_PORT_UNKNOWN; 1071 link_ksettings->base.port = get_connector_port(mdev, eth_proto_oper, connector_type); 1072 ptys2ethtool_supported_advertised_port(mdev, link_ksettings, eth_proto_admin, 1073 connector_type); 1074 get_lp_advertising(mdev, eth_proto_lp, link_ksettings); 1075 1076 if (an_status == MLX5_AN_COMPLETE) 1077 ethtool_link_ksettings_add_link_mode(link_ksettings, 1078 lp_advertising, Autoneg); 1079 1080 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE : 1081 AUTONEG_ENABLE; 1082 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, 1083 Autoneg); 1084 1085 err = get_fec_supported_advertised(mdev, link_ksettings); 1086 if (err) { 1087 netdev_dbg(priv->netdev, "%s: FEC caps query failed: %d\n", 1088 __func__, err); 1089 err = 0; /* don't fail caps query because of FEC error */ 1090 } 1091 1092 if (!an_disable_admin) 1093 ethtool_link_ksettings_add_link_mode(link_ksettings, 1094 advertising, Autoneg); 1095 1096 err_query_regs: 1097 return err; 1098 } 1099 1100 static int mlx5e_get_link_ksettings(struct net_device *netdev, 1101 struct ethtool_link_ksettings *link_ksettings) 1102 { 1103 struct mlx5e_priv *priv = netdev_priv(netdev); 1104 1105 return mlx5e_ethtool_get_link_ksettings(priv, link_ksettings); 1106 } 1107 1108 static int mlx5e_speed_validate(struct net_device *netdev, bool ext, 1109 const unsigned long link_modes, u8 autoneg) 1110 { 1111 /* Extended link-mode has no speed limitations. */ 1112 if (ext) 1113 return 0; 1114 1115 if ((link_modes & MLX5E_PROT_MASK(MLX5E_56GBASE_R4)) && 1116 autoneg != AUTONEG_ENABLE) { 1117 netdev_err(netdev, "%s: 56G link speed requires autoneg enabled\n", 1118 __func__); 1119 return -EINVAL; 1120 } 1121 return 0; 1122 } 1123 1124 static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes) 1125 { 1126 u32 i, ptys_modes = 0; 1127 1128 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) { 1129 if (*ptys2legacy_ethtool_table[i].advertised == 0) 1130 continue; 1131 if (bitmap_intersects(ptys2legacy_ethtool_table[i].advertised, 1132 link_modes, 1133 __ETHTOOL_LINK_MODE_MASK_NBITS)) 1134 ptys_modes |= MLX5E_PROT_MASK(i); 1135 } 1136 1137 return ptys_modes; 1138 } 1139 1140 static u32 mlx5e_ethtool2ptys_ext_adver_link(const unsigned long *link_modes) 1141 { 1142 u32 i, ptys_modes = 0; 1143 unsigned long modes[2]; 1144 1145 for (i = 0; i < MLX5E_EXT_LINK_MODES_NUMBER; ++i) { 1146 if (ptys2ext_ethtool_table[i].advertised[0] == 0 && 1147 ptys2ext_ethtool_table[i].advertised[1] == 0) 1148 continue; 1149 memset(modes, 0, sizeof(modes)); 1150 bitmap_and(modes, ptys2ext_ethtool_table[i].advertised, 1151 link_modes, __ETHTOOL_LINK_MODE_MASK_NBITS); 1152 1153 if (modes[0] == ptys2ext_ethtool_table[i].advertised[0] && 1154 modes[1] == ptys2ext_ethtool_table[i].advertised[1]) 1155 ptys_modes |= MLX5E_PROT_MASK(i); 1156 } 1157 return ptys_modes; 1158 } 1159 1160 static bool ext_link_mode_requested(const unsigned long *adver) 1161 { 1162 #define MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT ETHTOOL_LINK_MODE_50000baseKR_Full_BIT 1163 int size = __ETHTOOL_LINK_MODE_MASK_NBITS - MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT; 1164 __ETHTOOL_DECLARE_LINK_MODE_MASK(modes) = {0,}; 1165 1166 bitmap_set(modes, MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT, size); 1167 return bitmap_intersects(modes, adver, __ETHTOOL_LINK_MODE_MASK_NBITS); 1168 } 1169 1170 static bool ext_requested(u8 autoneg, const unsigned long *adver, bool ext_supported) 1171 { 1172 bool ext_link_mode = ext_link_mode_requested(adver); 1173 1174 return autoneg == AUTONEG_ENABLE ? ext_link_mode : ext_supported; 1175 } 1176 1177 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv, 1178 const struct ethtool_link_ksettings *link_ksettings) 1179 { 1180 struct mlx5_core_dev *mdev = priv->mdev; 1181 struct mlx5e_port_eth_proto eproto; 1182 const unsigned long *adver; 1183 bool an_changes = false; 1184 u8 an_disable_admin; 1185 bool ext_supported; 1186 u8 an_disable_cap; 1187 bool an_disable; 1188 u32 link_modes; 1189 u8 an_status; 1190 u8 autoneg; 1191 u32 speed; 1192 bool ext; 1193 int err; 1194 1195 u32 (*ethtool2ptys_adver_func)(const unsigned long *adver); 1196 1197 adver = link_ksettings->link_modes.advertising; 1198 autoneg = link_ksettings->base.autoneg; 1199 speed = link_ksettings->base.speed; 1200 1201 ext_supported = mlx5e_ptys_ext_supported(mdev); 1202 ext = ext_requested(autoneg, adver, ext_supported); 1203 if (!ext_supported && ext) 1204 return -EOPNOTSUPP; 1205 1206 ethtool2ptys_adver_func = ext ? mlx5e_ethtool2ptys_ext_adver_link : 1207 mlx5e_ethtool2ptys_adver_link; 1208 err = mlx5_port_query_eth_proto(mdev, 1, ext, &eproto); 1209 if (err) { 1210 netdev_err(priv->netdev, "%s: query port eth proto failed: %d\n", 1211 __func__, err); 1212 goto out; 1213 } 1214 link_modes = autoneg == AUTONEG_ENABLE ? ethtool2ptys_adver_func(adver) : 1215 mlx5e_port_speed2linkmodes(mdev, speed, !ext); 1216 1217 err = mlx5e_speed_validate(priv->netdev, ext, link_modes, autoneg); 1218 if (err) 1219 goto out; 1220 1221 link_modes = link_modes & eproto.cap; 1222 if (!link_modes) { 1223 netdev_err(priv->netdev, "%s: Not supported link mode(s) requested", 1224 __func__); 1225 err = -EINVAL; 1226 goto out; 1227 } 1228 1229 mlx5_port_query_eth_autoneg(mdev, &an_status, &an_disable_cap, 1230 &an_disable_admin); 1231 1232 an_disable = autoneg == AUTONEG_DISABLE; 1233 an_changes = ((!an_disable && an_disable_admin) || 1234 (an_disable && !an_disable_admin)); 1235 1236 if (!an_changes && link_modes == eproto.admin) 1237 goto out; 1238 1239 mlx5_port_set_eth_ptys(mdev, an_disable, link_modes, ext); 1240 mlx5_toggle_port_link(mdev); 1241 1242 out: 1243 return err; 1244 } 1245 1246 static int mlx5e_set_link_ksettings(struct net_device *netdev, 1247 const struct ethtool_link_ksettings *link_ksettings) 1248 { 1249 struct mlx5e_priv *priv = netdev_priv(netdev); 1250 1251 return mlx5e_ethtool_set_link_ksettings(priv, link_ksettings); 1252 } 1253 1254 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv) 1255 { 1256 return sizeof_field(struct mlx5e_rss_params_hash, toeplitz_hash_key); 1257 } 1258 1259 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev) 1260 { 1261 struct mlx5e_priv *priv = netdev_priv(netdev); 1262 1263 return mlx5e_ethtool_get_rxfh_key_size(priv); 1264 } 1265 1266 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv) 1267 { 1268 return MLX5E_INDIR_RQT_SIZE; 1269 } 1270 1271 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev) 1272 { 1273 struct mlx5e_priv *priv = netdev_priv(netdev); 1274 1275 return mlx5e_ethtool_get_rxfh_indir_size(priv); 1276 } 1277 1278 static int mlx5e_get_rxfh_context(struct net_device *dev, u32 *indir, 1279 u8 *key, u8 *hfunc, u32 rss_context) 1280 { 1281 struct mlx5e_priv *priv = netdev_priv(dev); 1282 int err; 1283 1284 mutex_lock(&priv->state_lock); 1285 err = mlx5e_rx_res_rss_get_rxfh(priv->rx_res, rss_context, indir, key, hfunc); 1286 mutex_unlock(&priv->state_lock); 1287 return err; 1288 } 1289 1290 static int mlx5e_set_rxfh_context(struct net_device *dev, const u32 *indir, 1291 const u8 *key, const u8 hfunc, 1292 u32 *rss_context, bool delete) 1293 { 1294 struct mlx5e_priv *priv = netdev_priv(dev); 1295 int err; 1296 1297 mutex_lock(&priv->state_lock); 1298 if (delete) { 1299 err = mlx5e_rx_res_rss_destroy(priv->rx_res, *rss_context); 1300 goto unlock; 1301 } 1302 1303 if (*rss_context == ETH_RXFH_CONTEXT_ALLOC) { 1304 unsigned int count = priv->channels.params.num_channels; 1305 1306 err = mlx5e_rx_res_rss_init(priv->rx_res, rss_context, count); 1307 if (err) 1308 goto unlock; 1309 } 1310 1311 err = mlx5e_rx_res_rss_set_rxfh(priv->rx_res, *rss_context, indir, key, 1312 hfunc == ETH_RSS_HASH_NO_CHANGE ? NULL : &hfunc); 1313 1314 unlock: 1315 mutex_unlock(&priv->state_lock); 1316 return err; 1317 } 1318 1319 int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, 1320 u8 *hfunc) 1321 { 1322 return mlx5e_get_rxfh_context(netdev, indir, key, hfunc, 0); 1323 } 1324 1325 int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir, 1326 const u8 *key, const u8 hfunc) 1327 { 1328 struct mlx5e_priv *priv = netdev_priv(dev); 1329 int err; 1330 1331 mutex_lock(&priv->state_lock); 1332 err = mlx5e_rx_res_rss_set_rxfh(priv->rx_res, 0, indir, key, 1333 hfunc == ETH_RSS_HASH_NO_CHANGE ? NULL : &hfunc); 1334 mutex_unlock(&priv->state_lock); 1335 return err; 1336 } 1337 1338 #define MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC 100 1339 #define MLX5E_PFC_PREVEN_TOUT_MAX_MSEC 8000 1340 #define MLX5E_PFC_PREVEN_MINOR_PRECENT 85 1341 #define MLX5E_PFC_PREVEN_TOUT_MIN_MSEC 80 1342 #define MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout) \ 1343 max_t(u16, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, \ 1344 (critical_tout * MLX5E_PFC_PREVEN_MINOR_PRECENT) / 100) 1345 1346 static int mlx5e_get_pfc_prevention_tout(struct net_device *netdev, 1347 u16 *pfc_prevention_tout) 1348 { 1349 struct mlx5e_priv *priv = netdev_priv(netdev); 1350 struct mlx5_core_dev *mdev = priv->mdev; 1351 1352 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) || 1353 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect)) 1354 return -EOPNOTSUPP; 1355 1356 return mlx5_query_port_stall_watermark(mdev, pfc_prevention_tout, NULL); 1357 } 1358 1359 static int mlx5e_set_pfc_prevention_tout(struct net_device *netdev, 1360 u16 pfc_preven) 1361 { 1362 struct mlx5e_priv *priv = netdev_priv(netdev); 1363 struct mlx5_core_dev *mdev = priv->mdev; 1364 u16 critical_tout; 1365 u16 minor; 1366 1367 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) || 1368 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect)) 1369 return -EOPNOTSUPP; 1370 1371 critical_tout = (pfc_preven == PFC_STORM_PREVENTION_AUTO) ? 1372 MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC : 1373 pfc_preven; 1374 1375 if (critical_tout != PFC_STORM_PREVENTION_DISABLE && 1376 (critical_tout > MLX5E_PFC_PREVEN_TOUT_MAX_MSEC || 1377 critical_tout < MLX5E_PFC_PREVEN_TOUT_MIN_MSEC)) { 1378 netdev_info(netdev, "%s: pfc prevention tout not in range (%d-%d)\n", 1379 __func__, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, 1380 MLX5E_PFC_PREVEN_TOUT_MAX_MSEC); 1381 return -EINVAL; 1382 } 1383 1384 minor = MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout); 1385 return mlx5_set_port_stall_watermark(mdev, critical_tout, 1386 minor); 1387 } 1388 1389 static int mlx5e_get_tunable(struct net_device *dev, 1390 const struct ethtool_tunable *tuna, 1391 void *data) 1392 { 1393 int err; 1394 1395 switch (tuna->id) { 1396 case ETHTOOL_PFC_PREVENTION_TOUT: 1397 err = mlx5e_get_pfc_prevention_tout(dev, data); 1398 break; 1399 default: 1400 err = -EINVAL; 1401 break; 1402 } 1403 1404 return err; 1405 } 1406 1407 static int mlx5e_set_tunable(struct net_device *dev, 1408 const struct ethtool_tunable *tuna, 1409 const void *data) 1410 { 1411 struct mlx5e_priv *priv = netdev_priv(dev); 1412 int err; 1413 1414 mutex_lock(&priv->state_lock); 1415 1416 switch (tuna->id) { 1417 case ETHTOOL_PFC_PREVENTION_TOUT: 1418 err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data); 1419 break; 1420 default: 1421 err = -EINVAL; 1422 break; 1423 } 1424 1425 mutex_unlock(&priv->state_lock); 1426 return err; 1427 } 1428 1429 static void mlx5e_get_pause_stats(struct net_device *netdev, 1430 struct ethtool_pause_stats *pause_stats) 1431 { 1432 struct mlx5e_priv *priv = netdev_priv(netdev); 1433 1434 mlx5e_stats_pause_get(priv, pause_stats); 1435 } 1436 1437 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv, 1438 struct ethtool_pauseparam *pauseparam) 1439 { 1440 struct mlx5_core_dev *mdev = priv->mdev; 1441 int err; 1442 1443 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause, 1444 &pauseparam->tx_pause); 1445 if (err) { 1446 netdev_err(priv->netdev, "%s: mlx5_query_port_pause failed:0x%x\n", 1447 __func__, err); 1448 } 1449 } 1450 1451 static void mlx5e_get_pauseparam(struct net_device *netdev, 1452 struct ethtool_pauseparam *pauseparam) 1453 { 1454 struct mlx5e_priv *priv = netdev_priv(netdev); 1455 1456 mlx5e_ethtool_get_pauseparam(priv, pauseparam); 1457 } 1458 1459 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv, 1460 struct ethtool_pauseparam *pauseparam) 1461 { 1462 struct mlx5_core_dev *mdev = priv->mdev; 1463 int err; 1464 1465 if (!MLX5_CAP_GEN(mdev, vport_group_manager)) 1466 return -EOPNOTSUPP; 1467 1468 if (pauseparam->autoneg) 1469 return -EINVAL; 1470 1471 err = mlx5_set_port_pause(mdev, 1472 pauseparam->rx_pause ? 1 : 0, 1473 pauseparam->tx_pause ? 1 : 0); 1474 if (err) { 1475 netdev_err(priv->netdev, "%s: mlx5_set_port_pause failed:0x%x\n", 1476 __func__, err); 1477 } 1478 1479 return err; 1480 } 1481 1482 static int mlx5e_set_pauseparam(struct net_device *netdev, 1483 struct ethtool_pauseparam *pauseparam) 1484 { 1485 struct mlx5e_priv *priv = netdev_priv(netdev); 1486 1487 return mlx5e_ethtool_set_pauseparam(priv, pauseparam); 1488 } 1489 1490 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv, 1491 struct ethtool_ts_info *info) 1492 { 1493 struct mlx5_core_dev *mdev = priv->mdev; 1494 1495 info->phc_index = mlx5_clock_get_ptp_index(mdev); 1496 1497 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) || 1498 info->phc_index == -1) 1499 return 0; 1500 1501 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE | 1502 SOF_TIMESTAMPING_RX_HARDWARE | 1503 SOF_TIMESTAMPING_RAW_HARDWARE; 1504 1505 info->tx_types = BIT(HWTSTAMP_TX_OFF) | 1506 BIT(HWTSTAMP_TX_ON); 1507 1508 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | 1509 BIT(HWTSTAMP_FILTER_ALL); 1510 1511 return 0; 1512 } 1513 1514 static int mlx5e_get_ts_info(struct net_device *dev, 1515 struct ethtool_ts_info *info) 1516 { 1517 struct mlx5e_priv *priv = netdev_priv(dev); 1518 1519 return mlx5e_ethtool_get_ts_info(priv, info); 1520 } 1521 1522 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev) 1523 { 1524 __u32 ret = 0; 1525 1526 if (MLX5_CAP_GEN(mdev, wol_g)) 1527 ret |= WAKE_MAGIC; 1528 1529 if (MLX5_CAP_GEN(mdev, wol_s)) 1530 ret |= WAKE_MAGICSECURE; 1531 1532 if (MLX5_CAP_GEN(mdev, wol_a)) 1533 ret |= WAKE_ARP; 1534 1535 if (MLX5_CAP_GEN(mdev, wol_b)) 1536 ret |= WAKE_BCAST; 1537 1538 if (MLX5_CAP_GEN(mdev, wol_m)) 1539 ret |= WAKE_MCAST; 1540 1541 if (MLX5_CAP_GEN(mdev, wol_u)) 1542 ret |= WAKE_UCAST; 1543 1544 if (MLX5_CAP_GEN(mdev, wol_p)) 1545 ret |= WAKE_PHY; 1546 1547 return ret; 1548 } 1549 1550 static __u32 mlx5e_reformat_wol_mode_mlx5_to_linux(u8 mode) 1551 { 1552 __u32 ret = 0; 1553 1554 if (mode & MLX5_WOL_MAGIC) 1555 ret |= WAKE_MAGIC; 1556 1557 if (mode & MLX5_WOL_SECURED_MAGIC) 1558 ret |= WAKE_MAGICSECURE; 1559 1560 if (mode & MLX5_WOL_ARP) 1561 ret |= WAKE_ARP; 1562 1563 if (mode & MLX5_WOL_BROADCAST) 1564 ret |= WAKE_BCAST; 1565 1566 if (mode & MLX5_WOL_MULTICAST) 1567 ret |= WAKE_MCAST; 1568 1569 if (mode & MLX5_WOL_UNICAST) 1570 ret |= WAKE_UCAST; 1571 1572 if (mode & MLX5_WOL_PHY_ACTIVITY) 1573 ret |= WAKE_PHY; 1574 1575 return ret; 1576 } 1577 1578 static u8 mlx5e_reformat_wol_mode_linux_to_mlx5(__u32 mode) 1579 { 1580 u8 ret = 0; 1581 1582 if (mode & WAKE_MAGIC) 1583 ret |= MLX5_WOL_MAGIC; 1584 1585 if (mode & WAKE_MAGICSECURE) 1586 ret |= MLX5_WOL_SECURED_MAGIC; 1587 1588 if (mode & WAKE_ARP) 1589 ret |= MLX5_WOL_ARP; 1590 1591 if (mode & WAKE_BCAST) 1592 ret |= MLX5_WOL_BROADCAST; 1593 1594 if (mode & WAKE_MCAST) 1595 ret |= MLX5_WOL_MULTICAST; 1596 1597 if (mode & WAKE_UCAST) 1598 ret |= MLX5_WOL_UNICAST; 1599 1600 if (mode & WAKE_PHY) 1601 ret |= MLX5_WOL_PHY_ACTIVITY; 1602 1603 return ret; 1604 } 1605 1606 static void mlx5e_get_wol(struct net_device *netdev, 1607 struct ethtool_wolinfo *wol) 1608 { 1609 struct mlx5e_priv *priv = netdev_priv(netdev); 1610 struct mlx5_core_dev *mdev = priv->mdev; 1611 u8 mlx5_wol_mode; 1612 int err; 1613 1614 memset(wol, 0, sizeof(*wol)); 1615 1616 wol->supported = mlx5e_get_wol_supported(mdev); 1617 if (!wol->supported) 1618 return; 1619 1620 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode); 1621 if (err) 1622 return; 1623 1624 wol->wolopts = mlx5e_reformat_wol_mode_mlx5_to_linux(mlx5_wol_mode); 1625 } 1626 1627 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 1628 { 1629 struct mlx5e_priv *priv = netdev_priv(netdev); 1630 struct mlx5_core_dev *mdev = priv->mdev; 1631 __u32 wol_supported = mlx5e_get_wol_supported(mdev); 1632 u32 mlx5_wol_mode; 1633 1634 if (!wol_supported) 1635 return -EOPNOTSUPP; 1636 1637 if (wol->wolopts & ~wol_supported) 1638 return -EINVAL; 1639 1640 mlx5_wol_mode = mlx5e_reformat_wol_mode_linux_to_mlx5(wol->wolopts); 1641 1642 return mlx5_set_port_wol(mdev, mlx5_wol_mode); 1643 } 1644 1645 static void mlx5e_get_fec_stats(struct net_device *netdev, 1646 struct ethtool_fec_stats *fec_stats) 1647 { 1648 struct mlx5e_priv *priv = netdev_priv(netdev); 1649 1650 mlx5e_stats_fec_get(priv, fec_stats); 1651 } 1652 1653 static int mlx5e_get_fecparam(struct net_device *netdev, 1654 struct ethtool_fecparam *fecparam) 1655 { 1656 struct mlx5e_priv *priv = netdev_priv(netdev); 1657 struct mlx5_core_dev *mdev = priv->mdev; 1658 u16 fec_configured; 1659 u32 fec_active; 1660 int err; 1661 1662 err = mlx5e_get_fec_mode(mdev, &fec_active, &fec_configured); 1663 1664 if (err) 1665 return err; 1666 1667 fecparam->active_fec = pplm2ethtool_fec((unsigned long)fec_active, 1668 sizeof(unsigned long) * BITS_PER_BYTE); 1669 1670 if (!fecparam->active_fec) 1671 return -EOPNOTSUPP; 1672 1673 fecparam->fec = pplm2ethtool_fec((unsigned long)fec_configured, 1674 sizeof(unsigned long) * BITS_PER_BYTE); 1675 1676 return 0; 1677 } 1678 1679 static int mlx5e_set_fecparam(struct net_device *netdev, 1680 struct ethtool_fecparam *fecparam) 1681 { 1682 struct mlx5e_priv *priv = netdev_priv(netdev); 1683 struct mlx5_core_dev *mdev = priv->mdev; 1684 unsigned long fec_bitmap; 1685 u16 fec_policy = 0; 1686 int mode; 1687 int err; 1688 1689 bitmap_from_arr32(&fec_bitmap, &fecparam->fec, sizeof(fecparam->fec) * BITS_PER_BYTE); 1690 if (bitmap_weight(&fec_bitmap, ETHTOOL_FEC_LLRS_BIT + 1) > 1) 1691 return -EOPNOTSUPP; 1692 1693 for (mode = 0; mode < ARRAY_SIZE(pplm_fec_2_ethtool); mode++) { 1694 if (!(pplm_fec_2_ethtool[mode] & fecparam->fec)) 1695 continue; 1696 fec_policy |= (1 << mode); 1697 break; 1698 } 1699 1700 err = mlx5e_set_fec_mode(mdev, fec_policy); 1701 1702 if (err) 1703 return err; 1704 1705 mlx5_toggle_port_link(mdev); 1706 1707 return 0; 1708 } 1709 1710 static u32 mlx5e_get_msglevel(struct net_device *dev) 1711 { 1712 return ((struct mlx5e_priv *)netdev_priv(dev))->msglevel; 1713 } 1714 1715 static void mlx5e_set_msglevel(struct net_device *dev, u32 val) 1716 { 1717 ((struct mlx5e_priv *)netdev_priv(dev))->msglevel = val; 1718 } 1719 1720 static int mlx5e_set_phys_id(struct net_device *dev, 1721 enum ethtool_phys_id_state state) 1722 { 1723 struct mlx5e_priv *priv = netdev_priv(dev); 1724 struct mlx5_core_dev *mdev = priv->mdev; 1725 u16 beacon_duration; 1726 1727 if (!MLX5_CAP_GEN(mdev, beacon_led)) 1728 return -EOPNOTSUPP; 1729 1730 switch (state) { 1731 case ETHTOOL_ID_ACTIVE: 1732 beacon_duration = MLX5_BEACON_DURATION_INF; 1733 break; 1734 case ETHTOOL_ID_INACTIVE: 1735 beacon_duration = MLX5_BEACON_DURATION_OFF; 1736 break; 1737 default: 1738 return -EOPNOTSUPP; 1739 } 1740 1741 return mlx5_set_port_beacon(mdev, beacon_duration); 1742 } 1743 1744 static int mlx5e_get_module_info(struct net_device *netdev, 1745 struct ethtool_modinfo *modinfo) 1746 { 1747 struct mlx5e_priv *priv = netdev_priv(netdev); 1748 struct mlx5_core_dev *dev = priv->mdev; 1749 int size_read = 0; 1750 u8 data[4] = {0}; 1751 1752 size_read = mlx5_query_module_eeprom(dev, 0, 2, data); 1753 if (size_read < 2) 1754 return -EIO; 1755 1756 /* data[0] = identifier byte */ 1757 switch (data[0]) { 1758 case MLX5_MODULE_ID_QSFP: 1759 modinfo->type = ETH_MODULE_SFF_8436; 1760 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN; 1761 break; 1762 case MLX5_MODULE_ID_QSFP_PLUS: 1763 case MLX5_MODULE_ID_QSFP28: 1764 /* data[1] = revision id */ 1765 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) { 1766 modinfo->type = ETH_MODULE_SFF_8636; 1767 modinfo->eeprom_len = ETH_MODULE_SFF_8636_MAX_LEN; 1768 } else { 1769 modinfo->type = ETH_MODULE_SFF_8436; 1770 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN; 1771 } 1772 break; 1773 case MLX5_MODULE_ID_SFP: 1774 modinfo->type = ETH_MODULE_SFF_8472; 1775 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 1776 break; 1777 default: 1778 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n", 1779 __func__, data[0]); 1780 return -EINVAL; 1781 } 1782 1783 return 0; 1784 } 1785 1786 static int mlx5e_get_module_eeprom(struct net_device *netdev, 1787 struct ethtool_eeprom *ee, 1788 u8 *data) 1789 { 1790 struct mlx5e_priv *priv = netdev_priv(netdev); 1791 struct mlx5_core_dev *mdev = priv->mdev; 1792 int offset = ee->offset; 1793 int size_read; 1794 int i = 0; 1795 1796 if (!ee->len) 1797 return -EINVAL; 1798 1799 memset(data, 0, ee->len); 1800 1801 while (i < ee->len) { 1802 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i, 1803 data + i); 1804 1805 if (!size_read) 1806 /* Done reading */ 1807 return 0; 1808 1809 if (size_read < 0) { 1810 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n", 1811 __func__, size_read); 1812 return size_read; 1813 } 1814 1815 i += size_read; 1816 offset += size_read; 1817 } 1818 1819 return 0; 1820 } 1821 1822 static int mlx5e_get_module_eeprom_by_page(struct net_device *netdev, 1823 const struct ethtool_module_eeprom *page_data, 1824 struct netlink_ext_ack *extack) 1825 { 1826 struct mlx5e_priv *priv = netdev_priv(netdev); 1827 struct mlx5_module_eeprom_query_params query; 1828 struct mlx5_core_dev *mdev = priv->mdev; 1829 u8 *data = page_data->data; 1830 int size_read; 1831 int i = 0; 1832 1833 if (!page_data->length) 1834 return -EINVAL; 1835 1836 memset(data, 0, page_data->length); 1837 1838 query.offset = page_data->offset; 1839 query.i2c_address = page_data->i2c_address; 1840 query.bank = page_data->bank; 1841 query.page = page_data->page; 1842 while (i < page_data->length) { 1843 query.size = page_data->length - i; 1844 size_read = mlx5_query_module_eeprom_by_page(mdev, &query, data + i); 1845 1846 /* Done reading, return how many bytes was read */ 1847 if (!size_read) 1848 return i; 1849 1850 if (size_read == -EINVAL) 1851 return -EINVAL; 1852 if (size_read < 0) { 1853 netdev_err(priv->netdev, "%s: mlx5_query_module_eeprom_by_page failed:0x%x\n", 1854 __func__, size_read); 1855 return i; 1856 } 1857 1858 i += size_read; 1859 query.offset += size_read; 1860 } 1861 1862 return i; 1863 } 1864 1865 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv, 1866 struct ethtool_flash *flash) 1867 { 1868 struct mlx5_core_dev *mdev = priv->mdev; 1869 struct net_device *dev = priv->netdev; 1870 const struct firmware *fw; 1871 int err; 1872 1873 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS) 1874 return -EOPNOTSUPP; 1875 1876 err = request_firmware_direct(&fw, flash->data, &dev->dev); 1877 if (err) 1878 return err; 1879 1880 dev_hold(dev); 1881 rtnl_unlock(); 1882 1883 err = mlx5_firmware_flash(mdev, fw, NULL); 1884 release_firmware(fw); 1885 1886 rtnl_lock(); 1887 dev_put(dev); 1888 return err; 1889 } 1890 1891 static int mlx5e_flash_device(struct net_device *dev, 1892 struct ethtool_flash *flash) 1893 { 1894 struct mlx5e_priv *priv = netdev_priv(dev); 1895 1896 return mlx5e_ethtool_flash_device(priv, flash); 1897 } 1898 1899 static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable, 1900 bool is_rx_cq) 1901 { 1902 struct mlx5e_priv *priv = netdev_priv(netdev); 1903 u8 cq_period_mode, current_cq_period_mode; 1904 struct mlx5e_params new_params; 1905 1906 if (enable && !MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) 1907 return -EOPNOTSUPP; 1908 1909 cq_period_mode = cqe_mode_to_period_mode(enable); 1910 1911 current_cq_period_mode = is_rx_cq ? 1912 priv->channels.params.rx_cq_moderation.cq_period_mode : 1913 priv->channels.params.tx_cq_moderation.cq_period_mode; 1914 1915 if (cq_period_mode == current_cq_period_mode) 1916 return 0; 1917 1918 new_params = priv->channels.params; 1919 if (is_rx_cq) 1920 mlx5e_set_rx_cq_mode_params(&new_params, cq_period_mode); 1921 else 1922 mlx5e_set_tx_cq_mode_params(&new_params, cq_period_mode); 1923 1924 return mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true); 1925 } 1926 1927 static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable) 1928 { 1929 return set_pflag_cqe_based_moder(netdev, enable, false); 1930 } 1931 1932 static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable) 1933 { 1934 return set_pflag_cqe_based_moder(netdev, enable, true); 1935 } 1936 1937 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val, bool rx_filter) 1938 { 1939 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS); 1940 struct mlx5e_params new_params; 1941 int err = 0; 1942 1943 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression)) 1944 return new_val ? -EOPNOTSUPP : 0; 1945 1946 if (curr_val == new_val) 1947 return 0; 1948 1949 if (new_val && !mlx5e_profile_feature_cap(priv->profile, PTP_RX) && rx_filter) { 1950 netdev_err(priv->netdev, 1951 "Profile doesn't support enabling of CQE compression while hardware time-stamping is enabled.\n"); 1952 return -EINVAL; 1953 } 1954 1955 if (priv->channels.params.packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) { 1956 netdev_warn(priv->netdev, "Can't set CQE compression with HW-GRO, disable it first.\n"); 1957 return -EINVAL; 1958 } 1959 1960 new_params = priv->channels.params; 1961 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val); 1962 if (rx_filter) 1963 new_params.ptp_rx = new_val; 1964 1965 if (new_params.ptp_rx == priv->channels.params.ptp_rx) 1966 err = mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true); 1967 else 1968 err = mlx5e_safe_switch_params(priv, &new_params, mlx5e_ptp_rx_manage_fs_ctx, 1969 &new_params.ptp_rx, true); 1970 if (err) 1971 return err; 1972 1973 mlx5e_dbg(DRV, priv, "MLX5E: RxCqeCmprss was turned %s\n", 1974 MLX5E_GET_PFLAG(&priv->channels.params, 1975 MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF"); 1976 1977 return 0; 1978 } 1979 1980 static int set_pflag_rx_cqe_compress(struct net_device *netdev, 1981 bool enable) 1982 { 1983 struct mlx5e_priv *priv = netdev_priv(netdev); 1984 struct mlx5_core_dev *mdev = priv->mdev; 1985 bool rx_filter; 1986 int err; 1987 1988 if (!MLX5_CAP_GEN(mdev, cqe_compression)) 1989 return -EOPNOTSUPP; 1990 1991 rx_filter = priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE; 1992 err = mlx5e_modify_rx_cqe_compression_locked(priv, enable, rx_filter); 1993 if (err) 1994 return err; 1995 1996 priv->channels.params.rx_cqe_compress_def = enable; 1997 1998 return 0; 1999 } 2000 2001 static int set_pflag_rx_striding_rq(struct net_device *netdev, bool enable) 2002 { 2003 struct mlx5e_priv *priv = netdev_priv(netdev); 2004 struct mlx5_core_dev *mdev = priv->mdev; 2005 struct mlx5e_params new_params; 2006 2007 if (enable) { 2008 /* Checking the regular RQ here; mlx5e_validate_xsk_param called 2009 * from mlx5e_open_xsk will check for each XSK queue, and 2010 * mlx5e_safe_switch_params will be reverted if any check fails. 2011 */ 2012 int err = mlx5e_mpwrq_validate_regular(mdev, &priv->channels.params); 2013 2014 if (err) 2015 return err; 2016 } else if (priv->channels.params.packet_merge.type != MLX5E_PACKET_MERGE_NONE) { 2017 netdev_warn(netdev, "Can't set legacy RQ with HW-GRO/LRO, disable them first\n"); 2018 return -EINVAL; 2019 } 2020 2021 new_params = priv->channels.params; 2022 2023 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_RX_STRIDING_RQ, enable); 2024 mlx5e_set_rq_type(mdev, &new_params); 2025 2026 return mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true); 2027 } 2028 2029 static int set_pflag_rx_no_csum_complete(struct net_device *netdev, bool enable) 2030 { 2031 struct mlx5e_priv *priv = netdev_priv(netdev); 2032 struct mlx5e_channels *channels = &priv->channels; 2033 struct mlx5e_channel *c; 2034 int i; 2035 2036 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || 2037 priv->channels.params.xdp_prog) 2038 return 0; 2039 2040 for (i = 0; i < channels->num; i++) { 2041 c = channels->c[i]; 2042 if (enable) 2043 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state); 2044 else 2045 __clear_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state); 2046 } 2047 2048 return 0; 2049 } 2050 2051 static int set_pflag_tx_mpwqe_common(struct net_device *netdev, u32 flag, bool enable) 2052 { 2053 struct mlx5e_priv *priv = netdev_priv(netdev); 2054 struct mlx5_core_dev *mdev = priv->mdev; 2055 struct mlx5e_params new_params; 2056 2057 if (enable && !mlx5e_tx_mpwqe_supported(mdev)) 2058 return -EOPNOTSUPP; 2059 2060 new_params = priv->channels.params; 2061 2062 MLX5E_SET_PFLAG(&new_params, flag, enable); 2063 2064 return mlx5e_safe_switch_params(priv, &new_params, NULL, NULL, true); 2065 } 2066 2067 static int set_pflag_xdp_tx_mpwqe(struct net_device *netdev, bool enable) 2068 { 2069 return set_pflag_tx_mpwqe_common(netdev, MLX5E_PFLAG_XDP_TX_MPWQE, enable); 2070 } 2071 2072 static int set_pflag_skb_tx_mpwqe(struct net_device *netdev, bool enable) 2073 { 2074 return set_pflag_tx_mpwqe_common(netdev, MLX5E_PFLAG_SKB_TX_MPWQE, enable); 2075 } 2076 2077 static int set_pflag_tx_port_ts(struct net_device *netdev, bool enable) 2078 { 2079 struct mlx5e_priv *priv = netdev_priv(netdev); 2080 struct mlx5_core_dev *mdev = priv->mdev; 2081 struct mlx5e_params new_params; 2082 int err; 2083 2084 if (!MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn)) 2085 return -EOPNOTSUPP; 2086 2087 /* Don't allow changing the PTP state if HTB offload is active, because 2088 * the numeration of the QoS SQs will change, while per-queue qdiscs are 2089 * attached. 2090 */ 2091 if (mlx5e_selq_is_htb_enabled(&priv->selq)) { 2092 netdev_err(priv->netdev, "%s: HTB offload is active, cannot change the PTP state\n", 2093 __func__); 2094 return -EINVAL; 2095 } 2096 2097 new_params = priv->channels.params; 2098 /* Don't allow enabling TX-port-TS if MQPRIO mode channel offload is 2099 * active, since it defines explicitly which TC accepts the packet. 2100 * This conflicts with TX-port-TS hijacking the PTP traffic to a specific 2101 * HW TX-queue. 2102 */ 2103 if (enable && new_params.mqprio.mode == TC_MQPRIO_MODE_CHANNEL) { 2104 netdev_err(priv->netdev, 2105 "%s: MQPRIO mode channel offload is active, cannot set the TX-port-TS\n", 2106 __func__); 2107 return -EINVAL; 2108 } 2109 MLX5E_SET_PFLAG(&new_params, MLX5E_PFLAG_TX_PORT_TS, enable); 2110 /* No need to verify SQ stop room as 2111 * ptpsq.txqsq.stop_room <= generic_sq->stop_room, and both 2112 * has the same log_sq_size. 2113 */ 2114 2115 err = mlx5e_safe_switch_params(priv, &new_params, 2116 mlx5e_num_channels_changed_ctx, NULL, true); 2117 if (!err) 2118 priv->tx_ptp_opened = true; 2119 2120 return err; 2121 } 2122 2123 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS] = { 2124 { "rx_cqe_moder", set_pflag_rx_cqe_based_moder }, 2125 { "tx_cqe_moder", set_pflag_tx_cqe_based_moder }, 2126 { "rx_cqe_compress", set_pflag_rx_cqe_compress }, 2127 { "rx_striding_rq", set_pflag_rx_striding_rq }, 2128 { "rx_no_csum_complete", set_pflag_rx_no_csum_complete }, 2129 { "xdp_tx_mpwqe", set_pflag_xdp_tx_mpwqe }, 2130 { "skb_tx_mpwqe", set_pflag_skb_tx_mpwqe }, 2131 { "tx_port_ts", set_pflag_tx_port_ts }, 2132 }; 2133 2134 static int mlx5e_handle_pflag(struct net_device *netdev, 2135 u32 wanted_flags, 2136 enum mlx5e_priv_flag flag) 2137 { 2138 struct mlx5e_priv *priv = netdev_priv(netdev); 2139 bool enable = !!(wanted_flags & BIT(flag)); 2140 u32 changes = wanted_flags ^ priv->channels.params.pflags; 2141 int err; 2142 2143 if (!(changes & BIT(flag))) 2144 return 0; 2145 2146 err = mlx5e_priv_flags[flag].handler(netdev, enable); 2147 if (err) { 2148 netdev_err(netdev, "%s private flag '%s' failed err %d\n", 2149 enable ? "Enable" : "Disable", mlx5e_priv_flags[flag].name, err); 2150 return err; 2151 } 2152 2153 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable); 2154 return 0; 2155 } 2156 2157 static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags) 2158 { 2159 struct mlx5e_priv *priv = netdev_priv(netdev); 2160 enum mlx5e_priv_flag pflag; 2161 int err; 2162 2163 mutex_lock(&priv->state_lock); 2164 2165 for (pflag = 0; pflag < MLX5E_NUM_PFLAGS; pflag++) { 2166 err = mlx5e_handle_pflag(netdev, pflags, pflag); 2167 if (err) 2168 break; 2169 } 2170 2171 mutex_unlock(&priv->state_lock); 2172 2173 /* Need to fix some features.. */ 2174 netdev_update_features(netdev); 2175 2176 return err; 2177 } 2178 2179 static u32 mlx5e_get_priv_flags(struct net_device *netdev) 2180 { 2181 struct mlx5e_priv *priv = netdev_priv(netdev); 2182 2183 return priv->channels.params.pflags; 2184 } 2185 2186 int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, 2187 u32 *rule_locs) 2188 { 2189 struct mlx5e_priv *priv = netdev_priv(dev); 2190 2191 /* ETHTOOL_GRXRINGS is needed by ethtool -x which is not part 2192 * of rxnfc. We keep this logic out of mlx5e_ethtool_get_rxnfc, 2193 * to avoid breaking "ethtool -x" when mlx5e_ethtool_get_rxnfc 2194 * is compiled out via CONFIG_MLX5_EN_RXNFC=n. 2195 */ 2196 if (info->cmd == ETHTOOL_GRXRINGS) { 2197 info->data = priv->channels.params.num_channels; 2198 return 0; 2199 } 2200 2201 return mlx5e_ethtool_get_rxnfc(priv, info, rule_locs); 2202 } 2203 2204 int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2205 { 2206 struct mlx5e_priv *priv = netdev_priv(dev); 2207 2208 return mlx5e_ethtool_set_rxnfc(priv, cmd); 2209 } 2210 2211 static int query_port_status_opcode(struct mlx5_core_dev *mdev, u32 *status_opcode) 2212 { 2213 struct mlx5_ifc_pddr_troubleshooting_page_bits *pddr_troubleshooting_page; 2214 u32 in[MLX5_ST_SZ_DW(pddr_reg)] = {}; 2215 u32 out[MLX5_ST_SZ_DW(pddr_reg)]; 2216 int err; 2217 2218 MLX5_SET(pddr_reg, in, local_port, 1); 2219 MLX5_SET(pddr_reg, in, page_select, 2220 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE); 2221 2222 pddr_troubleshooting_page = MLX5_ADDR_OF(pddr_reg, in, page_data); 2223 MLX5_SET(pddr_troubleshooting_page, pddr_troubleshooting_page, 2224 group_opcode, MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR); 2225 err = mlx5_core_access_reg(mdev, in, sizeof(in), out, 2226 sizeof(out), MLX5_REG_PDDR, 0, 0); 2227 if (err) 2228 return err; 2229 2230 pddr_troubleshooting_page = MLX5_ADDR_OF(pddr_reg, out, page_data); 2231 *status_opcode = MLX5_GET(pddr_troubleshooting_page, pddr_troubleshooting_page, 2232 status_opcode); 2233 return 0; 2234 } 2235 2236 struct mlx5e_ethtool_link_ext_state_opcode_mapping { 2237 u32 status_opcode; 2238 enum ethtool_link_ext_state link_ext_state; 2239 u8 link_ext_substate; 2240 }; 2241 2242 static const struct mlx5e_ethtool_link_ext_state_opcode_mapping 2243 mlx5e_link_ext_state_opcode_map[] = { 2244 /* States relating to the autonegotiation or issues therein */ 2245 {2, ETHTOOL_LINK_EXT_STATE_AUTONEG, 2246 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED}, 2247 {3, ETHTOOL_LINK_EXT_STATE_AUTONEG, 2248 ETHTOOL_LINK_EXT_SUBSTATE_AN_ACK_NOT_RECEIVED}, 2249 {4, ETHTOOL_LINK_EXT_STATE_AUTONEG, 2250 ETHTOOL_LINK_EXT_SUBSTATE_AN_NEXT_PAGE_EXCHANGE_FAILED}, 2251 {36, ETHTOOL_LINK_EXT_STATE_AUTONEG, 2252 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED_FORCE_MODE}, 2253 {38, ETHTOOL_LINK_EXT_STATE_AUTONEG, 2254 ETHTOOL_LINK_EXT_SUBSTATE_AN_FEC_MISMATCH_DURING_OVERRIDE}, 2255 {39, ETHTOOL_LINK_EXT_STATE_AUTONEG, 2256 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_HCD}, 2257 2258 /* Failure during link training */ 2259 {5, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE, 2260 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_FRAME_LOCK_NOT_ACQUIRED}, 2261 {6, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE, 2262 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_INHIBIT_TIMEOUT}, 2263 {7, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE, 2264 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_PARTNER_DID_NOT_SET_RECEIVER_READY}, 2265 {8, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE, 0}, 2266 {14, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE, 2267 ETHTOOL_LINK_EXT_SUBSTATE_LT_REMOTE_FAULT}, 2268 2269 /* Logical mismatch in physical coding sublayer or forward error correction sublayer */ 2270 {9, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH, 2271 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_BLOCK_LOCK}, 2272 {10, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH, 2273 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_AM_LOCK}, 2274 {11, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH, 2275 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_GET_ALIGN_STATUS}, 2276 {12, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH, 2277 ETHTOOL_LINK_EXT_SUBSTATE_LLM_FC_FEC_IS_NOT_LOCKED}, 2278 {13, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH, 2279 ETHTOOL_LINK_EXT_SUBSTATE_LLM_RS_FEC_IS_NOT_LOCKED}, 2280 2281 /* Signal integrity issues */ 2282 {15, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY, 0}, 2283 {17, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY, 2284 ETHTOOL_LINK_EXT_SUBSTATE_BSI_LARGE_NUMBER_OF_PHYSICAL_ERRORS}, 2285 {42, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY, 2286 ETHTOOL_LINK_EXT_SUBSTATE_BSI_UNSUPPORTED_RATE}, 2287 2288 /* No cable connected */ 2289 {1024, ETHTOOL_LINK_EXT_STATE_NO_CABLE, 0}, 2290 2291 /* Failure is related to cable, e.g., unsupported cable */ 2292 {16, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE, 2293 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE}, 2294 {20, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE, 2295 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE}, 2296 {29, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE, 2297 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE}, 2298 {1025, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE, 2299 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE}, 2300 {1029, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE, 2301 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE}, 2302 {1031, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE, 0}, 2303 2304 /* Failure is related to EEPROM, e.g., failure during reading or parsing the data */ 2305 {1027, ETHTOOL_LINK_EXT_STATE_EEPROM_ISSUE, 0}, 2306 2307 /* Failure during calibration algorithm */ 2308 {23, ETHTOOL_LINK_EXT_STATE_CALIBRATION_FAILURE, 0}, 2309 2310 /* The hardware is not able to provide the power required from cable or module */ 2311 {1032, ETHTOOL_LINK_EXT_STATE_POWER_BUDGET_EXCEEDED, 0}, 2312 2313 /* The module is overheated */ 2314 {1030, ETHTOOL_LINK_EXT_STATE_OVERHEAT, 0}, 2315 }; 2316 2317 static void 2318 mlx5e_set_link_ext_state(struct mlx5e_ethtool_link_ext_state_opcode_mapping 2319 link_ext_state_mapping, 2320 struct ethtool_link_ext_state_info *link_ext_state_info) 2321 { 2322 switch (link_ext_state_mapping.link_ext_state) { 2323 case ETHTOOL_LINK_EXT_STATE_AUTONEG: 2324 link_ext_state_info->autoneg = 2325 link_ext_state_mapping.link_ext_substate; 2326 break; 2327 case ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE: 2328 link_ext_state_info->link_training = 2329 link_ext_state_mapping.link_ext_substate; 2330 break; 2331 case ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH: 2332 link_ext_state_info->link_logical_mismatch = 2333 link_ext_state_mapping.link_ext_substate; 2334 break; 2335 case ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY: 2336 link_ext_state_info->bad_signal_integrity = 2337 link_ext_state_mapping.link_ext_substate; 2338 break; 2339 case ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE: 2340 link_ext_state_info->cable_issue = 2341 link_ext_state_mapping.link_ext_substate; 2342 break; 2343 default: 2344 break; 2345 } 2346 2347 link_ext_state_info->link_ext_state = link_ext_state_mapping.link_ext_state; 2348 } 2349 2350 static int 2351 mlx5e_get_link_ext_state(struct net_device *dev, 2352 struct ethtool_link_ext_state_info *link_ext_state_info) 2353 { 2354 struct mlx5e_ethtool_link_ext_state_opcode_mapping link_ext_state_mapping; 2355 struct mlx5e_priv *priv = netdev_priv(dev); 2356 u32 status_opcode = 0; 2357 int i; 2358 2359 /* Exit without data if the interface state is OK, since no extended data is 2360 * available in such case 2361 */ 2362 if (netif_carrier_ok(dev)) 2363 return -ENODATA; 2364 2365 if (query_port_status_opcode(priv->mdev, &status_opcode) || 2366 !status_opcode) 2367 return -ENODATA; 2368 2369 for (i = 0; i < ARRAY_SIZE(mlx5e_link_ext_state_opcode_map); i++) { 2370 link_ext_state_mapping = mlx5e_link_ext_state_opcode_map[i]; 2371 if (link_ext_state_mapping.status_opcode == status_opcode) { 2372 mlx5e_set_link_ext_state(link_ext_state_mapping, 2373 link_ext_state_info); 2374 return 0; 2375 } 2376 } 2377 2378 return -ENODATA; 2379 } 2380 2381 static void mlx5e_get_eth_phy_stats(struct net_device *netdev, 2382 struct ethtool_eth_phy_stats *phy_stats) 2383 { 2384 struct mlx5e_priv *priv = netdev_priv(netdev); 2385 2386 mlx5e_stats_eth_phy_get(priv, phy_stats); 2387 } 2388 2389 static void mlx5e_get_eth_mac_stats(struct net_device *netdev, 2390 struct ethtool_eth_mac_stats *mac_stats) 2391 { 2392 struct mlx5e_priv *priv = netdev_priv(netdev); 2393 2394 mlx5e_stats_eth_mac_get(priv, mac_stats); 2395 } 2396 2397 static void mlx5e_get_eth_ctrl_stats(struct net_device *netdev, 2398 struct ethtool_eth_ctrl_stats *ctrl_stats) 2399 { 2400 struct mlx5e_priv *priv = netdev_priv(netdev); 2401 2402 mlx5e_stats_eth_ctrl_get(priv, ctrl_stats); 2403 } 2404 2405 static void mlx5e_get_rmon_stats(struct net_device *netdev, 2406 struct ethtool_rmon_stats *rmon_stats, 2407 const struct ethtool_rmon_hist_range **ranges) 2408 { 2409 struct mlx5e_priv *priv = netdev_priv(netdev); 2410 2411 mlx5e_stats_rmon_get(priv, rmon_stats, ranges); 2412 } 2413 2414 const struct ethtool_ops mlx5e_ethtool_ops = { 2415 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2416 ETHTOOL_COALESCE_MAX_FRAMES | 2417 ETHTOOL_COALESCE_USE_ADAPTIVE | 2418 ETHTOOL_COALESCE_USE_CQE, 2419 .get_drvinfo = mlx5e_get_drvinfo, 2420 .get_link = ethtool_op_get_link, 2421 .get_link_ext_state = mlx5e_get_link_ext_state, 2422 .get_strings = mlx5e_get_strings, 2423 .get_sset_count = mlx5e_get_sset_count, 2424 .get_ethtool_stats = mlx5e_get_ethtool_stats, 2425 .get_ringparam = mlx5e_get_ringparam, 2426 .set_ringparam = mlx5e_set_ringparam, 2427 .get_channels = mlx5e_get_channels, 2428 .set_channels = mlx5e_set_channels, 2429 .get_coalesce = mlx5e_get_coalesce, 2430 .set_coalesce = mlx5e_set_coalesce, 2431 .get_link_ksettings = mlx5e_get_link_ksettings, 2432 .set_link_ksettings = mlx5e_set_link_ksettings, 2433 .get_rxfh_key_size = mlx5e_get_rxfh_key_size, 2434 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size, 2435 .get_rxfh = mlx5e_get_rxfh, 2436 .set_rxfh = mlx5e_set_rxfh, 2437 .get_rxfh_context = mlx5e_get_rxfh_context, 2438 .set_rxfh_context = mlx5e_set_rxfh_context, 2439 .get_rxnfc = mlx5e_get_rxnfc, 2440 .set_rxnfc = mlx5e_set_rxnfc, 2441 .get_tunable = mlx5e_get_tunable, 2442 .set_tunable = mlx5e_set_tunable, 2443 .get_pause_stats = mlx5e_get_pause_stats, 2444 .get_pauseparam = mlx5e_get_pauseparam, 2445 .set_pauseparam = mlx5e_set_pauseparam, 2446 .get_ts_info = mlx5e_get_ts_info, 2447 .set_phys_id = mlx5e_set_phys_id, 2448 .get_wol = mlx5e_get_wol, 2449 .set_wol = mlx5e_set_wol, 2450 .get_module_info = mlx5e_get_module_info, 2451 .get_module_eeprom = mlx5e_get_module_eeprom, 2452 .get_module_eeprom_by_page = mlx5e_get_module_eeprom_by_page, 2453 .flash_device = mlx5e_flash_device, 2454 .get_priv_flags = mlx5e_get_priv_flags, 2455 .set_priv_flags = mlx5e_set_priv_flags, 2456 .self_test = mlx5e_self_test, 2457 .get_msglevel = mlx5e_get_msglevel, 2458 .set_msglevel = mlx5e_set_msglevel, 2459 .get_fec_stats = mlx5e_get_fec_stats, 2460 .get_fecparam = mlx5e_get_fecparam, 2461 .set_fecparam = mlx5e_set_fecparam, 2462 .get_eth_phy_stats = mlx5e_get_eth_phy_stats, 2463 .get_eth_mac_stats = mlx5e_get_eth_mac_stats, 2464 .get_eth_ctrl_stats = mlx5e_get_eth_ctrl_stats, 2465 .get_rmon_stats = mlx5e_get_rmon_stats, 2466 }; 2467