1 /* 2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include "en.h" 34 #include "en/port.h" 35 #include "en/params.h" 36 #include "en/xsk/pool.h" 37 #include "lib/clock.h" 38 39 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv, 40 struct ethtool_drvinfo *drvinfo) 41 { 42 struct mlx5_core_dev *mdev = priv->mdev; 43 44 strlcpy(drvinfo->driver, KBUILD_MODNAME, sizeof(drvinfo->driver)); 45 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), 46 "%d.%d.%04d (%.16s)", 47 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev), 48 mdev->board_id); 49 strlcpy(drvinfo->bus_info, dev_name(mdev->device), 50 sizeof(drvinfo->bus_info)); 51 } 52 53 static void mlx5e_get_drvinfo(struct net_device *dev, 54 struct ethtool_drvinfo *drvinfo) 55 { 56 struct mlx5e_priv *priv = netdev_priv(dev); 57 58 mlx5e_ethtool_get_drvinfo(priv, drvinfo); 59 } 60 61 struct ptys2ethtool_config { 62 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); 63 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised); 64 }; 65 66 static 67 struct ptys2ethtool_config ptys2legacy_ethtool_table[MLX5E_LINK_MODES_NUMBER]; 68 static 69 struct ptys2ethtool_config ptys2ext_ethtool_table[MLX5E_EXT_LINK_MODES_NUMBER]; 70 71 #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, table, ...) \ 72 ({ \ 73 struct ptys2ethtool_config *cfg; \ 74 const unsigned int modes[] = { __VA_ARGS__ }; \ 75 unsigned int i, bit, idx; \ 76 cfg = &ptys2##table##_ethtool_table[reg_]; \ 77 bitmap_zero(cfg->supported, \ 78 __ETHTOOL_LINK_MODE_MASK_NBITS); \ 79 bitmap_zero(cfg->advertised, \ 80 __ETHTOOL_LINK_MODE_MASK_NBITS); \ 81 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \ 82 bit = modes[i] % 64; \ 83 idx = modes[i] / 64; \ 84 __set_bit(bit, &cfg->supported[idx]); \ 85 __set_bit(bit, &cfg->advertised[idx]); \ 86 } \ 87 }) 88 89 void mlx5e_build_ptys2ethtool_map(void) 90 { 91 memset(ptys2legacy_ethtool_table, 0, sizeof(ptys2legacy_ethtool_table)); 92 memset(ptys2ext_ethtool_table, 0, sizeof(ptys2ext_ethtool_table)); 93 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, legacy, 94 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT); 95 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, legacy, 96 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT); 97 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, legacy, 98 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT); 99 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, legacy, 100 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT); 101 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, legacy, 102 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); 103 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, legacy, 104 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT); 105 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, legacy, 106 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT); 107 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, legacy, 108 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT); 109 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, legacy, 110 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT); 111 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, legacy, 112 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); 113 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, legacy, 114 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); 115 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, legacy, 116 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); 117 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, legacy, 118 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT); 119 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, legacy, 120 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT); 121 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, legacy, 122 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT); 123 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, legacy, 124 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT); 125 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, legacy, 126 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT); 127 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, legacy, 128 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT); 129 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, legacy, 130 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT); 131 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, legacy, 132 ETHTOOL_LINK_MODE_10000baseT_Full_BIT); 133 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, legacy, 134 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT); 135 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, legacy, 136 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT); 137 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, legacy, 138 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT); 139 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, legacy, 140 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT); 141 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, legacy, 142 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT); 143 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_SGMII_100M, ext, 144 ETHTOOL_LINK_MODE_100baseT_Full_BIT); 145 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_X_SGMII, ext, 146 ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 147 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, 148 ETHTOOL_LINK_MODE_1000baseX_Full_BIT); 149 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_5GBASE_R, ext, 150 ETHTOOL_LINK_MODE_5000baseT_Full_BIT); 151 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_XFI_XAUI_1, ext, 152 ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 153 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 154 ETHTOOL_LINK_MODE_10000baseR_FEC_BIT, 155 ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, 156 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 157 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 158 ETHTOOL_LINK_MODE_10000baseER_Full_BIT); 159 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_XLAUI_4_XLPPI_4, ext, 160 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 161 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 162 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 163 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT); 164 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GAUI_1_25GBASE_CR_KR, ext, 165 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 166 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 167 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT); 168 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2, 169 ext, 170 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT, 171 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT, 172 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT); 173 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR, ext, 174 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, 175 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, 176 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, 177 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 178 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT); 179 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_CAUI_4_100GBASE_CR4_KR4, ext, 180 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, 181 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 182 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 183 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT); 184 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_2_100GBASE_CR2_KR2, ext, 185 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT, 186 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT, 187 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT, 188 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT, 189 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT); 190 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_4_200GBASE_CR4_KR4, ext, 191 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT, 192 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT, 193 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT, 194 ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT, 195 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT); 196 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_1_100GBASE_CR_KR, ext, 197 ETHTOOL_LINK_MODE_100000baseKR_Full_BIT, 198 ETHTOOL_LINK_MODE_100000baseSR_Full_BIT, 199 ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT, 200 ETHTOOL_LINK_MODE_100000baseDR_Full_BIT, 201 ETHTOOL_LINK_MODE_100000baseCR_Full_BIT); 202 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_2_200GBASE_CR2_KR2, ext, 203 ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT, 204 ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT, 205 ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT, 206 ETHTOOL_LINK_MODE_200000baseDR2_Full_BIT, 207 ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT); 208 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_4_400GBASE_CR4_KR4, ext, 209 ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT, 210 ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT, 211 ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT, 212 ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT, 213 ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT); 214 } 215 216 static void mlx5e_ethtool_get_speed_arr(struct mlx5_core_dev *mdev, 217 struct ptys2ethtool_config **arr, 218 u32 *size) 219 { 220 bool ext = mlx5e_ptys_ext_supported(mdev); 221 222 *arr = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table; 223 *size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) : 224 ARRAY_SIZE(ptys2legacy_ethtool_table); 225 } 226 227 typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable); 228 229 struct pflag_desc { 230 char name[ETH_GSTRING_LEN]; 231 mlx5e_pflag_handler handler; 232 }; 233 234 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS]; 235 236 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset) 237 { 238 switch (sset) { 239 case ETH_SS_STATS: 240 return mlx5e_stats_total_num(priv); 241 case ETH_SS_PRIV_FLAGS: 242 return MLX5E_NUM_PFLAGS; 243 case ETH_SS_TEST: 244 return mlx5e_self_test_num(priv); 245 default: 246 return -EOPNOTSUPP; 247 } 248 } 249 250 static int mlx5e_get_sset_count(struct net_device *dev, int sset) 251 { 252 struct mlx5e_priv *priv = netdev_priv(dev); 253 254 return mlx5e_ethtool_get_sset_count(priv, sset); 255 } 256 257 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, u32 stringset, u8 *data) 258 { 259 int i; 260 261 switch (stringset) { 262 case ETH_SS_PRIV_FLAGS: 263 for (i = 0; i < MLX5E_NUM_PFLAGS; i++) 264 strcpy(data + i * ETH_GSTRING_LEN, 265 mlx5e_priv_flags[i].name); 266 break; 267 268 case ETH_SS_TEST: 269 for (i = 0; i < mlx5e_self_test_num(priv); i++) 270 strcpy(data + i * ETH_GSTRING_LEN, 271 mlx5e_self_tests[i]); 272 break; 273 274 case ETH_SS_STATS: 275 mlx5e_stats_fill_strings(priv, data); 276 break; 277 } 278 } 279 280 static void mlx5e_get_strings(struct net_device *dev, u32 stringset, u8 *data) 281 { 282 struct mlx5e_priv *priv = netdev_priv(dev); 283 284 mlx5e_ethtool_get_strings(priv, stringset, data); 285 } 286 287 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv, 288 struct ethtool_stats *stats, u64 *data) 289 { 290 int idx = 0; 291 292 mutex_lock(&priv->state_lock); 293 mlx5e_stats_update(priv); 294 mutex_unlock(&priv->state_lock); 295 296 mlx5e_stats_fill(priv, data, idx); 297 } 298 299 static void mlx5e_get_ethtool_stats(struct net_device *dev, 300 struct ethtool_stats *stats, 301 u64 *data) 302 { 303 struct mlx5e_priv *priv = netdev_priv(dev); 304 305 mlx5e_ethtool_get_ethtool_stats(priv, stats, data); 306 } 307 308 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv, 309 struct ethtool_ringparam *param) 310 { 311 param->rx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE; 312 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE; 313 param->rx_pending = 1 << priv->channels.params.log_rq_mtu_frames; 314 param->tx_pending = 1 << priv->channels.params.log_sq_size; 315 } 316 317 static void mlx5e_get_ringparam(struct net_device *dev, 318 struct ethtool_ringparam *param) 319 { 320 struct mlx5e_priv *priv = netdev_priv(dev); 321 322 mlx5e_ethtool_get_ringparam(priv, param); 323 } 324 325 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, 326 struct ethtool_ringparam *param) 327 { 328 struct mlx5e_channels new_channels = {}; 329 u8 log_rq_size; 330 u8 log_sq_size; 331 int err = 0; 332 333 if (param->rx_jumbo_pending) { 334 netdev_info(priv->netdev, "%s: rx_jumbo_pending not supported\n", 335 __func__); 336 return -EINVAL; 337 } 338 if (param->rx_mini_pending) { 339 netdev_info(priv->netdev, "%s: rx_mini_pending not supported\n", 340 __func__); 341 return -EINVAL; 342 } 343 344 if (param->rx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) { 345 netdev_info(priv->netdev, "%s: rx_pending (%d) < min (%d)\n", 346 __func__, param->rx_pending, 347 1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE); 348 return -EINVAL; 349 } 350 351 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) { 352 netdev_info(priv->netdev, "%s: tx_pending (%d) < min (%d)\n", 353 __func__, param->tx_pending, 354 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE); 355 return -EINVAL; 356 } 357 358 log_rq_size = order_base_2(param->rx_pending); 359 log_sq_size = order_base_2(param->tx_pending); 360 361 if (log_rq_size == priv->channels.params.log_rq_mtu_frames && 362 log_sq_size == priv->channels.params.log_sq_size) 363 return 0; 364 365 mutex_lock(&priv->state_lock); 366 367 new_channels.params = priv->channels.params; 368 new_channels.params.log_rq_mtu_frames = log_rq_size; 369 new_channels.params.log_sq_size = log_sq_size; 370 371 err = mlx5e_validate_params(priv, &new_channels.params); 372 if (err) 373 goto unlock; 374 375 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { 376 priv->channels.params = new_channels.params; 377 goto unlock; 378 } 379 380 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL); 381 382 unlock: 383 mutex_unlock(&priv->state_lock); 384 385 return err; 386 } 387 388 static int mlx5e_set_ringparam(struct net_device *dev, 389 struct ethtool_ringparam *param) 390 { 391 struct mlx5e_priv *priv = netdev_priv(dev); 392 393 return mlx5e_ethtool_set_ringparam(priv, param); 394 } 395 396 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv, 397 struct ethtool_channels *ch) 398 { 399 mutex_lock(&priv->state_lock); 400 401 ch->max_combined = priv->max_nch; 402 ch->combined_count = priv->channels.params.num_channels; 403 if (priv->xsk.refcnt) { 404 /* The upper half are XSK queues. */ 405 ch->max_combined *= 2; 406 ch->combined_count *= 2; 407 } 408 409 mutex_unlock(&priv->state_lock); 410 } 411 412 static void mlx5e_get_channels(struct net_device *dev, 413 struct ethtool_channels *ch) 414 { 415 struct mlx5e_priv *priv = netdev_priv(dev); 416 417 mlx5e_ethtool_get_channels(priv, ch); 418 } 419 420 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, 421 struct ethtool_channels *ch) 422 { 423 struct mlx5e_params *cur_params = &priv->channels.params; 424 unsigned int count = ch->combined_count; 425 struct mlx5e_channels new_channels = {}; 426 bool arfs_enabled; 427 int err = 0; 428 429 if (!count) { 430 netdev_info(priv->netdev, "%s: combined_count=0 not supported\n", 431 __func__); 432 return -EINVAL; 433 } 434 435 if (cur_params->num_channels == count) 436 return 0; 437 438 mutex_lock(&priv->state_lock); 439 440 /* Don't allow changing the number of channels if there is an active 441 * XSK, because the numeration of the XSK and regular RQs will change. 442 */ 443 if (priv->xsk.refcnt) { 444 err = -EINVAL; 445 netdev_err(priv->netdev, "%s: AF_XDP is active, cannot change the number of channels\n", 446 __func__); 447 goto out; 448 } 449 450 /* Don't allow changing the number of channels if HTB offload is active, 451 * because the numeration of the QoS SQs will change, while per-queue 452 * qdiscs are attached. 453 */ 454 if (priv->htb.maj_id) { 455 err = -EINVAL; 456 netdev_err(priv->netdev, "%s: HTB offload is active, cannot change the number of channels\n", 457 __func__); 458 goto out; 459 } 460 461 new_channels.params = *cur_params; 462 new_channels.params.num_channels = count; 463 464 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { 465 struct mlx5e_params old_params; 466 467 old_params = *cur_params; 468 *cur_params = new_channels.params; 469 err = mlx5e_num_channels_changed(priv); 470 if (err) 471 *cur_params = old_params; 472 473 goto out; 474 } 475 476 arfs_enabled = priv->netdev->features & NETIF_F_NTUPLE; 477 if (arfs_enabled) 478 mlx5e_arfs_disable(priv); 479 480 /* Switch to new channels, set new parameters and close old ones */ 481 err = mlx5e_safe_switch_channels(priv, &new_channels, 482 mlx5e_num_channels_changed_ctx, NULL); 483 484 if (arfs_enabled) { 485 int err2 = mlx5e_arfs_enable(priv); 486 487 if (err2) 488 netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n", 489 __func__, err2); 490 } 491 492 out: 493 mutex_unlock(&priv->state_lock); 494 495 return err; 496 } 497 498 static int mlx5e_set_channels(struct net_device *dev, 499 struct ethtool_channels *ch) 500 { 501 struct mlx5e_priv *priv = netdev_priv(dev); 502 503 return mlx5e_ethtool_set_channels(priv, ch); 504 } 505 506 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv, 507 struct ethtool_coalesce *coal) 508 { 509 struct dim_cq_moder *rx_moder, *tx_moder; 510 511 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation)) 512 return -EOPNOTSUPP; 513 514 rx_moder = &priv->channels.params.rx_cq_moderation; 515 coal->rx_coalesce_usecs = rx_moder->usec; 516 coal->rx_max_coalesced_frames = rx_moder->pkts; 517 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_dim_enabled; 518 519 tx_moder = &priv->channels.params.tx_cq_moderation; 520 coal->tx_coalesce_usecs = tx_moder->usec; 521 coal->tx_max_coalesced_frames = tx_moder->pkts; 522 coal->use_adaptive_tx_coalesce = priv->channels.params.tx_dim_enabled; 523 524 return 0; 525 } 526 527 static int mlx5e_get_coalesce(struct net_device *netdev, 528 struct ethtool_coalesce *coal) 529 { 530 struct mlx5e_priv *priv = netdev_priv(netdev); 531 532 return mlx5e_ethtool_get_coalesce(priv, coal); 533 } 534 535 #define MLX5E_MAX_COAL_TIME MLX5_MAX_CQ_PERIOD 536 #define MLX5E_MAX_COAL_FRAMES MLX5_MAX_CQ_COUNT 537 538 static void 539 mlx5e_set_priv_channels_tx_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal) 540 { 541 struct mlx5_core_dev *mdev = priv->mdev; 542 int tc; 543 int i; 544 545 for (i = 0; i < priv->channels.num; ++i) { 546 struct mlx5e_channel *c = priv->channels.c[i]; 547 548 for (tc = 0; tc < c->num_tc; tc++) { 549 mlx5_core_modify_cq_moderation(mdev, 550 &c->sq[tc].cq.mcq, 551 coal->tx_coalesce_usecs, 552 coal->tx_max_coalesced_frames); 553 } 554 } 555 } 556 557 static void 558 mlx5e_set_priv_channels_rx_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal) 559 { 560 struct mlx5_core_dev *mdev = priv->mdev; 561 int i; 562 563 for (i = 0; i < priv->channels.num; ++i) { 564 struct mlx5e_channel *c = priv->channels.c[i]; 565 566 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq, 567 coal->rx_coalesce_usecs, 568 coal->rx_max_coalesced_frames); 569 } 570 } 571 572 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, 573 struct ethtool_coalesce *coal) 574 { 575 struct dim_cq_moder *rx_moder, *tx_moder; 576 struct mlx5_core_dev *mdev = priv->mdev; 577 struct mlx5e_channels new_channels = {}; 578 bool reset_rx, reset_tx; 579 int err = 0; 580 581 if (!MLX5_CAP_GEN(mdev, cq_moderation)) 582 return -EOPNOTSUPP; 583 584 if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME || 585 coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) { 586 netdev_info(priv->netdev, "%s: maximum coalesce time supported is %lu usecs\n", 587 __func__, MLX5E_MAX_COAL_TIME); 588 return -ERANGE; 589 } 590 591 if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES || 592 coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) { 593 netdev_info(priv->netdev, "%s: maximum coalesced frames supported is %lu\n", 594 __func__, MLX5E_MAX_COAL_FRAMES); 595 return -ERANGE; 596 } 597 598 mutex_lock(&priv->state_lock); 599 new_channels.params = priv->channels.params; 600 601 rx_moder = &new_channels.params.rx_cq_moderation; 602 rx_moder->usec = coal->rx_coalesce_usecs; 603 rx_moder->pkts = coal->rx_max_coalesced_frames; 604 new_channels.params.rx_dim_enabled = !!coal->use_adaptive_rx_coalesce; 605 606 tx_moder = &new_channels.params.tx_cq_moderation; 607 tx_moder->usec = coal->tx_coalesce_usecs; 608 tx_moder->pkts = coal->tx_max_coalesced_frames; 609 new_channels.params.tx_dim_enabled = !!coal->use_adaptive_tx_coalesce; 610 611 reset_rx = !!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_dim_enabled; 612 reset_tx = !!coal->use_adaptive_tx_coalesce != priv->channels.params.tx_dim_enabled; 613 614 if (reset_rx) { 615 u8 mode = MLX5E_GET_PFLAG(&new_channels.params, 616 MLX5E_PFLAG_RX_CQE_BASED_MODER); 617 618 mlx5e_reset_rx_moderation(&new_channels.params, mode); 619 } 620 if (reset_tx) { 621 u8 mode = MLX5E_GET_PFLAG(&new_channels.params, 622 MLX5E_PFLAG_TX_CQE_BASED_MODER); 623 624 mlx5e_reset_tx_moderation(&new_channels.params, mode); 625 } 626 627 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { 628 priv->channels.params = new_channels.params; 629 goto out; 630 } 631 632 if (!reset_rx && !reset_tx) { 633 if (!coal->use_adaptive_rx_coalesce) 634 mlx5e_set_priv_channels_rx_coalesce(priv, coal); 635 if (!coal->use_adaptive_tx_coalesce) 636 mlx5e_set_priv_channels_tx_coalesce(priv, coal); 637 priv->channels.params = new_channels.params; 638 goto out; 639 } 640 641 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL); 642 643 out: 644 mutex_unlock(&priv->state_lock); 645 return err; 646 } 647 648 static int mlx5e_set_coalesce(struct net_device *netdev, 649 struct ethtool_coalesce *coal) 650 { 651 struct mlx5e_priv *priv = netdev_priv(netdev); 652 653 return mlx5e_ethtool_set_coalesce(priv, coal); 654 } 655 656 static void ptys2ethtool_supported_link(struct mlx5_core_dev *mdev, 657 unsigned long *supported_modes, 658 u32 eth_proto_cap) 659 { 660 unsigned long proto_cap = eth_proto_cap; 661 struct ptys2ethtool_config *table; 662 u32 max_size; 663 int proto; 664 665 mlx5e_ethtool_get_speed_arr(mdev, &table, &max_size); 666 for_each_set_bit(proto, &proto_cap, max_size) 667 bitmap_or(supported_modes, supported_modes, 668 table[proto].supported, 669 __ETHTOOL_LINK_MODE_MASK_NBITS); 670 } 671 672 static void ptys2ethtool_adver_link(unsigned long *advertising_modes, 673 u32 eth_proto_cap, bool ext) 674 { 675 unsigned long proto_cap = eth_proto_cap; 676 struct ptys2ethtool_config *table; 677 u32 max_size; 678 int proto; 679 680 table = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table; 681 max_size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) : 682 ARRAY_SIZE(ptys2legacy_ethtool_table); 683 684 for_each_set_bit(proto, &proto_cap, max_size) 685 bitmap_or(advertising_modes, advertising_modes, 686 table[proto].advertised, 687 __ETHTOOL_LINK_MODE_MASK_NBITS); 688 } 689 690 static const u32 pplm_fec_2_ethtool[] = { 691 [MLX5E_FEC_NOFEC] = ETHTOOL_FEC_OFF, 692 [MLX5E_FEC_FIRECODE] = ETHTOOL_FEC_BASER, 693 [MLX5E_FEC_RS_528_514] = ETHTOOL_FEC_RS, 694 [MLX5E_FEC_RS_544_514] = ETHTOOL_FEC_RS, 695 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_FEC_LLRS, 696 }; 697 698 static u32 pplm2ethtool_fec(u_long fec_mode, unsigned long size) 699 { 700 int mode = 0; 701 702 if (!fec_mode) 703 return ETHTOOL_FEC_AUTO; 704 705 mode = find_first_bit(&fec_mode, size); 706 707 if (mode < ARRAY_SIZE(pplm_fec_2_ethtool)) 708 return pplm_fec_2_ethtool[mode]; 709 710 return 0; 711 } 712 713 #define MLX5E_ADVERTISE_SUPPORTED_FEC(mlx5_fec, ethtool_fec) \ 714 do { \ 715 if (mlx5e_fec_in_caps(dev, 1 << (mlx5_fec))) \ 716 __set_bit(ethtool_fec, \ 717 link_ksettings->link_modes.supported);\ 718 } while (0) 719 720 static const u32 pplm_fec_2_ethtool_linkmodes[] = { 721 [MLX5E_FEC_NOFEC] = ETHTOOL_LINK_MODE_FEC_NONE_BIT, 722 [MLX5E_FEC_FIRECODE] = ETHTOOL_LINK_MODE_FEC_BASER_BIT, 723 [MLX5E_FEC_RS_528_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT, 724 [MLX5E_FEC_RS_544_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT, 725 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_LINK_MODE_FEC_LLRS_BIT, 726 }; 727 728 static int get_fec_supported_advertised(struct mlx5_core_dev *dev, 729 struct ethtool_link_ksettings *link_ksettings) 730 { 731 unsigned long active_fec_long; 732 u32 active_fec; 733 u32 bitn; 734 int err; 735 736 err = mlx5e_get_fec_mode(dev, &active_fec, NULL); 737 if (err) 738 return (err == -EOPNOTSUPP) ? 0 : err; 739 740 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_NOFEC, 741 ETHTOOL_LINK_MODE_FEC_NONE_BIT); 742 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_FIRECODE, 743 ETHTOOL_LINK_MODE_FEC_BASER_BIT); 744 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_RS_528_514, 745 ETHTOOL_LINK_MODE_FEC_RS_BIT); 746 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_LLRS_272_257_1, 747 ETHTOOL_LINK_MODE_FEC_LLRS_BIT); 748 749 active_fec_long = active_fec; 750 /* active fec is a bit set, find out which bit is set and 751 * advertise the corresponding ethtool bit 752 */ 753 bitn = find_first_bit(&active_fec_long, sizeof(active_fec_long) * BITS_PER_BYTE); 754 if (bitn < ARRAY_SIZE(pplm_fec_2_ethtool_linkmodes)) 755 __set_bit(pplm_fec_2_ethtool_linkmodes[bitn], 756 link_ksettings->link_modes.advertising); 757 758 return 0; 759 } 760 761 static void ptys2ethtool_supported_advertised_port(struct ethtool_link_ksettings *link_ksettings, 762 u32 eth_proto_cap, 763 u8 connector_type, bool ext) 764 { 765 if ((!connector_type && !ext) || connector_type >= MLX5E_CONNECTOR_TYPE_NUMBER) { 766 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR) 767 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR) 768 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) 769 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) 770 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) 771 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) { 772 ethtool_link_ksettings_add_link_mode(link_ksettings, 773 supported, 774 FIBRE); 775 ethtool_link_ksettings_add_link_mode(link_ksettings, 776 advertising, 777 FIBRE); 778 } 779 780 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4) 781 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) 782 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR) 783 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) 784 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) { 785 ethtool_link_ksettings_add_link_mode(link_ksettings, 786 supported, 787 Backplane); 788 ethtool_link_ksettings_add_link_mode(link_ksettings, 789 advertising, 790 Backplane); 791 } 792 return; 793 } 794 795 switch (connector_type) { 796 case MLX5E_PORT_TP: 797 ethtool_link_ksettings_add_link_mode(link_ksettings, 798 supported, TP); 799 ethtool_link_ksettings_add_link_mode(link_ksettings, 800 advertising, TP); 801 break; 802 case MLX5E_PORT_AUI: 803 ethtool_link_ksettings_add_link_mode(link_ksettings, 804 supported, AUI); 805 ethtool_link_ksettings_add_link_mode(link_ksettings, 806 advertising, AUI); 807 break; 808 case MLX5E_PORT_BNC: 809 ethtool_link_ksettings_add_link_mode(link_ksettings, 810 supported, BNC); 811 ethtool_link_ksettings_add_link_mode(link_ksettings, 812 advertising, BNC); 813 break; 814 case MLX5E_PORT_MII: 815 ethtool_link_ksettings_add_link_mode(link_ksettings, 816 supported, MII); 817 ethtool_link_ksettings_add_link_mode(link_ksettings, 818 advertising, MII); 819 break; 820 case MLX5E_PORT_FIBRE: 821 ethtool_link_ksettings_add_link_mode(link_ksettings, 822 supported, FIBRE); 823 ethtool_link_ksettings_add_link_mode(link_ksettings, 824 advertising, FIBRE); 825 break; 826 case MLX5E_PORT_DA: 827 ethtool_link_ksettings_add_link_mode(link_ksettings, 828 supported, Backplane); 829 ethtool_link_ksettings_add_link_mode(link_ksettings, 830 advertising, Backplane); 831 break; 832 case MLX5E_PORT_NONE: 833 case MLX5E_PORT_OTHER: 834 default: 835 break; 836 } 837 } 838 839 static void get_speed_duplex(struct net_device *netdev, 840 u32 eth_proto_oper, bool force_legacy, 841 u16 data_rate_oper, 842 struct ethtool_link_ksettings *link_ksettings) 843 { 844 struct mlx5e_priv *priv = netdev_priv(netdev); 845 u32 speed = SPEED_UNKNOWN; 846 u8 duplex = DUPLEX_UNKNOWN; 847 848 if (!netif_carrier_ok(netdev)) 849 goto out; 850 851 speed = mlx5e_port_ptys2speed(priv->mdev, eth_proto_oper, force_legacy); 852 if (!speed) { 853 if (data_rate_oper) 854 speed = 100 * data_rate_oper; 855 else 856 speed = SPEED_UNKNOWN; 857 goto out; 858 } 859 860 duplex = DUPLEX_FULL; 861 862 out: 863 link_ksettings->base.speed = speed; 864 link_ksettings->base.duplex = duplex; 865 } 866 867 static void get_supported(struct mlx5_core_dev *mdev, u32 eth_proto_cap, 868 struct ethtool_link_ksettings *link_ksettings) 869 { 870 unsigned long *supported = link_ksettings->link_modes.supported; 871 ptys2ethtool_supported_link(mdev, supported, eth_proto_cap); 872 873 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause); 874 } 875 876 static void get_advertising(u32 eth_proto_cap, u8 tx_pause, u8 rx_pause, 877 struct ethtool_link_ksettings *link_ksettings, 878 bool ext) 879 { 880 unsigned long *advertising = link_ksettings->link_modes.advertising; 881 ptys2ethtool_adver_link(advertising, eth_proto_cap, ext); 882 883 if (rx_pause) 884 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause); 885 if (tx_pause ^ rx_pause) 886 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause); 887 } 888 889 static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = { 890 [MLX5E_PORT_UNKNOWN] = PORT_OTHER, 891 [MLX5E_PORT_NONE] = PORT_NONE, 892 [MLX5E_PORT_TP] = PORT_TP, 893 [MLX5E_PORT_AUI] = PORT_AUI, 894 [MLX5E_PORT_BNC] = PORT_BNC, 895 [MLX5E_PORT_MII] = PORT_MII, 896 [MLX5E_PORT_FIBRE] = PORT_FIBRE, 897 [MLX5E_PORT_DA] = PORT_DA, 898 [MLX5E_PORT_OTHER] = PORT_OTHER, 899 }; 900 901 static u8 get_connector_port(u32 eth_proto, u8 connector_type, bool ext) 902 { 903 if ((connector_type || ext) && connector_type < MLX5E_CONNECTOR_TYPE_NUMBER) 904 return ptys2connector_type[connector_type]; 905 906 if (eth_proto & 907 (MLX5E_PROT_MASK(MLX5E_10GBASE_SR) | 908 MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) | 909 MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) | 910 MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) { 911 return PORT_FIBRE; 912 } 913 914 if (eth_proto & 915 (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) | 916 MLX5E_PROT_MASK(MLX5E_10GBASE_CR) | 917 MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) { 918 return PORT_DA; 919 } 920 921 if (eth_proto & 922 (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) | 923 MLX5E_PROT_MASK(MLX5E_10GBASE_KR) | 924 MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) | 925 MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) { 926 return PORT_NONE; 927 } 928 929 return PORT_OTHER; 930 } 931 932 static void get_lp_advertising(struct mlx5_core_dev *mdev, u32 eth_proto_lp, 933 struct ethtool_link_ksettings *link_ksettings) 934 { 935 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising; 936 bool ext = mlx5e_ptys_ext_supported(mdev); 937 938 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp, ext); 939 } 940 941 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv, 942 struct ethtool_link_ksettings *link_ksettings) 943 { 944 struct mlx5_core_dev *mdev = priv->mdev; 945 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {}; 946 u32 eth_proto_admin; 947 u8 an_disable_admin; 948 u16 data_rate_oper; 949 u32 eth_proto_oper; 950 u32 eth_proto_cap; 951 u8 connector_type; 952 u32 rx_pause = 0; 953 u32 tx_pause = 0; 954 u32 eth_proto_lp; 955 bool admin_ext; 956 u8 an_status; 957 bool ext; 958 int err; 959 960 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1); 961 if (err) { 962 netdev_err(priv->netdev, "%s: query port ptys failed: %d\n", 963 __func__, err); 964 goto err_query_regs; 965 } 966 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability); 967 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 968 eth_proto_capability); 969 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, 970 eth_proto_admin); 971 /* Fields: eth_proto_admin and ext_eth_proto_admin are 972 * mutually exclusive. Hence try reading legacy advertising 973 * when extended advertising is zero. 974 * admin_ext indicates which proto_admin (ext vs. legacy) 975 * should be read and interpreted 976 */ 977 admin_ext = ext; 978 if (ext && !eth_proto_admin) { 979 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, false, 980 eth_proto_admin); 981 admin_ext = false; 982 } 983 984 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, admin_ext, 985 eth_proto_oper); 986 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise); 987 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin); 988 an_status = MLX5_GET(ptys_reg, out, an_status); 989 connector_type = MLX5_GET(ptys_reg, out, connector_type); 990 data_rate_oper = MLX5_GET(ptys_reg, out, data_rate_oper); 991 992 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause); 993 994 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported); 995 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising); 996 997 get_supported(mdev, eth_proto_cap, link_ksettings); 998 get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings, 999 admin_ext); 1000 get_speed_duplex(priv->netdev, eth_proto_oper, !admin_ext, 1001 data_rate_oper, link_ksettings); 1002 1003 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap; 1004 1005 link_ksettings->base.port = get_connector_port(eth_proto_oper, 1006 connector_type, ext); 1007 ptys2ethtool_supported_advertised_port(link_ksettings, eth_proto_admin, 1008 connector_type, ext); 1009 get_lp_advertising(mdev, eth_proto_lp, link_ksettings); 1010 1011 if (an_status == MLX5_AN_COMPLETE) 1012 ethtool_link_ksettings_add_link_mode(link_ksettings, 1013 lp_advertising, Autoneg); 1014 1015 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE : 1016 AUTONEG_ENABLE; 1017 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, 1018 Autoneg); 1019 1020 err = get_fec_supported_advertised(mdev, link_ksettings); 1021 if (err) { 1022 netdev_dbg(priv->netdev, "%s: FEC caps query failed: %d\n", 1023 __func__, err); 1024 err = 0; /* don't fail caps query because of FEC error */ 1025 } 1026 1027 if (!an_disable_admin) 1028 ethtool_link_ksettings_add_link_mode(link_ksettings, 1029 advertising, Autoneg); 1030 1031 err_query_regs: 1032 return err; 1033 } 1034 1035 static int mlx5e_get_link_ksettings(struct net_device *netdev, 1036 struct ethtool_link_ksettings *link_ksettings) 1037 { 1038 struct mlx5e_priv *priv = netdev_priv(netdev); 1039 1040 return mlx5e_ethtool_get_link_ksettings(priv, link_ksettings); 1041 } 1042 1043 static int mlx5e_speed_validate(struct net_device *netdev, bool ext, 1044 const unsigned long link_modes, u8 autoneg) 1045 { 1046 /* Extended link-mode has no speed limitations. */ 1047 if (ext) 1048 return 0; 1049 1050 if ((link_modes & MLX5E_PROT_MASK(MLX5E_56GBASE_R4)) && 1051 autoneg != AUTONEG_ENABLE) { 1052 netdev_err(netdev, "%s: 56G link speed requires autoneg enabled\n", 1053 __func__); 1054 return -EINVAL; 1055 } 1056 return 0; 1057 } 1058 1059 static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes) 1060 { 1061 u32 i, ptys_modes = 0; 1062 1063 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) { 1064 if (*ptys2legacy_ethtool_table[i].advertised == 0) 1065 continue; 1066 if (bitmap_intersects(ptys2legacy_ethtool_table[i].advertised, 1067 link_modes, 1068 __ETHTOOL_LINK_MODE_MASK_NBITS)) 1069 ptys_modes |= MLX5E_PROT_MASK(i); 1070 } 1071 1072 return ptys_modes; 1073 } 1074 1075 static u32 mlx5e_ethtool2ptys_ext_adver_link(const unsigned long *link_modes) 1076 { 1077 u32 i, ptys_modes = 0; 1078 unsigned long modes[2]; 1079 1080 for (i = 0; i < MLX5E_EXT_LINK_MODES_NUMBER; ++i) { 1081 if (ptys2ext_ethtool_table[i].advertised[0] == 0 && 1082 ptys2ext_ethtool_table[i].advertised[1] == 0) 1083 continue; 1084 memset(modes, 0, sizeof(modes)); 1085 bitmap_and(modes, ptys2ext_ethtool_table[i].advertised, 1086 link_modes, __ETHTOOL_LINK_MODE_MASK_NBITS); 1087 1088 if (modes[0] == ptys2ext_ethtool_table[i].advertised[0] && 1089 modes[1] == ptys2ext_ethtool_table[i].advertised[1]) 1090 ptys_modes |= MLX5E_PROT_MASK(i); 1091 } 1092 return ptys_modes; 1093 } 1094 1095 static bool ext_link_mode_requested(const unsigned long *adver) 1096 { 1097 #define MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT ETHTOOL_LINK_MODE_50000baseKR_Full_BIT 1098 int size = __ETHTOOL_LINK_MODE_MASK_NBITS - MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT; 1099 __ETHTOOL_DECLARE_LINK_MODE_MASK(modes) = {0,}; 1100 1101 bitmap_set(modes, MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT, size); 1102 return bitmap_intersects(modes, adver, __ETHTOOL_LINK_MODE_MASK_NBITS); 1103 } 1104 1105 static bool ext_requested(u8 autoneg, const unsigned long *adver, bool ext_supported) 1106 { 1107 bool ext_link_mode = ext_link_mode_requested(adver); 1108 1109 return autoneg == AUTONEG_ENABLE ? ext_link_mode : ext_supported; 1110 } 1111 1112 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv, 1113 const struct ethtool_link_ksettings *link_ksettings) 1114 { 1115 struct mlx5_core_dev *mdev = priv->mdev; 1116 struct mlx5e_port_eth_proto eproto; 1117 const unsigned long *adver; 1118 bool an_changes = false; 1119 u8 an_disable_admin; 1120 bool ext_supported; 1121 u8 an_disable_cap; 1122 bool an_disable; 1123 u32 link_modes; 1124 u8 an_status; 1125 u8 autoneg; 1126 u32 speed; 1127 bool ext; 1128 int err; 1129 1130 u32 (*ethtool2ptys_adver_func)(const unsigned long *adver); 1131 1132 adver = link_ksettings->link_modes.advertising; 1133 autoneg = link_ksettings->base.autoneg; 1134 speed = link_ksettings->base.speed; 1135 1136 ext_supported = mlx5e_ptys_ext_supported(mdev); 1137 ext = ext_requested(autoneg, adver, ext_supported); 1138 if (!ext_supported && ext) 1139 return -EOPNOTSUPP; 1140 1141 ethtool2ptys_adver_func = ext ? mlx5e_ethtool2ptys_ext_adver_link : 1142 mlx5e_ethtool2ptys_adver_link; 1143 err = mlx5_port_query_eth_proto(mdev, 1, ext, &eproto); 1144 if (err) { 1145 netdev_err(priv->netdev, "%s: query port eth proto failed: %d\n", 1146 __func__, err); 1147 goto out; 1148 } 1149 link_modes = autoneg == AUTONEG_ENABLE ? ethtool2ptys_adver_func(adver) : 1150 mlx5e_port_speed2linkmodes(mdev, speed, !ext); 1151 1152 err = mlx5e_speed_validate(priv->netdev, ext, link_modes, autoneg); 1153 if (err) 1154 goto out; 1155 1156 link_modes = link_modes & eproto.cap; 1157 if (!link_modes) { 1158 netdev_err(priv->netdev, "%s: Not supported link mode(s) requested", 1159 __func__); 1160 err = -EINVAL; 1161 goto out; 1162 } 1163 1164 mlx5_port_query_eth_autoneg(mdev, &an_status, &an_disable_cap, 1165 &an_disable_admin); 1166 1167 an_disable = autoneg == AUTONEG_DISABLE; 1168 an_changes = ((!an_disable && an_disable_admin) || 1169 (an_disable && !an_disable_admin)); 1170 1171 if (!an_changes && link_modes == eproto.admin) 1172 goto out; 1173 1174 mlx5_port_set_eth_ptys(mdev, an_disable, link_modes, ext); 1175 mlx5_toggle_port_link(mdev); 1176 1177 out: 1178 return err; 1179 } 1180 1181 static int mlx5e_set_link_ksettings(struct net_device *netdev, 1182 const struct ethtool_link_ksettings *link_ksettings) 1183 { 1184 struct mlx5e_priv *priv = netdev_priv(netdev); 1185 1186 return mlx5e_ethtool_set_link_ksettings(priv, link_ksettings); 1187 } 1188 1189 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv) 1190 { 1191 return sizeof(priv->rss_params.toeplitz_hash_key); 1192 } 1193 1194 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev) 1195 { 1196 struct mlx5e_priv *priv = netdev_priv(netdev); 1197 1198 return mlx5e_ethtool_get_rxfh_key_size(priv); 1199 } 1200 1201 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv) 1202 { 1203 return MLX5E_INDIR_RQT_SIZE; 1204 } 1205 1206 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev) 1207 { 1208 struct mlx5e_priv *priv = netdev_priv(netdev); 1209 1210 return mlx5e_ethtool_get_rxfh_indir_size(priv); 1211 } 1212 1213 int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, 1214 u8 *hfunc) 1215 { 1216 struct mlx5e_priv *priv = netdev_priv(netdev); 1217 struct mlx5e_rss_params *rss = &priv->rss_params; 1218 1219 if (indir) 1220 memcpy(indir, rss->indirection_rqt, 1221 sizeof(rss->indirection_rqt)); 1222 1223 if (key) 1224 memcpy(key, rss->toeplitz_hash_key, 1225 sizeof(rss->toeplitz_hash_key)); 1226 1227 if (hfunc) 1228 *hfunc = rss->hfunc; 1229 1230 return 0; 1231 } 1232 1233 int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir, 1234 const u8 *key, const u8 hfunc) 1235 { 1236 struct mlx5e_priv *priv = netdev_priv(dev); 1237 struct mlx5e_rss_params *rss = &priv->rss_params; 1238 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in); 1239 bool refresh_tirs = false; 1240 bool refresh_rqt = false; 1241 void *in; 1242 1243 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) && 1244 (hfunc != ETH_RSS_HASH_XOR) && 1245 (hfunc != ETH_RSS_HASH_TOP)) 1246 return -EINVAL; 1247 1248 in = kvzalloc(inlen, GFP_KERNEL); 1249 if (!in) 1250 return -ENOMEM; 1251 1252 mutex_lock(&priv->state_lock); 1253 1254 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != rss->hfunc) { 1255 rss->hfunc = hfunc; 1256 refresh_rqt = true; 1257 refresh_tirs = true; 1258 } 1259 1260 if (indir) { 1261 memcpy(rss->indirection_rqt, indir, 1262 sizeof(rss->indirection_rqt)); 1263 refresh_rqt = true; 1264 } 1265 1266 if (key) { 1267 memcpy(rss->toeplitz_hash_key, key, 1268 sizeof(rss->toeplitz_hash_key)); 1269 refresh_tirs = refresh_tirs || rss->hfunc == ETH_RSS_HASH_TOP; 1270 } 1271 1272 if (refresh_rqt && test_bit(MLX5E_STATE_OPENED, &priv->state)) { 1273 struct mlx5e_redirect_rqt_param rrp = { 1274 .is_rss = true, 1275 { 1276 .rss = { 1277 .hfunc = rss->hfunc, 1278 .channels = &priv->channels, 1279 }, 1280 }, 1281 }; 1282 u32 rqtn = priv->indir_rqt.rqtn; 1283 1284 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp); 1285 } 1286 1287 if (refresh_tirs) 1288 mlx5e_modify_tirs_hash(priv, in); 1289 1290 mutex_unlock(&priv->state_lock); 1291 1292 kvfree(in); 1293 1294 return 0; 1295 } 1296 1297 #define MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC 100 1298 #define MLX5E_PFC_PREVEN_TOUT_MAX_MSEC 8000 1299 #define MLX5E_PFC_PREVEN_MINOR_PRECENT 85 1300 #define MLX5E_PFC_PREVEN_TOUT_MIN_MSEC 80 1301 #define MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout) \ 1302 max_t(u16, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, \ 1303 (critical_tout * MLX5E_PFC_PREVEN_MINOR_PRECENT) / 100) 1304 1305 static int mlx5e_get_pfc_prevention_tout(struct net_device *netdev, 1306 u16 *pfc_prevention_tout) 1307 { 1308 struct mlx5e_priv *priv = netdev_priv(netdev); 1309 struct mlx5_core_dev *mdev = priv->mdev; 1310 1311 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) || 1312 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect)) 1313 return -EOPNOTSUPP; 1314 1315 return mlx5_query_port_stall_watermark(mdev, pfc_prevention_tout, NULL); 1316 } 1317 1318 static int mlx5e_set_pfc_prevention_tout(struct net_device *netdev, 1319 u16 pfc_preven) 1320 { 1321 struct mlx5e_priv *priv = netdev_priv(netdev); 1322 struct mlx5_core_dev *mdev = priv->mdev; 1323 u16 critical_tout; 1324 u16 minor; 1325 1326 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) || 1327 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect)) 1328 return -EOPNOTSUPP; 1329 1330 critical_tout = (pfc_preven == PFC_STORM_PREVENTION_AUTO) ? 1331 MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC : 1332 pfc_preven; 1333 1334 if (critical_tout != PFC_STORM_PREVENTION_DISABLE && 1335 (critical_tout > MLX5E_PFC_PREVEN_TOUT_MAX_MSEC || 1336 critical_tout < MLX5E_PFC_PREVEN_TOUT_MIN_MSEC)) { 1337 netdev_info(netdev, "%s: pfc prevention tout not in range (%d-%d)\n", 1338 __func__, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, 1339 MLX5E_PFC_PREVEN_TOUT_MAX_MSEC); 1340 return -EINVAL; 1341 } 1342 1343 minor = MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout); 1344 return mlx5_set_port_stall_watermark(mdev, critical_tout, 1345 minor); 1346 } 1347 1348 static int mlx5e_get_tunable(struct net_device *dev, 1349 const struct ethtool_tunable *tuna, 1350 void *data) 1351 { 1352 int err; 1353 1354 switch (tuna->id) { 1355 case ETHTOOL_PFC_PREVENTION_TOUT: 1356 err = mlx5e_get_pfc_prevention_tout(dev, data); 1357 break; 1358 default: 1359 err = -EINVAL; 1360 break; 1361 } 1362 1363 return err; 1364 } 1365 1366 static int mlx5e_set_tunable(struct net_device *dev, 1367 const struct ethtool_tunable *tuna, 1368 const void *data) 1369 { 1370 struct mlx5e_priv *priv = netdev_priv(dev); 1371 int err; 1372 1373 mutex_lock(&priv->state_lock); 1374 1375 switch (tuna->id) { 1376 case ETHTOOL_PFC_PREVENTION_TOUT: 1377 err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data); 1378 break; 1379 default: 1380 err = -EINVAL; 1381 break; 1382 } 1383 1384 mutex_unlock(&priv->state_lock); 1385 return err; 1386 } 1387 1388 static void mlx5e_get_pause_stats(struct net_device *netdev, 1389 struct ethtool_pause_stats *pause_stats) 1390 { 1391 struct mlx5e_priv *priv = netdev_priv(netdev); 1392 1393 mlx5e_stats_pause_get(priv, pause_stats); 1394 } 1395 1396 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv, 1397 struct ethtool_pauseparam *pauseparam) 1398 { 1399 struct mlx5_core_dev *mdev = priv->mdev; 1400 int err; 1401 1402 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause, 1403 &pauseparam->tx_pause); 1404 if (err) { 1405 netdev_err(priv->netdev, "%s: mlx5_query_port_pause failed:0x%x\n", 1406 __func__, err); 1407 } 1408 } 1409 1410 static void mlx5e_get_pauseparam(struct net_device *netdev, 1411 struct ethtool_pauseparam *pauseparam) 1412 { 1413 struct mlx5e_priv *priv = netdev_priv(netdev); 1414 1415 mlx5e_ethtool_get_pauseparam(priv, pauseparam); 1416 } 1417 1418 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv, 1419 struct ethtool_pauseparam *pauseparam) 1420 { 1421 struct mlx5_core_dev *mdev = priv->mdev; 1422 int err; 1423 1424 if (!MLX5_CAP_GEN(mdev, vport_group_manager)) 1425 return -EOPNOTSUPP; 1426 1427 if (pauseparam->autoneg) 1428 return -EINVAL; 1429 1430 err = mlx5_set_port_pause(mdev, 1431 pauseparam->rx_pause ? 1 : 0, 1432 pauseparam->tx_pause ? 1 : 0); 1433 if (err) { 1434 netdev_err(priv->netdev, "%s: mlx5_set_port_pause failed:0x%x\n", 1435 __func__, err); 1436 } 1437 1438 return err; 1439 } 1440 1441 static int mlx5e_set_pauseparam(struct net_device *netdev, 1442 struct ethtool_pauseparam *pauseparam) 1443 { 1444 struct mlx5e_priv *priv = netdev_priv(netdev); 1445 1446 return mlx5e_ethtool_set_pauseparam(priv, pauseparam); 1447 } 1448 1449 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv, 1450 struct ethtool_ts_info *info) 1451 { 1452 struct mlx5_core_dev *mdev = priv->mdev; 1453 1454 info->phc_index = mlx5_clock_get_ptp_index(mdev); 1455 1456 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) || 1457 info->phc_index == -1) 1458 return 0; 1459 1460 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE | 1461 SOF_TIMESTAMPING_RX_HARDWARE | 1462 SOF_TIMESTAMPING_RAW_HARDWARE; 1463 1464 info->tx_types = BIT(HWTSTAMP_TX_OFF) | 1465 BIT(HWTSTAMP_TX_ON); 1466 1467 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | 1468 BIT(HWTSTAMP_FILTER_ALL); 1469 1470 return 0; 1471 } 1472 1473 static int mlx5e_get_ts_info(struct net_device *dev, 1474 struct ethtool_ts_info *info) 1475 { 1476 struct mlx5e_priv *priv = netdev_priv(dev); 1477 1478 return mlx5e_ethtool_get_ts_info(priv, info); 1479 } 1480 1481 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev) 1482 { 1483 __u32 ret = 0; 1484 1485 if (MLX5_CAP_GEN(mdev, wol_g)) 1486 ret |= WAKE_MAGIC; 1487 1488 if (MLX5_CAP_GEN(mdev, wol_s)) 1489 ret |= WAKE_MAGICSECURE; 1490 1491 if (MLX5_CAP_GEN(mdev, wol_a)) 1492 ret |= WAKE_ARP; 1493 1494 if (MLX5_CAP_GEN(mdev, wol_b)) 1495 ret |= WAKE_BCAST; 1496 1497 if (MLX5_CAP_GEN(mdev, wol_m)) 1498 ret |= WAKE_MCAST; 1499 1500 if (MLX5_CAP_GEN(mdev, wol_u)) 1501 ret |= WAKE_UCAST; 1502 1503 if (MLX5_CAP_GEN(mdev, wol_p)) 1504 ret |= WAKE_PHY; 1505 1506 return ret; 1507 } 1508 1509 static __u32 mlx5e_reformat_wol_mode_mlx5_to_linux(u8 mode) 1510 { 1511 __u32 ret = 0; 1512 1513 if (mode & MLX5_WOL_MAGIC) 1514 ret |= WAKE_MAGIC; 1515 1516 if (mode & MLX5_WOL_SECURED_MAGIC) 1517 ret |= WAKE_MAGICSECURE; 1518 1519 if (mode & MLX5_WOL_ARP) 1520 ret |= WAKE_ARP; 1521 1522 if (mode & MLX5_WOL_BROADCAST) 1523 ret |= WAKE_BCAST; 1524 1525 if (mode & MLX5_WOL_MULTICAST) 1526 ret |= WAKE_MCAST; 1527 1528 if (mode & MLX5_WOL_UNICAST) 1529 ret |= WAKE_UCAST; 1530 1531 if (mode & MLX5_WOL_PHY_ACTIVITY) 1532 ret |= WAKE_PHY; 1533 1534 return ret; 1535 } 1536 1537 static u8 mlx5e_reformat_wol_mode_linux_to_mlx5(__u32 mode) 1538 { 1539 u8 ret = 0; 1540 1541 if (mode & WAKE_MAGIC) 1542 ret |= MLX5_WOL_MAGIC; 1543 1544 if (mode & WAKE_MAGICSECURE) 1545 ret |= MLX5_WOL_SECURED_MAGIC; 1546 1547 if (mode & WAKE_ARP) 1548 ret |= MLX5_WOL_ARP; 1549 1550 if (mode & WAKE_BCAST) 1551 ret |= MLX5_WOL_BROADCAST; 1552 1553 if (mode & WAKE_MCAST) 1554 ret |= MLX5_WOL_MULTICAST; 1555 1556 if (mode & WAKE_UCAST) 1557 ret |= MLX5_WOL_UNICAST; 1558 1559 if (mode & WAKE_PHY) 1560 ret |= MLX5_WOL_PHY_ACTIVITY; 1561 1562 return ret; 1563 } 1564 1565 static void mlx5e_get_wol(struct net_device *netdev, 1566 struct ethtool_wolinfo *wol) 1567 { 1568 struct mlx5e_priv *priv = netdev_priv(netdev); 1569 struct mlx5_core_dev *mdev = priv->mdev; 1570 u8 mlx5_wol_mode; 1571 int err; 1572 1573 memset(wol, 0, sizeof(*wol)); 1574 1575 wol->supported = mlx5e_get_wol_supported(mdev); 1576 if (!wol->supported) 1577 return; 1578 1579 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode); 1580 if (err) 1581 return; 1582 1583 wol->wolopts = mlx5e_reformat_wol_mode_mlx5_to_linux(mlx5_wol_mode); 1584 } 1585 1586 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 1587 { 1588 struct mlx5e_priv *priv = netdev_priv(netdev); 1589 struct mlx5_core_dev *mdev = priv->mdev; 1590 __u32 wol_supported = mlx5e_get_wol_supported(mdev); 1591 u32 mlx5_wol_mode; 1592 1593 if (!wol_supported) 1594 return -EOPNOTSUPP; 1595 1596 if (wol->wolopts & ~wol_supported) 1597 return -EINVAL; 1598 1599 mlx5_wol_mode = mlx5e_reformat_wol_mode_linux_to_mlx5(wol->wolopts); 1600 1601 return mlx5_set_port_wol(mdev, mlx5_wol_mode); 1602 } 1603 1604 static int mlx5e_get_fecparam(struct net_device *netdev, 1605 struct ethtool_fecparam *fecparam) 1606 { 1607 struct mlx5e_priv *priv = netdev_priv(netdev); 1608 struct mlx5_core_dev *mdev = priv->mdev; 1609 u16 fec_configured; 1610 u32 fec_active; 1611 int err; 1612 1613 err = mlx5e_get_fec_mode(mdev, &fec_active, &fec_configured); 1614 1615 if (err) 1616 return err; 1617 1618 fecparam->active_fec = pplm2ethtool_fec((unsigned long)fec_active, 1619 sizeof(unsigned long) * BITS_PER_BYTE); 1620 1621 if (!fecparam->active_fec) 1622 return -EOPNOTSUPP; 1623 1624 fecparam->fec = pplm2ethtool_fec((unsigned long)fec_configured, 1625 sizeof(unsigned long) * BITS_PER_BYTE); 1626 1627 return 0; 1628 } 1629 1630 static int mlx5e_set_fecparam(struct net_device *netdev, 1631 struct ethtool_fecparam *fecparam) 1632 { 1633 struct mlx5e_priv *priv = netdev_priv(netdev); 1634 struct mlx5_core_dev *mdev = priv->mdev; 1635 u16 fec_policy = 0; 1636 int mode; 1637 int err; 1638 1639 if (bitmap_weight((unsigned long *)&fecparam->fec, 1640 ETHTOOL_FEC_LLRS_BIT + 1) > 1) 1641 return -EOPNOTSUPP; 1642 1643 for (mode = 0; mode < ARRAY_SIZE(pplm_fec_2_ethtool); mode++) { 1644 if (!(pplm_fec_2_ethtool[mode] & fecparam->fec)) 1645 continue; 1646 fec_policy |= (1 << mode); 1647 break; 1648 } 1649 1650 err = mlx5e_set_fec_mode(mdev, fec_policy); 1651 1652 if (err) 1653 return err; 1654 1655 mlx5_toggle_port_link(mdev); 1656 1657 return 0; 1658 } 1659 1660 static u32 mlx5e_get_msglevel(struct net_device *dev) 1661 { 1662 return ((struct mlx5e_priv *)netdev_priv(dev))->msglevel; 1663 } 1664 1665 static void mlx5e_set_msglevel(struct net_device *dev, u32 val) 1666 { 1667 ((struct mlx5e_priv *)netdev_priv(dev))->msglevel = val; 1668 } 1669 1670 static int mlx5e_set_phys_id(struct net_device *dev, 1671 enum ethtool_phys_id_state state) 1672 { 1673 struct mlx5e_priv *priv = netdev_priv(dev); 1674 struct mlx5_core_dev *mdev = priv->mdev; 1675 u16 beacon_duration; 1676 1677 if (!MLX5_CAP_GEN(mdev, beacon_led)) 1678 return -EOPNOTSUPP; 1679 1680 switch (state) { 1681 case ETHTOOL_ID_ACTIVE: 1682 beacon_duration = MLX5_BEACON_DURATION_INF; 1683 break; 1684 case ETHTOOL_ID_INACTIVE: 1685 beacon_duration = MLX5_BEACON_DURATION_OFF; 1686 break; 1687 default: 1688 return -EOPNOTSUPP; 1689 } 1690 1691 return mlx5_set_port_beacon(mdev, beacon_duration); 1692 } 1693 1694 static int mlx5e_get_module_info(struct net_device *netdev, 1695 struct ethtool_modinfo *modinfo) 1696 { 1697 struct mlx5e_priv *priv = netdev_priv(netdev); 1698 struct mlx5_core_dev *dev = priv->mdev; 1699 int size_read = 0; 1700 u8 data[4] = {0}; 1701 1702 size_read = mlx5_query_module_eeprom(dev, 0, 2, data); 1703 if (size_read < 2) 1704 return -EIO; 1705 1706 /* data[0] = identifier byte */ 1707 switch (data[0]) { 1708 case MLX5_MODULE_ID_QSFP: 1709 modinfo->type = ETH_MODULE_SFF_8436; 1710 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN; 1711 break; 1712 case MLX5_MODULE_ID_QSFP_PLUS: 1713 case MLX5_MODULE_ID_QSFP28: 1714 /* data[1] = revision id */ 1715 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) { 1716 modinfo->type = ETH_MODULE_SFF_8636; 1717 modinfo->eeprom_len = ETH_MODULE_SFF_8636_MAX_LEN; 1718 } else { 1719 modinfo->type = ETH_MODULE_SFF_8436; 1720 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN; 1721 } 1722 break; 1723 case MLX5_MODULE_ID_SFP: 1724 modinfo->type = ETH_MODULE_SFF_8472; 1725 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; 1726 break; 1727 default: 1728 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n", 1729 __func__, data[0]); 1730 return -EINVAL; 1731 } 1732 1733 return 0; 1734 } 1735 1736 static int mlx5e_get_module_eeprom(struct net_device *netdev, 1737 struct ethtool_eeprom *ee, 1738 u8 *data) 1739 { 1740 struct mlx5e_priv *priv = netdev_priv(netdev); 1741 struct mlx5_core_dev *mdev = priv->mdev; 1742 int offset = ee->offset; 1743 int size_read; 1744 int i = 0; 1745 1746 if (!ee->len) 1747 return -EINVAL; 1748 1749 memset(data, 0, ee->len); 1750 1751 while (i < ee->len) { 1752 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i, 1753 data + i); 1754 1755 if (!size_read) 1756 /* Done reading */ 1757 return 0; 1758 1759 if (size_read < 0) { 1760 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n", 1761 __func__, size_read); 1762 return 0; 1763 } 1764 1765 i += size_read; 1766 offset += size_read; 1767 } 1768 1769 return 0; 1770 } 1771 1772 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv, 1773 struct ethtool_flash *flash) 1774 { 1775 struct mlx5_core_dev *mdev = priv->mdev; 1776 struct net_device *dev = priv->netdev; 1777 const struct firmware *fw; 1778 int err; 1779 1780 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS) 1781 return -EOPNOTSUPP; 1782 1783 err = request_firmware_direct(&fw, flash->data, &dev->dev); 1784 if (err) 1785 return err; 1786 1787 dev_hold(dev); 1788 rtnl_unlock(); 1789 1790 err = mlx5_firmware_flash(mdev, fw, NULL); 1791 release_firmware(fw); 1792 1793 rtnl_lock(); 1794 dev_put(dev); 1795 return err; 1796 } 1797 1798 static int mlx5e_flash_device(struct net_device *dev, 1799 struct ethtool_flash *flash) 1800 { 1801 struct mlx5e_priv *priv = netdev_priv(dev); 1802 1803 return mlx5e_ethtool_flash_device(priv, flash); 1804 } 1805 1806 static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable, 1807 bool is_rx_cq) 1808 { 1809 struct mlx5e_priv *priv = netdev_priv(netdev); 1810 struct mlx5_core_dev *mdev = priv->mdev; 1811 struct mlx5e_channels new_channels = {}; 1812 bool mode_changed; 1813 u8 cq_period_mode, current_cq_period_mode; 1814 1815 cq_period_mode = enable ? 1816 MLX5_CQ_PERIOD_MODE_START_FROM_CQE : 1817 MLX5_CQ_PERIOD_MODE_START_FROM_EQE; 1818 current_cq_period_mode = is_rx_cq ? 1819 priv->channels.params.rx_cq_moderation.cq_period_mode : 1820 priv->channels.params.tx_cq_moderation.cq_period_mode; 1821 mode_changed = cq_period_mode != current_cq_period_mode; 1822 1823 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE && 1824 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe)) 1825 return -EOPNOTSUPP; 1826 1827 if (!mode_changed) 1828 return 0; 1829 1830 new_channels.params = priv->channels.params; 1831 if (is_rx_cq) 1832 mlx5e_set_rx_cq_mode_params(&new_channels.params, cq_period_mode); 1833 else 1834 mlx5e_set_tx_cq_mode_params(&new_channels.params, cq_period_mode); 1835 1836 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { 1837 priv->channels.params = new_channels.params; 1838 return 0; 1839 } 1840 1841 return mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL); 1842 } 1843 1844 static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable) 1845 { 1846 return set_pflag_cqe_based_moder(netdev, enable, false); 1847 } 1848 1849 static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable) 1850 { 1851 return set_pflag_cqe_based_moder(netdev, enable, true); 1852 } 1853 1854 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val) 1855 { 1856 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS); 1857 struct mlx5e_channels new_channels = {}; 1858 int err = 0; 1859 1860 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression)) 1861 return new_val ? -EOPNOTSUPP : 0; 1862 1863 if (curr_val == new_val) 1864 return 0; 1865 1866 new_channels.params = priv->channels.params; 1867 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val); 1868 1869 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { 1870 priv->channels.params = new_channels.params; 1871 return 0; 1872 } 1873 1874 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL); 1875 if (err) 1876 return err; 1877 1878 mlx5e_dbg(DRV, priv, "MLX5E: RxCqeCmprss was turned %s\n", 1879 MLX5E_GET_PFLAG(&priv->channels.params, 1880 MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF"); 1881 1882 return 0; 1883 } 1884 1885 static int set_pflag_rx_cqe_compress(struct net_device *netdev, 1886 bool enable) 1887 { 1888 struct mlx5e_priv *priv = netdev_priv(netdev); 1889 struct mlx5_core_dev *mdev = priv->mdev; 1890 1891 if (!MLX5_CAP_GEN(mdev, cqe_compression)) 1892 return -EOPNOTSUPP; 1893 1894 if (enable && priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE) { 1895 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n"); 1896 return -EINVAL; 1897 } 1898 1899 mlx5e_modify_rx_cqe_compression_locked(priv, enable); 1900 priv->channels.params.rx_cqe_compress_def = enable; 1901 1902 return 0; 1903 } 1904 1905 static int set_pflag_rx_striding_rq(struct net_device *netdev, bool enable) 1906 { 1907 struct mlx5e_priv *priv = netdev_priv(netdev); 1908 struct mlx5_core_dev *mdev = priv->mdev; 1909 struct mlx5e_channels new_channels = {}; 1910 1911 if (enable) { 1912 if (!mlx5e_check_fragmented_striding_rq_cap(mdev)) 1913 return -EOPNOTSUPP; 1914 if (!mlx5e_striding_rq_possible(mdev, &priv->channels.params)) 1915 return -EINVAL; 1916 } else if (priv->channels.params.lro_en) { 1917 netdev_warn(netdev, "Can't set legacy RQ with LRO, disable LRO first\n"); 1918 return -EINVAL; 1919 } 1920 1921 new_channels.params = priv->channels.params; 1922 1923 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_STRIDING_RQ, enable); 1924 mlx5e_set_rq_type(mdev, &new_channels.params); 1925 1926 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { 1927 priv->channels.params = new_channels.params; 1928 return 0; 1929 } 1930 1931 return mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL); 1932 } 1933 1934 static int set_pflag_rx_no_csum_complete(struct net_device *netdev, bool enable) 1935 { 1936 struct mlx5e_priv *priv = netdev_priv(netdev); 1937 struct mlx5e_channels *channels = &priv->channels; 1938 struct mlx5e_channel *c; 1939 int i; 1940 1941 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || 1942 priv->channels.params.xdp_prog) 1943 return 0; 1944 1945 for (i = 0; i < channels->num; i++) { 1946 c = channels->c[i]; 1947 if (enable) 1948 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state); 1949 else 1950 __clear_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state); 1951 } 1952 1953 return 0; 1954 } 1955 1956 static int set_pflag_tx_mpwqe_common(struct net_device *netdev, u32 flag, bool enable) 1957 { 1958 struct mlx5e_priv *priv = netdev_priv(netdev); 1959 struct mlx5_core_dev *mdev = priv->mdev; 1960 struct mlx5e_channels new_channels = {}; 1961 int err; 1962 1963 if (enable && !MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1964 return -EOPNOTSUPP; 1965 1966 new_channels.params = priv->channels.params; 1967 1968 MLX5E_SET_PFLAG(&new_channels.params, flag, enable); 1969 1970 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { 1971 priv->channels.params = new_channels.params; 1972 return 0; 1973 } 1974 1975 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL); 1976 return err; 1977 } 1978 1979 static int set_pflag_xdp_tx_mpwqe(struct net_device *netdev, bool enable) 1980 { 1981 return set_pflag_tx_mpwqe_common(netdev, MLX5E_PFLAG_XDP_TX_MPWQE, enable); 1982 } 1983 1984 static int set_pflag_skb_tx_mpwqe(struct net_device *netdev, bool enable) 1985 { 1986 return set_pflag_tx_mpwqe_common(netdev, MLX5E_PFLAG_SKB_TX_MPWQE, enable); 1987 } 1988 1989 static int set_pflag_tx_port_ts(struct net_device *netdev, bool enable) 1990 { 1991 struct mlx5e_priv *priv = netdev_priv(netdev); 1992 struct mlx5_core_dev *mdev = priv->mdev; 1993 struct mlx5e_channels new_channels = {}; 1994 int err; 1995 1996 if (!MLX5_CAP_GEN(mdev, ts_cqe_to_dest_cqn)) 1997 return -EOPNOTSUPP; 1998 1999 /* Don't allow changing the PTP state if HTB offload is active, because 2000 * the numeration of the QoS SQs will change, while per-queue qdiscs are 2001 * attached. 2002 */ 2003 if (priv->htb.maj_id) { 2004 netdev_err(priv->netdev, "%s: HTB offload is active, cannot change the PTP state\n", 2005 __func__); 2006 return -EINVAL; 2007 } 2008 2009 new_channels.params = priv->channels.params; 2010 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_TX_PORT_TS, enable); 2011 /* No need to verify SQ stop room as 2012 * ptpsq.txqsq.stop_room <= generic_sq->stop_room, and both 2013 * has the same log_sq_size. 2014 */ 2015 2016 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { 2017 priv->channels.params = new_channels.params; 2018 err = mlx5e_num_channels_changed(priv); 2019 goto out; 2020 } 2021 2022 err = mlx5e_safe_switch_channels(priv, &new_channels, 2023 mlx5e_num_channels_changed_ctx, NULL); 2024 out: 2025 if (!err) 2026 priv->port_ptp_opened = true; 2027 2028 return err; 2029 } 2030 2031 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS] = { 2032 { "rx_cqe_moder", set_pflag_rx_cqe_based_moder }, 2033 { "tx_cqe_moder", set_pflag_tx_cqe_based_moder }, 2034 { "rx_cqe_compress", set_pflag_rx_cqe_compress }, 2035 { "rx_striding_rq", set_pflag_rx_striding_rq }, 2036 { "rx_no_csum_complete", set_pflag_rx_no_csum_complete }, 2037 { "xdp_tx_mpwqe", set_pflag_xdp_tx_mpwqe }, 2038 { "skb_tx_mpwqe", set_pflag_skb_tx_mpwqe }, 2039 { "tx_port_ts", set_pflag_tx_port_ts }, 2040 }; 2041 2042 static int mlx5e_handle_pflag(struct net_device *netdev, 2043 u32 wanted_flags, 2044 enum mlx5e_priv_flag flag) 2045 { 2046 struct mlx5e_priv *priv = netdev_priv(netdev); 2047 bool enable = !!(wanted_flags & BIT(flag)); 2048 u32 changes = wanted_flags ^ priv->channels.params.pflags; 2049 int err; 2050 2051 if (!(changes & BIT(flag))) 2052 return 0; 2053 2054 err = mlx5e_priv_flags[flag].handler(netdev, enable); 2055 if (err) { 2056 netdev_err(netdev, "%s private flag '%s' failed err %d\n", 2057 enable ? "Enable" : "Disable", mlx5e_priv_flags[flag].name, err); 2058 return err; 2059 } 2060 2061 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable); 2062 return 0; 2063 } 2064 2065 static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags) 2066 { 2067 struct mlx5e_priv *priv = netdev_priv(netdev); 2068 enum mlx5e_priv_flag pflag; 2069 int err; 2070 2071 mutex_lock(&priv->state_lock); 2072 2073 for (pflag = 0; pflag < MLX5E_NUM_PFLAGS; pflag++) { 2074 err = mlx5e_handle_pflag(netdev, pflags, pflag); 2075 if (err) 2076 break; 2077 } 2078 2079 mutex_unlock(&priv->state_lock); 2080 2081 /* Need to fix some features.. */ 2082 netdev_update_features(netdev); 2083 2084 return err; 2085 } 2086 2087 static u32 mlx5e_get_priv_flags(struct net_device *netdev) 2088 { 2089 struct mlx5e_priv *priv = netdev_priv(netdev); 2090 2091 return priv->channels.params.pflags; 2092 } 2093 2094 int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, 2095 u32 *rule_locs) 2096 { 2097 struct mlx5e_priv *priv = netdev_priv(dev); 2098 2099 /* ETHTOOL_GRXRINGS is needed by ethtool -x which is not part 2100 * of rxnfc. We keep this logic out of mlx5e_ethtool_get_rxnfc, 2101 * to avoid breaking "ethtool -x" when mlx5e_ethtool_get_rxnfc 2102 * is compiled out via CONFIG_MLX5_EN_RXNFC=n. 2103 */ 2104 if (info->cmd == ETHTOOL_GRXRINGS) { 2105 info->data = priv->channels.params.num_channels; 2106 return 0; 2107 } 2108 2109 return mlx5e_ethtool_get_rxnfc(dev, info, rule_locs); 2110 } 2111 2112 int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2113 { 2114 return mlx5e_ethtool_set_rxnfc(dev, cmd); 2115 } 2116 2117 const struct ethtool_ops mlx5e_ethtool_ops = { 2118 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 2119 ETHTOOL_COALESCE_MAX_FRAMES | 2120 ETHTOOL_COALESCE_USE_ADAPTIVE, 2121 .get_drvinfo = mlx5e_get_drvinfo, 2122 .get_link = ethtool_op_get_link, 2123 .get_strings = mlx5e_get_strings, 2124 .get_sset_count = mlx5e_get_sset_count, 2125 .get_ethtool_stats = mlx5e_get_ethtool_stats, 2126 .get_ringparam = mlx5e_get_ringparam, 2127 .set_ringparam = mlx5e_set_ringparam, 2128 .get_channels = mlx5e_get_channels, 2129 .set_channels = mlx5e_set_channels, 2130 .get_coalesce = mlx5e_get_coalesce, 2131 .set_coalesce = mlx5e_set_coalesce, 2132 .get_link_ksettings = mlx5e_get_link_ksettings, 2133 .set_link_ksettings = mlx5e_set_link_ksettings, 2134 .get_rxfh_key_size = mlx5e_get_rxfh_key_size, 2135 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size, 2136 .get_rxfh = mlx5e_get_rxfh, 2137 .set_rxfh = mlx5e_set_rxfh, 2138 .get_rxnfc = mlx5e_get_rxnfc, 2139 .set_rxnfc = mlx5e_set_rxnfc, 2140 .get_tunable = mlx5e_get_tunable, 2141 .set_tunable = mlx5e_set_tunable, 2142 .get_pause_stats = mlx5e_get_pause_stats, 2143 .get_pauseparam = mlx5e_get_pauseparam, 2144 .set_pauseparam = mlx5e_set_pauseparam, 2145 .get_ts_info = mlx5e_get_ts_info, 2146 .set_phys_id = mlx5e_set_phys_id, 2147 .get_wol = mlx5e_get_wol, 2148 .set_wol = mlx5e_set_wol, 2149 .get_module_info = mlx5e_get_module_info, 2150 .get_module_eeprom = mlx5e_get_module_eeprom, 2151 .flash_device = mlx5e_flash_device, 2152 .get_priv_flags = mlx5e_get_priv_flags, 2153 .set_priv_flags = mlx5e_set_priv_flags, 2154 .self_test = mlx5e_self_test, 2155 .get_msglevel = mlx5e_get_msglevel, 2156 .set_msglevel = mlx5e_set_msglevel, 2157 .get_fecparam = mlx5e_get_fecparam, 2158 .set_fecparam = mlx5e_set_fecparam, 2159 }; 2160