1 /* 2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include "en.h" 34 35 /* mlx5e global resources should be placed in this file. 36 * Global resources are common to all the netdevices crated on the same nic. 37 */ 38 39 int mlx5e_create_tir(struct mlx5_core_dev *mdev, struct mlx5e_tir *tir, u32 *in) 40 { 41 struct mlx5e_hw_objs *res = &mdev->mlx5e_res.hw_objs; 42 int err; 43 44 err = mlx5_core_create_tir(mdev, in, &tir->tirn); 45 if (err) 46 return err; 47 48 mutex_lock(&res->td.list_lock); 49 list_add(&tir->list, &res->td.tirs_list); 50 mutex_unlock(&res->td.list_lock); 51 52 return 0; 53 } 54 55 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev, 56 struct mlx5e_tir *tir) 57 { 58 struct mlx5e_hw_objs *res = &mdev->mlx5e_res.hw_objs; 59 60 mutex_lock(&res->td.list_lock); 61 mlx5_core_destroy_tir(mdev, tir->tirn); 62 list_del(&tir->list); 63 mutex_unlock(&res->td.list_lock); 64 } 65 66 void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc) 67 { 68 bool ro_pci_enable = pcie_relaxed_ordering_enabled(mdev->pdev); 69 bool ro_write = MLX5_CAP_GEN(mdev, relaxed_ordering_write); 70 bool ro_read = MLX5_CAP_GEN(mdev, relaxed_ordering_read); 71 72 MLX5_SET(mkc, mkc, relaxed_ordering_read, ro_pci_enable && ro_read); 73 MLX5_SET(mkc, mkc, relaxed_ordering_write, ro_pci_enable && ro_write); 74 } 75 76 static int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, 77 struct mlx5_core_mkey *mkey) 78 { 79 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 80 void *mkc; 81 u32 *in; 82 int err; 83 84 in = kvzalloc(inlen, GFP_KERNEL); 85 if (!in) 86 return -ENOMEM; 87 88 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 89 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_PA); 90 MLX5_SET(mkc, mkc, lw, 1); 91 MLX5_SET(mkc, mkc, lr, 1); 92 mlx5e_mkey_set_relaxed_ordering(mdev, mkc); 93 MLX5_SET(mkc, mkc, pd, pdn); 94 MLX5_SET(mkc, mkc, length64, 1); 95 MLX5_SET(mkc, mkc, qpn, 0xffffff); 96 97 err = mlx5_core_create_mkey(mdev, mkey, in, inlen); 98 99 kvfree(in); 100 return err; 101 } 102 103 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev) 104 { 105 struct mlx5e_hw_objs *res = &mdev->mlx5e_res.hw_objs; 106 int err; 107 108 err = mlx5_core_alloc_pd(mdev, &res->pdn); 109 if (err) { 110 mlx5_core_err(mdev, "alloc pd failed, %d\n", err); 111 return err; 112 } 113 114 err = mlx5_core_alloc_transport_domain(mdev, &res->td.tdn); 115 if (err) { 116 mlx5_core_err(mdev, "alloc td failed, %d\n", err); 117 goto err_dealloc_pd; 118 } 119 120 err = mlx5e_create_mkey(mdev, res->pdn, &res->mkey); 121 if (err) { 122 mlx5_core_err(mdev, "create mkey failed, %d\n", err); 123 goto err_dealloc_transport_domain; 124 } 125 126 err = mlx5_alloc_bfreg(mdev, &res->bfreg, false, false); 127 if (err) { 128 mlx5_core_err(mdev, "alloc bfreg failed, %d\n", err); 129 goto err_destroy_mkey; 130 } 131 132 INIT_LIST_HEAD(&res->td.tirs_list); 133 mutex_init(&res->td.list_lock); 134 135 return 0; 136 137 err_destroy_mkey: 138 mlx5_core_destroy_mkey(mdev, &res->mkey); 139 err_dealloc_transport_domain: 140 mlx5_core_dealloc_transport_domain(mdev, res->td.tdn); 141 err_dealloc_pd: 142 mlx5_core_dealloc_pd(mdev, res->pdn); 143 return err; 144 } 145 146 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev) 147 { 148 struct mlx5e_hw_objs *res = &mdev->mlx5e_res.hw_objs; 149 150 mlx5_free_bfreg(mdev, &res->bfreg); 151 mlx5_core_destroy_mkey(mdev, &res->mkey); 152 mlx5_core_dealloc_transport_domain(mdev, res->td.tdn); 153 mlx5_core_dealloc_pd(mdev, res->pdn); 154 memset(res, 0, sizeof(*res)); 155 } 156 157 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb, 158 bool enable_mc_lb) 159 { 160 struct mlx5_core_dev *mdev = priv->mdev; 161 struct mlx5e_tir *tir; 162 u8 lb_flags = 0; 163 int err = 0; 164 u32 tirn = 0; 165 int inlen; 166 void *in; 167 168 inlen = MLX5_ST_SZ_BYTES(modify_tir_in); 169 in = kvzalloc(inlen, GFP_KERNEL); 170 if (!in) { 171 err = -ENOMEM; 172 goto out; 173 } 174 175 if (enable_uc_lb) 176 lb_flags = MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 177 178 if (enable_mc_lb) 179 lb_flags |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 180 181 if (lb_flags) 182 MLX5_SET(modify_tir_in, in, ctx.self_lb_block, lb_flags); 183 184 MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1); 185 186 mutex_lock(&mdev->mlx5e_res.hw_objs.td.list_lock); 187 list_for_each_entry(tir, &mdev->mlx5e_res.hw_objs.td.tirs_list, list) { 188 tirn = tir->tirn; 189 err = mlx5_core_modify_tir(mdev, tirn, in); 190 if (err) 191 goto out; 192 } 193 194 out: 195 kvfree(in); 196 if (err) 197 netdev_err(priv->netdev, "refresh tir(0x%x) failed, %d\n", tirn, err); 198 mutex_unlock(&mdev->mlx5e_res.hw_objs.td.list_lock); 199 200 return err; 201 } 202