1 /* 2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include "en.h" 34 35 /* mlx5e global resources should be placed in this file. 36 * Global resources are common to all the netdevices crated on the same nic. 37 */ 38 39 int mlx5e_create_tir(struct mlx5_core_dev *mdev, struct mlx5e_tir *tir, u32 *in) 40 { 41 int err; 42 43 err = mlx5_core_create_tir(mdev, in, &tir->tirn); 44 if (err) 45 return err; 46 47 mutex_lock(&mdev->mlx5e_res.td.list_lock); 48 list_add(&tir->list, &mdev->mlx5e_res.td.tirs_list); 49 mutex_unlock(&mdev->mlx5e_res.td.list_lock); 50 51 return 0; 52 } 53 54 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev, 55 struct mlx5e_tir *tir) 56 { 57 mutex_lock(&mdev->mlx5e_res.td.list_lock); 58 mlx5_core_destroy_tir(mdev, tir->tirn); 59 list_del(&tir->list); 60 mutex_unlock(&mdev->mlx5e_res.td.list_lock); 61 } 62 63 void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc) 64 { 65 bool ro_pci_enable = pcie_relaxed_ordering_enabled(mdev->pdev); 66 bool ro_write = MLX5_CAP_GEN(mdev, relaxed_ordering_write); 67 bool ro_read = MLX5_CAP_GEN(mdev, relaxed_ordering_read); 68 69 MLX5_SET(mkc, mkc, relaxed_ordering_read, ro_pci_enable && ro_read); 70 MLX5_SET(mkc, mkc, relaxed_ordering_write, ro_pci_enable && ro_write); 71 } 72 73 static int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, 74 struct mlx5_core_mkey *mkey) 75 { 76 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 77 void *mkc; 78 u32 *in; 79 int err; 80 81 in = kvzalloc(inlen, GFP_KERNEL); 82 if (!in) 83 return -ENOMEM; 84 85 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 86 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_PA); 87 MLX5_SET(mkc, mkc, lw, 1); 88 MLX5_SET(mkc, mkc, lr, 1); 89 mlx5e_mkey_set_relaxed_ordering(mdev, mkc); 90 MLX5_SET(mkc, mkc, pd, pdn); 91 MLX5_SET(mkc, mkc, length64, 1); 92 MLX5_SET(mkc, mkc, qpn, 0xffffff); 93 94 err = mlx5_core_create_mkey(mdev, mkey, in, inlen); 95 96 kvfree(in); 97 return err; 98 } 99 100 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev) 101 { 102 struct mlx5e_resources *res = &mdev->mlx5e_res; 103 int err; 104 105 err = mlx5_core_alloc_pd(mdev, &res->pdn); 106 if (err) { 107 mlx5_core_err(mdev, "alloc pd failed, %d\n", err); 108 return err; 109 } 110 111 err = mlx5_core_alloc_transport_domain(mdev, &res->td.tdn); 112 if (err) { 113 mlx5_core_err(mdev, "alloc td failed, %d\n", err); 114 goto err_dealloc_pd; 115 } 116 117 err = mlx5e_create_mkey(mdev, res->pdn, &res->mkey); 118 if (err) { 119 mlx5_core_err(mdev, "create mkey failed, %d\n", err); 120 goto err_dealloc_transport_domain; 121 } 122 123 err = mlx5_alloc_bfreg(mdev, &res->bfreg, false, false); 124 if (err) { 125 mlx5_core_err(mdev, "alloc bfreg failed, %d\n", err); 126 goto err_destroy_mkey; 127 } 128 129 INIT_LIST_HEAD(&mdev->mlx5e_res.td.tirs_list); 130 mutex_init(&mdev->mlx5e_res.td.list_lock); 131 132 return 0; 133 134 err_destroy_mkey: 135 mlx5_core_destroy_mkey(mdev, &res->mkey); 136 err_dealloc_transport_domain: 137 mlx5_core_dealloc_transport_domain(mdev, res->td.tdn); 138 err_dealloc_pd: 139 mlx5_core_dealloc_pd(mdev, res->pdn); 140 return err; 141 } 142 143 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev) 144 { 145 struct mlx5e_resources *res = &mdev->mlx5e_res; 146 147 mlx5_free_bfreg(mdev, &res->bfreg); 148 mlx5_core_destroy_mkey(mdev, &res->mkey); 149 mlx5_core_dealloc_transport_domain(mdev, res->td.tdn); 150 mlx5_core_dealloc_pd(mdev, res->pdn); 151 memset(res, 0, sizeof(*res)); 152 } 153 154 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb, 155 bool enable_mc_lb) 156 { 157 struct mlx5_core_dev *mdev = priv->mdev; 158 struct mlx5e_tir *tir; 159 u8 lb_flags = 0; 160 int err = 0; 161 u32 tirn = 0; 162 int inlen; 163 void *in; 164 165 inlen = MLX5_ST_SZ_BYTES(modify_tir_in); 166 in = kvzalloc(inlen, GFP_KERNEL); 167 if (!in) { 168 err = -ENOMEM; 169 goto out; 170 } 171 172 if (enable_uc_lb) 173 lb_flags = MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; 174 175 if (enable_mc_lb) 176 lb_flags |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; 177 178 if (lb_flags) 179 MLX5_SET(modify_tir_in, in, ctx.self_lb_block, lb_flags); 180 181 MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1); 182 183 mutex_lock(&mdev->mlx5e_res.td.list_lock); 184 list_for_each_entry(tir, &mdev->mlx5e_res.td.tirs_list, list) { 185 tirn = tir->tirn; 186 err = mlx5_core_modify_tir(mdev, tirn, in); 187 if (err) 188 goto out; 189 } 190 191 out: 192 kvfree(in); 193 if (err) 194 netdev_err(priv->netdev, "refresh tir(0x%x) failed, %d\n", tirn, err); 195 mutex_unlock(&mdev->mlx5e_res.td.list_lock); 196 197 return err; 198 } 199