1 /*
2  * Copyright (c) 2017 Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  *
32  */
33 
34 #ifndef __MLX5E_IPSEC_RXTX_H__
35 #define __MLX5E_IPSEC_RXTX_H__
36 
37 #include <linux/skbuff.h>
38 #include <net/xfrm.h>
39 #include "en.h"
40 #include "en/txrx.h"
41 
42 /* Bit31: IPsec marker, Bit30-24: IPsec syndrome, Bit23-0: IPsec obj id */
43 #define MLX5_IPSEC_METADATA_MARKER(metadata)  (((metadata) >> 31) & 0x1)
44 #define MLX5_IPSEC_METADATA_SYNDROM(metadata) (((metadata) >> 24) & GENMASK(6, 0))
45 #define MLX5_IPSEC_METADATA_HANDLE(metadata)  ((metadata) & GENMASK(23, 0))
46 
47 struct mlx5e_accel_tx_ipsec_state {
48 	struct xfrm_offload *xo;
49 	struct xfrm_state *x;
50 	u32 tailen;
51 	u32 plen;
52 };
53 
54 #ifdef CONFIG_MLX5_EN_IPSEC
55 
56 void mlx5e_ipsec_inverse_table_init(void);
57 void mlx5e_ipsec_set_iv_esn(struct sk_buff *skb, struct xfrm_state *x,
58 			    struct xfrm_offload *xo);
59 void mlx5e_ipsec_set_iv(struct sk_buff *skb, struct xfrm_state *x,
60 			struct xfrm_offload *xo);
61 bool mlx5e_ipsec_handle_tx_skb(struct net_device *netdev,
62 			       struct sk_buff *skb,
63 			       struct mlx5e_accel_tx_ipsec_state *ipsec_st);
64 void mlx5e_ipsec_handle_tx_wqe(struct mlx5e_tx_wqe *wqe,
65 			       struct mlx5e_accel_tx_ipsec_state *ipsec_st,
66 			       struct mlx5_wqe_inline_seg *inlseg);
67 void mlx5e_ipsec_offload_handle_rx_skb(struct net_device *netdev,
68 				       struct sk_buff *skb,
69 				       struct mlx5_cqe64 *cqe);
70 static inline unsigned int mlx5e_ipsec_tx_ids_len(struct mlx5e_accel_tx_ipsec_state *ipsec_st)
71 {
72 	return ipsec_st->tailen;
73 }
74 
75 static inline bool mlx5_ipsec_is_rx_flow(struct mlx5_cqe64 *cqe)
76 {
77 	return MLX5_IPSEC_METADATA_MARKER(be32_to_cpu(cqe->ft_metadata));
78 }
79 
80 static inline bool mlx5e_ipsec_is_tx_flow(struct mlx5e_accel_tx_ipsec_state *ipsec_st)
81 {
82 	return ipsec_st->x;
83 }
84 
85 static inline bool mlx5e_ipsec_eseg_meta(struct mlx5_wqe_eth_seg *eseg)
86 {
87 	return eseg->flow_table_metadata & cpu_to_be32(MLX5_ETH_WQE_FT_META_IPSEC);
88 }
89 
90 void mlx5e_ipsec_tx_build_eseg(struct mlx5e_priv *priv, struct sk_buff *skb,
91 			       struct mlx5_wqe_eth_seg *eseg);
92 
93 static inline netdev_features_t
94 mlx5e_ipsec_feature_check(struct sk_buff *skb, netdev_features_t features)
95 {
96 	struct xfrm_offload *xo = xfrm_offload(skb);
97 	struct sec_path *sp = skb_sec_path(skb);
98 
99 	if (sp && sp->len && xo) {
100 		struct xfrm_state *x = sp->xvec[0];
101 
102 		if (!x || !x->xso.offload_handle)
103 			goto out_disable;
104 
105 		if (xo->inner_ipproto) {
106 			/* Cannot support tunnel packet over IPsec tunnel mode
107 			 * because we cannot offload three IP header csum
108 			 */
109 			if (x->props.mode == XFRM_MODE_TUNNEL)
110 				goto out_disable;
111 
112 			/* Only support UDP or TCP L4 checksum */
113 			if (xo->inner_ipproto != IPPROTO_UDP &&
114 			    xo->inner_ipproto != IPPROTO_TCP)
115 				goto out_disable;
116 		}
117 
118 		return features;
119 
120 	}
121 
122 	/* Disable CSUM and GSO for software IPsec */
123 out_disable:
124 	return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
125 }
126 
127 static inline bool
128 mlx5e_ipsec_txwqe_build_eseg_csum(struct mlx5e_txqsq *sq, struct sk_buff *skb,
129 				  struct mlx5_wqe_eth_seg *eseg)
130 {
131 	u8 inner_ipproto;
132 
133 	if (!mlx5e_ipsec_eseg_meta(eseg))
134 		return false;
135 
136 	eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM;
137 	inner_ipproto = xfrm_offload(skb)->inner_ipproto;
138 	if (inner_ipproto) {
139 		eseg->cs_flags |= MLX5_ETH_WQE_L3_INNER_CSUM;
140 		if (inner_ipproto == IPPROTO_TCP || inner_ipproto == IPPROTO_UDP)
141 			eseg->cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
142 	} else if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
143 		eseg->cs_flags |= MLX5_ETH_WQE_L4_CSUM;
144 		sq->stats->csum_partial_inner++;
145 	}
146 
147 	return true;
148 }
149 #else
150 static inline
151 void mlx5e_ipsec_offload_handle_rx_skb(struct net_device *netdev,
152 				       struct sk_buff *skb,
153 				       struct mlx5_cqe64 *cqe)
154 {}
155 
156 static inline bool mlx5e_ipsec_eseg_meta(struct mlx5_wqe_eth_seg *eseg)
157 {
158 	return false;
159 }
160 
161 static inline bool mlx5_ipsec_is_rx_flow(struct mlx5_cqe64 *cqe) { return false; }
162 static inline netdev_features_t
163 mlx5e_ipsec_feature_check(struct sk_buff *skb, netdev_features_t features)
164 { return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); }
165 
166 static inline bool
167 mlx5e_ipsec_txwqe_build_eseg_csum(struct mlx5e_txqsq *sq, struct sk_buff *skb,
168 				  struct mlx5_wqe_eth_seg *eseg)
169 {
170 	return false;
171 }
172 #endif /* CONFIG_MLX5_EN_IPSEC */
173 
174 #endif /* __MLX5E_IPSEC_RXTX_H__ */
175