1 /* 2 * Copyright (c) 2018, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef __MLX5_EN_XDP_H__ 33 #define __MLX5_EN_XDP_H__ 34 35 #include <linux/indirect_call_wrapper.h> 36 37 #include "en.h" 38 #include "en/txrx.h" 39 40 #define MLX5E_XDP_MIN_INLINE (ETH_HLEN + VLAN_HLEN) 41 42 #define MLX5E_XDP_INLINE_WQE_MAX_DS_CNT 16 43 #define MLX5E_XDP_INLINE_WQE_SZ_THRSD \ 44 (MLX5E_XDP_INLINE_WQE_MAX_DS_CNT * MLX5_SEND_WQE_DS - \ 45 sizeof(struct mlx5_wqe_inline_seg)) 46 47 struct mlx5e_xdp_buff { 48 struct xdp_buff xdp; 49 struct mlx5_cqe64 *cqe; 50 struct mlx5e_rq *rq; 51 }; 52 53 /* XDP packets can be transmitted in different ways. On completion, we need to 54 * distinguish between them to clean up things in a proper way. 55 */ 56 enum mlx5e_xdp_xmit_mode { 57 /* An xdp_frame was transmitted due to either XDP_REDIRECT from another 58 * device or XDP_TX from an XSK RQ. The frame has to be unmapped and 59 * returned. 60 */ 61 MLX5E_XDP_XMIT_MODE_FRAME, 62 63 /* The xdp_frame was created in place as a result of XDP_TX from a 64 * regular RQ. No DMA remapping happened, and the page belongs to us. 65 */ 66 MLX5E_XDP_XMIT_MODE_PAGE, 67 68 /* No xdp_frame was created at all, the transmit happened from a UMEM 69 * page. The UMEM Completion Ring producer pointer has to be increased. 70 */ 71 MLX5E_XDP_XMIT_MODE_XSK, 72 }; 73 74 struct mlx5e_xdp_info { 75 enum mlx5e_xdp_xmit_mode mode; 76 union { 77 struct { 78 struct xdp_frame *xdpf; 79 dma_addr_t dma_addr; 80 } frame; 81 struct { 82 struct mlx5e_rq *rq; 83 struct page *page; 84 } page; 85 }; 86 }; 87 88 struct mlx5e_xsk_param; 89 int mlx5e_xdp_max_mtu(struct mlx5e_params *params, struct mlx5e_xsk_param *xsk); 90 bool mlx5e_xdp_handle(struct mlx5e_rq *rq, 91 struct bpf_prog *prog, struct mlx5e_xdp_buff *mlctx); 92 void mlx5e_xdp_mpwqe_complete(struct mlx5e_xdpsq *sq); 93 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq); 94 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq); 95 void mlx5e_set_xmit_fp(struct mlx5e_xdpsq *sq, bool is_mpw); 96 void mlx5e_xdp_rx_poll_complete(struct mlx5e_rq *rq); 97 int mlx5e_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames, 98 u32 flags); 99 100 extern const struct xdp_metadata_ops mlx5e_xdp_metadata_ops; 101 102 INDIRECT_CALLABLE_DECLARE(bool mlx5e_xmit_xdp_frame_mpwqe(struct mlx5e_xdpsq *sq, 103 struct mlx5e_xmit_data *xdptxd, 104 struct skb_shared_info *sinfo, 105 int check_result)); 106 INDIRECT_CALLABLE_DECLARE(bool mlx5e_xmit_xdp_frame(struct mlx5e_xdpsq *sq, 107 struct mlx5e_xmit_data *xdptxd, 108 struct skb_shared_info *sinfo, 109 int check_result)); 110 INDIRECT_CALLABLE_DECLARE(int mlx5e_xmit_xdp_frame_check_mpwqe(struct mlx5e_xdpsq *sq)); 111 INDIRECT_CALLABLE_DECLARE(int mlx5e_xmit_xdp_frame_check(struct mlx5e_xdpsq *sq)); 112 113 static inline void mlx5e_xdp_tx_enable(struct mlx5e_priv *priv) 114 { 115 set_bit(MLX5E_STATE_XDP_TX_ENABLED, &priv->state); 116 117 if (priv->channels.params.xdp_prog) 118 set_bit(MLX5E_STATE_XDP_ACTIVE, &priv->state); 119 } 120 121 static inline void mlx5e_xdp_tx_disable(struct mlx5e_priv *priv) 122 { 123 if (priv->channels.params.xdp_prog) 124 clear_bit(MLX5E_STATE_XDP_ACTIVE, &priv->state); 125 126 clear_bit(MLX5E_STATE_XDP_TX_ENABLED, &priv->state); 127 /* Let other device's napi(s) and XSK wakeups see our new state. */ 128 synchronize_net(); 129 } 130 131 static inline bool mlx5e_xdp_tx_is_enabled(struct mlx5e_priv *priv) 132 { 133 return test_bit(MLX5E_STATE_XDP_TX_ENABLED, &priv->state); 134 } 135 136 static inline bool mlx5e_xdp_is_active(struct mlx5e_priv *priv) 137 { 138 return test_bit(MLX5E_STATE_XDP_ACTIVE, &priv->state); 139 } 140 141 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq) 142 { 143 if (sq->doorbell_cseg) { 144 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, sq->doorbell_cseg); 145 sq->doorbell_cseg = NULL; 146 } 147 } 148 149 /* Enable inline WQEs to shift some load from a congested HCA (HW) to 150 * a less congested cpu (SW). 151 */ 152 static inline bool mlx5e_xdp_get_inline_state(struct mlx5e_xdpsq *sq, bool cur) 153 { 154 u16 outstanding = sq->xdpi_fifo_pc - sq->xdpi_fifo_cc; 155 156 #define MLX5E_XDP_INLINE_WATERMARK_LOW 10 157 #define MLX5E_XDP_INLINE_WATERMARK_HIGH 128 158 159 if (cur && outstanding <= MLX5E_XDP_INLINE_WATERMARK_LOW) 160 return false; 161 162 if (!cur && outstanding >= MLX5E_XDP_INLINE_WATERMARK_HIGH) 163 return true; 164 165 return cur; 166 } 167 168 static inline bool mlx5e_xdp_mpwqe_is_full(struct mlx5e_tx_mpwqe *session, u8 max_sq_mpw_wqebbs) 169 { 170 if (session->inline_on) 171 return session->ds_count + MLX5E_XDP_INLINE_WQE_MAX_DS_CNT > 172 max_sq_mpw_wqebbs * MLX5_SEND_WQEBB_NUM_DS; 173 174 return mlx5e_tx_mpwqe_is_full(session, max_sq_mpw_wqebbs); 175 } 176 177 struct mlx5e_xdp_wqe_info { 178 u8 num_wqebbs; 179 u8 num_pkts; 180 }; 181 182 static inline void 183 mlx5e_xdp_mpwqe_add_dseg(struct mlx5e_xdpsq *sq, 184 struct mlx5e_xmit_data *xdptxd, 185 struct mlx5e_xdpsq_stats *stats) 186 { 187 struct mlx5e_tx_mpwqe *session = &sq->mpwqe; 188 struct mlx5_wqe_data_seg *dseg = 189 (struct mlx5_wqe_data_seg *)session->wqe + session->ds_count; 190 u32 dma_len = xdptxd->len; 191 192 session->pkt_count++; 193 session->bytes_count += dma_len; 194 195 if (session->inline_on && dma_len <= MLX5E_XDP_INLINE_WQE_SZ_THRSD) { 196 struct mlx5_wqe_inline_seg *inline_dseg = 197 (struct mlx5_wqe_inline_seg *)dseg; 198 u16 ds_len = sizeof(*inline_dseg) + dma_len; 199 u16 ds_cnt = DIV_ROUND_UP(ds_len, MLX5_SEND_WQE_DS); 200 201 inline_dseg->byte_count = cpu_to_be32(dma_len | MLX5_INLINE_SEG); 202 memcpy(inline_dseg->data, xdptxd->data, dma_len); 203 204 session->ds_count += ds_cnt; 205 stats->inlnw++; 206 return; 207 } 208 209 dseg->addr = cpu_to_be64(xdptxd->dma_addr); 210 dseg->byte_count = cpu_to_be32(dma_len); 211 dseg->lkey = sq->mkey_be; 212 session->ds_count++; 213 } 214 215 static inline void 216 mlx5e_xdpi_fifo_push(struct mlx5e_xdp_info_fifo *fifo, 217 struct mlx5e_xdp_info *xi) 218 { 219 u32 i = (*fifo->pc)++ & fifo->mask; 220 221 fifo->xi[i] = *xi; 222 } 223 224 static inline struct mlx5e_xdp_info 225 mlx5e_xdpi_fifo_pop(struct mlx5e_xdp_info_fifo *fifo) 226 { 227 return fifo->xi[(*fifo->cc)++ & fifo->mask]; 228 } 229 #endif 230