1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* Copyright (c) 2019 Mellanox Technologies. */ 3 4 #ifndef __MLX5_EN_TXRX_H___ 5 #define __MLX5_EN_TXRX_H___ 6 7 #include "en.h" 8 #include <linux/indirect_call_wrapper.h> 9 10 #define MLX5E_TX_WQE_EMPTY_DS_COUNT (sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS) 11 12 #define INL_HDR_START_SZ (sizeof(((struct mlx5_wqe_eth_seg *)NULL)->inline_hdr.start)) 13 14 /* IPSEC inline data includes: 15 * 1. ESP trailer: up to 255 bytes of padding, 1 byte for pad length, 1 byte for 16 * next header. 17 * 2. ESP authentication data: 16 bytes for ICV. 18 */ 19 #define MLX5E_MAX_TX_IPSEC_DS DIV_ROUND_UP(sizeof(struct mlx5_wqe_inline_seg) + \ 20 255 + 1 + 1 + 16, MLX5_SEND_WQE_DS) 21 22 /* 366 should be big enough to cover all L2, L3 and L4 headers with possible 23 * encapsulations. 24 */ 25 #define MLX5E_MAX_TX_INLINE_DS DIV_ROUND_UP(366 - INL_HDR_START_SZ + VLAN_HLEN, \ 26 MLX5_SEND_WQE_DS) 27 28 /* Sync the calculation with mlx5e_sq_calc_wqe_attr. */ 29 #define MLX5E_MAX_TX_WQEBBS DIV_ROUND_UP(MLX5E_TX_WQE_EMPTY_DS_COUNT + \ 30 MLX5E_MAX_TX_INLINE_DS + \ 31 MLX5E_MAX_TX_IPSEC_DS + \ 32 MAX_SKB_FRAGS + 1, \ 33 MLX5_SEND_WQEBB_NUM_DS) 34 35 #define MLX5E_RX_ERR_CQE(cqe) (get_cqe_opcode(cqe) != MLX5_CQE_RESP_SEND) 36 37 static inline 38 ktime_t mlx5e_cqe_ts_to_ns(cqe_ts_to_ns func, struct mlx5_clock *clock, u64 cqe_ts) 39 { 40 return INDIRECT_CALL_2(func, mlx5_real_time_cyc2time, mlx5_timecounter_cyc2time, 41 clock, cqe_ts); 42 } 43 44 enum mlx5e_icosq_wqe_type { 45 MLX5E_ICOSQ_WQE_NOP, 46 MLX5E_ICOSQ_WQE_UMR_RX, 47 MLX5E_ICOSQ_WQE_SHAMPO_HD_UMR, 48 #ifdef CONFIG_MLX5_EN_TLS 49 MLX5E_ICOSQ_WQE_UMR_TLS, 50 MLX5E_ICOSQ_WQE_SET_PSV_TLS, 51 MLX5E_ICOSQ_WQE_GET_PSV_TLS, 52 #endif 53 }; 54 55 /* General */ 56 static inline bool mlx5e_skb_is_multicast(struct sk_buff *skb) 57 { 58 return skb->pkt_type == PACKET_MULTICAST || skb->pkt_type == PACKET_BROADCAST; 59 } 60 61 void mlx5e_trigger_irq(struct mlx5e_icosq *sq); 62 void mlx5e_completion_event(struct mlx5_core_cq *mcq, struct mlx5_eqe *eqe); 63 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); 64 int mlx5e_napi_poll(struct napi_struct *napi, int budget); 65 int mlx5e_poll_ico_cq(struct mlx5e_cq *cq); 66 67 /* RX */ 68 INDIRECT_CALLABLE_DECLARE(bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)); 69 INDIRECT_CALLABLE_DECLARE(bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)); 70 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); 71 void mlx5e_free_rx_descs(struct mlx5e_rq *rq); 72 void mlx5e_free_rx_missing_descs(struct mlx5e_rq *rq); 73 74 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config) 75 { 76 return config->rx_filter == HWTSTAMP_FILTER_ALL; 77 } 78 79 /* TX */ 80 struct mlx5e_xmit_data { 81 dma_addr_t dma_addr; 82 void *data; 83 u32 len : 31; 84 u32 has_frags : 1; 85 }; 86 87 struct mlx5e_xmit_data_frags { 88 struct mlx5e_xmit_data xd; 89 struct skb_shared_info *sinfo; 90 dma_addr_t *dma_arr; 91 }; 92 93 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); 94 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget); 95 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq); 96 97 static inline bool 98 mlx5e_skb_fifo_has_room(struct mlx5e_skb_fifo *fifo) 99 { 100 return (u16)(*fifo->pc - *fifo->cc) <= fifo->mask; 101 } 102 103 static inline bool 104 mlx5e_wqc_has_room_for(struct mlx5_wq_cyc *wq, u16 cc, u16 pc, u16 n) 105 { 106 return (mlx5_wq_cyc_ctr2ix(wq, cc - pc) >= n) || (cc == pc); 107 } 108 109 static inline void *mlx5e_fetch_wqe(struct mlx5_wq_cyc *wq, u16 pi, size_t wqe_size) 110 { 111 void *wqe; 112 113 wqe = mlx5_wq_cyc_get_wqe(wq, pi); 114 memset(wqe, 0, wqe_size); 115 116 return wqe; 117 } 118 119 #define MLX5E_TX_FETCH_WQE(sq, pi) \ 120 ((struct mlx5e_tx_wqe *)mlx5e_fetch_wqe(&(sq)->wq, pi, sizeof(struct mlx5e_tx_wqe))) 121 122 static inline struct mlx5e_tx_wqe * 123 mlx5e_post_nop(struct mlx5_wq_cyc *wq, u32 sqn, u16 *pc) 124 { 125 u16 pi = mlx5_wq_cyc_ctr2ix(wq, *pc); 126 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi); 127 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; 128 129 memset(cseg, 0, sizeof(*cseg)); 130 131 cseg->opmod_idx_opcode = cpu_to_be32((*pc << 8) | MLX5_OPCODE_NOP); 132 cseg->qpn_ds = cpu_to_be32((sqn << 8) | 0x01); 133 134 (*pc)++; 135 136 return wqe; 137 } 138 139 static inline struct mlx5e_tx_wqe * 140 mlx5e_post_nop_fence(struct mlx5_wq_cyc *wq, u32 sqn, u16 *pc) 141 { 142 u16 pi = mlx5_wq_cyc_ctr2ix(wq, *pc); 143 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi); 144 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; 145 146 memset(cseg, 0, sizeof(*cseg)); 147 148 cseg->opmod_idx_opcode = cpu_to_be32((*pc << 8) | MLX5_OPCODE_NOP); 149 cseg->qpn_ds = cpu_to_be32((sqn << 8) | 0x01); 150 cseg->fm_ce_se = MLX5_FENCE_MODE_INITIATOR_SMALL; 151 152 (*pc)++; 153 154 return wqe; 155 } 156 157 struct mlx5e_tx_wqe_info { 158 struct sk_buff *skb; 159 u32 num_bytes; 160 u8 num_wqebbs; 161 u8 num_dma; 162 u8 num_fifo_pkts; 163 #ifdef CONFIG_MLX5_EN_TLS 164 struct page *resync_dump_frag_page; 165 #endif 166 }; 167 168 static inline u16 mlx5e_txqsq_get_next_pi(struct mlx5e_txqsq *sq, u16 size) 169 { 170 struct mlx5_wq_cyc *wq = &sq->wq; 171 u16 pi, contig_wqebbs; 172 173 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc); 174 contig_wqebbs = mlx5_wq_cyc_get_contig_wqebbs(wq, pi); 175 if (unlikely(contig_wqebbs < size)) { 176 struct mlx5e_tx_wqe_info *wi, *edge_wi; 177 178 wi = &sq->db.wqe_info[pi]; 179 edge_wi = wi + contig_wqebbs; 180 181 /* Fill SQ frag edge with NOPs to avoid WQE wrapping two pages. */ 182 for (; wi < edge_wi; wi++) { 183 *wi = (struct mlx5e_tx_wqe_info) { 184 .num_wqebbs = 1, 185 }; 186 mlx5e_post_nop(wq, sq->sqn, &sq->pc); 187 } 188 sq->stats->nop += contig_wqebbs; 189 190 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc); 191 } 192 193 return pi; 194 } 195 196 static inline u16 mlx5e_shampo_get_cqe_header_index(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) 197 { 198 return be16_to_cpu(cqe->shampo.header_entry_index) & (rq->mpwqe.shampo->hd_per_wq - 1); 199 } 200 201 struct mlx5e_shampo_umr { 202 u16 len; 203 }; 204 205 struct mlx5e_icosq_wqe_info { 206 u8 wqe_type; 207 u8 num_wqebbs; 208 209 /* Auxiliary data for different wqe types. */ 210 union { 211 struct { 212 struct mlx5e_rq *rq; 213 } umr; 214 struct mlx5e_shampo_umr shampo; 215 #ifdef CONFIG_MLX5_EN_TLS 216 struct { 217 struct mlx5e_ktls_offload_context_rx *priv_rx; 218 } tls_set_params; 219 struct { 220 struct mlx5e_ktls_rx_resync_buf *buf; 221 } tls_get_params; 222 #endif 223 }; 224 }; 225 226 void mlx5e_free_icosq_descs(struct mlx5e_icosq *sq); 227 228 static inline u16 mlx5e_icosq_get_next_pi(struct mlx5e_icosq *sq, u16 size) 229 { 230 struct mlx5_wq_cyc *wq = &sq->wq; 231 u16 pi, contig_wqebbs; 232 233 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc); 234 contig_wqebbs = mlx5_wq_cyc_get_contig_wqebbs(wq, pi); 235 if (unlikely(contig_wqebbs < size)) { 236 struct mlx5e_icosq_wqe_info *wi, *edge_wi; 237 238 wi = &sq->db.wqe_info[pi]; 239 edge_wi = wi + contig_wqebbs; 240 241 /* Fill SQ frag edge with NOPs to avoid WQE wrapping two pages. */ 242 for (; wi < edge_wi; wi++) { 243 *wi = (struct mlx5e_icosq_wqe_info) { 244 .wqe_type = MLX5E_ICOSQ_WQE_NOP, 245 .num_wqebbs = 1, 246 }; 247 mlx5e_post_nop(wq, sq->sqn, &sq->pc); 248 } 249 250 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc); 251 } 252 253 return pi; 254 } 255 256 static inline void 257 mlx5e_notify_hw(struct mlx5_wq_cyc *wq, u16 pc, void __iomem *uar_map, 258 struct mlx5_wqe_ctrl_seg *ctrl) 259 { 260 ctrl->fm_ce_se |= MLX5_WQE_CTRL_CQ_UPDATE; 261 /* ensure wqe is visible to device before updating doorbell record */ 262 dma_wmb(); 263 264 *wq->db = cpu_to_be32(pc); 265 266 /* ensure doorbell record is visible to device before ringing the 267 * doorbell 268 */ 269 wmb(); 270 271 mlx5_write64((__be32 *)ctrl, uar_map); 272 } 273 274 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) 275 { 276 struct mlx5_core_cq *mcq; 277 278 mcq = &cq->mcq; 279 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc); 280 } 281 282 static inline struct mlx5e_sq_dma * 283 mlx5e_dma_get(struct mlx5e_txqsq *sq, u32 i) 284 { 285 return &sq->db.dma_fifo[i & sq->dma_fifo_mask]; 286 } 287 288 static inline void 289 mlx5e_dma_push(struct mlx5e_txqsq *sq, dma_addr_t addr, u32 size, 290 enum mlx5e_dma_map_type map_type) 291 { 292 struct mlx5e_sq_dma *dma = mlx5e_dma_get(sq, sq->dma_fifo_pc++); 293 294 dma->addr = addr; 295 dma->size = size; 296 dma->type = map_type; 297 } 298 299 static inline 300 struct sk_buff **mlx5e_skb_fifo_get(struct mlx5e_skb_fifo *fifo, u16 i) 301 { 302 return &fifo->fifo[i & fifo->mask]; 303 } 304 305 static inline 306 void mlx5e_skb_fifo_push(struct mlx5e_skb_fifo *fifo, struct sk_buff *skb) 307 { 308 struct sk_buff **skb_item = mlx5e_skb_fifo_get(fifo, (*fifo->pc)++); 309 310 *skb_item = skb; 311 } 312 313 static inline 314 struct sk_buff *mlx5e_skb_fifo_pop(struct mlx5e_skb_fifo *fifo) 315 { 316 WARN_ON_ONCE(*fifo->pc == *fifo->cc); 317 318 return *mlx5e_skb_fifo_get(fifo, (*fifo->cc)++); 319 } 320 321 static inline void 322 mlx5e_tx_dma_unmap(struct device *pdev, struct mlx5e_sq_dma *dma) 323 { 324 switch (dma->type) { 325 case MLX5E_DMA_MAP_SINGLE: 326 dma_unmap_single(pdev, dma->addr, dma->size, DMA_TO_DEVICE); 327 break; 328 case MLX5E_DMA_MAP_PAGE: 329 dma_unmap_page(pdev, dma->addr, dma->size, DMA_TO_DEVICE); 330 break; 331 default: 332 WARN_ONCE(true, "mlx5e_tx_dma_unmap unknown DMA type!\n"); 333 } 334 } 335 336 void mlx5e_tx_mpwqe_ensure_complete(struct mlx5e_txqsq *sq); 337 338 static inline bool mlx5e_tx_mpwqe_is_full(struct mlx5e_tx_mpwqe *session, u8 max_sq_mpw_wqebbs) 339 { 340 return session->ds_count == max_sq_mpw_wqebbs * MLX5_SEND_WQEBB_NUM_DS; 341 } 342 343 static inline void mlx5e_rqwq_reset(struct mlx5e_rq *rq) 344 { 345 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) { 346 mlx5_wq_ll_reset(&rq->mpwqe.wq); 347 rq->mpwqe.actual_wq_head = 0; 348 } else { 349 mlx5_wq_cyc_reset(&rq->wqe.wq); 350 } 351 } 352 353 static inline void mlx5e_dump_error_cqe(struct mlx5e_cq *cq, u32 qn, 354 struct mlx5_err_cqe *err_cqe) 355 { 356 struct mlx5_cqwq *wq = &cq->wq; 357 u32 ci; 358 359 ci = mlx5_cqwq_ctr2ix(wq, wq->cc - 1); 360 361 netdev_err(cq->netdev, 362 "Error cqe on cqn 0x%x, ci 0x%x, qn 0x%x, opcode 0x%x, syndrome 0x%x, vendor syndrome 0x%x\n", 363 cq->mcq.cqn, ci, qn, 364 get_cqe_opcode((struct mlx5_cqe64 *)err_cqe), 365 err_cqe->syndrome, err_cqe->vendor_err_synd); 366 mlx5_dump_err_cqe(cq->mdev, err_cqe); 367 } 368 369 static inline u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq) 370 { 371 switch (rq->wq_type) { 372 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 373 return mlx5_wq_ll_get_size(&rq->mpwqe.wq); 374 default: 375 return mlx5_wq_cyc_get_size(&rq->wqe.wq); 376 } 377 } 378 379 static inline u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq) 380 { 381 switch (rq->wq_type) { 382 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 383 return rq->mpwqe.wq.cur_sz; 384 default: 385 return rq->wqe.wq.cur_sz; 386 } 387 } 388 389 static inline u16 mlx5e_rqwq_get_head(struct mlx5e_rq *rq) 390 { 391 switch (rq->wq_type) { 392 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 393 return mlx5_wq_ll_get_head(&rq->mpwqe.wq); 394 default: 395 return mlx5_wq_cyc_get_head(&rq->wqe.wq); 396 } 397 } 398 399 static inline u16 mlx5e_rqwq_get_wqe_counter(struct mlx5e_rq *rq) 400 { 401 switch (rq->wq_type) { 402 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 403 return mlx5_wq_ll_get_counter(&rq->mpwqe.wq); 404 default: 405 return mlx5_wq_cyc_get_counter(&rq->wqe.wq); 406 } 407 } 408 409 /* SW parser related functions */ 410 411 struct mlx5e_swp_spec { 412 __be16 l3_proto; 413 u8 l4_proto; 414 u8 is_tun; 415 __be16 tun_l3_proto; 416 u8 tun_l4_proto; 417 }; 418 419 static inline void mlx5e_eseg_swp_offsets_add_vlan(struct mlx5_wqe_eth_seg *eseg) 420 { 421 /* SWP offsets are in 2-bytes words */ 422 eseg->swp_outer_l3_offset += VLAN_HLEN / 2; 423 eseg->swp_outer_l4_offset += VLAN_HLEN / 2; 424 eseg->swp_inner_l3_offset += VLAN_HLEN / 2; 425 eseg->swp_inner_l4_offset += VLAN_HLEN / 2; 426 } 427 428 static inline void 429 mlx5e_set_eseg_swp(struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg, 430 struct mlx5e_swp_spec *swp_spec) 431 { 432 /* SWP offsets are in 2-bytes words */ 433 eseg->swp_outer_l3_offset = skb_network_offset(skb) / 2; 434 if (swp_spec->l3_proto == htons(ETH_P_IPV6)) 435 eseg->swp_flags |= MLX5_ETH_WQE_SWP_OUTER_L3_IPV6; 436 if (swp_spec->l4_proto) { 437 eseg->swp_outer_l4_offset = skb_transport_offset(skb) / 2; 438 if (swp_spec->l4_proto == IPPROTO_UDP) 439 eseg->swp_flags |= MLX5_ETH_WQE_SWP_OUTER_L4_UDP; 440 } 441 442 if (swp_spec->is_tun) { 443 eseg->swp_inner_l3_offset = skb_inner_network_offset(skb) / 2; 444 if (swp_spec->tun_l3_proto == htons(ETH_P_IPV6)) 445 eseg->swp_flags |= MLX5_ETH_WQE_SWP_INNER_L3_IPV6; 446 } else { /* typically for ipsec when xfrm mode != XFRM_MODE_TUNNEL */ 447 eseg->swp_inner_l3_offset = skb_network_offset(skb) / 2; 448 if (swp_spec->l3_proto == htons(ETH_P_IPV6)) 449 eseg->swp_flags |= MLX5_ETH_WQE_SWP_INNER_L3_IPV6; 450 } 451 switch (swp_spec->tun_l4_proto) { 452 case IPPROTO_UDP: 453 eseg->swp_flags |= MLX5_ETH_WQE_SWP_INNER_L4_UDP; 454 fallthrough; 455 case IPPROTO_TCP: 456 eseg->swp_inner_l4_offset = skb_inner_transport_offset(skb) / 2; 457 break; 458 } 459 } 460 461 #define MLX5E_STOP_ROOM(wqebbs) ((wqebbs) * 2 - 1) 462 463 static inline u16 mlx5e_stop_room_for_wqe(struct mlx5_core_dev *mdev, u16 wqe_size) 464 { 465 WARN_ON_ONCE(PAGE_SIZE / MLX5_SEND_WQE_BB < (u16)mlx5e_get_max_sq_wqebbs(mdev)); 466 467 /* A WQE must not cross the page boundary, hence two conditions: 468 * 1. Its size must not exceed the page size. 469 * 2. If the WQE size is X, and the space remaining in a page is less 470 * than X, this space needs to be padded with NOPs. So, one WQE of 471 * size X may require up to X-1 WQEBBs of padding, which makes the 472 * stop room of X-1 + X. 473 * WQE size is also limited by the hardware limit. 474 */ 475 WARN_ONCE(wqe_size > mlx5e_get_max_sq_wqebbs(mdev), 476 "wqe_size %u is greater than max SQ WQEBBs %u", 477 wqe_size, mlx5e_get_max_sq_wqebbs(mdev)); 478 479 return MLX5E_STOP_ROOM(wqe_size); 480 } 481 482 static inline u16 mlx5e_stop_room_for_max_wqe(struct mlx5_core_dev *mdev) 483 { 484 return MLX5E_STOP_ROOM(mlx5e_get_max_sq_wqebbs(mdev)); 485 } 486 487 static inline u16 mlx5e_stop_room_for_mpwqe(struct mlx5_core_dev *mdev) 488 { 489 u8 mpwqe_wqebbs = mlx5e_get_max_sq_aligned_wqebbs(mdev); 490 491 return mlx5e_stop_room_for_wqe(mdev, mpwqe_wqebbs); 492 } 493 494 static inline bool mlx5e_icosq_can_post_wqe(struct mlx5e_icosq *sq, u16 wqe_size) 495 { 496 u16 room = sq->reserved_room + MLX5E_STOP_ROOM(wqe_size); 497 498 return mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, room); 499 } 500 501 static inline struct mlx5e_mpw_info *mlx5e_get_mpw_info(struct mlx5e_rq *rq, int i) 502 { 503 size_t isz = struct_size(rq->mpwqe.info, alloc_units.frag_pages, rq->mpwqe.pages_per_wqe); 504 505 return (struct mlx5e_mpw_info *)((char *)rq->mpwqe.info + array_size(i, isz)); 506 } 507 #endif 508