1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* Copyright (c) 2019 Mellanox Technologies. */ 3 4 #include "en/params.h" 5 #include "en/txrx.h" 6 #include "en/port.h" 7 #include "en_accel/en_accel.h" 8 #include "accel/ipsec.h" 9 #include "fpga/ipsec.h" 10 11 static bool mlx5e_rx_is_xdp(struct mlx5e_params *params, 12 struct mlx5e_xsk_param *xsk) 13 { 14 return params->xdp_prog || xsk; 15 } 16 17 u16 mlx5e_get_linear_rq_headroom(struct mlx5e_params *params, 18 struct mlx5e_xsk_param *xsk) 19 { 20 u16 headroom; 21 22 if (xsk) 23 return xsk->headroom; 24 25 headroom = NET_IP_ALIGN; 26 if (mlx5e_rx_is_xdp(params, xsk)) 27 headroom += XDP_PACKET_HEADROOM; 28 else 29 headroom += MLX5_RX_HEADROOM; 30 31 return headroom; 32 } 33 34 u32 mlx5e_rx_get_min_frag_sz(struct mlx5e_params *params, 35 struct mlx5e_xsk_param *xsk) 36 { 37 u32 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu); 38 u16 linear_rq_headroom = mlx5e_get_linear_rq_headroom(params, xsk); 39 40 return linear_rq_headroom + hw_mtu; 41 } 42 43 static u32 mlx5e_rx_get_linear_frag_sz(struct mlx5e_params *params, 44 struct mlx5e_xsk_param *xsk) 45 { 46 u32 frag_sz = mlx5e_rx_get_min_frag_sz(params, xsk); 47 48 /* AF_XDP doesn't build SKBs in place. */ 49 if (!xsk) 50 frag_sz = MLX5_SKB_FRAG_SZ(frag_sz); 51 52 /* XDP in mlx5e doesn't support multiple packets per page. AF_XDP is a 53 * special case. It can run with frames smaller than a page, as it 54 * doesn't allocate pages dynamically. However, here we pretend that 55 * fragments are page-sized: it allows to treat XSK frames like pages 56 * by redirecting alloc and free operations to XSK rings and by using 57 * the fact there are no multiple packets per "page" (which is a frame). 58 * The latter is important, because frames may come in a random order, 59 * and we will have trouble assemblying a real page of multiple frames. 60 */ 61 if (mlx5e_rx_is_xdp(params, xsk)) 62 frag_sz = max_t(u32, frag_sz, PAGE_SIZE); 63 64 /* Even if we can go with a smaller fragment size, we must not put 65 * multiple packets into a single frame. 66 */ 67 if (xsk) 68 frag_sz = max_t(u32, frag_sz, xsk->chunk_size); 69 70 return frag_sz; 71 } 72 73 u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params, 74 struct mlx5e_xsk_param *xsk) 75 { 76 u32 linear_frag_sz = mlx5e_rx_get_linear_frag_sz(params, xsk); 77 78 return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz); 79 } 80 81 bool mlx5e_rx_is_linear_skb(struct mlx5e_params *params, 82 struct mlx5e_xsk_param *xsk) 83 { 84 /* AF_XDP allocates SKBs on XDP_PASS - ensure they don't occupy more 85 * than one page. For this, check both with and without xsk. 86 */ 87 u32 linear_frag_sz = max(mlx5e_rx_get_linear_frag_sz(params, xsk), 88 mlx5e_rx_get_linear_frag_sz(params, NULL)); 89 90 return params->packet_merge.type == MLX5E_PACKET_MERGE_NONE && 91 linear_frag_sz <= PAGE_SIZE; 92 } 93 94 bool mlx5e_verify_rx_mpwqe_strides(struct mlx5_core_dev *mdev, 95 u8 log_stride_sz, u8 log_num_strides) 96 { 97 if (log_stride_sz + log_num_strides != MLX5_MPWRQ_LOG_WQE_SZ) 98 return false; 99 100 if (log_stride_sz < MLX5_MPWQE_LOG_STRIDE_SZ_BASE || 101 log_stride_sz > MLX5_MPWQE_LOG_STRIDE_SZ_MAX) 102 return false; 103 104 if (log_num_strides > MLX5_MPWQE_LOG_NUM_STRIDES_MAX) 105 return false; 106 107 if (MLX5_CAP_GEN(mdev, ext_stride_num_range)) 108 return log_num_strides >= MLX5_MPWQE_LOG_NUM_STRIDES_EXT_BASE; 109 110 return log_num_strides >= MLX5_MPWQE_LOG_NUM_STRIDES_BASE; 111 } 112 113 bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev, 114 struct mlx5e_params *params, 115 struct mlx5e_xsk_param *xsk) 116 { 117 s8 log_num_strides; 118 u8 log_stride_sz; 119 120 if (!mlx5e_rx_is_linear_skb(params, xsk)) 121 return false; 122 123 log_stride_sz = order_base_2(mlx5e_rx_get_linear_frag_sz(params, xsk)); 124 log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - log_stride_sz; 125 126 return mlx5e_verify_rx_mpwqe_strides(mdev, log_stride_sz, log_num_strides); 127 } 128 129 u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params, 130 struct mlx5e_xsk_param *xsk) 131 { 132 u8 log_pkts_per_wqe = mlx5e_mpwqe_log_pkts_per_wqe(params, xsk); 133 134 /* Numbers are unsigned, don't subtract to avoid underflow. */ 135 if (params->log_rq_mtu_frames < 136 log_pkts_per_wqe + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW) 137 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW; 138 139 return params->log_rq_mtu_frames - log_pkts_per_wqe; 140 } 141 142 u8 mlx5e_shampo_get_log_hd_entry_size(struct mlx5_core_dev *mdev, 143 struct mlx5e_params *params) 144 { 145 return order_base_2(DIV_ROUND_UP(MLX5E_RX_MAX_HEAD, MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE)); 146 } 147 148 u8 mlx5e_shampo_get_log_rsrv_size(struct mlx5_core_dev *mdev, 149 struct mlx5e_params *params) 150 { 151 return order_base_2(MLX5E_SHAMPO_WQ_RESRV_SIZE / MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE); 152 } 153 154 u8 mlx5e_shampo_get_log_pkt_per_rsrv(struct mlx5_core_dev *mdev, 155 struct mlx5e_params *params) 156 { 157 u32 resrv_size = BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) * 158 PAGE_SIZE; 159 160 return order_base_2(DIV_ROUND_UP(resrv_size, params->sw_mtu)); 161 } 162 163 u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev, 164 struct mlx5e_params *params, 165 struct mlx5e_xsk_param *xsk) 166 { 167 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, xsk)) 168 return order_base_2(mlx5e_rx_get_linear_frag_sz(params, xsk)); 169 170 return MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev); 171 } 172 173 u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev, 174 struct mlx5e_params *params, 175 struct mlx5e_xsk_param *xsk) 176 { 177 return MLX5_MPWRQ_LOG_WQE_SZ - 178 mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk); 179 } 180 181 u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev, 182 struct mlx5e_params *params, 183 struct mlx5e_xsk_param *xsk) 184 { 185 bool is_linear_skb = (params->rq_wq_type == MLX5_WQ_TYPE_CYCLIC) ? 186 mlx5e_rx_is_linear_skb(params, xsk) : 187 mlx5e_rx_mpwqe_is_linear_skb(mdev, params, xsk); 188 189 return is_linear_skb || params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO ? 190 mlx5e_get_linear_rq_headroom(params, xsk) : 0; 191 } 192 193 u16 mlx5e_calc_sq_stop_room(struct mlx5_core_dev *mdev, struct mlx5e_params *params) 194 { 195 bool is_mpwqe = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE); 196 u16 stop_room; 197 198 stop_room = mlx5e_tls_get_stop_room(mdev, params); 199 stop_room += mlx5e_stop_room_for_wqe(MLX5_SEND_WQE_MAX_WQEBBS); 200 if (is_mpwqe) 201 /* A MPWQE can take up to the maximum-sized WQE + all the normal 202 * stop room can be taken if a new packet breaks the active 203 * MPWQE session and allocates its WQEs right away. 204 */ 205 stop_room += mlx5e_stop_room_for_wqe(MLX5_SEND_WQE_MAX_WQEBBS); 206 207 return stop_room; 208 } 209 210 int mlx5e_validate_params(struct mlx5_core_dev *mdev, struct mlx5e_params *params) 211 { 212 size_t sq_size = 1 << params->log_sq_size; 213 u16 stop_room; 214 215 stop_room = mlx5e_calc_sq_stop_room(mdev, params); 216 if (stop_room >= sq_size) { 217 mlx5_core_err(mdev, "Stop room %u is bigger than the SQ size %zu\n", 218 stop_room, sq_size); 219 return -EINVAL; 220 } 221 222 return 0; 223 } 224 225 static struct dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode) 226 { 227 struct dim_cq_moder moder = {}; 228 229 moder.cq_period_mode = cq_period_mode; 230 moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS; 231 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC; 232 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE) 233 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE; 234 235 return moder; 236 } 237 238 static struct dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode) 239 { 240 struct dim_cq_moder moder = {}; 241 242 moder.cq_period_mode = cq_period_mode; 243 moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS; 244 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC; 245 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE) 246 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE; 247 248 return moder; 249 } 250 251 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode) 252 { 253 return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ? 254 DIM_CQ_PERIOD_MODE_START_FROM_CQE : 255 DIM_CQ_PERIOD_MODE_START_FROM_EQE; 256 } 257 258 void mlx5e_reset_tx_moderation(struct mlx5e_params *params, u8 cq_period_mode) 259 { 260 if (params->tx_dim_enabled) { 261 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode); 262 263 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode); 264 } else { 265 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode); 266 } 267 } 268 269 void mlx5e_reset_rx_moderation(struct mlx5e_params *params, u8 cq_period_mode) 270 { 271 if (params->rx_dim_enabled) { 272 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode); 273 274 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode); 275 } else { 276 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode); 277 } 278 } 279 280 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode) 281 { 282 mlx5e_reset_tx_moderation(params, cq_period_mode); 283 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER, 284 params->tx_cq_moderation.cq_period_mode == 285 MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 286 } 287 288 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode) 289 { 290 mlx5e_reset_rx_moderation(params, cq_period_mode); 291 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER, 292 params->rx_cq_moderation.cq_period_mode == 293 MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 294 } 295 296 bool slow_pci_heuristic(struct mlx5_core_dev *mdev) 297 { 298 u32 link_speed = 0; 299 u32 pci_bw = 0; 300 301 mlx5e_port_max_linkspeed(mdev, &link_speed); 302 pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL); 303 mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n", 304 link_speed, pci_bw); 305 306 #define MLX5E_SLOW_PCI_RATIO (2) 307 308 return link_speed && pci_bw && 309 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw; 310 } 311 312 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev, 313 struct mlx5e_params *params) 314 { 315 if (!mlx5e_check_fragmented_striding_rq_cap(mdev)) 316 return false; 317 318 if (mlx5_fpga_is_ipsec_device(mdev)) 319 return false; 320 321 if (params->xdp_prog) { 322 /* XSK params are not considered here. If striding RQ is in use, 323 * and an XSK is being opened, mlx5e_rx_mpwqe_is_linear_skb will 324 * be called with the known XSK params. 325 */ 326 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL)) 327 return false; 328 } 329 330 return true; 331 } 332 333 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev, 334 struct mlx5e_params *params) 335 { 336 params->log_rq_mtu_frames = is_kdump_kernel() ? 337 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE : 338 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE; 339 340 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n", 341 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ, 342 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ? 343 BIT(mlx5e_mpwqe_get_log_rq_size(params, NULL)) : 344 BIT(params->log_rq_mtu_frames), 345 BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL)), 346 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)); 347 } 348 349 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params) 350 { 351 params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) && 352 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ? 353 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ : 354 MLX5_WQ_TYPE_CYCLIC; 355 } 356 357 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev, 358 struct mlx5e_params *params) 359 { 360 /* Prefer Striding RQ, unless any of the following holds: 361 * - Striding RQ configuration is not possible/supported. 362 * - Slow PCI heuristic. 363 * - Legacy RQ would use linear SKB while Striding RQ would use non-linear. 364 * 365 * No XSK params: checking the availability of striding RQ in general. 366 */ 367 if (!slow_pci_heuristic(mdev) && 368 mlx5e_striding_rq_possible(mdev, params) && 369 (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) || 370 !mlx5e_rx_is_linear_skb(params, NULL))) 371 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true); 372 mlx5e_set_rq_type(mdev, params); 373 mlx5e_init_rq_type_params(mdev, params); 374 } 375 376 /* Build queue parameters */ 377 378 void mlx5e_build_create_cq_param(struct mlx5e_create_cq_param *ccp, struct mlx5e_channel *c) 379 { 380 *ccp = (struct mlx5e_create_cq_param) { 381 .napi = &c->napi, 382 .ch_stats = c->stats, 383 .node = cpu_to_node(c->cpu), 384 .ix = c->ix, 385 }; 386 } 387 388 #define DEFAULT_FRAG_SIZE (2048) 389 390 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev, 391 struct mlx5e_params *params, 392 struct mlx5e_xsk_param *xsk, 393 struct mlx5e_rq_frags_info *info) 394 { 395 u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu); 396 int frag_size_max = DEFAULT_FRAG_SIZE; 397 u32 buf_size = 0; 398 int i; 399 400 if (mlx5_fpga_is_ipsec_device(mdev)) 401 byte_count += MLX5E_METADATA_ETHER_LEN; 402 403 if (mlx5e_rx_is_linear_skb(params, xsk)) { 404 int frag_stride; 405 406 frag_stride = mlx5e_rx_get_linear_frag_sz(params, xsk); 407 frag_stride = roundup_pow_of_two(frag_stride); 408 409 info->arr[0].frag_size = byte_count; 410 info->arr[0].frag_stride = frag_stride; 411 info->num_frags = 1; 412 info->wqe_bulk = PAGE_SIZE / frag_stride; 413 goto out; 414 } 415 416 if (byte_count > PAGE_SIZE + 417 (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max) 418 frag_size_max = PAGE_SIZE; 419 420 i = 0; 421 while (buf_size < byte_count) { 422 int frag_size = byte_count - buf_size; 423 424 if (i < MLX5E_MAX_RX_FRAGS - 1) 425 frag_size = min(frag_size, frag_size_max); 426 427 info->arr[i].frag_size = frag_size; 428 info->arr[i].frag_stride = roundup_pow_of_two(frag_size); 429 430 buf_size += frag_size; 431 i++; 432 } 433 info->num_frags = i; 434 /* number of different wqes sharing a page */ 435 info->wqe_bulk = 1 + (info->num_frags % 2); 436 437 out: 438 info->wqe_bulk = max_t(u8, info->wqe_bulk, 8); 439 info->log_num_frags = order_base_2(info->num_frags); 440 } 441 442 static u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs) 443 { 444 int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs; 445 446 switch (wq_type) { 447 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 448 sz += sizeof(struct mlx5e_rx_wqe_ll); 449 break; 450 default: /* MLX5_WQ_TYPE_CYCLIC */ 451 sz += sizeof(struct mlx5e_rx_wqe_cyc); 452 } 453 454 return order_base_2(sz); 455 } 456 457 static void mlx5e_build_common_cq_param(struct mlx5_core_dev *mdev, 458 struct mlx5e_cq_param *param) 459 { 460 void *cqc = param->cqc; 461 462 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index); 463 if (MLX5_CAP_GEN(mdev, cqe_128_always) && cache_line_size() >= 128) 464 MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD); 465 } 466 467 static u32 mlx5e_shampo_get_log_cq_size(struct mlx5_core_dev *mdev, 468 struct mlx5e_params *params, 469 struct mlx5e_xsk_param *xsk) 470 { 471 int rsrv_size = BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) * PAGE_SIZE; 472 u16 num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk)); 473 int pkt_per_rsrv = BIT(mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params)); 474 u8 log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk); 475 int wq_size = BIT(mlx5e_mpwqe_get_log_rq_size(params, xsk)); 476 int wqe_size = BIT(log_stride_sz) * num_strides; 477 478 /* +1 is for the case that the pkt_per_rsrv dont consume the reservation 479 * so we get a filler cqe for the rest of the reservation. 480 */ 481 return order_base_2((wqe_size / rsrv_size) * wq_size * (pkt_per_rsrv + 1)); 482 } 483 484 static void mlx5e_build_rx_cq_param(struct mlx5_core_dev *mdev, 485 struct mlx5e_params *params, 486 struct mlx5e_xsk_param *xsk, 487 struct mlx5e_cq_param *param) 488 { 489 bool hw_stridx = false; 490 void *cqc = param->cqc; 491 u8 log_cq_size; 492 493 switch (params->rq_wq_type) { 494 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 495 hw_stridx = MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index); 496 if (params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) 497 log_cq_size = mlx5e_shampo_get_log_cq_size(mdev, params, xsk); 498 else 499 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params, xsk) + 500 mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk); 501 break; 502 default: /* MLX5_WQ_TYPE_CYCLIC */ 503 log_cq_size = params->log_rq_mtu_frames; 504 } 505 506 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size); 507 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) { 508 MLX5_SET(cqc, cqc, mini_cqe_res_format, hw_stridx ? 509 MLX5_CQE_FORMAT_CSUM_STRIDX : MLX5_CQE_FORMAT_CSUM); 510 MLX5_SET(cqc, cqc, cqe_comp_en, 1); 511 } 512 513 mlx5e_build_common_cq_param(mdev, param); 514 param->cq_period_mode = params->rx_cq_moderation.cq_period_mode; 515 } 516 517 static u8 rq_end_pad_mode(struct mlx5_core_dev *mdev, struct mlx5e_params *params) 518 { 519 bool lro_en = params->packet_merge.type == MLX5E_PACKET_MERGE_LRO; 520 bool ro = pcie_relaxed_ordering_enabled(mdev->pdev) && 521 MLX5_CAP_GEN(mdev, relaxed_ordering_write); 522 523 return ro && lro_en ? 524 MLX5_WQ_END_PAD_MODE_NONE : MLX5_WQ_END_PAD_MODE_ALIGN; 525 } 526 527 int mlx5e_build_rq_param(struct mlx5_core_dev *mdev, 528 struct mlx5e_params *params, 529 struct mlx5e_xsk_param *xsk, 530 u16 q_counter, 531 struct mlx5e_rq_param *param) 532 { 533 void *rqc = param->rqc; 534 void *wq = MLX5_ADDR_OF(rqc, rqc, wq); 535 int ndsegs = 1; 536 537 switch (params->rq_wq_type) { 538 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: { 539 u8 log_wqe_num_of_strides = mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk); 540 u8 log_wqe_stride_size = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk); 541 542 if (!mlx5e_verify_rx_mpwqe_strides(mdev, log_wqe_stride_size, 543 log_wqe_num_of_strides)) { 544 mlx5_core_err(mdev, 545 "Bad RX MPWQE params: log_stride_size %u, log_num_strides %u\n", 546 log_wqe_stride_size, log_wqe_num_of_strides); 547 return -EINVAL; 548 } 549 550 MLX5_SET(wq, wq, log_wqe_num_of_strides, 551 log_wqe_num_of_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE); 552 MLX5_SET(wq, wq, log_wqe_stride_size, 553 log_wqe_stride_size - MLX5_MPWQE_LOG_STRIDE_SZ_BASE); 554 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params, xsk)); 555 if (params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) { 556 MLX5_SET(wq, wq, shampo_enable, true); 557 MLX5_SET(wq, wq, log_reservation_size, 558 mlx5e_shampo_get_log_rsrv_size(mdev, params)); 559 MLX5_SET(wq, wq, 560 log_max_num_of_packets_per_reservation, 561 mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params)); 562 MLX5_SET(wq, wq, log_headers_entry_size, 563 mlx5e_shampo_get_log_hd_entry_size(mdev, params)); 564 MLX5_SET(rqc, rqc, reservation_timeout, 565 params->packet_merge.timeout); 566 MLX5_SET(rqc, rqc, shampo_match_criteria_type, 567 params->packet_merge.shampo.match_criteria_type); 568 MLX5_SET(rqc, rqc, shampo_no_match_alignment_granularity, 569 params->packet_merge.shampo.alignment_granularity); 570 } 571 break; 572 } 573 default: /* MLX5_WQ_TYPE_CYCLIC */ 574 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames); 575 mlx5e_build_rq_frags_info(mdev, params, xsk, ¶m->frags_info); 576 ndsegs = param->frags_info.num_frags; 577 } 578 579 MLX5_SET(wq, wq, wq_type, params->rq_wq_type); 580 MLX5_SET(wq, wq, end_padding_mode, rq_end_pad_mode(mdev, params)); 581 MLX5_SET(wq, wq, log_wq_stride, 582 mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs)); 583 MLX5_SET(wq, wq, pd, mdev->mlx5e_res.hw_objs.pdn); 584 MLX5_SET(rqc, rqc, counter_set_id, q_counter); 585 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable); 586 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en); 587 588 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev)); 589 mlx5e_build_rx_cq_param(mdev, params, xsk, ¶m->cqp); 590 591 return 0; 592 } 593 594 void mlx5e_build_drop_rq_param(struct mlx5_core_dev *mdev, 595 u16 q_counter, 596 struct mlx5e_rq_param *param) 597 { 598 void *rqc = param->rqc; 599 void *wq = MLX5_ADDR_OF(rqc, rqc, wq); 600 601 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 602 MLX5_SET(wq, wq, log_wq_stride, 603 mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1)); 604 MLX5_SET(rqc, rqc, counter_set_id, q_counter); 605 606 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev)); 607 } 608 609 void mlx5e_build_tx_cq_param(struct mlx5_core_dev *mdev, 610 struct mlx5e_params *params, 611 struct mlx5e_cq_param *param) 612 { 613 void *cqc = param->cqc; 614 615 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size); 616 617 mlx5e_build_common_cq_param(mdev, param); 618 param->cq_period_mode = params->tx_cq_moderation.cq_period_mode; 619 } 620 621 void mlx5e_build_sq_param_common(struct mlx5_core_dev *mdev, 622 struct mlx5e_sq_param *param) 623 { 624 void *sqc = param->sqc; 625 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 626 627 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 628 MLX5_SET(wq, wq, pd, mdev->mlx5e_res.hw_objs.pdn); 629 630 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev)); 631 } 632 633 void mlx5e_build_sq_param(struct mlx5_core_dev *mdev, 634 struct mlx5e_params *params, 635 struct mlx5e_sq_param *param) 636 { 637 void *sqc = param->sqc; 638 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 639 bool allow_swp; 640 641 allow_swp = mlx5_geneve_tx_allowed(mdev) || 642 !!MLX5_IPSEC_DEV(mdev); 643 mlx5e_build_sq_param_common(mdev, param); 644 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size); 645 MLX5_SET(sqc, sqc, allow_swp, allow_swp); 646 param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE); 647 param->stop_room = mlx5e_calc_sq_stop_room(mdev, params); 648 mlx5e_build_tx_cq_param(mdev, params, ¶m->cqp); 649 } 650 651 static void mlx5e_build_ico_cq_param(struct mlx5_core_dev *mdev, 652 u8 log_wq_size, 653 struct mlx5e_cq_param *param) 654 { 655 void *cqc = param->cqc; 656 657 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size); 658 659 mlx5e_build_common_cq_param(mdev, param); 660 661 param->cq_period_mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 662 } 663 664 static u8 mlx5e_get_rq_log_wq_sz(void *rqc) 665 { 666 void *wq = MLX5_ADDR_OF(rqc, rqc, wq); 667 668 return MLX5_GET(wq, wq, log_wq_sz); 669 } 670 671 /* This function calculates the maximum number of headers entries that are needed 672 * per WQE, the formula is based on the size of the reservations and the 673 * restriction we have about max packets for reservation that is equal to max 674 * headers per reservation. 675 */ 676 u32 mlx5e_shampo_hd_per_wqe(struct mlx5_core_dev *mdev, 677 struct mlx5e_params *params, 678 struct mlx5e_rq_param *rq_param) 679 { 680 int resv_size = BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) * PAGE_SIZE; 681 u16 num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, NULL)); 682 int pkt_per_resv = BIT(mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params)); 683 u8 log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL); 684 int wqe_size = BIT(log_stride_sz) * num_strides; 685 u32 hd_per_wqe; 686 687 /* Assumption: hd_per_wqe % 8 == 0. */ 688 hd_per_wqe = (wqe_size / resv_size) * pkt_per_resv; 689 mlx5_core_dbg(mdev, "%s hd_per_wqe = %d rsrv_size = %d wqe_size = %d pkt_per_resv = %d\n", 690 __func__, hd_per_wqe, resv_size, wqe_size, pkt_per_resv); 691 return hd_per_wqe; 692 } 693 694 /* This function calculates the maximum number of headers entries that are needed 695 * for the WQ, this value is uesed to allocate the header buffer in HW, thus 696 * must be a pow of 2. 697 */ 698 u32 mlx5e_shampo_hd_per_wq(struct mlx5_core_dev *mdev, 699 struct mlx5e_params *params, 700 struct mlx5e_rq_param *rq_param) 701 { 702 void *wqc = MLX5_ADDR_OF(rqc, rq_param->rqc, wq); 703 int wq_size = BIT(MLX5_GET(wq, wqc, log_wq_sz)); 704 u32 hd_per_wqe, hd_per_wq; 705 706 hd_per_wqe = mlx5e_shampo_hd_per_wqe(mdev, params, rq_param); 707 hd_per_wq = roundup_pow_of_two(hd_per_wqe * wq_size); 708 return hd_per_wq; 709 } 710 711 static u32 mlx5e_shampo_icosq_sz(struct mlx5_core_dev *mdev, 712 struct mlx5e_params *params, 713 struct mlx5e_rq_param *rq_param) 714 { 715 int max_num_of_umr_per_wqe, max_hd_per_wqe, max_klm_per_umr, rest; 716 void *wqc = MLX5_ADDR_OF(rqc, rq_param->rqc, wq); 717 int wq_size = BIT(MLX5_GET(wq, wqc, log_wq_sz)); 718 u32 wqebbs; 719 720 max_klm_per_umr = MLX5E_MAX_KLM_PER_WQE(mdev); 721 max_hd_per_wqe = mlx5e_shampo_hd_per_wqe(mdev, params, rq_param); 722 max_num_of_umr_per_wqe = max_hd_per_wqe / max_klm_per_umr; 723 rest = max_hd_per_wqe % max_klm_per_umr; 724 wqebbs = MLX5E_KLM_UMR_WQEBBS(max_klm_per_umr) * max_num_of_umr_per_wqe; 725 if (rest) 726 wqebbs += MLX5E_KLM_UMR_WQEBBS(rest); 727 wqebbs *= wq_size; 728 return wqebbs; 729 } 730 731 static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5_core_dev *mdev, 732 struct mlx5e_params *params, 733 struct mlx5e_rq_param *rqp) 734 { 735 u32 wqebbs; 736 737 /* MLX5_WQ_TYPE_CYCLIC */ 738 if (params->rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) 739 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE; 740 741 wqebbs = MLX5E_UMR_WQEBBS * BIT(mlx5e_get_rq_log_wq_sz(rqp->rqc)); 742 if (params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) 743 wqebbs += mlx5e_shampo_icosq_sz(mdev, params, rqp); 744 return max_t(u8, MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE, order_base_2(wqebbs)); 745 } 746 747 static u8 mlx5e_build_async_icosq_log_wq_sz(struct mlx5_core_dev *mdev) 748 { 749 if (mlx5e_accel_is_ktls_rx(mdev)) 750 return MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; 751 752 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE; 753 } 754 755 static void mlx5e_build_icosq_param(struct mlx5_core_dev *mdev, 756 u8 log_wq_size, 757 struct mlx5e_sq_param *param) 758 { 759 void *sqc = param->sqc; 760 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 761 762 mlx5e_build_sq_param_common(mdev, param); 763 764 MLX5_SET(wq, wq, log_wq_sz, log_wq_size); 765 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(mdev, reg_umr_sq)); 766 mlx5e_build_ico_cq_param(mdev, log_wq_size, ¶m->cqp); 767 } 768 769 static void mlx5e_build_async_icosq_param(struct mlx5_core_dev *mdev, 770 u8 log_wq_size, 771 struct mlx5e_sq_param *param) 772 { 773 void *sqc = param->sqc; 774 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 775 776 mlx5e_build_sq_param_common(mdev, param); 777 param->stop_room = mlx5e_stop_room_for_wqe(1); /* for XSK NOP */ 778 param->is_tls = mlx5e_accel_is_ktls_rx(mdev); 779 if (param->is_tls) 780 param->stop_room += mlx5e_stop_room_for_wqe(1); /* for TLS RX resync NOP */ 781 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(mdev, reg_umr_sq)); 782 MLX5_SET(wq, wq, log_wq_sz, log_wq_size); 783 mlx5e_build_ico_cq_param(mdev, log_wq_size, ¶m->cqp); 784 } 785 786 void mlx5e_build_xdpsq_param(struct mlx5_core_dev *mdev, 787 struct mlx5e_params *params, 788 struct mlx5e_sq_param *param) 789 { 790 void *sqc = param->sqc; 791 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 792 793 mlx5e_build_sq_param_common(mdev, param); 794 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size); 795 param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE); 796 mlx5e_build_tx_cq_param(mdev, params, ¶m->cqp); 797 } 798 799 int mlx5e_build_channel_param(struct mlx5_core_dev *mdev, 800 struct mlx5e_params *params, 801 u16 q_counter, 802 struct mlx5e_channel_param *cparam) 803 { 804 u8 icosq_log_wq_sz, async_icosq_log_wq_sz; 805 int err; 806 807 err = mlx5e_build_rq_param(mdev, params, NULL, q_counter, &cparam->rq); 808 if (err) 809 return err; 810 811 icosq_log_wq_sz = mlx5e_build_icosq_log_wq_sz(mdev, params, &cparam->rq); 812 async_icosq_log_wq_sz = mlx5e_build_async_icosq_log_wq_sz(mdev); 813 814 mlx5e_build_sq_param(mdev, params, &cparam->txq_sq); 815 mlx5e_build_xdpsq_param(mdev, params, &cparam->xdp_sq); 816 mlx5e_build_icosq_param(mdev, icosq_log_wq_sz, &cparam->icosq); 817 mlx5e_build_async_icosq_param(mdev, async_icosq_log_wq_sz, &cparam->async_icosq); 818 819 return 0; 820 } 821