1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* Copyright (c) 2019 Mellanox Technologies. */ 3 4 #include "en/params.h" 5 #include "en/txrx.h" 6 #include "en/port.h" 7 #include "en_accel/en_accel.h" 8 #include "accel/ipsec.h" 9 #include "fpga/ipsec.h" 10 11 static bool mlx5e_rx_is_xdp(struct mlx5e_params *params, 12 struct mlx5e_xsk_param *xsk) 13 { 14 return params->xdp_prog || xsk; 15 } 16 17 u16 mlx5e_get_linear_rq_headroom(struct mlx5e_params *params, 18 struct mlx5e_xsk_param *xsk) 19 { 20 u16 headroom; 21 22 if (xsk) 23 return xsk->headroom; 24 25 headroom = NET_IP_ALIGN; 26 if (mlx5e_rx_is_xdp(params, xsk)) 27 headroom += XDP_PACKET_HEADROOM; 28 else 29 headroom += MLX5_RX_HEADROOM; 30 31 return headroom; 32 } 33 34 u32 mlx5e_rx_get_min_frag_sz(struct mlx5e_params *params, 35 struct mlx5e_xsk_param *xsk) 36 { 37 u32 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu); 38 u16 linear_rq_headroom = mlx5e_get_linear_rq_headroom(params, xsk); 39 40 return linear_rq_headroom + hw_mtu; 41 } 42 43 static u32 mlx5e_rx_get_linear_frag_sz(struct mlx5e_params *params, 44 struct mlx5e_xsk_param *xsk) 45 { 46 u32 frag_sz = mlx5e_rx_get_min_frag_sz(params, xsk); 47 48 /* AF_XDP doesn't build SKBs in place. */ 49 if (!xsk) 50 frag_sz = MLX5_SKB_FRAG_SZ(frag_sz); 51 52 /* XDP in mlx5e doesn't support multiple packets per page. AF_XDP is a 53 * special case. It can run with frames smaller than a page, as it 54 * doesn't allocate pages dynamically. However, here we pretend that 55 * fragments are page-sized: it allows to treat XSK frames like pages 56 * by redirecting alloc and free operations to XSK rings and by using 57 * the fact there are no multiple packets per "page" (which is a frame). 58 * The latter is important, because frames may come in a random order, 59 * and we will have trouble assemblying a real page of multiple frames. 60 */ 61 if (mlx5e_rx_is_xdp(params, xsk)) 62 frag_sz = max_t(u32, frag_sz, PAGE_SIZE); 63 64 /* Even if we can go with a smaller fragment size, we must not put 65 * multiple packets into a single frame. 66 */ 67 if (xsk) 68 frag_sz = max_t(u32, frag_sz, xsk->chunk_size); 69 70 return frag_sz; 71 } 72 73 u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params, 74 struct mlx5e_xsk_param *xsk) 75 { 76 u32 linear_frag_sz = mlx5e_rx_get_linear_frag_sz(params, xsk); 77 78 return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz); 79 } 80 81 bool mlx5e_rx_is_linear_skb(struct mlx5e_params *params, 82 struct mlx5e_xsk_param *xsk) 83 { 84 /* AF_XDP allocates SKBs on XDP_PASS - ensure they don't occupy more 85 * than one page. For this, check both with and without xsk. 86 */ 87 u32 linear_frag_sz = max(mlx5e_rx_get_linear_frag_sz(params, xsk), 88 mlx5e_rx_get_linear_frag_sz(params, NULL)); 89 90 return params->packet_merge.type == MLX5E_PACKET_MERGE_NONE && 91 linear_frag_sz <= PAGE_SIZE; 92 } 93 94 bool mlx5e_verify_rx_mpwqe_strides(struct mlx5_core_dev *mdev, 95 u8 log_stride_sz, u8 log_num_strides) 96 { 97 if (log_stride_sz + log_num_strides != MLX5_MPWRQ_LOG_WQE_SZ) 98 return false; 99 100 if (log_stride_sz < MLX5_MPWQE_LOG_STRIDE_SZ_BASE || 101 log_stride_sz > MLX5_MPWQE_LOG_STRIDE_SZ_MAX) 102 return false; 103 104 if (log_num_strides > MLX5_MPWQE_LOG_NUM_STRIDES_MAX) 105 return false; 106 107 if (MLX5_CAP_GEN(mdev, ext_stride_num_range)) 108 return log_num_strides >= MLX5_MPWQE_LOG_NUM_STRIDES_EXT_BASE; 109 110 return log_num_strides >= MLX5_MPWQE_LOG_NUM_STRIDES_BASE; 111 } 112 113 bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev, 114 struct mlx5e_params *params, 115 struct mlx5e_xsk_param *xsk) 116 { 117 s8 log_num_strides; 118 u8 log_stride_sz; 119 120 if (!mlx5e_rx_is_linear_skb(params, xsk)) 121 return false; 122 123 log_stride_sz = order_base_2(mlx5e_rx_get_linear_frag_sz(params, xsk)); 124 log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - log_stride_sz; 125 126 return mlx5e_verify_rx_mpwqe_strides(mdev, log_stride_sz, log_num_strides); 127 } 128 129 u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params, 130 struct mlx5e_xsk_param *xsk) 131 { 132 u8 log_pkts_per_wqe = mlx5e_mpwqe_log_pkts_per_wqe(params, xsk); 133 134 /* Numbers are unsigned, don't subtract to avoid underflow. */ 135 if (params->log_rq_mtu_frames < 136 log_pkts_per_wqe + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW) 137 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW; 138 139 return params->log_rq_mtu_frames - log_pkts_per_wqe; 140 } 141 142 u8 mlx5e_shampo_get_log_hd_entry_size(struct mlx5_core_dev *mdev, 143 struct mlx5e_params *params) 144 { 145 return order_base_2(DIV_ROUND_UP(MLX5E_RX_MAX_HEAD, MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE)); 146 } 147 148 u8 mlx5e_shampo_get_log_rsrv_size(struct mlx5_core_dev *mdev, 149 struct mlx5e_params *params) 150 { 151 return order_base_2(MLX5E_SHAMPO_WQ_RESRV_SIZE / MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE); 152 } 153 154 u8 mlx5e_shampo_get_log_pkt_per_rsrv(struct mlx5_core_dev *mdev, 155 struct mlx5e_params *params) 156 { 157 u32 resrv_size = BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) * 158 PAGE_SIZE; 159 160 return order_base_2(DIV_ROUND_UP(resrv_size, params->sw_mtu)); 161 } 162 163 u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev, 164 struct mlx5e_params *params, 165 struct mlx5e_xsk_param *xsk) 166 { 167 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, xsk)) 168 return order_base_2(mlx5e_rx_get_linear_frag_sz(params, xsk)); 169 170 return MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev); 171 } 172 173 u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev, 174 struct mlx5e_params *params, 175 struct mlx5e_xsk_param *xsk) 176 { 177 return MLX5_MPWRQ_LOG_WQE_SZ - 178 mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk); 179 } 180 181 u8 mlx5e_mpwqe_get_min_wqe_bulk(unsigned int wq_sz) 182 { 183 #define UMR_WQE_BULK (2) 184 return min_t(unsigned int, UMR_WQE_BULK, wq_sz / 2 - 1); 185 } 186 187 u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev, 188 struct mlx5e_params *params, 189 struct mlx5e_xsk_param *xsk) 190 { 191 bool is_linear_skb = (params->rq_wq_type == MLX5_WQ_TYPE_CYCLIC) ? 192 mlx5e_rx_is_linear_skb(params, xsk) : 193 mlx5e_rx_mpwqe_is_linear_skb(mdev, params, xsk); 194 195 return is_linear_skb || params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO ? 196 mlx5e_get_linear_rq_headroom(params, xsk) : 0; 197 } 198 199 u16 mlx5e_calc_sq_stop_room(struct mlx5_core_dev *mdev, struct mlx5e_params *params) 200 { 201 bool is_mpwqe = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE); 202 u16 stop_room; 203 204 stop_room = mlx5e_tls_get_stop_room(mdev, params); 205 stop_room += mlx5e_stop_room_for_max_wqe(mdev); 206 if (is_mpwqe) 207 /* A MPWQE can take up to the maximum-sized WQE + all the normal 208 * stop room can be taken if a new packet breaks the active 209 * MPWQE session and allocates its WQEs right away. 210 */ 211 stop_room += mlx5e_stop_room_for_max_wqe(mdev); 212 213 return stop_room; 214 } 215 216 int mlx5e_validate_params(struct mlx5_core_dev *mdev, struct mlx5e_params *params) 217 { 218 size_t sq_size = 1 << params->log_sq_size; 219 u16 stop_room; 220 221 stop_room = mlx5e_calc_sq_stop_room(mdev, params); 222 if (stop_room >= sq_size) { 223 mlx5_core_err(mdev, "Stop room %u is bigger than the SQ size %zu\n", 224 stop_room, sq_size); 225 return -EINVAL; 226 } 227 228 return 0; 229 } 230 231 static struct dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode) 232 { 233 struct dim_cq_moder moder = {}; 234 235 moder.cq_period_mode = cq_period_mode; 236 moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS; 237 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC; 238 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE) 239 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE; 240 241 return moder; 242 } 243 244 static struct dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode) 245 { 246 struct dim_cq_moder moder = {}; 247 248 moder.cq_period_mode = cq_period_mode; 249 moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS; 250 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC; 251 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE) 252 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE; 253 254 return moder; 255 } 256 257 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode) 258 { 259 return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ? 260 DIM_CQ_PERIOD_MODE_START_FROM_CQE : 261 DIM_CQ_PERIOD_MODE_START_FROM_EQE; 262 } 263 264 void mlx5e_reset_tx_moderation(struct mlx5e_params *params, u8 cq_period_mode) 265 { 266 if (params->tx_dim_enabled) { 267 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode); 268 269 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode); 270 } else { 271 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode); 272 } 273 } 274 275 void mlx5e_reset_rx_moderation(struct mlx5e_params *params, u8 cq_period_mode) 276 { 277 if (params->rx_dim_enabled) { 278 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode); 279 280 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode); 281 } else { 282 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode); 283 } 284 } 285 286 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode) 287 { 288 mlx5e_reset_tx_moderation(params, cq_period_mode); 289 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER, 290 params->tx_cq_moderation.cq_period_mode == 291 MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 292 } 293 294 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode) 295 { 296 mlx5e_reset_rx_moderation(params, cq_period_mode); 297 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER, 298 params->rx_cq_moderation.cq_period_mode == 299 MLX5_CQ_PERIOD_MODE_START_FROM_CQE); 300 } 301 302 bool slow_pci_heuristic(struct mlx5_core_dev *mdev) 303 { 304 u32 link_speed = 0; 305 u32 pci_bw = 0; 306 307 mlx5e_port_max_linkspeed(mdev, &link_speed); 308 pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL); 309 mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n", 310 link_speed, pci_bw); 311 312 #define MLX5E_SLOW_PCI_RATIO (2) 313 314 return link_speed && pci_bw && 315 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw; 316 } 317 318 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev, 319 struct mlx5e_params *params) 320 { 321 if (!mlx5e_check_fragmented_striding_rq_cap(mdev)) 322 return false; 323 324 if (mlx5_fpga_is_ipsec_device(mdev)) 325 return false; 326 327 if (params->xdp_prog) { 328 /* XSK params are not considered here. If striding RQ is in use, 329 * and an XSK is being opened, mlx5e_rx_mpwqe_is_linear_skb will 330 * be called with the known XSK params. 331 */ 332 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL)) 333 return false; 334 } 335 336 return true; 337 } 338 339 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev, 340 struct mlx5e_params *params) 341 { 342 params->log_rq_mtu_frames = is_kdump_kernel() ? 343 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE : 344 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE; 345 346 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n", 347 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ, 348 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ? 349 BIT(mlx5e_mpwqe_get_log_rq_size(params, NULL)) : 350 BIT(params->log_rq_mtu_frames), 351 BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL)), 352 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)); 353 } 354 355 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params) 356 { 357 params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) && 358 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ? 359 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ : 360 MLX5_WQ_TYPE_CYCLIC; 361 } 362 363 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev, 364 struct mlx5e_params *params) 365 { 366 /* Prefer Striding RQ, unless any of the following holds: 367 * - Striding RQ configuration is not possible/supported. 368 * - CQE compression is ON, and stride_index mini_cqe layout is not supported. 369 * - Legacy RQ would use linear SKB while Striding RQ would use non-linear. 370 * 371 * No XSK params: checking the availability of striding RQ in general. 372 */ 373 if ((!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS) || 374 MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index)) && 375 mlx5e_striding_rq_possible(mdev, params) && 376 (mlx5e_rx_mpwqe_is_linear_skb(mdev, params, NULL) || 377 !mlx5e_rx_is_linear_skb(params, NULL))) 378 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true); 379 mlx5e_set_rq_type(mdev, params); 380 mlx5e_init_rq_type_params(mdev, params); 381 } 382 383 /* Build queue parameters */ 384 385 void mlx5e_build_create_cq_param(struct mlx5e_create_cq_param *ccp, struct mlx5e_channel *c) 386 { 387 *ccp = (struct mlx5e_create_cq_param) { 388 .napi = &c->napi, 389 .ch_stats = c->stats, 390 .node = cpu_to_node(c->cpu), 391 .ix = c->ix, 392 }; 393 } 394 395 #define DEFAULT_FRAG_SIZE (2048) 396 397 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev, 398 struct mlx5e_params *params, 399 struct mlx5e_xsk_param *xsk, 400 struct mlx5e_rq_frags_info *info) 401 { 402 u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu); 403 int frag_size_max = DEFAULT_FRAG_SIZE; 404 u32 buf_size = 0; 405 int i; 406 407 if (mlx5_fpga_is_ipsec_device(mdev)) 408 byte_count += MLX5E_METADATA_ETHER_LEN; 409 410 if (mlx5e_rx_is_linear_skb(params, xsk)) { 411 int frag_stride; 412 413 frag_stride = mlx5e_rx_get_linear_frag_sz(params, xsk); 414 frag_stride = roundup_pow_of_two(frag_stride); 415 416 info->arr[0].frag_size = byte_count; 417 info->arr[0].frag_stride = frag_stride; 418 info->num_frags = 1; 419 info->wqe_bulk = PAGE_SIZE / frag_stride; 420 goto out; 421 } 422 423 if (byte_count > PAGE_SIZE + 424 (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max) 425 frag_size_max = PAGE_SIZE; 426 427 i = 0; 428 while (buf_size < byte_count) { 429 int frag_size = byte_count - buf_size; 430 431 if (i < MLX5E_MAX_RX_FRAGS - 1) 432 frag_size = min(frag_size, frag_size_max); 433 434 info->arr[i].frag_size = frag_size; 435 info->arr[i].frag_stride = roundup_pow_of_two(frag_size); 436 437 buf_size += frag_size; 438 i++; 439 } 440 info->num_frags = i; 441 /* number of different wqes sharing a page */ 442 info->wqe_bulk = 1 + (info->num_frags % 2); 443 444 out: 445 info->wqe_bulk = max_t(u8, info->wqe_bulk, 8); 446 info->log_num_frags = order_base_2(info->num_frags); 447 } 448 449 static u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs) 450 { 451 int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs; 452 453 switch (wq_type) { 454 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 455 sz += sizeof(struct mlx5e_rx_wqe_ll); 456 break; 457 default: /* MLX5_WQ_TYPE_CYCLIC */ 458 sz += sizeof(struct mlx5e_rx_wqe_cyc); 459 } 460 461 return order_base_2(sz); 462 } 463 464 static void mlx5e_build_common_cq_param(struct mlx5_core_dev *mdev, 465 struct mlx5e_cq_param *param) 466 { 467 void *cqc = param->cqc; 468 469 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index); 470 if (MLX5_CAP_GEN(mdev, cqe_128_always) && cache_line_size() >= 128) 471 MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD); 472 } 473 474 static u32 mlx5e_shampo_get_log_cq_size(struct mlx5_core_dev *mdev, 475 struct mlx5e_params *params, 476 struct mlx5e_xsk_param *xsk) 477 { 478 int rsrv_size = BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) * PAGE_SIZE; 479 u16 num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk)); 480 int pkt_per_rsrv = BIT(mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params)); 481 u8 log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk); 482 int wq_size = BIT(mlx5e_mpwqe_get_log_rq_size(params, xsk)); 483 int wqe_size = BIT(log_stride_sz) * num_strides; 484 485 /* +1 is for the case that the pkt_per_rsrv dont consume the reservation 486 * so we get a filler cqe for the rest of the reservation. 487 */ 488 return order_base_2((wqe_size / rsrv_size) * wq_size * (pkt_per_rsrv + 1)); 489 } 490 491 static void mlx5e_build_rx_cq_param(struct mlx5_core_dev *mdev, 492 struct mlx5e_params *params, 493 struct mlx5e_xsk_param *xsk, 494 struct mlx5e_cq_param *param) 495 { 496 bool hw_stridx = false; 497 void *cqc = param->cqc; 498 u8 log_cq_size; 499 500 switch (params->rq_wq_type) { 501 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 502 hw_stridx = MLX5_CAP_GEN(mdev, mini_cqe_resp_stride_index); 503 if (params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) 504 log_cq_size = mlx5e_shampo_get_log_cq_size(mdev, params, xsk); 505 else 506 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params, xsk) + 507 mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk); 508 break; 509 default: /* MLX5_WQ_TYPE_CYCLIC */ 510 log_cq_size = params->log_rq_mtu_frames; 511 } 512 513 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size); 514 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) { 515 MLX5_SET(cqc, cqc, mini_cqe_res_format, hw_stridx ? 516 MLX5_CQE_FORMAT_CSUM_STRIDX : MLX5_CQE_FORMAT_CSUM); 517 MLX5_SET(cqc, cqc, cqe_comp_en, 1); 518 } 519 520 mlx5e_build_common_cq_param(mdev, param); 521 param->cq_period_mode = params->rx_cq_moderation.cq_period_mode; 522 } 523 524 static u8 rq_end_pad_mode(struct mlx5_core_dev *mdev, struct mlx5e_params *params) 525 { 526 bool lro_en = params->packet_merge.type == MLX5E_PACKET_MERGE_LRO; 527 bool ro = pcie_relaxed_ordering_enabled(mdev->pdev) && 528 MLX5_CAP_GEN(mdev, relaxed_ordering_write); 529 530 return ro && lro_en ? 531 MLX5_WQ_END_PAD_MODE_NONE : MLX5_WQ_END_PAD_MODE_ALIGN; 532 } 533 534 int mlx5e_build_rq_param(struct mlx5_core_dev *mdev, 535 struct mlx5e_params *params, 536 struct mlx5e_xsk_param *xsk, 537 u16 q_counter, 538 struct mlx5e_rq_param *param) 539 { 540 void *rqc = param->rqc; 541 void *wq = MLX5_ADDR_OF(rqc, rqc, wq); 542 int ndsegs = 1; 543 544 switch (params->rq_wq_type) { 545 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: { 546 u8 log_wqe_num_of_strides = mlx5e_mpwqe_get_log_num_strides(mdev, params, xsk); 547 u8 log_wqe_stride_size = mlx5e_mpwqe_get_log_stride_size(mdev, params, xsk); 548 549 if (!mlx5e_verify_rx_mpwqe_strides(mdev, log_wqe_stride_size, 550 log_wqe_num_of_strides)) { 551 mlx5_core_err(mdev, 552 "Bad RX MPWQE params: log_stride_size %u, log_num_strides %u\n", 553 log_wqe_stride_size, log_wqe_num_of_strides); 554 return -EINVAL; 555 } 556 557 MLX5_SET(wq, wq, log_wqe_num_of_strides, 558 log_wqe_num_of_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE); 559 MLX5_SET(wq, wq, log_wqe_stride_size, 560 log_wqe_stride_size - MLX5_MPWQE_LOG_STRIDE_SZ_BASE); 561 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params, xsk)); 562 if (params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) { 563 MLX5_SET(wq, wq, shampo_enable, true); 564 MLX5_SET(wq, wq, log_reservation_size, 565 mlx5e_shampo_get_log_rsrv_size(mdev, params)); 566 MLX5_SET(wq, wq, 567 log_max_num_of_packets_per_reservation, 568 mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params)); 569 MLX5_SET(wq, wq, log_headers_entry_size, 570 mlx5e_shampo_get_log_hd_entry_size(mdev, params)); 571 MLX5_SET(rqc, rqc, reservation_timeout, 572 params->packet_merge.timeout); 573 MLX5_SET(rqc, rqc, shampo_match_criteria_type, 574 params->packet_merge.shampo.match_criteria_type); 575 MLX5_SET(rqc, rqc, shampo_no_match_alignment_granularity, 576 params->packet_merge.shampo.alignment_granularity); 577 } 578 break; 579 } 580 default: /* MLX5_WQ_TYPE_CYCLIC */ 581 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames); 582 mlx5e_build_rq_frags_info(mdev, params, xsk, ¶m->frags_info); 583 ndsegs = param->frags_info.num_frags; 584 } 585 586 MLX5_SET(wq, wq, wq_type, params->rq_wq_type); 587 MLX5_SET(wq, wq, end_padding_mode, rq_end_pad_mode(mdev, params)); 588 MLX5_SET(wq, wq, log_wq_stride, 589 mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs)); 590 MLX5_SET(wq, wq, pd, mdev->mlx5e_res.hw_objs.pdn); 591 MLX5_SET(rqc, rqc, counter_set_id, q_counter); 592 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable); 593 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en); 594 595 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev)); 596 mlx5e_build_rx_cq_param(mdev, params, xsk, ¶m->cqp); 597 598 return 0; 599 } 600 601 void mlx5e_build_drop_rq_param(struct mlx5_core_dev *mdev, 602 u16 q_counter, 603 struct mlx5e_rq_param *param) 604 { 605 void *rqc = param->rqc; 606 void *wq = MLX5_ADDR_OF(rqc, rqc, wq); 607 608 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); 609 MLX5_SET(wq, wq, log_wq_stride, 610 mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1)); 611 MLX5_SET(rqc, rqc, counter_set_id, q_counter); 612 613 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev)); 614 } 615 616 void mlx5e_build_tx_cq_param(struct mlx5_core_dev *mdev, 617 struct mlx5e_params *params, 618 struct mlx5e_cq_param *param) 619 { 620 void *cqc = param->cqc; 621 622 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size); 623 624 mlx5e_build_common_cq_param(mdev, param); 625 param->cq_period_mode = params->tx_cq_moderation.cq_period_mode; 626 } 627 628 void mlx5e_build_sq_param_common(struct mlx5_core_dev *mdev, 629 struct mlx5e_sq_param *param) 630 { 631 void *sqc = param->sqc; 632 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 633 634 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); 635 MLX5_SET(wq, wq, pd, mdev->mlx5e_res.hw_objs.pdn); 636 637 param->wq.buf_numa_node = dev_to_node(mlx5_core_dma_dev(mdev)); 638 } 639 640 void mlx5e_build_sq_param(struct mlx5_core_dev *mdev, 641 struct mlx5e_params *params, 642 struct mlx5e_sq_param *param) 643 { 644 void *sqc = param->sqc; 645 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 646 bool allow_swp; 647 648 allow_swp = mlx5_geneve_tx_allowed(mdev) || 649 !!MLX5_IPSEC_DEV(mdev); 650 mlx5e_build_sq_param_common(mdev, param); 651 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size); 652 MLX5_SET(sqc, sqc, allow_swp, allow_swp); 653 param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_SKB_TX_MPWQE); 654 param->stop_room = mlx5e_calc_sq_stop_room(mdev, params); 655 mlx5e_build_tx_cq_param(mdev, params, ¶m->cqp); 656 } 657 658 static void mlx5e_build_ico_cq_param(struct mlx5_core_dev *mdev, 659 u8 log_wq_size, 660 struct mlx5e_cq_param *param) 661 { 662 void *cqc = param->cqc; 663 664 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size); 665 666 mlx5e_build_common_cq_param(mdev, param); 667 668 param->cq_period_mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 669 } 670 671 static u8 mlx5e_get_rq_log_wq_sz(void *rqc) 672 { 673 void *wq = MLX5_ADDR_OF(rqc, rqc, wq); 674 675 return MLX5_GET(wq, wq, log_wq_sz); 676 } 677 678 /* This function calculates the maximum number of headers entries that are needed 679 * per WQE, the formula is based on the size of the reservations and the 680 * restriction we have about max packets for reservation that is equal to max 681 * headers per reservation. 682 */ 683 u32 mlx5e_shampo_hd_per_wqe(struct mlx5_core_dev *mdev, 684 struct mlx5e_params *params, 685 struct mlx5e_rq_param *rq_param) 686 { 687 int resv_size = BIT(mlx5e_shampo_get_log_rsrv_size(mdev, params)) * PAGE_SIZE; 688 u16 num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, NULL)); 689 int pkt_per_resv = BIT(mlx5e_shampo_get_log_pkt_per_rsrv(mdev, params)); 690 u8 log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL); 691 int wqe_size = BIT(log_stride_sz) * num_strides; 692 u32 hd_per_wqe; 693 694 /* Assumption: hd_per_wqe % 8 == 0. */ 695 hd_per_wqe = (wqe_size / resv_size) * pkt_per_resv; 696 mlx5_core_dbg(mdev, "%s hd_per_wqe = %d rsrv_size = %d wqe_size = %d pkt_per_resv = %d\n", 697 __func__, hd_per_wqe, resv_size, wqe_size, pkt_per_resv); 698 return hd_per_wqe; 699 } 700 701 /* This function calculates the maximum number of headers entries that are needed 702 * for the WQ, this value is uesed to allocate the header buffer in HW, thus 703 * must be a pow of 2. 704 */ 705 u32 mlx5e_shampo_hd_per_wq(struct mlx5_core_dev *mdev, 706 struct mlx5e_params *params, 707 struct mlx5e_rq_param *rq_param) 708 { 709 void *wqc = MLX5_ADDR_OF(rqc, rq_param->rqc, wq); 710 int wq_size = BIT(MLX5_GET(wq, wqc, log_wq_sz)); 711 u32 hd_per_wqe, hd_per_wq; 712 713 hd_per_wqe = mlx5e_shampo_hd_per_wqe(mdev, params, rq_param); 714 hd_per_wq = roundup_pow_of_two(hd_per_wqe * wq_size); 715 return hd_per_wq; 716 } 717 718 static u32 mlx5e_shampo_icosq_sz(struct mlx5_core_dev *mdev, 719 struct mlx5e_params *params, 720 struct mlx5e_rq_param *rq_param) 721 { 722 int max_num_of_umr_per_wqe, max_hd_per_wqe, max_klm_per_umr, rest; 723 void *wqc = MLX5_ADDR_OF(rqc, rq_param->rqc, wq); 724 int wq_size = BIT(MLX5_GET(wq, wqc, log_wq_sz)); 725 u32 wqebbs; 726 727 max_klm_per_umr = MLX5E_MAX_KLM_PER_WQE(mdev); 728 max_hd_per_wqe = mlx5e_shampo_hd_per_wqe(mdev, params, rq_param); 729 max_num_of_umr_per_wqe = max_hd_per_wqe / max_klm_per_umr; 730 rest = max_hd_per_wqe % max_klm_per_umr; 731 wqebbs = MLX5E_KLM_UMR_WQEBBS(max_klm_per_umr) * max_num_of_umr_per_wqe; 732 if (rest) 733 wqebbs += MLX5E_KLM_UMR_WQEBBS(rest); 734 wqebbs *= wq_size; 735 return wqebbs; 736 } 737 738 static u8 mlx5e_build_icosq_log_wq_sz(struct mlx5_core_dev *mdev, 739 struct mlx5e_params *params, 740 struct mlx5e_rq_param *rqp) 741 { 742 u32 wqebbs; 743 744 /* MLX5_WQ_TYPE_CYCLIC */ 745 if (params->rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) 746 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE; 747 748 wqebbs = MLX5E_UMR_WQEBBS * BIT(mlx5e_get_rq_log_wq_sz(rqp->rqc)); 749 if (params->packet_merge.type == MLX5E_PACKET_MERGE_SHAMPO) 750 wqebbs += mlx5e_shampo_icosq_sz(mdev, params, rqp); 751 return max_t(u8, MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE, order_base_2(wqebbs)); 752 } 753 754 static u8 mlx5e_build_async_icosq_log_wq_sz(struct mlx5_core_dev *mdev) 755 { 756 if (mlx5e_accel_is_ktls_rx(mdev)) 757 return MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; 758 759 return MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE; 760 } 761 762 static void mlx5e_build_icosq_param(struct mlx5_core_dev *mdev, 763 u8 log_wq_size, 764 struct mlx5e_sq_param *param) 765 { 766 void *sqc = param->sqc; 767 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 768 769 mlx5e_build_sq_param_common(mdev, param); 770 771 MLX5_SET(wq, wq, log_wq_sz, log_wq_size); 772 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(mdev, reg_umr_sq)); 773 mlx5e_build_ico_cq_param(mdev, log_wq_size, ¶m->cqp); 774 } 775 776 static void mlx5e_build_async_icosq_param(struct mlx5_core_dev *mdev, 777 u8 log_wq_size, 778 struct mlx5e_sq_param *param) 779 { 780 void *sqc = param->sqc; 781 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 782 783 mlx5e_build_sq_param_common(mdev, param); 784 param->stop_room = mlx5e_stop_room_for_wqe(mdev, 1); /* for XSK NOP */ 785 param->is_tls = mlx5e_accel_is_ktls_rx(mdev); 786 if (param->is_tls) 787 param->stop_room += mlx5e_stop_room_for_wqe(mdev, 1); /* for TLS RX resync NOP */ 788 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(mdev, reg_umr_sq)); 789 MLX5_SET(wq, wq, log_wq_sz, log_wq_size); 790 mlx5e_build_ico_cq_param(mdev, log_wq_size, ¶m->cqp); 791 } 792 793 void mlx5e_build_xdpsq_param(struct mlx5_core_dev *mdev, 794 struct mlx5e_params *params, 795 struct mlx5e_sq_param *param) 796 { 797 void *sqc = param->sqc; 798 void *wq = MLX5_ADDR_OF(sqc, sqc, wq); 799 800 mlx5e_build_sq_param_common(mdev, param); 801 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size); 802 param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE); 803 mlx5e_build_tx_cq_param(mdev, params, ¶m->cqp); 804 } 805 806 int mlx5e_build_channel_param(struct mlx5_core_dev *mdev, 807 struct mlx5e_params *params, 808 u16 q_counter, 809 struct mlx5e_channel_param *cparam) 810 { 811 u8 icosq_log_wq_sz, async_icosq_log_wq_sz; 812 int err; 813 814 err = mlx5e_build_rq_param(mdev, params, NULL, q_counter, &cparam->rq); 815 if (err) 816 return err; 817 818 icosq_log_wq_sz = mlx5e_build_icosq_log_wq_sz(mdev, params, &cparam->rq); 819 async_icosq_log_wq_sz = mlx5e_build_async_icosq_log_wq_sz(mdev); 820 821 mlx5e_build_sq_param(mdev, params, &cparam->txq_sq); 822 mlx5e_build_xdpsq_param(mdev, params, &cparam->xdp_sq); 823 mlx5e_build_icosq_param(mdev, icosq_log_wq_sz, &cparam->icosq); 824 mlx5e_build_async_icosq_param(mdev, async_icosq_log_wq_sz, &cparam->async_icosq); 825 826 return 0; 827 } 828