1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* Copyright (c) 2018 Mellanox Technologies. */ 3 4 #ifndef __MLX5E_FLOW_STEER_H__ 5 #define __MLX5E_FLOW_STEER_H__ 6 7 enum { 8 MLX5E_TC_FT_LEVEL = 0, 9 MLX5E_TC_TTC_FT_LEVEL, 10 }; 11 12 struct mlx5e_tc_table { 13 /* protects flow table */ 14 struct mutex t_lock; 15 struct mlx5_flow_table *t; 16 17 struct rhashtable ht; 18 19 struct mod_hdr_tbl mod_hdr; 20 struct mutex hairpin_tbl_lock; /* protects hairpin_tbl */ 21 DECLARE_HASHTABLE(hairpin_tbl, 8); 22 23 struct notifier_block netdevice_nb; 24 struct netdev_net_notifier netdevice_nn; 25 }; 26 27 struct mlx5e_flow_table { 28 int num_groups; 29 struct mlx5_flow_table *t; 30 struct mlx5_flow_group **g; 31 }; 32 33 struct mlx5e_l2_rule { 34 u8 addr[ETH_ALEN + 2]; 35 struct mlx5_flow_handle *rule; 36 }; 37 38 #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE) 39 40 struct mlx5e_vlan_table { 41 struct mlx5e_flow_table ft; 42 DECLARE_BITMAP(active_cvlans, VLAN_N_VID); 43 DECLARE_BITMAP(active_svlans, VLAN_N_VID); 44 struct mlx5_flow_handle *active_cvlans_rule[VLAN_N_VID]; 45 struct mlx5_flow_handle *active_svlans_rule[VLAN_N_VID]; 46 struct mlx5_flow_handle *untagged_rule; 47 struct mlx5_flow_handle *any_cvlan_rule; 48 struct mlx5_flow_handle *any_svlan_rule; 49 bool cvlan_filter_disabled; 50 }; 51 52 struct mlx5e_l2_table { 53 struct mlx5e_flow_table ft; 54 struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE]; 55 struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE]; 56 struct mlx5e_l2_rule broadcast; 57 struct mlx5e_l2_rule allmulti; 58 struct mlx5e_l2_rule promisc; 59 bool broadcast_enabled; 60 bool allmulti_enabled; 61 bool promisc_enabled; 62 }; 63 64 enum mlx5e_traffic_types { 65 MLX5E_TT_IPV4_TCP, 66 MLX5E_TT_IPV6_TCP, 67 MLX5E_TT_IPV4_UDP, 68 MLX5E_TT_IPV6_UDP, 69 MLX5E_TT_IPV4_IPSEC_AH, 70 MLX5E_TT_IPV6_IPSEC_AH, 71 MLX5E_TT_IPV4_IPSEC_ESP, 72 MLX5E_TT_IPV6_IPSEC_ESP, 73 MLX5E_TT_IPV4, 74 MLX5E_TT_IPV6, 75 MLX5E_TT_ANY, 76 MLX5E_NUM_TT, 77 MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY, 78 }; 79 80 struct mlx5e_tirc_config { 81 u8 l3_prot_type; 82 u8 l4_prot_type; 83 u32 rx_hash_fields; 84 }; 85 86 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\ 87 MLX5_HASH_FIELD_SEL_DST_IP) 88 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\ 89 MLX5_HASH_FIELD_SEL_DST_IP |\ 90 MLX5_HASH_FIELD_SEL_L4_SPORT |\ 91 MLX5_HASH_FIELD_SEL_L4_DPORT) 92 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\ 93 MLX5_HASH_FIELD_SEL_DST_IP |\ 94 MLX5_HASH_FIELD_SEL_IPSEC_SPI) 95 96 enum mlx5e_tunnel_types { 97 MLX5E_TT_IPV4_GRE, 98 MLX5E_TT_IPV6_GRE, 99 MLX5E_TT_IPV4_IPIP, 100 MLX5E_TT_IPV6_IPIP, 101 MLX5E_TT_IPV4_IPV6, 102 MLX5E_TT_IPV6_IPV6, 103 MLX5E_NUM_TUNNEL_TT, 104 }; 105 106 bool mlx5e_tunnel_inner_ft_supported(struct mlx5_core_dev *mdev); 107 108 /* L3/L4 traffic type classifier */ 109 struct mlx5e_ttc_table { 110 struct mlx5e_flow_table ft; 111 struct mlx5_flow_handle *rules[MLX5E_NUM_TT]; 112 struct mlx5_flow_handle *tunnel_rules[MLX5E_NUM_TUNNEL_TT]; 113 }; 114 115 /* NIC prio FTS */ 116 enum { 117 MLX5E_VLAN_FT_LEVEL = 0, 118 MLX5E_L2_FT_LEVEL, 119 MLX5E_TTC_FT_LEVEL, 120 MLX5E_INNER_TTC_FT_LEVEL, 121 #ifdef CONFIG_MLX5_EN_ARFS 122 MLX5E_ARFS_FT_LEVEL 123 #endif 124 }; 125 126 #define MLX5E_TTC_NUM_GROUPS 3 127 #define MLX5E_TTC_GROUP1_SIZE (BIT(3) + MLX5E_NUM_TUNNEL_TT) 128 #define MLX5E_TTC_GROUP2_SIZE BIT(1) 129 #define MLX5E_TTC_GROUP3_SIZE BIT(0) 130 #define MLX5E_TTC_TABLE_SIZE (MLX5E_TTC_GROUP1_SIZE +\ 131 MLX5E_TTC_GROUP2_SIZE +\ 132 MLX5E_TTC_GROUP3_SIZE) 133 134 #define MLX5E_INNER_TTC_NUM_GROUPS 3 135 #define MLX5E_INNER_TTC_GROUP1_SIZE BIT(3) 136 #define MLX5E_INNER_TTC_GROUP2_SIZE BIT(1) 137 #define MLX5E_INNER_TTC_GROUP3_SIZE BIT(0) 138 #define MLX5E_INNER_TTC_TABLE_SIZE (MLX5E_INNER_TTC_GROUP1_SIZE +\ 139 MLX5E_INNER_TTC_GROUP2_SIZE +\ 140 MLX5E_INNER_TTC_GROUP3_SIZE) 141 142 #ifdef CONFIG_MLX5_EN_RXNFC 143 144 struct mlx5e_ethtool_table { 145 struct mlx5_flow_table *ft; 146 int num_rules; 147 }; 148 149 #define ETHTOOL_NUM_L3_L4_FTS 7 150 #define ETHTOOL_NUM_L2_FTS 4 151 152 struct mlx5e_ethtool_steering { 153 struct mlx5e_ethtool_table l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS]; 154 struct mlx5e_ethtool_table l2_ft[ETHTOOL_NUM_L2_FTS]; 155 struct list_head rules; 156 int tot_num_rules; 157 }; 158 159 void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv); 160 void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv); 161 int mlx5e_ethtool_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd); 162 int mlx5e_ethtool_get_rxnfc(struct net_device *dev, 163 struct ethtool_rxnfc *info, u32 *rule_locs); 164 #else 165 static inline void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv) { } 166 static inline void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv) { } 167 static inline int mlx5e_ethtool_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 168 { return -EOPNOTSUPP; } 169 static inline int mlx5e_ethtool_get_rxnfc(struct net_device *dev, 170 struct ethtool_rxnfc *info, u32 *rule_locs) 171 { return -EOPNOTSUPP; } 172 #endif /* CONFIG_MLX5_EN_RXNFC */ 173 174 #ifdef CONFIG_MLX5_EN_ARFS 175 #define ARFS_HASH_SHIFT BITS_PER_BYTE 176 #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE) 177 178 struct arfs_table { 179 struct mlx5e_flow_table ft; 180 struct mlx5_flow_handle *default_rule; 181 struct hlist_head rules_hash[ARFS_HASH_SIZE]; 182 }; 183 184 enum arfs_type { 185 ARFS_IPV4_TCP, 186 ARFS_IPV6_TCP, 187 ARFS_IPV4_UDP, 188 ARFS_IPV6_UDP, 189 ARFS_NUM_TYPES, 190 }; 191 192 struct mlx5e_arfs_tables { 193 struct arfs_table arfs_tables[ARFS_NUM_TYPES]; 194 /* Protect aRFS rules list */ 195 spinlock_t arfs_lock; 196 struct list_head rules; 197 int last_filter_id; 198 struct workqueue_struct *wq; 199 }; 200 201 int mlx5e_arfs_create_tables(struct mlx5e_priv *priv); 202 void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv); 203 int mlx5e_arfs_enable(struct mlx5e_priv *priv); 204 int mlx5e_arfs_disable(struct mlx5e_priv *priv); 205 int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 206 u16 rxq_index, u32 flow_id); 207 #else 208 static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv) { return 0; } 209 static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {} 210 static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv) { return -EOPNOTSUPP; } 211 static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv) { return -EOPNOTSUPP; } 212 #endif 213 214 struct mlx5e_flow_steering { 215 struct mlx5_flow_namespace *ns; 216 #ifdef CONFIG_MLX5_EN_RXNFC 217 struct mlx5e_ethtool_steering ethtool; 218 #endif 219 struct mlx5e_tc_table tc; 220 struct mlx5e_vlan_table vlan; 221 struct mlx5e_l2_table l2; 222 struct mlx5e_ttc_table ttc; 223 struct mlx5e_ttc_table inner_ttc; 224 #ifdef CONFIG_MLX5_EN_ARFS 225 struct mlx5e_arfs_tables arfs; 226 #endif 227 }; 228 229 struct ttc_params { 230 struct mlx5_flow_table_attr ft_attr; 231 u32 any_tt_tirn; 232 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS]; 233 struct mlx5e_ttc_table *inner_ttc; 234 }; 235 236 void mlx5e_set_ttc_basic_params(struct mlx5e_priv *priv, struct ttc_params *ttc_params); 237 void mlx5e_set_ttc_ft_params(struct ttc_params *ttc_params); 238 void mlx5e_set_inner_ttc_ft_params(struct ttc_params *ttc_params); 239 240 int mlx5e_create_ttc_table(struct mlx5e_priv *priv, struct ttc_params *params, 241 struct mlx5e_ttc_table *ttc); 242 void mlx5e_destroy_ttc_table(struct mlx5e_priv *priv, 243 struct mlx5e_ttc_table *ttc); 244 245 int mlx5e_create_inner_ttc_table(struct mlx5e_priv *priv, struct ttc_params *params, 246 struct mlx5e_ttc_table *ttc); 247 void mlx5e_destroy_inner_ttc_table(struct mlx5e_priv *priv, 248 struct mlx5e_ttc_table *ttc); 249 250 void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft); 251 252 void mlx5e_enable_cvlan_filter(struct mlx5e_priv *priv); 253 void mlx5e_disable_cvlan_filter(struct mlx5e_priv *priv); 254 255 int mlx5e_create_flow_steering(struct mlx5e_priv *priv); 256 void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv); 257 258 bool mlx5e_tunnel_proto_supported(struct mlx5_core_dev *mdev, u8 proto_type); 259 bool mlx5e_any_tunnel_proto_supported(struct mlx5_core_dev *mdev); 260 261 #endif /* __MLX5E_FLOW_STEER_H__ */ 262 263