1 /* 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef __MLX5_EN_H__ 33 #define __MLX5_EN_H__ 34 35 #include <linux/if_vlan.h> 36 #include <linux/etherdevice.h> 37 #include <linux/timecounter.h> 38 #include <linux/net_tstamp.h> 39 #include <linux/crash_dump.h> 40 #include <linux/mlx5/driver.h> 41 #include <linux/mlx5/qp.h> 42 #include <linux/mlx5/cq.h> 43 #include <linux/mlx5/port.h> 44 #include <linux/mlx5/vport.h> 45 #include <linux/mlx5/transobj.h> 46 #include <linux/mlx5/fs.h> 47 #include <linux/rhashtable.h> 48 #include <net/udp_tunnel.h> 49 #include <net/switchdev.h> 50 #include <net/xdp.h> 51 #include <linux/dim.h> 52 #include <linux/bits.h> 53 #include "wq.h" 54 #include "mlx5_core.h" 55 #include "en_stats.h" 56 #include "en/dcbnl.h" 57 #include "en/fs.h" 58 #include "en/qos.h" 59 #include "lib/hv_vhca.h" 60 #include "lib/clock.h" 61 #include "en/rx_res.h" 62 63 extern const struct net_device_ops mlx5e_netdev_ops; 64 struct page_pool; 65 66 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4) 67 #define MLX5E_METADATA_ETHER_LEN 8 68 69 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) 70 71 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu)) 72 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu)) 73 74 #define MLX5E_MAX_NUM_TC 8 75 #define MLX5E_MAX_NUM_MQPRIO_CH_TC TC_QOPT_MAX_QUEUE 76 77 #define MLX5_RX_HEADROOM NET_SKB_PAD 78 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \ 79 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 80 81 #define MLX5E_RX_MAX_HEAD (256) 82 #define MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE (9) 83 #define MLX5E_SHAMPO_WQ_HEADER_PER_PAGE (PAGE_SIZE >> MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE) 84 #define MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE (64) 85 #define MLX5E_SHAMPO_WQ_RESRV_SIZE (64 * 1024) 86 #define MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE (4096) 87 88 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \ 89 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */ 90 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \ 91 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req) 92 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \ 93 MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD)) 94 95 #define MLX5_MPWRQ_LOG_WQE_SZ 18 96 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \ 97 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0) 98 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER) 99 100 #define MLX5_ALIGN_MTTS(mtts) (ALIGN(mtts, 8)) 101 #define MLX5_ALIGNED_MTTS_OCTW(mtts) ((mtts) / 2) 102 #define MLX5_MTT_OCTW(mtts) (MLX5_ALIGNED_MTTS_OCTW(MLX5_ALIGN_MTTS(mtts))) 103 /* Add another page to MLX5E_REQUIRED_WQE_MTTS as a buffer between 104 * WQEs, This page will absorb write overflow by the hardware, when 105 * receiving packets larger than MTU. These oversize packets are 106 * dropped by the driver at a later stage. 107 */ 108 #define MLX5E_REQUIRED_WQE_MTTS (MLX5_ALIGN_MTTS(MLX5_MPWRQ_PAGES_PER_WQE + 1)) 109 #define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS) 110 #define MLX5E_MAX_RQ_NUM_MTTS \ 111 ((1 << 16) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */ 112 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024)) 113 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW \ 114 (ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS)) 115 #define MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW \ 116 (MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW + \ 117 (MLX5_MPWRQ_LOG_WQE_SZ - MLX5E_ORDER2_MAX_PACKET_MTU)) 118 119 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM)) 120 #define MLX5E_LOG_MAX_RX_WQE_BULK \ 121 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ))) 122 123 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 124 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa 125 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd 126 127 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK) 128 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa 129 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE min_t(u8, 0xd, \ 130 MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW) 131 132 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2 133 134 #define MLX5E_DEFAULT_LRO_TIMEOUT 32 135 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4 136 137 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 138 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 139 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 140 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 141 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10 142 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 143 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 144 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 145 146 #define MLX5E_MIN_NUM_CHANNELS 0x1 147 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE / 2) 148 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC) 149 #define MLX5E_TX_CQ_POLL_BUDGET 128 150 #define MLX5E_TX_XSK_POLL_BUDGET 64 151 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */ 152 153 #define MLX5E_UMR_WQE_INLINE_SZ \ 154 (sizeof(struct mlx5e_umr_wqe) + \ 155 ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(struct mlx5_mtt), \ 156 MLX5_UMR_MTT_ALIGNMENT)) 157 #define MLX5E_UMR_WQEBBS \ 158 (DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_BB)) 159 160 #define MLX5E_KLM_UMR_WQE_SZ(sgl_len)\ 161 (sizeof(struct mlx5e_umr_wqe) +\ 162 (sizeof(struct mlx5_klm) * (sgl_len))) 163 164 #define MLX5E_KLM_UMR_WQEBBS(klm_entries) \ 165 (DIV_ROUND_UP(MLX5E_KLM_UMR_WQE_SZ(klm_entries), MLX5_SEND_WQE_BB)) 166 167 #define MLX5E_KLM_UMR_DS_CNT(klm_entries)\ 168 (DIV_ROUND_UP(MLX5E_KLM_UMR_WQE_SZ(klm_entries), MLX5_SEND_WQE_DS)) 169 170 #define MLX5E_KLM_MAX_ENTRIES_PER_WQE(wqe_size)\ 171 (((wqe_size) - sizeof(struct mlx5e_umr_wqe)) / sizeof(struct mlx5_klm)) 172 173 #define MLX5E_KLM_ENTRIES_PER_WQE(wqe_size)\ 174 ALIGN_DOWN(MLX5E_KLM_MAX_ENTRIES_PER_WQE(wqe_size), MLX5_UMR_KLM_ALIGNMENT) 175 176 #define MLX5E_MAX_KLM_PER_WQE(mdev) \ 177 MLX5E_KLM_ENTRIES_PER_WQE(MLX5E_TX_MPW_MAX_NUM_DS << MLX5_MKEY_BSF_OCTO_SIZE) 178 179 #define MLX5E_MSG_LEVEL NETIF_MSG_LINK 180 181 #define mlx5e_dbg(mlevel, priv, format, ...) \ 182 do { \ 183 if (NETIF_MSG_##mlevel & (priv)->msglevel) \ 184 netdev_warn(priv->netdev, format, \ 185 ##__VA_ARGS__); \ 186 } while (0) 187 188 #define mlx5e_state_dereference(priv, p) \ 189 rcu_dereference_protected((p), lockdep_is_held(&(priv)->state_lock)) 190 191 enum mlx5e_rq_group { 192 MLX5E_RQ_GROUP_REGULAR, 193 MLX5E_RQ_GROUP_XSK, 194 #define MLX5E_NUM_RQ_GROUPS(g) (1 + MLX5E_RQ_GROUP_##g) 195 }; 196 197 static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev) 198 { 199 if (mlx5_lag_is_lacp_owner(mdev)) 200 return 1; 201 202 return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS); 203 } 204 205 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) 206 { 207 switch (wq_type) { 208 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 209 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, 210 wq_size / 2); 211 default: 212 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, 213 wq_size / 2); 214 } 215 } 216 217 /* Use this function to get max num channels (rxqs/txqs) only to create netdev */ 218 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) 219 { 220 return is_kdump_kernel() ? 221 MLX5E_MIN_NUM_CHANNELS : 222 min_t(int, mlx5_comp_vectors_count(mdev), MLX5E_MAX_NUM_CHANNELS); 223 } 224 225 struct mlx5e_tx_wqe { 226 struct mlx5_wqe_ctrl_seg ctrl; 227 struct mlx5_wqe_eth_seg eth; 228 struct mlx5_wqe_data_seg data[0]; 229 }; 230 231 struct mlx5e_rx_wqe_ll { 232 struct mlx5_wqe_srq_next_seg next; 233 struct mlx5_wqe_data_seg data[]; 234 }; 235 236 struct mlx5e_rx_wqe_cyc { 237 struct mlx5_wqe_data_seg data[0]; 238 }; 239 240 struct mlx5e_umr_wqe { 241 struct mlx5_wqe_ctrl_seg ctrl; 242 struct mlx5_wqe_umr_ctrl_seg uctrl; 243 struct mlx5_mkey_seg mkc; 244 union { 245 struct mlx5_mtt inline_mtts[0]; 246 struct mlx5_klm inline_klms[0]; 247 }; 248 }; 249 250 enum mlx5e_priv_flag { 251 MLX5E_PFLAG_RX_CQE_BASED_MODER, 252 MLX5E_PFLAG_TX_CQE_BASED_MODER, 253 MLX5E_PFLAG_RX_CQE_COMPRESS, 254 MLX5E_PFLAG_RX_STRIDING_RQ, 255 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, 256 MLX5E_PFLAG_XDP_TX_MPWQE, 257 MLX5E_PFLAG_SKB_TX_MPWQE, 258 MLX5E_PFLAG_TX_PORT_TS, 259 MLX5E_NUM_PFLAGS, /* Keep last */ 260 }; 261 262 #define MLX5E_SET_PFLAG(params, pflag, enable) \ 263 do { \ 264 if (enable) \ 265 (params)->pflags |= BIT(pflag); \ 266 else \ 267 (params)->pflags &= ~(BIT(pflag)); \ 268 } while (0) 269 270 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag)))) 271 272 enum packet_merge { 273 MLX5E_PACKET_MERGE_NONE, 274 MLX5E_PACKET_MERGE_LRO, 275 MLX5E_PACKET_MERGE_SHAMPO, 276 }; 277 278 struct mlx5e_packet_merge_param { 279 enum packet_merge type; 280 u32 timeout; 281 struct { 282 u8 match_criteria_type; 283 u8 alignment_granularity; 284 } shampo; 285 }; 286 287 struct mlx5e_params { 288 u8 log_sq_size; 289 u8 rq_wq_type; 290 u8 log_rq_mtu_frames; 291 u16 num_channels; 292 struct { 293 u16 mode; 294 u8 num_tc; 295 struct netdev_tc_txq tc_to_txq[TC_MAX_QUEUE]; 296 struct { 297 struct mlx5e_mqprio_rl *rl; 298 } channel; 299 } mqprio; 300 bool rx_cqe_compress_def; 301 bool tunneled_offload_en; 302 struct dim_cq_moder rx_cq_moderation; 303 struct dim_cq_moder tx_cq_moderation; 304 struct mlx5e_packet_merge_param packet_merge; 305 u8 tx_min_inline_mode; 306 bool vlan_strip_disable; 307 bool scatter_fcs_en; 308 bool rx_dim_enabled; 309 bool tx_dim_enabled; 310 u32 pflags; 311 struct bpf_prog *xdp_prog; 312 struct mlx5e_xsk *xsk; 313 unsigned int sw_mtu; 314 int hard_mtu; 315 bool ptp_rx; 316 }; 317 318 static inline u8 mlx5e_get_dcb_num_tc(struct mlx5e_params *params) 319 { 320 return params->mqprio.mode == TC_MQPRIO_MODE_DCB ? 321 params->mqprio.num_tc : 1; 322 } 323 324 enum { 325 MLX5E_RQ_STATE_ENABLED, 326 MLX5E_RQ_STATE_RECOVERING, 327 MLX5E_RQ_STATE_AM, 328 MLX5E_RQ_STATE_NO_CSUM_COMPLETE, 329 MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */ 330 MLX5E_RQ_STATE_FPGA_TLS, /* FPGA TLS enabled */ 331 MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, /* set when mini_cqe_resp_stride_index cap is used */ 332 MLX5E_RQ_STATE_SHAMPO, /* set when SHAMPO cap is used */ 333 }; 334 335 struct mlx5e_cq { 336 /* data path - accessed per cqe */ 337 struct mlx5_cqwq wq; 338 339 /* data path - accessed per napi poll */ 340 u16 event_ctr; 341 struct napi_struct *napi; 342 struct mlx5_core_cq mcq; 343 struct mlx5e_ch_stats *ch_stats; 344 345 /* control */ 346 struct net_device *netdev; 347 struct mlx5_core_dev *mdev; 348 struct mlx5e_priv *priv; 349 struct mlx5_wq_ctrl wq_ctrl; 350 } ____cacheline_aligned_in_smp; 351 352 struct mlx5e_cq_decomp { 353 /* cqe decompression */ 354 struct mlx5_cqe64 title; 355 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; 356 u8 mini_arr_idx; 357 u16 left; 358 u16 wqe_counter; 359 } ____cacheline_aligned_in_smp; 360 361 enum mlx5e_dma_map_type { 362 MLX5E_DMA_MAP_SINGLE, 363 MLX5E_DMA_MAP_PAGE 364 }; 365 366 struct mlx5e_sq_dma { 367 dma_addr_t addr; 368 u32 size; 369 enum mlx5e_dma_map_type type; 370 }; 371 372 enum { 373 MLX5E_SQ_STATE_ENABLED, 374 MLX5E_SQ_STATE_MPWQE, 375 MLX5E_SQ_STATE_RECOVERING, 376 MLX5E_SQ_STATE_IPSEC, 377 MLX5E_SQ_STATE_AM, 378 MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, 379 MLX5E_SQ_STATE_PENDING_XSK_TX, 380 MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC, 381 }; 382 383 struct mlx5e_tx_mpwqe { 384 /* Current MPWQE session */ 385 struct mlx5e_tx_wqe *wqe; 386 u32 bytes_count; 387 u8 ds_count; 388 u8 pkt_count; 389 u8 inline_on; 390 }; 391 392 struct mlx5e_skb_fifo { 393 struct sk_buff **fifo; 394 u16 *pc; 395 u16 *cc; 396 u16 mask; 397 }; 398 399 struct mlx5e_ptpsq; 400 401 struct mlx5e_txqsq { 402 /* data path */ 403 404 /* dirtied @completion */ 405 u16 cc; 406 u16 skb_fifo_cc; 407 u32 dma_fifo_cc; 408 struct dim dim; /* Adaptive Moderation */ 409 410 /* dirtied @xmit */ 411 u16 pc ____cacheline_aligned_in_smp; 412 u16 skb_fifo_pc; 413 u32 dma_fifo_pc; 414 struct mlx5e_tx_mpwqe mpwqe; 415 416 struct mlx5e_cq cq; 417 418 /* read only */ 419 struct mlx5_wq_cyc wq; 420 u32 dma_fifo_mask; 421 struct mlx5e_sq_stats *stats; 422 struct { 423 struct mlx5e_sq_dma *dma_fifo; 424 struct mlx5e_skb_fifo skb_fifo; 425 struct mlx5e_tx_wqe_info *wqe_info; 426 } db; 427 void __iomem *uar_map; 428 struct netdev_queue *txq; 429 u32 sqn; 430 u16 stop_room; 431 u8 min_inline_mode; 432 struct device *pdev; 433 __be32 mkey_be; 434 unsigned long state; 435 unsigned int hw_mtu; 436 struct hwtstamp_config *tstamp; 437 struct mlx5_clock *clock; 438 struct net_device *netdev; 439 struct mlx5_core_dev *mdev; 440 struct mlx5e_priv *priv; 441 442 /* control path */ 443 struct mlx5_wq_ctrl wq_ctrl; 444 int ch_ix; 445 int txq_ix; 446 u32 rate_limit; 447 struct work_struct recover_work; 448 struct mlx5e_ptpsq *ptpsq; 449 cqe_ts_to_ns ptp_cyc2time; 450 } ____cacheline_aligned_in_smp; 451 452 struct mlx5e_dma_info { 453 dma_addr_t addr; 454 union { 455 struct page *page; 456 struct xdp_buff *xsk; 457 }; 458 }; 459 460 /* XDP packets can be transmitted in different ways. On completion, we need to 461 * distinguish between them to clean up things in a proper way. 462 */ 463 enum mlx5e_xdp_xmit_mode { 464 /* An xdp_frame was transmitted due to either XDP_REDIRECT from another 465 * device or XDP_TX from an XSK RQ. The frame has to be unmapped and 466 * returned. 467 */ 468 MLX5E_XDP_XMIT_MODE_FRAME, 469 470 /* The xdp_frame was created in place as a result of XDP_TX from a 471 * regular RQ. No DMA remapping happened, and the page belongs to us. 472 */ 473 MLX5E_XDP_XMIT_MODE_PAGE, 474 475 /* No xdp_frame was created at all, the transmit happened from a UMEM 476 * page. The UMEM Completion Ring producer pointer has to be increased. 477 */ 478 MLX5E_XDP_XMIT_MODE_XSK, 479 }; 480 481 struct mlx5e_xdp_info { 482 enum mlx5e_xdp_xmit_mode mode; 483 union { 484 struct { 485 struct xdp_frame *xdpf; 486 dma_addr_t dma_addr; 487 } frame; 488 struct { 489 struct mlx5e_rq *rq; 490 struct mlx5e_dma_info di; 491 } page; 492 }; 493 }; 494 495 struct mlx5e_xmit_data { 496 dma_addr_t dma_addr; 497 void *data; 498 u32 len; 499 }; 500 501 struct mlx5e_xdp_info_fifo { 502 struct mlx5e_xdp_info *xi; 503 u32 *cc; 504 u32 *pc; 505 u32 mask; 506 }; 507 508 struct mlx5e_xdpsq; 509 typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *); 510 typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *, 511 struct mlx5e_xmit_data *, 512 struct mlx5e_xdp_info *, 513 int); 514 515 struct mlx5e_xdpsq { 516 /* data path */ 517 518 /* dirtied @completion */ 519 u32 xdpi_fifo_cc; 520 u16 cc; 521 522 /* dirtied @xmit */ 523 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp; 524 u16 pc; 525 struct mlx5_wqe_ctrl_seg *doorbell_cseg; 526 struct mlx5e_tx_mpwqe mpwqe; 527 528 struct mlx5e_cq cq; 529 530 /* read only */ 531 struct xsk_buff_pool *xsk_pool; 532 struct mlx5_wq_cyc wq; 533 struct mlx5e_xdpsq_stats *stats; 534 mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check; 535 mlx5e_fp_xmit_xdp_frame xmit_xdp_frame; 536 struct { 537 struct mlx5e_xdp_wqe_info *wqe_info; 538 struct mlx5e_xdp_info_fifo xdpi_fifo; 539 } db; 540 void __iomem *uar_map; 541 u32 sqn; 542 struct device *pdev; 543 __be32 mkey_be; 544 u8 min_inline_mode; 545 unsigned long state; 546 unsigned int hw_mtu; 547 548 /* control path */ 549 struct mlx5_wq_ctrl wq_ctrl; 550 struct mlx5e_channel *channel; 551 } ____cacheline_aligned_in_smp; 552 553 struct mlx5e_ktls_resync_resp; 554 555 struct mlx5e_icosq { 556 /* data path */ 557 u16 cc; 558 u16 pc; 559 560 struct mlx5_wqe_ctrl_seg *doorbell_cseg; 561 struct mlx5e_cq cq; 562 563 /* write@xmit, read@completion */ 564 struct { 565 struct mlx5e_icosq_wqe_info *wqe_info; 566 } db; 567 568 /* read only */ 569 struct mlx5_wq_cyc wq; 570 void __iomem *uar_map; 571 u32 sqn; 572 u16 reserved_room; 573 unsigned long state; 574 struct mlx5e_ktls_resync_resp *ktls_resync; 575 576 /* control path */ 577 struct mlx5_wq_ctrl wq_ctrl; 578 struct mlx5e_channel *channel; 579 580 struct work_struct recover_work; 581 } ____cacheline_aligned_in_smp; 582 583 struct mlx5e_wqe_frag_info { 584 struct mlx5e_dma_info *di; 585 u32 offset; 586 bool last_in_page; 587 }; 588 589 struct mlx5e_umr_dma_info { 590 struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE]; 591 }; 592 593 struct mlx5e_mpw_info { 594 struct mlx5e_umr_dma_info umr; 595 u16 consumed_strides; 596 DECLARE_BITMAP(xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE); 597 }; 598 599 #define MLX5E_MAX_RX_FRAGS 4 600 601 /* a single cache unit is capable to serve one napi call (for non-striding rq) 602 * or a MPWQE (for striding rq). 603 */ 604 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \ 605 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT) 606 #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT)) 607 struct mlx5e_page_cache { 608 u32 head; 609 u32 tail; 610 struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE]; 611 }; 612 613 struct mlx5e_rq; 614 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*); 615 typedef struct sk_buff * 616 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, 617 u16 cqe_bcnt, u32 head_offset, u32 page_idx); 618 typedef struct sk_buff * 619 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, 620 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt); 621 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq); 622 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16); 623 typedef void (*mlx5e_fp_shampo_dealloc_hd)(struct mlx5e_rq*, u16, u16, bool); 624 625 int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk); 626 void mlx5e_rq_set_trap_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params); 627 628 enum mlx5e_rq_flag { 629 MLX5E_RQ_FLAG_XDP_XMIT, 630 MLX5E_RQ_FLAG_XDP_REDIRECT, 631 }; 632 633 struct mlx5e_rq_frag_info { 634 int frag_size; 635 int frag_stride; 636 }; 637 638 struct mlx5e_rq_frags_info { 639 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS]; 640 u8 num_frags; 641 u8 log_num_frags; 642 u8 wqe_bulk; 643 }; 644 645 struct mlx5e_shampo_hd { 646 u32 mkey; 647 struct mlx5e_dma_info *info; 648 struct page *last_page; 649 u16 hd_per_wq; 650 u16 hd_per_wqe; 651 unsigned long *bitmap; 652 u16 pi; 653 u16 ci; 654 __be32 key; 655 u64 last_addr; 656 }; 657 658 struct mlx5e_hw_gro_data { 659 struct sk_buff *skb; 660 struct flow_keys fk; 661 int second_ip_id; 662 }; 663 664 struct mlx5e_rq { 665 /* data path */ 666 union { 667 struct { 668 struct mlx5_wq_cyc wq; 669 struct mlx5e_wqe_frag_info *frags; 670 struct mlx5e_dma_info *di; 671 struct mlx5e_rq_frags_info info; 672 mlx5e_fp_skb_from_cqe skb_from_cqe; 673 } wqe; 674 struct { 675 struct mlx5_wq_ll wq; 676 struct mlx5e_umr_wqe umr_wqe; 677 struct mlx5e_mpw_info *info; 678 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq; 679 u16 num_strides; 680 u16 actual_wq_head; 681 u8 log_stride_sz; 682 u8 umr_in_progress; 683 u8 umr_last_bulk; 684 u8 umr_completed; 685 struct mlx5e_shampo_hd *shampo; 686 } mpwqe; 687 }; 688 struct { 689 u16 headroom; 690 u32 frame0_sz; 691 u8 map_dir; /* dma map direction */ 692 } buff; 693 694 struct device *pdev; 695 struct net_device *netdev; 696 struct mlx5e_rq_stats *stats; 697 struct mlx5e_cq cq; 698 struct mlx5e_cq_decomp cqd; 699 struct mlx5e_page_cache page_cache; 700 struct hwtstamp_config *tstamp; 701 struct mlx5_clock *clock; 702 struct mlx5e_icosq *icosq; 703 struct mlx5e_priv *priv; 704 705 struct mlx5e_hw_gro_data *hw_gro_data; 706 707 mlx5e_fp_handle_rx_cqe handle_rx_cqe; 708 mlx5e_fp_post_rx_wqes post_wqes; 709 mlx5e_fp_dealloc_wqe dealloc_wqe; 710 711 unsigned long state; 712 int ix; 713 unsigned int hw_mtu; 714 715 struct dim dim; /* Dynamic Interrupt Moderation */ 716 717 /* XDP */ 718 struct bpf_prog __rcu *xdp_prog; 719 struct mlx5e_xdpsq *xdpsq; 720 DECLARE_BITMAP(flags, 8); 721 struct page_pool *page_pool; 722 723 /* AF_XDP zero-copy */ 724 struct xsk_buff_pool *xsk_pool; 725 726 struct work_struct recover_work; 727 728 /* control */ 729 struct mlx5_wq_ctrl wq_ctrl; 730 __be32 mkey_be; 731 u8 wq_type; 732 u32 rqn; 733 struct mlx5_core_dev *mdev; 734 u32 umr_mkey; 735 struct mlx5e_dma_info wqe_overflow; 736 737 /* XDP read-mostly */ 738 struct xdp_rxq_info xdp_rxq; 739 cqe_ts_to_ns ptp_cyc2time; 740 } ____cacheline_aligned_in_smp; 741 742 enum mlx5e_channel_state { 743 MLX5E_CHANNEL_STATE_XSK, 744 MLX5E_CHANNEL_NUM_STATES 745 }; 746 747 struct mlx5e_channel { 748 /* data path */ 749 struct mlx5e_rq rq; 750 struct mlx5e_xdpsq rq_xdpsq; 751 struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC]; 752 struct mlx5e_icosq icosq; /* internal control operations */ 753 struct mlx5e_txqsq __rcu * __rcu *qos_sqs; 754 bool xdp; 755 struct napi_struct napi; 756 struct device *pdev; 757 struct net_device *netdev; 758 __be32 mkey_be; 759 u16 qos_sqs_size; 760 u8 num_tc; 761 u8 lag_port; 762 763 /* XDP_REDIRECT */ 764 struct mlx5e_xdpsq xdpsq; 765 766 /* AF_XDP zero-copy */ 767 struct mlx5e_rq xskrq; 768 struct mlx5e_xdpsq xsksq; 769 770 /* Async ICOSQ */ 771 struct mlx5e_icosq async_icosq; 772 /* async_icosq can be accessed from any CPU - the spinlock protects it. */ 773 spinlock_t async_icosq_lock; 774 775 /* data path - accessed per napi poll */ 776 const struct cpumask *aff_mask; 777 struct mlx5e_ch_stats *stats; 778 779 /* control */ 780 struct mlx5e_priv *priv; 781 struct mlx5_core_dev *mdev; 782 struct hwtstamp_config *tstamp; 783 DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES); 784 int ix; 785 int cpu; 786 }; 787 788 struct mlx5e_ptp; 789 790 struct mlx5e_channels { 791 struct mlx5e_channel **c; 792 struct mlx5e_ptp *ptp; 793 unsigned int num; 794 struct mlx5e_params params; 795 }; 796 797 struct mlx5e_channel_stats { 798 struct mlx5e_ch_stats ch; 799 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC]; 800 struct mlx5e_rq_stats rq; 801 struct mlx5e_rq_stats xskrq; 802 struct mlx5e_xdpsq_stats rq_xdpsq; 803 struct mlx5e_xdpsq_stats xdpsq; 804 struct mlx5e_xdpsq_stats xsksq; 805 } ____cacheline_aligned_in_smp; 806 807 struct mlx5e_ptp_stats { 808 struct mlx5e_ch_stats ch; 809 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC]; 810 struct mlx5e_ptp_cq_stats cq[MLX5E_MAX_NUM_TC]; 811 struct mlx5e_rq_stats rq; 812 } ____cacheline_aligned_in_smp; 813 814 enum { 815 MLX5E_STATE_OPENED, 816 MLX5E_STATE_DESTROYING, 817 MLX5E_STATE_XDP_TX_ENABLED, 818 MLX5E_STATE_XDP_ACTIVE, 819 }; 820 821 enum { 822 MLX5E_TC_PRIO = 0, 823 MLX5E_NIC_PRIO 824 }; 825 826 struct mlx5e_modify_sq_param { 827 int curr_state; 828 int next_state; 829 int rl_update; 830 int rl_index; 831 bool qos_update; 832 u16 qos_queue_group_id; 833 }; 834 835 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE) 836 struct mlx5e_hv_vhca_stats_agent { 837 struct mlx5_hv_vhca_agent *agent; 838 struct delayed_work work; 839 u16 delay; 840 void *buf; 841 }; 842 #endif 843 844 struct mlx5e_xsk { 845 /* XSK buffer pools are stored separately from channels, 846 * because we don't want to lose them when channels are 847 * recreated. The kernel also stores buffer pool, but it doesn't 848 * distinguish between zero-copy and non-zero-copy UMEMs, so 849 * rely on our mechanism. 850 */ 851 struct xsk_buff_pool **pools; 852 u16 refcnt; 853 bool ever_used; 854 }; 855 856 /* Temporary storage for variables that are allocated when struct mlx5e_priv is 857 * initialized, and used where we can't allocate them because that functions 858 * must not fail. Use with care and make sure the same variable is not used 859 * simultaneously by multiple users. 860 */ 861 struct mlx5e_scratchpad { 862 cpumask_var_t cpumask; 863 }; 864 865 struct mlx5e_htb { 866 DECLARE_HASHTABLE(qos_tc2node, order_base_2(MLX5E_QOS_MAX_LEAF_NODES)); 867 DECLARE_BITMAP(qos_used_qids, MLX5E_QOS_MAX_LEAF_NODES); 868 struct mlx5e_sq_stats **qos_sq_stats; 869 u16 max_qos_sqs; 870 u16 maj_id; 871 u16 defcls; 872 }; 873 874 struct mlx5e_trap; 875 876 struct mlx5e_priv { 877 /* priv data path fields - start */ 878 /* +1 for port ptp ts */ 879 struct mlx5e_txqsq *txq2sq[(MLX5E_MAX_NUM_CHANNELS + 1) * MLX5E_MAX_NUM_TC + 880 MLX5E_QOS_MAX_LEAF_NODES]; 881 int channel_tc2realtxq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC]; 882 int port_ptp_tc2realtxq[MLX5E_MAX_NUM_TC]; 883 #ifdef CONFIG_MLX5_CORE_EN_DCB 884 struct mlx5e_dcbx_dp dcbx_dp; 885 #endif 886 /* priv data path fields - end */ 887 888 u32 msglevel; 889 unsigned long state; 890 struct mutex state_lock; /* Protects Interface state */ 891 struct mlx5e_rq drop_rq; 892 893 struct mlx5e_channels channels; 894 u32 tisn[MLX5_MAX_PORTS][MLX5E_MAX_NUM_TC]; 895 struct mlx5e_rx_res *rx_res; 896 u32 tx_rates[MLX5E_MAX_NUM_SQS]; 897 898 struct mlx5e_flow_steering fs; 899 900 struct workqueue_struct *wq; 901 struct work_struct update_carrier_work; 902 struct work_struct set_rx_mode_work; 903 struct work_struct tx_timeout_work; 904 struct work_struct update_stats_work; 905 struct work_struct monitor_counters_work; 906 struct mlx5_nb monitor_counters_nb; 907 908 struct mlx5_core_dev *mdev; 909 struct net_device *netdev; 910 struct mlx5e_trap *en_trap; 911 struct mlx5e_stats stats; 912 struct mlx5e_channel_stats channel_stats[MLX5E_MAX_NUM_CHANNELS]; 913 struct mlx5e_channel_stats trap_stats; 914 struct mlx5e_ptp_stats ptp_stats; 915 u16 stats_nch; 916 u16 max_nch; 917 u8 max_opened_tc; 918 bool tx_ptp_opened; 919 bool rx_ptp_opened; 920 struct hwtstamp_config tstamp; 921 u16 q_counter; 922 u16 drop_rq_q_counter; 923 struct notifier_block events_nb; 924 struct notifier_block blocking_events_nb; 925 int num_tc_x_num_ch; 926 927 struct udp_tunnel_nic_info nic_info; 928 #ifdef CONFIG_MLX5_CORE_EN_DCB 929 struct mlx5e_dcbx dcbx; 930 #endif 931 932 const struct mlx5e_profile *profile; 933 void *ppriv; 934 #ifdef CONFIG_MLX5_EN_IPSEC 935 struct mlx5e_ipsec *ipsec; 936 #endif 937 #ifdef CONFIG_MLX5_EN_TLS 938 struct mlx5e_tls *tls; 939 #endif 940 struct devlink_health_reporter *tx_reporter; 941 struct devlink_health_reporter *rx_reporter; 942 struct mlx5e_xsk xsk; 943 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE) 944 struct mlx5e_hv_vhca_stats_agent stats_agent; 945 #endif 946 struct mlx5e_scratchpad scratchpad; 947 struct mlx5e_htb htb; 948 struct mlx5e_mqprio_rl *mqprio_rl; 949 }; 950 951 struct mlx5e_rx_handlers { 952 mlx5e_fp_handle_rx_cqe handle_rx_cqe; 953 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe; 954 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe_shampo; 955 }; 956 957 extern const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic; 958 959 struct mlx5e_profile { 960 int (*init)(struct mlx5_core_dev *mdev, 961 struct net_device *netdev); 962 void (*cleanup)(struct mlx5e_priv *priv); 963 int (*init_rx)(struct mlx5e_priv *priv); 964 void (*cleanup_rx)(struct mlx5e_priv *priv); 965 int (*init_tx)(struct mlx5e_priv *priv); 966 void (*cleanup_tx)(struct mlx5e_priv *priv); 967 void (*enable)(struct mlx5e_priv *priv); 968 void (*disable)(struct mlx5e_priv *priv); 969 int (*update_rx)(struct mlx5e_priv *priv); 970 void (*update_stats)(struct mlx5e_priv *priv); 971 void (*update_carrier)(struct mlx5e_priv *priv); 972 unsigned int (*stats_grps_num)(struct mlx5e_priv *priv); 973 mlx5e_stats_grp_t *stats_grps; 974 const struct mlx5e_rx_handlers *rx_handlers; 975 int max_tc; 976 u8 rq_groups; 977 bool rx_ptp_support; 978 }; 979 980 void mlx5e_build_ptys2ethtool_map(void); 981 982 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev); 983 984 void mlx5e_shampo_dealloc_hd(struct mlx5e_rq *rq, u16 len, u16 start, bool close); 985 void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats); 986 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s); 987 988 void mlx5e_init_l2_addr(struct mlx5e_priv *priv); 989 int mlx5e_self_test_num(struct mlx5e_priv *priv); 990 int mlx5e_self_test_fill_strings(struct mlx5e_priv *priv, u8 *data); 991 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest, 992 u64 *buf); 993 void mlx5e_set_rx_mode_work(struct work_struct *work); 994 995 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr); 996 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr); 997 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val, bool rx_filter); 998 999 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, 1000 u16 vid); 1001 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, 1002 u16 vid); 1003 void mlx5e_timestamp_init(struct mlx5e_priv *priv); 1004 1005 struct mlx5e_xsk_param; 1006 1007 struct mlx5e_rq_param; 1008 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param, 1009 struct mlx5e_xsk_param *xsk, int node, 1010 struct mlx5e_rq *rq); 1011 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time); 1012 void mlx5e_close_rq(struct mlx5e_rq *rq); 1013 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param); 1014 void mlx5e_destroy_rq(struct mlx5e_rq *rq); 1015 1016 struct mlx5e_sq_param; 1017 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params, 1018 struct mlx5e_sq_param *param, struct mlx5e_icosq *sq); 1019 void mlx5e_close_icosq(struct mlx5e_icosq *sq); 1020 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params, 1021 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool, 1022 struct mlx5e_xdpsq *sq, bool is_redirect); 1023 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq); 1024 1025 struct mlx5e_create_cq_param { 1026 struct napi_struct *napi; 1027 struct mlx5e_ch_stats *ch_stats; 1028 int node; 1029 int ix; 1030 }; 1031 1032 struct mlx5e_cq_param; 1033 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder, 1034 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp, 1035 struct mlx5e_cq *cq); 1036 void mlx5e_close_cq(struct mlx5e_cq *cq); 1037 1038 int mlx5e_open_locked(struct net_device *netdev); 1039 int mlx5e_close_locked(struct net_device *netdev); 1040 1041 int mlx5e_open_channels(struct mlx5e_priv *priv, 1042 struct mlx5e_channels *chs); 1043 void mlx5e_close_channels(struct mlx5e_channels *chs); 1044 1045 /* Function pointer to be used to modify HW or kernel settings while 1046 * switching channels 1047 */ 1048 typedef int (*mlx5e_fp_preactivate)(struct mlx5e_priv *priv, void *context); 1049 #define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \ 1050 int fn##_ctx(struct mlx5e_priv *priv, void *context) \ 1051 { \ 1052 return fn(priv); \ 1053 } 1054 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv); 1055 int mlx5e_safe_switch_params(struct mlx5e_priv *priv, 1056 struct mlx5e_params *new_params, 1057 mlx5e_fp_preactivate preactivate, 1058 void *context, bool reset); 1059 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv); 1060 int mlx5e_num_channels_changed(struct mlx5e_priv *priv); 1061 int mlx5e_num_channels_changed_ctx(struct mlx5e_priv *priv, void *context); 1062 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv); 1063 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv); 1064 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx); 1065 1066 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state); 1067 void mlx5e_activate_rq(struct mlx5e_rq *rq); 1068 void mlx5e_deactivate_rq(struct mlx5e_rq *rq); 1069 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq); 1070 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq); 1071 1072 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn, 1073 struct mlx5e_modify_sq_param *p); 1074 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix, 1075 struct mlx5e_params *params, struct mlx5e_sq_param *param, 1076 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id, 1077 struct mlx5e_sq_stats *sq_stats); 1078 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq); 1079 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq); 1080 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq); 1081 void mlx5e_tx_disable_queue(struct netdev_queue *txq); 1082 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa); 1083 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq); 1084 struct mlx5e_create_sq_param; 1085 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev, 1086 struct mlx5e_sq_param *param, 1087 struct mlx5e_create_sq_param *csp, 1088 u16 qos_queue_group_id, 1089 u32 *sqn); 1090 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work); 1091 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq); 1092 1093 static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev) 1094 { 1095 return MLX5_CAP_ETH(mdev, swp) && 1096 MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso); 1097 } 1098 1099 extern const struct ethtool_ops mlx5e_ethtool_ops; 1100 1101 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev); 1102 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); 1103 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb, 1104 bool enable_mc_lb); 1105 void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc); 1106 1107 /* common netdev helpers */ 1108 void mlx5e_create_q_counters(struct mlx5e_priv *priv); 1109 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv); 1110 int mlx5e_open_drop_rq(struct mlx5e_priv *priv, 1111 struct mlx5e_rq *drop_rq); 1112 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq); 1113 int mlx5e_init_di_list(struct mlx5e_rq *rq, int wq_sz, int node); 1114 void mlx5e_free_di_list(struct mlx5e_rq *rq); 1115 1116 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn); 1117 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn); 1118 1119 int mlx5e_create_tises(struct mlx5e_priv *priv); 1120 void mlx5e_destroy_tises(struct mlx5e_priv *priv); 1121 int mlx5e_update_nic_rx(struct mlx5e_priv *priv); 1122 void mlx5e_update_carrier(struct mlx5e_priv *priv); 1123 int mlx5e_close(struct net_device *netdev); 1124 int mlx5e_open(struct net_device *netdev); 1125 1126 void mlx5e_queue_update_stats(struct mlx5e_priv *priv); 1127 1128 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv); 1129 int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv *priv, void *context); 1130 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu, 1131 mlx5e_fp_preactivate preactivate); 1132 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv); 1133 1134 /* ethtool helpers */ 1135 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv, 1136 struct ethtool_drvinfo *drvinfo); 1137 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, 1138 uint32_t stringset, uint8_t *data); 1139 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset); 1140 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv, 1141 struct ethtool_stats *stats, u64 *data); 1142 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv, 1143 struct ethtool_ringparam *param); 1144 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, 1145 struct ethtool_ringparam *param); 1146 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv, 1147 struct ethtool_channels *ch); 1148 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, 1149 struct ethtool_channels *ch); 1150 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv, 1151 struct ethtool_coalesce *coal); 1152 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, 1153 struct ethtool_coalesce *coal); 1154 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv, 1155 struct ethtool_link_ksettings *link_ksettings); 1156 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv, 1157 const struct ethtool_link_ksettings *link_ksettings); 1158 int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, u8 *hfunc); 1159 int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key, 1160 const u8 hfunc); 1161 int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, 1162 u32 *rule_locs); 1163 int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd); 1164 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv); 1165 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv); 1166 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv, 1167 struct ethtool_ts_info *info); 1168 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv, 1169 struct ethtool_flash *flash); 1170 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv, 1171 struct ethtool_pauseparam *pauseparam); 1172 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv, 1173 struct ethtool_pauseparam *pauseparam); 1174 1175 /* mlx5e generic netdev management API */ 1176 static inline bool 1177 mlx5e_tx_mpwqe_supported(struct mlx5_core_dev *mdev) 1178 { 1179 return !is_kdump_kernel() && 1180 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe); 1181 } 1182 1183 int mlx5e_priv_init(struct mlx5e_priv *priv, 1184 const struct mlx5e_profile *profile, 1185 struct net_device *netdev, 1186 struct mlx5_core_dev *mdev); 1187 void mlx5e_priv_cleanup(struct mlx5e_priv *priv); 1188 struct net_device * 1189 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile, 1190 unsigned int txqs, unsigned int rxqs); 1191 int mlx5e_attach_netdev(struct mlx5e_priv *priv); 1192 void mlx5e_detach_netdev(struct mlx5e_priv *priv); 1193 void mlx5e_destroy_netdev(struct mlx5e_priv *priv); 1194 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv, 1195 const struct mlx5e_profile *new_profile, void *new_ppriv); 1196 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv); 1197 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv); 1198 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu); 1199 void mlx5e_rx_dim_work(struct work_struct *work); 1200 void mlx5e_tx_dim_work(struct work_struct *work); 1201 1202 netdev_features_t mlx5e_features_check(struct sk_buff *skb, 1203 struct net_device *netdev, 1204 netdev_features_t features); 1205 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features); 1206 #ifdef CONFIG_MLX5_ESWITCH 1207 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac); 1208 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate); 1209 int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi); 1210 int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats); 1211 #endif 1212 #endif /* __MLX5_EN_H__ */ 1213