1 /* 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef __MLX5_EN_H__ 33 #define __MLX5_EN_H__ 34 35 #include <linux/if_vlan.h> 36 #include <linux/etherdevice.h> 37 #include <linux/timecounter.h> 38 #include <linux/net_tstamp.h> 39 #include <linux/crash_dump.h> 40 #include <linux/mlx5/driver.h> 41 #include <linux/mlx5/qp.h> 42 #include <linux/mlx5/cq.h> 43 #include <linux/mlx5/port.h> 44 #include <linux/mlx5/vport.h> 45 #include <linux/mlx5/transobj.h> 46 #include <linux/mlx5/fs.h> 47 #include <linux/rhashtable.h> 48 #include <net/udp_tunnel.h> 49 #include <net/switchdev.h> 50 #include <net/xdp.h> 51 #include <linux/dim.h> 52 #include <linux/bits.h> 53 #include "wq.h" 54 #include "mlx5_core.h" 55 #include "en_stats.h" 56 #include "en/dcbnl.h" 57 #include "en/fs.h" 58 #include "en/qos.h" 59 #include "lib/hv_vhca.h" 60 #include "lib/clock.h" 61 #include "en/rx_res.h" 62 #include "en/selq.h" 63 64 extern const struct net_device_ops mlx5e_netdev_ops; 65 struct page_pool; 66 67 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4) 68 #define MLX5E_METADATA_ETHER_LEN 8 69 70 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) 71 72 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu)) 73 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu)) 74 75 #define MLX5E_MAX_NUM_TC 8 76 #define MLX5E_MAX_NUM_MQPRIO_CH_TC TC_QOPT_MAX_QUEUE 77 78 #define MLX5_RX_HEADROOM NET_SKB_PAD 79 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \ 80 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 81 82 #define MLX5E_RX_MAX_HEAD (256) 83 #define MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE (9) 84 #define MLX5E_SHAMPO_WQ_HEADER_PER_PAGE (PAGE_SIZE >> MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE) 85 #define MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE (64) 86 #define MLX5E_SHAMPO_WQ_RESRV_SIZE (64 * 1024) 87 #define MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE (4096) 88 89 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \ 90 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */ 91 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \ 92 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req) 93 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \ 94 MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD)) 95 96 #define MLX5_MPWRQ_LOG_WQE_SZ 18 97 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \ 98 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0) 99 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER) 100 101 #define MLX5_ALIGN_MTTS(mtts) (ALIGN(mtts, 8)) 102 #define MLX5_ALIGNED_MTTS_OCTW(mtts) ((mtts) / 2) 103 #define MLX5_MTT_OCTW(mtts) (MLX5_ALIGNED_MTTS_OCTW(MLX5_ALIGN_MTTS(mtts))) 104 /* Add another page to MLX5E_REQUIRED_WQE_MTTS as a buffer between 105 * WQEs, This page will absorb write overflow by the hardware, when 106 * receiving packets larger than MTU. These oversize packets are 107 * dropped by the driver at a later stage. 108 */ 109 #define MLX5E_REQUIRED_WQE_MTTS (MLX5_ALIGN_MTTS(MLX5_MPWRQ_PAGES_PER_WQE + 1)) 110 #define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS) 111 #define MLX5E_MAX_RQ_NUM_MTTS \ 112 ((1 << 16) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */ 113 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024)) 114 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW \ 115 (ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS)) 116 #define MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW \ 117 (MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW + \ 118 (MLX5_MPWRQ_LOG_WQE_SZ - MLX5E_ORDER2_MAX_PACKET_MTU)) 119 120 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM)) 121 #define MLX5E_LOG_MAX_RX_WQE_BULK \ 122 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ))) 123 124 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 125 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa 126 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd 127 128 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK) 129 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa 130 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE min_t(u8, 0xd, \ 131 MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW) 132 133 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2 134 135 #define MLX5E_DEFAULT_LRO_TIMEOUT 32 136 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4 137 138 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 139 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 140 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 141 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 142 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10 143 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 144 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 145 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 146 147 #define MLX5E_MIN_NUM_CHANNELS 0x1 148 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE / 2) 149 #define MLX5E_TX_CQ_POLL_BUDGET 128 150 #define MLX5E_TX_XSK_POLL_BUDGET 64 151 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */ 152 153 #define MLX5E_UMR_WQE_INLINE_SZ \ 154 (sizeof(struct mlx5e_umr_wqe) + \ 155 ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(struct mlx5_mtt), \ 156 MLX5_UMR_MTT_ALIGNMENT)) 157 #define MLX5E_UMR_WQEBBS \ 158 (DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_BB)) 159 160 #define MLX5E_KLM_UMR_WQE_SZ(sgl_len)\ 161 (sizeof(struct mlx5e_umr_wqe) +\ 162 (sizeof(struct mlx5_klm) * (sgl_len))) 163 164 #define MLX5E_KLM_UMR_WQEBBS(klm_entries) \ 165 (DIV_ROUND_UP(MLX5E_KLM_UMR_WQE_SZ(klm_entries), MLX5_SEND_WQE_BB)) 166 167 #define MLX5E_KLM_UMR_DS_CNT(klm_entries)\ 168 (DIV_ROUND_UP(MLX5E_KLM_UMR_WQE_SZ(klm_entries), MLX5_SEND_WQE_DS)) 169 170 #define MLX5E_KLM_MAX_ENTRIES_PER_WQE(wqe_size)\ 171 (((wqe_size) - sizeof(struct mlx5e_umr_wqe)) / sizeof(struct mlx5_klm)) 172 173 #define MLX5E_KLM_ENTRIES_PER_WQE(wqe_size)\ 174 ALIGN_DOWN(MLX5E_KLM_MAX_ENTRIES_PER_WQE(wqe_size), MLX5_UMR_KLM_ALIGNMENT) 175 176 #define MLX5E_MAX_KLM_PER_WQE(mdev) \ 177 MLX5E_KLM_ENTRIES_PER_WQE(mlx5e_get_sw_max_sq_mpw_wqebbs(mlx5e_get_max_sq_wqebbs(mdev)) \ 178 << MLX5_MKEY_BSF_OCTO_SIZE) 179 180 #define MLX5E_MSG_LEVEL NETIF_MSG_LINK 181 182 #define mlx5e_dbg(mlevel, priv, format, ...) \ 183 do { \ 184 if (NETIF_MSG_##mlevel & (priv)->msglevel) \ 185 netdev_warn(priv->netdev, format, \ 186 ##__VA_ARGS__); \ 187 } while (0) 188 189 #define mlx5e_state_dereference(priv, p) \ 190 rcu_dereference_protected((p), lockdep_is_held(&(priv)->state_lock)) 191 192 enum mlx5e_rq_group { 193 MLX5E_RQ_GROUP_REGULAR, 194 MLX5E_RQ_GROUP_XSK, 195 #define MLX5E_NUM_RQ_GROUPS(g) (1 + MLX5E_RQ_GROUP_##g) 196 }; 197 198 static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev) 199 { 200 if (mlx5_lag_is_lacp_owner(mdev)) 201 return 1; 202 203 return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS); 204 } 205 206 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) 207 { 208 switch (wq_type) { 209 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 210 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, 211 wq_size / 2); 212 default: 213 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, 214 wq_size / 2); 215 } 216 } 217 218 /* Use this function to get max num channels (rxqs/txqs) only to create netdev */ 219 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) 220 { 221 return is_kdump_kernel() ? 222 MLX5E_MIN_NUM_CHANNELS : 223 min_t(int, mlx5_comp_vectors_count(mdev), MLX5E_MAX_NUM_CHANNELS); 224 } 225 226 /* The maximum WQE size can be retrieved by max_wqe_sz_sq in 227 * bytes units. Driver hardens the limitation to 1KB (16 228 * WQEBBs), unless firmware capability is stricter. 229 */ 230 static inline u16 mlx5e_get_max_sq_wqebbs(struct mlx5_core_dev *mdev) 231 { 232 return min_t(u16, MLX5_SEND_WQE_MAX_WQEBBS, 233 MLX5_CAP_GEN(mdev, max_wqe_sz_sq) / MLX5_SEND_WQE_BB); 234 } 235 236 static inline u16 mlx5e_get_sw_max_sq_mpw_wqebbs(u16 max_sq_wqebbs) 237 { 238 /* The return value will be multiplied by MLX5_SEND_WQEBB_NUM_DS. 239 * Since max_sq_wqebbs may be up to MLX5_SEND_WQE_MAX_WQEBBS == 16, 240 * see mlx5e_get_max_sq_wqebbs(), the multiplication (16 * 4 == 64) 241 * overflows the 6-bit DS field of Ctrl Segment. Use a bound lower 242 * than MLX5_SEND_WQE_MAX_WQEBBS to let a full-session WQE be 243 * cache-aligned. 244 */ 245 #if L1_CACHE_BYTES < 128 246 return min_t(u16, max_sq_wqebbs, MLX5_SEND_WQE_MAX_WQEBBS - 1); 247 #else 248 return min_t(u16, max_sq_wqebbs, MLX5_SEND_WQE_MAX_WQEBBS - 2); 249 #endif 250 } 251 252 struct mlx5e_tx_wqe { 253 struct mlx5_wqe_ctrl_seg ctrl; 254 struct mlx5_wqe_eth_seg eth; 255 struct mlx5_wqe_data_seg data[]; 256 }; 257 258 struct mlx5e_rx_wqe_ll { 259 struct mlx5_wqe_srq_next_seg next; 260 struct mlx5_wqe_data_seg data[]; 261 }; 262 263 struct mlx5e_rx_wqe_cyc { 264 struct mlx5_wqe_data_seg data[0]; 265 }; 266 267 struct mlx5e_umr_wqe { 268 struct mlx5_wqe_ctrl_seg ctrl; 269 struct mlx5_wqe_umr_ctrl_seg uctrl; 270 struct mlx5_mkey_seg mkc; 271 union { 272 DECLARE_FLEX_ARRAY(struct mlx5_mtt, inline_mtts); 273 DECLARE_FLEX_ARRAY(struct mlx5_klm, inline_klms); 274 }; 275 }; 276 277 enum mlx5e_priv_flag { 278 MLX5E_PFLAG_RX_CQE_BASED_MODER, 279 MLX5E_PFLAG_TX_CQE_BASED_MODER, 280 MLX5E_PFLAG_RX_CQE_COMPRESS, 281 MLX5E_PFLAG_RX_STRIDING_RQ, 282 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, 283 MLX5E_PFLAG_XDP_TX_MPWQE, 284 MLX5E_PFLAG_SKB_TX_MPWQE, 285 MLX5E_PFLAG_TX_PORT_TS, 286 MLX5E_NUM_PFLAGS, /* Keep last */ 287 }; 288 289 #define MLX5E_SET_PFLAG(params, pflag, enable) \ 290 do { \ 291 if (enable) \ 292 (params)->pflags |= BIT(pflag); \ 293 else \ 294 (params)->pflags &= ~(BIT(pflag)); \ 295 } while (0) 296 297 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag)))) 298 299 enum packet_merge { 300 MLX5E_PACKET_MERGE_NONE, 301 MLX5E_PACKET_MERGE_LRO, 302 MLX5E_PACKET_MERGE_SHAMPO, 303 }; 304 305 struct mlx5e_packet_merge_param { 306 enum packet_merge type; 307 u32 timeout; 308 struct { 309 u8 match_criteria_type; 310 u8 alignment_granularity; 311 } shampo; 312 }; 313 314 struct mlx5e_params { 315 u8 log_sq_size; 316 u8 rq_wq_type; 317 u8 log_rq_mtu_frames; 318 u16 num_channels; 319 struct { 320 u16 mode; 321 u8 num_tc; 322 struct netdev_tc_txq tc_to_txq[TC_MAX_QUEUE]; 323 struct { 324 struct mlx5e_mqprio_rl *rl; 325 } channel; 326 } mqprio; 327 bool rx_cqe_compress_def; 328 bool tunneled_offload_en; 329 struct dim_cq_moder rx_cq_moderation; 330 struct dim_cq_moder tx_cq_moderation; 331 struct mlx5e_packet_merge_param packet_merge; 332 u8 tx_min_inline_mode; 333 bool vlan_strip_disable; 334 bool scatter_fcs_en; 335 bool rx_dim_enabled; 336 bool tx_dim_enabled; 337 u32 pflags; 338 struct bpf_prog *xdp_prog; 339 struct mlx5e_xsk *xsk; 340 unsigned int sw_mtu; 341 int hard_mtu; 342 bool ptp_rx; 343 }; 344 345 static inline u8 mlx5e_get_dcb_num_tc(struct mlx5e_params *params) 346 { 347 return params->mqprio.mode == TC_MQPRIO_MODE_DCB ? 348 params->mqprio.num_tc : 1; 349 } 350 351 enum { 352 MLX5E_RQ_STATE_ENABLED, 353 MLX5E_RQ_STATE_RECOVERING, 354 MLX5E_RQ_STATE_AM, 355 MLX5E_RQ_STATE_NO_CSUM_COMPLETE, 356 MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */ 357 MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, /* set when mini_cqe_resp_stride_index cap is used */ 358 MLX5E_RQ_STATE_SHAMPO, /* set when SHAMPO cap is used */ 359 }; 360 361 struct mlx5e_cq { 362 /* data path - accessed per cqe */ 363 struct mlx5_cqwq wq; 364 365 /* data path - accessed per napi poll */ 366 u16 event_ctr; 367 struct napi_struct *napi; 368 struct mlx5_core_cq mcq; 369 struct mlx5e_ch_stats *ch_stats; 370 371 /* control */ 372 struct net_device *netdev; 373 struct mlx5_core_dev *mdev; 374 struct mlx5e_priv *priv; 375 struct mlx5_wq_ctrl wq_ctrl; 376 } ____cacheline_aligned_in_smp; 377 378 struct mlx5e_cq_decomp { 379 /* cqe decompression */ 380 struct mlx5_cqe64 title; 381 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; 382 u8 mini_arr_idx; 383 u16 left; 384 u16 wqe_counter; 385 } ____cacheline_aligned_in_smp; 386 387 enum mlx5e_dma_map_type { 388 MLX5E_DMA_MAP_SINGLE, 389 MLX5E_DMA_MAP_PAGE 390 }; 391 392 struct mlx5e_sq_dma { 393 dma_addr_t addr; 394 u32 size; 395 enum mlx5e_dma_map_type type; 396 }; 397 398 enum { 399 MLX5E_SQ_STATE_ENABLED, 400 MLX5E_SQ_STATE_MPWQE, 401 MLX5E_SQ_STATE_RECOVERING, 402 MLX5E_SQ_STATE_IPSEC, 403 MLX5E_SQ_STATE_AM, 404 MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, 405 MLX5E_SQ_STATE_PENDING_XSK_TX, 406 MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC, 407 MLX5E_SQ_STATE_XDP_MULTIBUF, 408 }; 409 410 struct mlx5e_tx_mpwqe { 411 /* Current MPWQE session */ 412 struct mlx5e_tx_wqe *wqe; 413 u32 bytes_count; 414 u8 ds_count; 415 u8 pkt_count; 416 u8 inline_on; 417 }; 418 419 struct mlx5e_skb_fifo { 420 struct sk_buff **fifo; 421 u16 *pc; 422 u16 *cc; 423 u16 mask; 424 }; 425 426 struct mlx5e_ptpsq; 427 428 struct mlx5e_txqsq { 429 /* data path */ 430 431 /* dirtied @completion */ 432 u16 cc; 433 u16 skb_fifo_cc; 434 u32 dma_fifo_cc; 435 struct dim dim; /* Adaptive Moderation */ 436 437 /* dirtied @xmit */ 438 u16 pc ____cacheline_aligned_in_smp; 439 u16 skb_fifo_pc; 440 u32 dma_fifo_pc; 441 struct mlx5e_tx_mpwqe mpwqe; 442 443 struct mlx5e_cq cq; 444 445 /* read only */ 446 struct mlx5_wq_cyc wq; 447 u32 dma_fifo_mask; 448 struct mlx5e_sq_stats *stats; 449 struct { 450 struct mlx5e_sq_dma *dma_fifo; 451 struct mlx5e_skb_fifo skb_fifo; 452 struct mlx5e_tx_wqe_info *wqe_info; 453 } db; 454 void __iomem *uar_map; 455 struct netdev_queue *txq; 456 u32 sqn; 457 u16 stop_room; 458 u16 max_sq_mpw_wqebbs; 459 u8 min_inline_mode; 460 struct device *pdev; 461 __be32 mkey_be; 462 unsigned long state; 463 unsigned int hw_mtu; 464 struct mlx5_clock *clock; 465 struct net_device *netdev; 466 struct mlx5_core_dev *mdev; 467 struct mlx5e_priv *priv; 468 469 /* control path */ 470 struct mlx5_wq_ctrl wq_ctrl; 471 int ch_ix; 472 int txq_ix; 473 u32 rate_limit; 474 struct work_struct recover_work; 475 struct mlx5e_ptpsq *ptpsq; 476 cqe_ts_to_ns ptp_cyc2time; 477 u16 max_sq_wqebbs; 478 } ____cacheline_aligned_in_smp; 479 480 struct mlx5e_dma_info { 481 dma_addr_t addr; 482 union { 483 struct page *page; 484 struct xdp_buff *xsk; 485 }; 486 }; 487 488 /* XDP packets can be transmitted in different ways. On completion, we need to 489 * distinguish between them to clean up things in a proper way. 490 */ 491 enum mlx5e_xdp_xmit_mode { 492 /* An xdp_frame was transmitted due to either XDP_REDIRECT from another 493 * device or XDP_TX from an XSK RQ. The frame has to be unmapped and 494 * returned. 495 */ 496 MLX5E_XDP_XMIT_MODE_FRAME, 497 498 /* The xdp_frame was created in place as a result of XDP_TX from a 499 * regular RQ. No DMA remapping happened, and the page belongs to us. 500 */ 501 MLX5E_XDP_XMIT_MODE_PAGE, 502 503 /* No xdp_frame was created at all, the transmit happened from a UMEM 504 * page. The UMEM Completion Ring producer pointer has to be increased. 505 */ 506 MLX5E_XDP_XMIT_MODE_XSK, 507 }; 508 509 struct mlx5e_xdp_info { 510 enum mlx5e_xdp_xmit_mode mode; 511 union { 512 struct { 513 struct xdp_frame *xdpf; 514 dma_addr_t dma_addr; 515 } frame; 516 struct { 517 struct mlx5e_rq *rq; 518 struct page *page; 519 } page; 520 }; 521 }; 522 523 struct mlx5e_xmit_data { 524 dma_addr_t dma_addr; 525 void *data; 526 u32 len; 527 }; 528 529 struct mlx5e_xdp_info_fifo { 530 struct mlx5e_xdp_info *xi; 531 u32 *cc; 532 u32 *pc; 533 u32 mask; 534 }; 535 536 struct mlx5e_xdpsq; 537 typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *); 538 typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *, 539 struct mlx5e_xmit_data *, 540 struct skb_shared_info *, 541 int); 542 543 struct mlx5e_xdpsq { 544 /* data path */ 545 546 /* dirtied @completion */ 547 u32 xdpi_fifo_cc; 548 u16 cc; 549 550 /* dirtied @xmit */ 551 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp; 552 u16 pc; 553 struct mlx5_wqe_ctrl_seg *doorbell_cseg; 554 struct mlx5e_tx_mpwqe mpwqe; 555 556 struct mlx5e_cq cq; 557 558 /* read only */ 559 struct xsk_buff_pool *xsk_pool; 560 struct mlx5_wq_cyc wq; 561 struct mlx5e_xdpsq_stats *stats; 562 mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check; 563 mlx5e_fp_xmit_xdp_frame xmit_xdp_frame; 564 struct { 565 struct mlx5e_xdp_wqe_info *wqe_info; 566 struct mlx5e_xdp_info_fifo xdpi_fifo; 567 } db; 568 void __iomem *uar_map; 569 u32 sqn; 570 struct device *pdev; 571 __be32 mkey_be; 572 u16 stop_room; 573 u16 max_sq_mpw_wqebbs; 574 u8 min_inline_mode; 575 unsigned long state; 576 unsigned int hw_mtu; 577 578 /* control path */ 579 struct mlx5_wq_ctrl wq_ctrl; 580 struct mlx5e_channel *channel; 581 u16 max_sq_wqebbs; 582 } ____cacheline_aligned_in_smp; 583 584 struct mlx5e_ktls_resync_resp; 585 586 struct mlx5e_icosq { 587 /* data path */ 588 u16 cc; 589 u16 pc; 590 591 struct mlx5_wqe_ctrl_seg *doorbell_cseg; 592 struct mlx5e_cq cq; 593 594 /* write@xmit, read@completion */ 595 struct { 596 struct mlx5e_icosq_wqe_info *wqe_info; 597 } db; 598 599 /* read only */ 600 struct mlx5_wq_cyc wq; 601 void __iomem *uar_map; 602 u32 sqn; 603 u16 reserved_room; 604 unsigned long state; 605 struct mlx5e_ktls_resync_resp *ktls_resync; 606 607 /* control path */ 608 struct mlx5_wq_ctrl wq_ctrl; 609 struct mlx5e_channel *channel; 610 u16 max_sq_wqebbs; 611 612 struct work_struct recover_work; 613 } ____cacheline_aligned_in_smp; 614 615 struct mlx5e_wqe_frag_info { 616 struct mlx5e_dma_info *di; 617 u32 offset; 618 bool last_in_page; 619 }; 620 621 struct mlx5e_umr_dma_info { 622 struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE]; 623 }; 624 625 struct mlx5e_mpw_info { 626 struct mlx5e_umr_dma_info umr; 627 u16 consumed_strides; 628 DECLARE_BITMAP(xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE); 629 }; 630 631 #define MLX5E_MAX_RX_FRAGS 4 632 633 /* a single cache unit is capable to serve one napi call (for non-striding rq) 634 * or a MPWQE (for striding rq). 635 */ 636 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \ 637 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT) 638 #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT)) 639 struct mlx5e_page_cache { 640 u32 head; 641 u32 tail; 642 struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE]; 643 }; 644 645 struct mlx5e_rq; 646 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*); 647 typedef struct sk_buff * 648 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, 649 u16 cqe_bcnt, u32 head_offset, u32 page_idx); 650 typedef struct sk_buff * 651 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5e_wqe_frag_info *wi, 652 u32 cqe_bcnt); 653 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq); 654 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16); 655 typedef void (*mlx5e_fp_shampo_dealloc_hd)(struct mlx5e_rq*, u16, u16, bool); 656 657 int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk); 658 void mlx5e_rq_set_trap_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params); 659 660 enum mlx5e_rq_flag { 661 MLX5E_RQ_FLAG_XDP_XMIT, 662 MLX5E_RQ_FLAG_XDP_REDIRECT, 663 }; 664 665 struct mlx5e_rq_frag_info { 666 int frag_size; 667 int frag_stride; 668 }; 669 670 struct mlx5e_rq_frags_info { 671 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS]; 672 u8 num_frags; 673 u8 log_num_frags; 674 u8 wqe_bulk; 675 }; 676 677 struct mlx5e_shampo_hd { 678 u32 mkey; 679 struct mlx5e_dma_info *info; 680 struct page *last_page; 681 u16 hd_per_wq; 682 u16 hd_per_wqe; 683 unsigned long *bitmap; 684 u16 pi; 685 u16 ci; 686 __be32 key; 687 u64 last_addr; 688 }; 689 690 struct mlx5e_hw_gro_data { 691 struct sk_buff *skb; 692 struct flow_keys fk; 693 int second_ip_id; 694 }; 695 696 struct mlx5e_rq { 697 /* data path */ 698 union { 699 struct { 700 struct mlx5_wq_cyc wq; 701 struct mlx5e_wqe_frag_info *frags; 702 struct mlx5e_dma_info *di; 703 struct mlx5e_rq_frags_info info; 704 mlx5e_fp_skb_from_cqe skb_from_cqe; 705 } wqe; 706 struct { 707 struct mlx5_wq_ll wq; 708 struct mlx5e_umr_wqe umr_wqe; 709 struct mlx5e_mpw_info *info; 710 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq; 711 u16 num_strides; 712 u16 actual_wq_head; 713 u8 log_stride_sz; 714 u8 umr_in_progress; 715 u8 umr_last_bulk; 716 u8 umr_completed; 717 u8 min_wqe_bulk; 718 struct mlx5e_shampo_hd *shampo; 719 } mpwqe; 720 }; 721 struct { 722 u16 headroom; 723 u32 frame0_sz; 724 u8 map_dir; /* dma map direction */ 725 } buff; 726 727 struct device *pdev; 728 struct net_device *netdev; 729 struct mlx5e_rq_stats *stats; 730 struct mlx5e_cq cq; 731 struct mlx5e_cq_decomp cqd; 732 struct mlx5e_page_cache page_cache; 733 struct hwtstamp_config *tstamp; 734 struct mlx5_clock *clock; 735 struct mlx5e_icosq *icosq; 736 struct mlx5e_priv *priv; 737 738 struct mlx5e_hw_gro_data *hw_gro_data; 739 740 mlx5e_fp_handle_rx_cqe handle_rx_cqe; 741 mlx5e_fp_post_rx_wqes post_wqes; 742 mlx5e_fp_dealloc_wqe dealloc_wqe; 743 744 unsigned long state; 745 int ix; 746 unsigned int hw_mtu; 747 748 struct dim dim; /* Dynamic Interrupt Moderation */ 749 750 /* XDP */ 751 struct bpf_prog __rcu *xdp_prog; 752 struct mlx5e_xdpsq *xdpsq; 753 DECLARE_BITMAP(flags, 8); 754 struct page_pool *page_pool; 755 756 /* AF_XDP zero-copy */ 757 struct xsk_buff_pool *xsk_pool; 758 759 struct work_struct recover_work; 760 761 /* control */ 762 struct mlx5_wq_ctrl wq_ctrl; 763 __be32 mkey_be; 764 u8 wq_type; 765 u32 rqn; 766 struct mlx5_core_dev *mdev; 767 struct mlx5e_channel *channel; 768 u32 umr_mkey; 769 struct mlx5e_dma_info wqe_overflow; 770 771 /* XDP read-mostly */ 772 struct xdp_rxq_info xdp_rxq; 773 cqe_ts_to_ns ptp_cyc2time; 774 } ____cacheline_aligned_in_smp; 775 776 enum mlx5e_channel_state { 777 MLX5E_CHANNEL_STATE_XSK, 778 MLX5E_CHANNEL_NUM_STATES 779 }; 780 781 struct mlx5e_channel { 782 /* data path */ 783 struct mlx5e_rq rq; 784 struct mlx5e_xdpsq rq_xdpsq; 785 struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC]; 786 struct mlx5e_icosq icosq; /* internal control operations */ 787 struct mlx5e_txqsq __rcu * __rcu *qos_sqs; 788 bool xdp; 789 struct napi_struct napi; 790 struct device *pdev; 791 struct net_device *netdev; 792 __be32 mkey_be; 793 u16 qos_sqs_size; 794 u8 num_tc; 795 u8 lag_port; 796 797 /* XDP_REDIRECT */ 798 struct mlx5e_xdpsq xdpsq; 799 800 /* AF_XDP zero-copy */ 801 struct mlx5e_rq xskrq; 802 struct mlx5e_xdpsq xsksq; 803 804 /* Async ICOSQ */ 805 struct mlx5e_icosq async_icosq; 806 /* async_icosq can be accessed from any CPU - the spinlock protects it. */ 807 spinlock_t async_icosq_lock; 808 809 /* data path - accessed per napi poll */ 810 const struct cpumask *aff_mask; 811 struct mlx5e_ch_stats *stats; 812 813 /* control */ 814 struct mlx5e_priv *priv; 815 struct mlx5_core_dev *mdev; 816 struct hwtstamp_config *tstamp; 817 DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES); 818 int ix; 819 int cpu; 820 /* Sync between icosq recovery and XSK enable/disable. */ 821 struct mutex icosq_recovery_lock; 822 }; 823 824 struct mlx5e_ptp; 825 826 struct mlx5e_channels { 827 struct mlx5e_channel **c; 828 struct mlx5e_ptp *ptp; 829 unsigned int num; 830 struct mlx5e_params params; 831 }; 832 833 struct mlx5e_channel_stats { 834 struct mlx5e_ch_stats ch; 835 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC]; 836 struct mlx5e_rq_stats rq; 837 struct mlx5e_rq_stats xskrq; 838 struct mlx5e_xdpsq_stats rq_xdpsq; 839 struct mlx5e_xdpsq_stats xdpsq; 840 struct mlx5e_xdpsq_stats xsksq; 841 } ____cacheline_aligned_in_smp; 842 843 struct mlx5e_ptp_stats { 844 struct mlx5e_ch_stats ch; 845 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC]; 846 struct mlx5e_ptp_cq_stats cq[MLX5E_MAX_NUM_TC]; 847 struct mlx5e_rq_stats rq; 848 } ____cacheline_aligned_in_smp; 849 850 enum { 851 MLX5E_STATE_OPENED, 852 MLX5E_STATE_DESTROYING, 853 MLX5E_STATE_XDP_TX_ENABLED, 854 MLX5E_STATE_XDP_ACTIVE, 855 }; 856 857 enum { 858 MLX5E_TC_PRIO = 0, 859 MLX5E_NIC_PRIO 860 }; 861 862 struct mlx5e_modify_sq_param { 863 int curr_state; 864 int next_state; 865 int rl_update; 866 int rl_index; 867 bool qos_update; 868 u16 qos_queue_group_id; 869 }; 870 871 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE) 872 struct mlx5e_hv_vhca_stats_agent { 873 struct mlx5_hv_vhca_agent *agent; 874 struct delayed_work work; 875 u16 delay; 876 void *buf; 877 }; 878 #endif 879 880 struct mlx5e_xsk { 881 /* XSK buffer pools are stored separately from channels, 882 * because we don't want to lose them when channels are 883 * recreated. The kernel also stores buffer pool, but it doesn't 884 * distinguish between zero-copy and non-zero-copy UMEMs, so 885 * rely on our mechanism. 886 */ 887 struct xsk_buff_pool **pools; 888 u16 refcnt; 889 bool ever_used; 890 }; 891 892 /* Temporary storage for variables that are allocated when struct mlx5e_priv is 893 * initialized, and used where we can't allocate them because that functions 894 * must not fail. Use with care and make sure the same variable is not used 895 * simultaneously by multiple users. 896 */ 897 struct mlx5e_scratchpad { 898 cpumask_var_t cpumask; 899 }; 900 901 struct mlx5e_htb { 902 DECLARE_HASHTABLE(qos_tc2node, order_base_2(MLX5E_QOS_MAX_LEAF_NODES)); 903 DECLARE_BITMAP(qos_used_qids, MLX5E_QOS_MAX_LEAF_NODES); 904 struct mlx5e_sq_stats **qos_sq_stats; 905 u16 max_qos_sqs; 906 u16 maj_id; 907 u16 defcls; 908 }; 909 910 struct mlx5e_trap; 911 912 struct mlx5e_priv { 913 /* priv data path fields - start */ 914 struct mlx5e_selq selq; 915 struct mlx5e_txqsq **txq2sq; 916 #ifdef CONFIG_MLX5_CORE_EN_DCB 917 struct mlx5e_dcbx_dp dcbx_dp; 918 #endif 919 /* priv data path fields - end */ 920 921 u32 msglevel; 922 unsigned long state; 923 struct mutex state_lock; /* Protects Interface state */ 924 struct mlx5e_rq drop_rq; 925 926 struct mlx5e_channels channels; 927 u32 tisn[MLX5_MAX_PORTS][MLX5E_MAX_NUM_TC]; 928 struct mlx5e_rx_res *rx_res; 929 u32 *tx_rates; 930 931 struct mlx5e_flow_steering fs; 932 933 struct workqueue_struct *wq; 934 struct work_struct update_carrier_work; 935 struct work_struct set_rx_mode_work; 936 struct work_struct tx_timeout_work; 937 struct work_struct update_stats_work; 938 struct work_struct monitor_counters_work; 939 struct mlx5_nb monitor_counters_nb; 940 941 struct mlx5_core_dev *mdev; 942 struct net_device *netdev; 943 struct mlx5e_trap *en_trap; 944 struct mlx5e_stats stats; 945 struct mlx5e_channel_stats **channel_stats; 946 struct mlx5e_channel_stats trap_stats; 947 struct mlx5e_ptp_stats ptp_stats; 948 u16 stats_nch; 949 u16 max_nch; 950 u8 max_opened_tc; 951 bool tx_ptp_opened; 952 bool rx_ptp_opened; 953 struct hwtstamp_config tstamp; 954 u16 q_counter; 955 u16 drop_rq_q_counter; 956 struct notifier_block events_nb; 957 struct notifier_block blocking_events_nb; 958 959 struct udp_tunnel_nic_info nic_info; 960 #ifdef CONFIG_MLX5_CORE_EN_DCB 961 struct mlx5e_dcbx dcbx; 962 #endif 963 964 const struct mlx5e_profile *profile; 965 void *ppriv; 966 #ifdef CONFIG_MLX5_EN_IPSEC 967 struct mlx5e_ipsec *ipsec; 968 #endif 969 #ifdef CONFIG_MLX5_EN_TLS 970 struct mlx5e_tls *tls; 971 #endif 972 struct devlink_health_reporter *tx_reporter; 973 struct devlink_health_reporter *rx_reporter; 974 struct mlx5e_xsk xsk; 975 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE) 976 struct mlx5e_hv_vhca_stats_agent stats_agent; 977 #endif 978 struct mlx5e_scratchpad scratchpad; 979 struct mlx5e_htb htb; 980 struct mlx5e_mqprio_rl *mqprio_rl; 981 }; 982 983 struct mlx5e_rx_handlers { 984 mlx5e_fp_handle_rx_cqe handle_rx_cqe; 985 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe; 986 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe_shampo; 987 }; 988 989 extern const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic; 990 991 enum mlx5e_profile_feature { 992 MLX5E_PROFILE_FEATURE_PTP_RX, 993 MLX5E_PROFILE_FEATURE_PTP_TX, 994 MLX5E_PROFILE_FEATURE_QOS_HTB, 995 }; 996 997 struct mlx5e_profile { 998 int (*init)(struct mlx5_core_dev *mdev, 999 struct net_device *netdev); 1000 void (*cleanup)(struct mlx5e_priv *priv); 1001 int (*init_rx)(struct mlx5e_priv *priv); 1002 void (*cleanup_rx)(struct mlx5e_priv *priv); 1003 int (*init_tx)(struct mlx5e_priv *priv); 1004 void (*cleanup_tx)(struct mlx5e_priv *priv); 1005 void (*enable)(struct mlx5e_priv *priv); 1006 void (*disable)(struct mlx5e_priv *priv); 1007 int (*update_rx)(struct mlx5e_priv *priv); 1008 void (*update_stats)(struct mlx5e_priv *priv); 1009 void (*update_carrier)(struct mlx5e_priv *priv); 1010 int (*max_nch_limit)(struct mlx5_core_dev *mdev); 1011 unsigned int (*stats_grps_num)(struct mlx5e_priv *priv); 1012 mlx5e_stats_grp_t *stats_grps; 1013 const struct mlx5e_rx_handlers *rx_handlers; 1014 int max_tc; 1015 u8 rq_groups; 1016 u32 features; 1017 }; 1018 1019 #define mlx5e_profile_feature_cap(profile, feature) \ 1020 ((profile)->features & BIT(MLX5E_PROFILE_FEATURE_##feature)) 1021 1022 void mlx5e_build_ptys2ethtool_map(void); 1023 1024 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev); 1025 1026 void mlx5e_shampo_dealloc_hd(struct mlx5e_rq *rq, u16 len, u16 start, bool close); 1027 void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats); 1028 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s); 1029 1030 void mlx5e_init_l2_addr(struct mlx5e_priv *priv); 1031 int mlx5e_self_test_num(struct mlx5e_priv *priv); 1032 int mlx5e_self_test_fill_strings(struct mlx5e_priv *priv, u8 *data); 1033 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest, 1034 u64 *buf); 1035 void mlx5e_set_rx_mode_work(struct work_struct *work); 1036 1037 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr); 1038 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr); 1039 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val, bool rx_filter); 1040 1041 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, 1042 u16 vid); 1043 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, 1044 u16 vid); 1045 void mlx5e_timestamp_init(struct mlx5e_priv *priv); 1046 1047 struct mlx5e_xsk_param; 1048 1049 struct mlx5e_rq_param; 1050 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param, 1051 struct mlx5e_xsk_param *xsk, int node, 1052 struct mlx5e_rq *rq); 1053 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time); 1054 void mlx5e_close_rq(struct mlx5e_rq *rq); 1055 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param); 1056 void mlx5e_destroy_rq(struct mlx5e_rq *rq); 1057 1058 struct mlx5e_sq_param; 1059 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params, 1060 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool, 1061 struct mlx5e_xdpsq *sq, bool is_redirect); 1062 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq); 1063 1064 struct mlx5e_create_cq_param { 1065 struct napi_struct *napi; 1066 struct mlx5e_ch_stats *ch_stats; 1067 int node; 1068 int ix; 1069 }; 1070 1071 struct mlx5e_cq_param; 1072 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder, 1073 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp, 1074 struct mlx5e_cq *cq); 1075 void mlx5e_close_cq(struct mlx5e_cq *cq); 1076 1077 int mlx5e_open_locked(struct net_device *netdev); 1078 int mlx5e_close_locked(struct net_device *netdev); 1079 1080 void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c); 1081 void mlx5e_trigger_napi_sched(struct napi_struct *napi); 1082 1083 int mlx5e_open_channels(struct mlx5e_priv *priv, 1084 struct mlx5e_channels *chs); 1085 void mlx5e_close_channels(struct mlx5e_channels *chs); 1086 1087 /* Function pointer to be used to modify HW or kernel settings while 1088 * switching channels 1089 */ 1090 typedef int (*mlx5e_fp_preactivate)(struct mlx5e_priv *priv, void *context); 1091 #define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \ 1092 int fn##_ctx(struct mlx5e_priv *priv, void *context) \ 1093 { \ 1094 return fn(priv); \ 1095 } 1096 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv); 1097 int mlx5e_safe_switch_params(struct mlx5e_priv *priv, 1098 struct mlx5e_params *new_params, 1099 mlx5e_fp_preactivate preactivate, 1100 void *context, bool reset); 1101 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv); 1102 int mlx5e_num_channels_changed_ctx(struct mlx5e_priv *priv, void *context); 1103 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv); 1104 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv); 1105 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx); 1106 1107 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state); 1108 void mlx5e_activate_rq(struct mlx5e_rq *rq); 1109 void mlx5e_deactivate_rq(struct mlx5e_rq *rq); 1110 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq); 1111 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq); 1112 1113 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn, 1114 struct mlx5e_modify_sq_param *p); 1115 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix, 1116 struct mlx5e_params *params, struct mlx5e_sq_param *param, 1117 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id, 1118 struct mlx5e_sq_stats *sq_stats); 1119 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq); 1120 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq); 1121 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq); 1122 void mlx5e_tx_disable_queue(struct netdev_queue *txq); 1123 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa); 1124 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq); 1125 struct mlx5e_create_sq_param; 1126 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev, 1127 struct mlx5e_sq_param *param, 1128 struct mlx5e_create_sq_param *csp, 1129 u16 qos_queue_group_id, 1130 u32 *sqn); 1131 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work); 1132 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq); 1133 1134 static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev) 1135 { 1136 return MLX5_CAP_ETH(mdev, swp) && 1137 MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso); 1138 } 1139 1140 extern const struct ethtool_ops mlx5e_ethtool_ops; 1141 1142 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev); 1143 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); 1144 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb, 1145 bool enable_mc_lb); 1146 void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc); 1147 1148 /* common netdev helpers */ 1149 void mlx5e_create_q_counters(struct mlx5e_priv *priv); 1150 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv); 1151 int mlx5e_open_drop_rq(struct mlx5e_priv *priv, 1152 struct mlx5e_rq *drop_rq); 1153 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq); 1154 int mlx5e_init_di_list(struct mlx5e_rq *rq, int wq_sz, int node); 1155 void mlx5e_free_di_list(struct mlx5e_rq *rq); 1156 1157 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn); 1158 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn); 1159 1160 int mlx5e_create_tises(struct mlx5e_priv *priv); 1161 void mlx5e_destroy_tises(struct mlx5e_priv *priv); 1162 int mlx5e_update_nic_rx(struct mlx5e_priv *priv); 1163 void mlx5e_update_carrier(struct mlx5e_priv *priv); 1164 int mlx5e_close(struct net_device *netdev); 1165 int mlx5e_open(struct net_device *netdev); 1166 1167 void mlx5e_queue_update_stats(struct mlx5e_priv *priv); 1168 1169 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv); 1170 int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv *priv, void *context); 1171 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu, 1172 mlx5e_fp_preactivate preactivate); 1173 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv); 1174 1175 /* ethtool helpers */ 1176 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv, 1177 struct ethtool_drvinfo *drvinfo); 1178 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, 1179 uint32_t stringset, uint8_t *data); 1180 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset); 1181 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv, 1182 struct ethtool_stats *stats, u64 *data); 1183 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv, 1184 struct ethtool_ringparam *param); 1185 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, 1186 struct ethtool_ringparam *param); 1187 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv, 1188 struct ethtool_channels *ch); 1189 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, 1190 struct ethtool_channels *ch); 1191 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv, 1192 struct ethtool_coalesce *coal, 1193 struct kernel_ethtool_coalesce *kernel_coal); 1194 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, 1195 struct ethtool_coalesce *coal, 1196 struct kernel_ethtool_coalesce *kernel_coal, 1197 struct netlink_ext_ack *extack); 1198 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv, 1199 struct ethtool_link_ksettings *link_ksettings); 1200 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv, 1201 const struct ethtool_link_ksettings *link_ksettings); 1202 int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, u8 *hfunc); 1203 int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key, 1204 const u8 hfunc); 1205 int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, 1206 u32 *rule_locs); 1207 int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd); 1208 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv); 1209 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv); 1210 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv, 1211 struct ethtool_ts_info *info); 1212 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv, 1213 struct ethtool_flash *flash); 1214 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv, 1215 struct ethtool_pauseparam *pauseparam); 1216 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv, 1217 struct ethtool_pauseparam *pauseparam); 1218 1219 /* mlx5e generic netdev management API */ 1220 static inline bool 1221 mlx5e_tx_mpwqe_supported(struct mlx5_core_dev *mdev) 1222 { 1223 return !is_kdump_kernel() && 1224 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe); 1225 } 1226 1227 int mlx5e_get_pf_num_tirs(struct mlx5_core_dev *mdev); 1228 int mlx5e_priv_init(struct mlx5e_priv *priv, 1229 const struct mlx5e_profile *profile, 1230 struct net_device *netdev, 1231 struct mlx5_core_dev *mdev); 1232 void mlx5e_priv_cleanup(struct mlx5e_priv *priv); 1233 struct net_device * 1234 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile); 1235 int mlx5e_attach_netdev(struct mlx5e_priv *priv); 1236 void mlx5e_detach_netdev(struct mlx5e_priv *priv); 1237 void mlx5e_destroy_netdev(struct mlx5e_priv *priv); 1238 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv, 1239 const struct mlx5e_profile *new_profile, void *new_ppriv); 1240 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv); 1241 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv); 1242 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu); 1243 void mlx5e_rx_dim_work(struct work_struct *work); 1244 void mlx5e_tx_dim_work(struct work_struct *work); 1245 1246 netdev_features_t mlx5e_features_check(struct sk_buff *skb, 1247 struct net_device *netdev, 1248 netdev_features_t features); 1249 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features); 1250 #ifdef CONFIG_MLX5_ESWITCH 1251 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac); 1252 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate); 1253 int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi); 1254 int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats); 1255 #endif 1256 #endif /* __MLX5_EN_H__ */ 1257