1 /* 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef __MLX5_EN_H__ 33 #define __MLX5_EN_H__ 34 35 #include <linux/if_vlan.h> 36 #include <linux/etherdevice.h> 37 #include <linux/timecounter.h> 38 #include <linux/net_tstamp.h> 39 #include <linux/ptp_clock_kernel.h> 40 #include <linux/crash_dump.h> 41 #include <linux/mlx5/driver.h> 42 #include <linux/mlx5/qp.h> 43 #include <linux/mlx5/cq.h> 44 #include <linux/mlx5/port.h> 45 #include <linux/mlx5/vport.h> 46 #include <linux/mlx5/transobj.h> 47 #include <linux/rhashtable.h> 48 #include <net/switchdev.h> 49 #include "wq.h" 50 #include "mlx5_core.h" 51 #include "en_stats.h" 52 53 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v) 54 55 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) 56 57 #define MLX5E_HW2SW_MTU(priv, hwmtu) ((hwmtu) - ((priv)->hard_mtu)) 58 #define MLX5E_SW2HW_MTU(priv, swmtu) ((swmtu) + ((priv)->hard_mtu)) 59 60 #define MLX5E_MAX_NUM_TC 8 61 62 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 63 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa 64 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd 65 66 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1 67 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa 68 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd 69 70 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1 71 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x3 72 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6 73 74 #define MLX5_RX_HEADROOM NET_SKB_PAD 75 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \ 76 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 77 78 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \ 79 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */ 80 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \ 81 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req) 82 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 6) 83 #define MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 8) 84 85 #define MLX5_MPWRQ_LOG_WQE_SZ 18 86 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \ 87 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0) 88 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER) 89 #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \ 90 MLX5_MPWRQ_WQE_PAGE_ORDER) 91 92 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2) 93 #define MLX5E_REQUIRED_MTTS(wqes) \ 94 (wqes * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8)) 95 #define MLX5E_VALID_NUM_MTTS(num_mtts) (MLX5_MTT_OCTW(num_mtts) - 1 <= U16_MAX) 96 97 #define MLX5_UMR_ALIGN (2048) 98 #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (256) 99 100 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024) 101 #define MLX5E_DEFAULT_LRO_TIMEOUT 32 102 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4 103 104 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 105 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 106 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 107 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 108 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 109 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 110 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 111 112 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7 113 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE) 114 #define MLX5E_MIN_NUM_CHANNELS 0x1 115 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1) 116 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC) 117 #define MLX5E_TX_CQ_POLL_BUDGET 128 118 #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */ 119 120 #define MLX5E_ICOSQ_MAX_WQEBBS \ 121 (DIV_ROUND_UP(sizeof(struct mlx5e_umr_wqe), MLX5_SEND_WQE_BB)) 122 123 #define MLX5E_XDP_MIN_INLINE (ETH_HLEN + VLAN_HLEN) 124 #define MLX5E_XDP_TX_DS_COUNT \ 125 ((sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS) + 1 /* SG DS */) 126 127 #define MLX5E_NUM_MAIN_GROUPS 9 128 129 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) 130 { 131 switch (wq_type) { 132 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 133 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, 134 wq_size / 2); 135 default: 136 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, 137 wq_size / 2); 138 } 139 } 140 141 static inline int mlx5_min_log_rq_size(int wq_type) 142 { 143 switch (wq_type) { 144 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 145 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW; 146 default: 147 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE; 148 } 149 } 150 151 static inline int mlx5_max_log_rq_size(int wq_type) 152 { 153 switch (wq_type) { 154 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 155 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW; 156 default: 157 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE; 158 } 159 } 160 161 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) 162 { 163 return is_kdump_kernel() ? 164 MLX5E_MIN_NUM_CHANNELS : 165 min_t(int, mdev->priv.eq_table.num_comp_vectors, 166 MLX5E_MAX_NUM_CHANNELS); 167 } 168 169 struct mlx5e_tx_wqe { 170 struct mlx5_wqe_ctrl_seg ctrl; 171 struct mlx5_wqe_eth_seg eth; 172 }; 173 174 struct mlx5e_rx_wqe { 175 struct mlx5_wqe_srq_next_seg next; 176 struct mlx5_wqe_data_seg data; 177 }; 178 179 struct mlx5e_umr_wqe { 180 struct mlx5_wqe_ctrl_seg ctrl; 181 struct mlx5_wqe_umr_ctrl_seg uctrl; 182 struct mlx5_mkey_seg mkc; 183 struct mlx5_wqe_data_seg data; 184 }; 185 186 extern const char mlx5e_self_tests[][ETH_GSTRING_LEN]; 187 188 static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = { 189 "rx_cqe_moder", 190 "rx_cqe_compress", 191 }; 192 193 enum mlx5e_priv_flag { 194 MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0), 195 MLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 1), 196 }; 197 198 #define MLX5E_SET_PFLAG(params, pflag, enable) \ 199 do { \ 200 if (enable) \ 201 (params)->pflags |= (pflag); \ 202 else \ 203 (params)->pflags &= ~(pflag); \ 204 } while (0) 205 206 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (pflag))) 207 208 #ifdef CONFIG_MLX5_CORE_EN_DCB 209 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */ 210 #endif 211 212 struct mlx5e_cq_moder { 213 u16 usec; 214 u16 pkts; 215 }; 216 217 struct mlx5e_params { 218 u8 log_sq_size; 219 u8 rq_wq_type; 220 u16 rq_headroom; 221 u8 mpwqe_log_stride_sz; 222 u8 mpwqe_log_num_strides; 223 u8 log_rq_size; 224 u16 num_channels; 225 u8 num_tc; 226 u8 rx_cq_period_mode; 227 bool rx_cqe_compress_def; 228 struct mlx5e_cq_moder rx_cq_moderation; 229 struct mlx5e_cq_moder tx_cq_moderation; 230 bool lro_en; 231 u32 lro_wqe_sz; 232 u16 tx_max_inline; 233 u8 tx_min_inline_mode; 234 u8 rss_hfunc; 235 u8 toeplitz_hash_key[40]; 236 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE]; 237 bool vlan_strip_disable; 238 bool scatter_fcs_en; 239 bool rx_am_enabled; 240 u32 lro_timeout; 241 u32 pflags; 242 struct bpf_prog *xdp_prog; 243 }; 244 245 #ifdef CONFIG_MLX5_CORE_EN_DCB 246 struct mlx5e_cee_config { 247 /* bw pct for priority group */ 248 u8 pg_bw_pct[CEE_DCBX_MAX_PGS]; 249 u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO]; 250 bool pfc_setting[CEE_DCBX_MAX_PRIO]; 251 bool pfc_enable; 252 }; 253 254 enum { 255 MLX5_DCB_CHG_RESET, 256 MLX5_DCB_NO_CHG, 257 MLX5_DCB_CHG_NO_RESET, 258 }; 259 260 struct mlx5e_dcbx { 261 enum mlx5_dcbx_oper_mode mode; 262 struct mlx5e_cee_config cee_cfg; /* pending configuration */ 263 264 /* The only setting that cannot be read from FW */ 265 u8 tc_tsa[IEEE_8021QAZ_MAX_TCS]; 266 u8 cap; 267 }; 268 #endif 269 270 #define MAX_PIN_NUM 8 271 struct mlx5e_pps { 272 u8 pin_caps[MAX_PIN_NUM]; 273 struct work_struct out_work; 274 u64 start[MAX_PIN_NUM]; 275 u8 enabled; 276 }; 277 278 struct mlx5e_tstamp { 279 rwlock_t lock; 280 struct cyclecounter cycles; 281 struct timecounter clock; 282 struct hwtstamp_config hwtstamp_config; 283 u32 nominal_c_mult; 284 unsigned long overflow_period; 285 struct delayed_work overflow_work; 286 struct mlx5_core_dev *mdev; 287 struct ptp_clock *ptp; 288 struct ptp_clock_info ptp_info; 289 struct mlx5e_pps pps_info; 290 }; 291 292 enum { 293 MLX5E_RQ_STATE_ENABLED, 294 MLX5E_RQ_STATE_AM, 295 }; 296 297 #define MLX5E_TEST_BIT(state, nr) (state & BIT(nr)) 298 299 struct mlx5e_cq { 300 /* data path - accessed per cqe */ 301 struct mlx5_cqwq wq; 302 303 /* data path - accessed per napi poll */ 304 u16 event_ctr; 305 struct napi_struct *napi; 306 struct mlx5_core_cq mcq; 307 struct mlx5e_channel *channel; 308 309 /* cqe decompression */ 310 struct mlx5_cqe64 title; 311 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; 312 u8 mini_arr_idx; 313 u16 decmprs_left; 314 u16 decmprs_wqe_counter; 315 316 /* control */ 317 struct mlx5_core_dev *mdev; 318 struct mlx5_frag_wq_ctrl wq_ctrl; 319 } ____cacheline_aligned_in_smp; 320 321 struct mlx5e_tx_wqe_info { 322 struct sk_buff *skb; 323 u32 num_bytes; 324 u8 num_wqebbs; 325 u8 num_dma; 326 }; 327 328 enum mlx5e_dma_map_type { 329 MLX5E_DMA_MAP_SINGLE, 330 MLX5E_DMA_MAP_PAGE 331 }; 332 333 struct mlx5e_sq_dma { 334 dma_addr_t addr; 335 u32 size; 336 enum mlx5e_dma_map_type type; 337 }; 338 339 enum { 340 MLX5E_SQ_STATE_ENABLED, 341 MLX5E_SQ_STATE_IPSEC, 342 }; 343 344 struct mlx5e_sq_wqe_info { 345 u8 opcode; 346 }; 347 348 struct mlx5e_txqsq { 349 /* data path */ 350 351 /* dirtied @completion */ 352 u16 cc; 353 u32 dma_fifo_cc; 354 355 /* dirtied @xmit */ 356 u16 pc ____cacheline_aligned_in_smp; 357 u32 dma_fifo_pc; 358 struct mlx5e_sq_stats stats; 359 360 struct mlx5e_cq cq; 361 362 /* write@xmit, read@completion */ 363 struct { 364 struct mlx5e_sq_dma *dma_fifo; 365 struct mlx5e_tx_wqe_info *wqe_info; 366 } db; 367 368 /* read only */ 369 struct mlx5_wq_cyc wq; 370 u32 dma_fifo_mask; 371 void __iomem *uar_map; 372 struct netdev_queue *txq; 373 u32 sqn; 374 u16 max_inline; 375 u8 min_inline_mode; 376 u16 edge; 377 struct device *pdev; 378 struct mlx5e_tstamp *tstamp; 379 __be32 mkey_be; 380 unsigned long state; 381 382 /* control path */ 383 struct mlx5_wq_ctrl wq_ctrl; 384 struct mlx5e_channel *channel; 385 int txq_ix; 386 u32 rate_limit; 387 } ____cacheline_aligned_in_smp; 388 389 struct mlx5e_xdpsq { 390 /* data path */ 391 392 /* dirtied @rx completion */ 393 u16 cc; 394 u16 pc; 395 396 struct mlx5e_cq cq; 397 398 /* write@xmit, read@completion */ 399 struct { 400 struct mlx5e_dma_info *di; 401 bool doorbell; 402 } db; 403 404 /* read only */ 405 struct mlx5_wq_cyc wq; 406 void __iomem *uar_map; 407 u32 sqn; 408 struct device *pdev; 409 __be32 mkey_be; 410 u8 min_inline_mode; 411 unsigned long state; 412 413 /* control path */ 414 struct mlx5_wq_ctrl wq_ctrl; 415 struct mlx5e_channel *channel; 416 } ____cacheline_aligned_in_smp; 417 418 struct mlx5e_icosq { 419 /* data path */ 420 421 /* dirtied @xmit */ 422 u16 pc ____cacheline_aligned_in_smp; 423 424 struct mlx5e_cq cq; 425 426 /* write@xmit, read@completion */ 427 struct { 428 struct mlx5e_sq_wqe_info *ico_wqe; 429 } db; 430 431 /* read only */ 432 struct mlx5_wq_cyc wq; 433 void __iomem *uar_map; 434 u32 sqn; 435 u16 edge; 436 __be32 mkey_be; 437 unsigned long state; 438 439 /* control path */ 440 struct mlx5_wq_ctrl wq_ctrl; 441 struct mlx5e_channel *channel; 442 } ____cacheline_aligned_in_smp; 443 444 static inline bool 445 mlx5e_wqc_has_room_for(struct mlx5_wq_cyc *wq, u16 cc, u16 pc, u16 n) 446 { 447 return (((wq->sz_m1 & (cc - pc)) >= n) || (cc == pc)); 448 } 449 450 struct mlx5e_dma_info { 451 struct page *page; 452 dma_addr_t addr; 453 }; 454 455 struct mlx5e_wqe_frag_info { 456 struct mlx5e_dma_info di; 457 u32 offset; 458 }; 459 460 struct mlx5e_umr_dma_info { 461 __be64 *mtt; 462 dma_addr_t mtt_addr; 463 struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE]; 464 struct mlx5e_umr_wqe wqe; 465 }; 466 467 struct mlx5e_mpw_info { 468 struct mlx5e_umr_dma_info umr; 469 u16 consumed_strides; 470 u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE]; 471 }; 472 473 struct mlx5e_rx_am_stats { 474 int ppms; /* packets per msec */ 475 int bpms; /* bytes per msec */ 476 int epms; /* events per msec */ 477 }; 478 479 struct mlx5e_rx_am_sample { 480 ktime_t time; 481 u32 pkt_ctr; 482 u32 byte_ctr; 483 u16 event_ctr; 484 }; 485 486 struct mlx5e_rx_am { /* Adaptive Moderation */ 487 u8 state; 488 struct mlx5e_rx_am_stats prev_stats; 489 struct mlx5e_rx_am_sample start_sample; 490 struct work_struct work; 491 u8 profile_ix; 492 u8 mode; 493 u8 tune_state; 494 u8 steps_right; 495 u8 steps_left; 496 u8 tired; 497 }; 498 499 /* a single cache unit is capable to serve one napi call (for non-striding rq) 500 * or a MPWQE (for striding rq). 501 */ 502 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \ 503 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT) 504 #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT)) 505 struct mlx5e_page_cache { 506 u32 head; 507 u32 tail; 508 struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE]; 509 }; 510 511 struct mlx5e_rq; 512 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*); 513 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq); 514 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16); 515 516 struct mlx5e_rq { 517 /* data path */ 518 struct mlx5_wq_ll wq; 519 520 union { 521 struct { 522 struct mlx5e_wqe_frag_info *frag_info; 523 u32 frag_sz; /* max possible skb frag_sz */ 524 union { 525 bool page_reuse; 526 bool xdp_xmit; 527 }; 528 } wqe; 529 struct { 530 struct mlx5e_mpw_info *info; 531 void *mtt_no_align; 532 u16 num_strides; 533 u8 log_stride_sz; 534 bool umr_in_progress; 535 } mpwqe; 536 }; 537 struct { 538 u16 headroom; 539 u8 page_order; 540 u8 map_dir; /* dma map direction */ 541 } buff; 542 543 struct mlx5e_channel *channel; 544 struct device *pdev; 545 struct net_device *netdev; 546 struct mlx5e_tstamp *tstamp; 547 struct mlx5e_rq_stats stats; 548 struct mlx5e_cq cq; 549 struct mlx5e_page_cache page_cache; 550 551 mlx5e_fp_handle_rx_cqe handle_rx_cqe; 552 mlx5e_fp_post_rx_wqes post_wqes; 553 mlx5e_fp_dealloc_wqe dealloc_wqe; 554 555 unsigned long state; 556 int ix; 557 558 struct mlx5e_rx_am am; /* Adaptive Moderation */ 559 560 /* XDP */ 561 struct bpf_prog *xdp_prog; 562 struct mlx5e_xdpsq xdpsq; 563 564 /* control */ 565 struct mlx5_wq_ctrl wq_ctrl; 566 __be32 mkey_be; 567 u8 wq_type; 568 u32 rqn; 569 struct mlx5_core_dev *mdev; 570 struct mlx5_core_mkey umr_mkey; 571 } ____cacheline_aligned_in_smp; 572 573 struct mlx5e_channel { 574 /* data path */ 575 struct mlx5e_rq rq; 576 struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC]; 577 struct mlx5e_icosq icosq; /* internal control operations */ 578 bool xdp; 579 struct napi_struct napi; 580 struct device *pdev; 581 struct net_device *netdev; 582 __be32 mkey_be; 583 u8 num_tc; 584 585 /* data path - accessed per napi poll */ 586 struct irq_desc *irq_desc; 587 588 /* control */ 589 struct mlx5e_priv *priv; 590 struct mlx5_core_dev *mdev; 591 struct mlx5e_tstamp *tstamp; 592 int ix; 593 }; 594 595 struct mlx5e_channels { 596 struct mlx5e_channel **c; 597 unsigned int num; 598 struct mlx5e_params params; 599 }; 600 601 enum mlx5e_traffic_types { 602 MLX5E_TT_IPV4_TCP, 603 MLX5E_TT_IPV6_TCP, 604 MLX5E_TT_IPV4_UDP, 605 MLX5E_TT_IPV6_UDP, 606 MLX5E_TT_IPV4_IPSEC_AH, 607 MLX5E_TT_IPV6_IPSEC_AH, 608 MLX5E_TT_IPV4_IPSEC_ESP, 609 MLX5E_TT_IPV6_IPSEC_ESP, 610 MLX5E_TT_IPV4, 611 MLX5E_TT_IPV6, 612 MLX5E_TT_ANY, 613 MLX5E_NUM_TT, 614 MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY, 615 }; 616 617 enum mlx5e_tunnel_types { 618 MLX5E_TT_IPV4_GRE, 619 MLX5E_TT_IPV6_GRE, 620 MLX5E_NUM_TUNNEL_TT, 621 }; 622 623 enum { 624 MLX5E_STATE_ASYNC_EVENTS_ENABLED, 625 MLX5E_STATE_OPENED, 626 MLX5E_STATE_DESTROYING, 627 }; 628 629 struct mlx5e_vxlan_db { 630 spinlock_t lock; /* protect vxlan table */ 631 struct radix_tree_root tree; 632 }; 633 634 struct mlx5e_l2_rule { 635 u8 addr[ETH_ALEN + 2]; 636 struct mlx5_flow_handle *rule; 637 }; 638 639 struct mlx5e_flow_table { 640 int num_groups; 641 struct mlx5_flow_table *t; 642 struct mlx5_flow_group **g; 643 }; 644 645 #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE) 646 647 struct mlx5e_tc_table { 648 struct mlx5_flow_table *t; 649 650 struct rhashtable_params ht_params; 651 struct rhashtable ht; 652 653 DECLARE_HASHTABLE(mod_hdr_tbl, 8); 654 }; 655 656 struct mlx5e_vlan_table { 657 struct mlx5e_flow_table ft; 658 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 659 struct mlx5_flow_handle *active_vlans_rule[VLAN_N_VID]; 660 struct mlx5_flow_handle *untagged_rule; 661 struct mlx5_flow_handle *any_cvlan_rule; 662 struct mlx5_flow_handle *any_svlan_rule; 663 bool filter_disabled; 664 }; 665 666 struct mlx5e_l2_table { 667 struct mlx5e_flow_table ft; 668 struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE]; 669 struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE]; 670 struct mlx5e_l2_rule broadcast; 671 struct mlx5e_l2_rule allmulti; 672 struct mlx5e_l2_rule promisc; 673 bool broadcast_enabled; 674 bool allmulti_enabled; 675 bool promisc_enabled; 676 }; 677 678 /* L3/L4 traffic type classifier */ 679 struct mlx5e_ttc_table { 680 struct mlx5e_flow_table ft; 681 struct mlx5_flow_handle *rules[MLX5E_NUM_TT]; 682 struct mlx5_flow_handle *tunnel_rules[MLX5E_NUM_TUNNEL_TT]; 683 }; 684 685 #define ARFS_HASH_SHIFT BITS_PER_BYTE 686 #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE) 687 struct arfs_table { 688 struct mlx5e_flow_table ft; 689 struct mlx5_flow_handle *default_rule; 690 struct hlist_head rules_hash[ARFS_HASH_SIZE]; 691 }; 692 693 enum arfs_type { 694 ARFS_IPV4_TCP, 695 ARFS_IPV6_TCP, 696 ARFS_IPV4_UDP, 697 ARFS_IPV6_UDP, 698 ARFS_NUM_TYPES, 699 }; 700 701 struct mlx5e_arfs_tables { 702 struct arfs_table arfs_tables[ARFS_NUM_TYPES]; 703 /* Protect aRFS rules list */ 704 spinlock_t arfs_lock; 705 struct list_head rules; 706 int last_filter_id; 707 struct workqueue_struct *wq; 708 }; 709 710 /* NIC prio FTS */ 711 enum { 712 MLX5E_VLAN_FT_LEVEL = 0, 713 MLX5E_L2_FT_LEVEL, 714 MLX5E_TTC_FT_LEVEL, 715 MLX5E_INNER_TTC_FT_LEVEL, 716 MLX5E_ARFS_FT_LEVEL 717 }; 718 719 struct mlx5e_ethtool_table { 720 struct mlx5_flow_table *ft; 721 int num_rules; 722 }; 723 724 #define ETHTOOL_NUM_L3_L4_FTS 7 725 #define ETHTOOL_NUM_L2_FTS 4 726 727 struct mlx5e_ethtool_steering { 728 struct mlx5e_ethtool_table l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS]; 729 struct mlx5e_ethtool_table l2_ft[ETHTOOL_NUM_L2_FTS]; 730 struct list_head rules; 731 int tot_num_rules; 732 }; 733 734 struct mlx5e_flow_steering { 735 struct mlx5_flow_namespace *ns; 736 struct mlx5e_ethtool_steering ethtool; 737 struct mlx5e_tc_table tc; 738 struct mlx5e_vlan_table vlan; 739 struct mlx5e_l2_table l2; 740 struct mlx5e_ttc_table ttc; 741 struct mlx5e_ttc_table inner_ttc; 742 struct mlx5e_arfs_tables arfs; 743 }; 744 745 struct mlx5e_rqt { 746 u32 rqtn; 747 bool enabled; 748 }; 749 750 struct mlx5e_tir { 751 u32 tirn; 752 struct mlx5e_rqt rqt; 753 struct list_head list; 754 }; 755 756 enum { 757 MLX5E_TC_PRIO = 0, 758 MLX5E_NIC_PRIO 759 }; 760 761 struct mlx5e_priv { 762 /* priv data path fields - start */ 763 struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC]; 764 int channel_tc2txq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC]; 765 /* priv data path fields - end */ 766 767 unsigned long state; 768 struct mutex state_lock; /* Protects Interface state */ 769 struct mlx5e_rq drop_rq; 770 771 struct mlx5e_channels channels; 772 u32 tisn[MLX5E_MAX_NUM_TC]; 773 struct mlx5e_rqt indir_rqt; 774 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS]; 775 struct mlx5e_tir inner_indir_tir[MLX5E_NUM_INDIR_TIRS]; 776 struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS]; 777 u32 tx_rates[MLX5E_MAX_NUM_SQS]; 778 int hard_mtu; 779 780 struct mlx5e_flow_steering fs; 781 struct mlx5e_vxlan_db vxlan; 782 783 struct workqueue_struct *wq; 784 struct work_struct update_carrier_work; 785 struct work_struct set_rx_mode_work; 786 struct work_struct tx_timeout_work; 787 struct delayed_work update_stats_work; 788 789 struct mlx5_core_dev *mdev; 790 struct net_device *netdev; 791 struct mlx5e_stats stats; 792 struct mlx5e_tstamp tstamp; 793 u16 q_counter; 794 #ifdef CONFIG_MLX5_CORE_EN_DCB 795 struct mlx5e_dcbx dcbx; 796 #endif 797 798 const struct mlx5e_profile *profile; 799 void *ppriv; 800 #ifdef CONFIG_MLX5_EN_IPSEC 801 struct mlx5e_ipsec *ipsec; 802 #endif 803 }; 804 805 struct mlx5e_profile { 806 void (*init)(struct mlx5_core_dev *mdev, 807 struct net_device *netdev, 808 const struct mlx5e_profile *profile, void *ppriv); 809 void (*cleanup)(struct mlx5e_priv *priv); 810 int (*init_rx)(struct mlx5e_priv *priv); 811 void (*cleanup_rx)(struct mlx5e_priv *priv); 812 int (*init_tx)(struct mlx5e_priv *priv); 813 void (*cleanup_tx)(struct mlx5e_priv *priv); 814 void (*enable)(struct mlx5e_priv *priv); 815 void (*disable)(struct mlx5e_priv *priv); 816 void (*update_stats)(struct mlx5e_priv *priv); 817 void (*update_carrier)(struct mlx5e_priv *priv); 818 int (*max_nch)(struct mlx5_core_dev *mdev); 819 struct { 820 mlx5e_fp_handle_rx_cqe handle_rx_cqe; 821 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe; 822 } rx_handlers; 823 int max_tc; 824 }; 825 826 void mlx5e_build_ptys2ethtool_map(void); 827 828 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, 829 void *accel_priv, select_queue_fallback_t fallback); 830 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); 831 832 void mlx5e_completion_event(struct mlx5_core_cq *mcq); 833 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); 834 int mlx5e_napi_poll(struct napi_struct *napi, int budget); 835 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget); 836 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); 837 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq); 838 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq); 839 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq); 840 841 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info, 842 bool recycle); 843 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); 844 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); 845 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq); 846 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq); 847 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix); 848 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix); 849 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi); 850 851 void mlx5e_rx_am(struct mlx5e_rq *rq); 852 void mlx5e_rx_am_work(struct work_struct *work); 853 struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode); 854 855 void mlx5e_update_stats(struct mlx5e_priv *priv, bool full); 856 857 int mlx5e_create_flow_steering(struct mlx5e_priv *priv); 858 void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv); 859 void mlx5e_init_l2_addr(struct mlx5e_priv *priv); 860 void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft); 861 int mlx5e_self_test_num(struct mlx5e_priv *priv); 862 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest, 863 u64 *buf); 864 int mlx5e_ethtool_get_flow(struct mlx5e_priv *priv, struct ethtool_rxnfc *info, 865 int location); 866 int mlx5e_ethtool_get_all_flows(struct mlx5e_priv *priv, 867 struct ethtool_rxnfc *info, u32 *rule_locs); 868 int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv, 869 struct ethtool_rx_flow_spec *fs); 870 int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv, 871 int location); 872 void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv); 873 void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv); 874 void mlx5e_set_rx_mode_work(struct work_struct *work); 875 876 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp, 877 struct skb_shared_hwtstamps *hwts); 878 void mlx5e_timestamp_init(struct mlx5e_priv *priv); 879 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv); 880 void mlx5e_pps_event_handler(struct mlx5e_priv *priv, 881 struct ptp_clock_event *event); 882 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr); 883 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr); 884 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val); 885 886 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, 887 u16 vid); 888 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, 889 u16 vid); 890 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); 891 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); 892 893 struct mlx5e_redirect_rqt_param { 894 bool is_rss; 895 union { 896 u32 rqn; /* Direct RQN (Non-RSS) */ 897 struct { 898 u8 hfunc; 899 struct mlx5e_channels *channels; 900 } rss; /* RSS data */ 901 }; 902 }; 903 904 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, 905 struct mlx5e_redirect_rqt_param rrp); 906 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params, 907 enum mlx5e_traffic_types tt, 908 void *tirc, bool inner); 909 910 int mlx5e_open_locked(struct net_device *netdev); 911 int mlx5e_close_locked(struct net_device *netdev); 912 913 int mlx5e_open_channels(struct mlx5e_priv *priv, 914 struct mlx5e_channels *chs); 915 void mlx5e_close_channels(struct mlx5e_channels *chs); 916 917 /* Function pointer to be used to modify WH settings while 918 * switching channels 919 */ 920 typedef int (*mlx5e_fp_hw_modify)(struct mlx5e_priv *priv); 921 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv, 922 struct mlx5e_channels *new_chs, 923 mlx5e_fp_hw_modify hw_modify); 924 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv); 925 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv); 926 927 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len, 928 int num_channels); 929 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed); 930 931 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, 932 u8 cq_period_mode); 933 void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev, 934 struct mlx5e_params *params, u8 rq_type); 935 936 static inline bool mlx5e_tunnel_inner_ft_supported(struct mlx5_core_dev *mdev) 937 { 938 return (MLX5_CAP_ETH(mdev, tunnel_stateless_gre) && 939 MLX5_CAP_FLOWTABLE_NIC_RX(mdev, ft_field_support.inner_ip_version)); 940 } 941 942 static inline 943 struct mlx5e_tx_wqe *mlx5e_post_nop(struct mlx5_wq_cyc *wq, u32 sqn, u16 *pc) 944 { 945 u16 pi = *pc & wq->sz_m1; 946 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi); 947 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; 948 949 memset(cseg, 0, sizeof(*cseg)); 950 951 cseg->opmod_idx_opcode = cpu_to_be32((*pc << 8) | MLX5_OPCODE_NOP); 952 cseg->qpn_ds = cpu_to_be32((sqn << 8) | 0x01); 953 954 (*pc)++; 955 956 return wqe; 957 } 958 959 static inline 960 void mlx5e_notify_hw(struct mlx5_wq_cyc *wq, u16 pc, 961 void __iomem *uar_map, 962 struct mlx5_wqe_ctrl_seg *ctrl) 963 { 964 ctrl->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE; 965 /* ensure wqe is visible to device before updating doorbell record */ 966 dma_wmb(); 967 968 *wq->db = cpu_to_be32(pc); 969 970 /* ensure doorbell record is visible to device before ringing the 971 * doorbell 972 */ 973 wmb(); 974 975 mlx5_write64((__be32 *)ctrl, uar_map, NULL); 976 } 977 978 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) 979 { 980 struct mlx5_core_cq *mcq; 981 982 mcq = &cq->mcq; 983 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc); 984 } 985 986 static inline u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix) 987 { 988 return wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8); 989 } 990 991 extern const struct ethtool_ops mlx5e_ethtool_ops; 992 #ifdef CONFIG_MLX5_CORE_EN_DCB 993 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops; 994 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets); 995 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv); 996 #endif 997 998 #ifndef CONFIG_RFS_ACCEL 999 static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv) 1000 { 1001 return 0; 1002 } 1003 1004 static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {} 1005 1006 static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv) 1007 { 1008 return -EOPNOTSUPP; 1009 } 1010 1011 static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv) 1012 { 1013 return -EOPNOTSUPP; 1014 } 1015 #else 1016 int mlx5e_arfs_create_tables(struct mlx5e_priv *priv); 1017 void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv); 1018 int mlx5e_arfs_enable(struct mlx5e_priv *priv); 1019 int mlx5e_arfs_disable(struct mlx5e_priv *priv); 1020 int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, 1021 u16 rxq_index, u32 flow_id); 1022 #endif 1023 1024 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev); 1025 int mlx5e_create_tir(struct mlx5_core_dev *mdev, 1026 struct mlx5e_tir *tir, u32 *in, int inlen); 1027 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev, 1028 struct mlx5e_tir *tir); 1029 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev); 1030 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); 1031 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb); 1032 1033 /* common netdev helpers */ 1034 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv); 1035 1036 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv); 1037 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv); 1038 1039 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv); 1040 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv); 1041 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv); 1042 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv); 1043 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt); 1044 1045 int mlx5e_create_ttc_table(struct mlx5e_priv *priv); 1046 void mlx5e_destroy_ttc_table(struct mlx5e_priv *priv); 1047 1048 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc, 1049 u32 underlay_qpn, u32 *tisn); 1050 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn); 1051 1052 int mlx5e_create_tises(struct mlx5e_priv *priv); 1053 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv); 1054 int mlx5e_close(struct net_device *netdev); 1055 int mlx5e_open(struct net_device *netdev); 1056 void mlx5e_update_stats_work(struct work_struct *work); 1057 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout); 1058 1059 /* ethtool helpers */ 1060 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv, 1061 struct ethtool_drvinfo *drvinfo); 1062 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, 1063 uint32_t stringset, uint8_t *data); 1064 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset); 1065 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv, 1066 struct ethtool_stats *stats, u64 *data); 1067 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv, 1068 struct ethtool_ringparam *param); 1069 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, 1070 struct ethtool_ringparam *param); 1071 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv, 1072 struct ethtool_channels *ch); 1073 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, 1074 struct ethtool_channels *ch); 1075 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv, 1076 struct ethtool_coalesce *coal); 1077 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, 1078 struct ethtool_coalesce *coal); 1079 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv, 1080 struct ethtool_ts_info *info); 1081 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv, 1082 struct ethtool_flash *flash); 1083 1084 /* mlx5e generic netdev management API */ 1085 struct net_device* 1086 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile, 1087 void *ppriv); 1088 int mlx5e_attach_netdev(struct mlx5e_priv *priv); 1089 void mlx5e_detach_netdev(struct mlx5e_priv *priv); 1090 void mlx5e_destroy_netdev(struct mlx5e_priv *priv); 1091 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev, 1092 struct mlx5e_params *params, 1093 u16 max_channels); 1094 1095 #endif /* __MLX5_EN_H__ */ 1096