1 /* 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef __MLX5_EN_H__ 33 #define __MLX5_EN_H__ 34 35 #include <linux/if_vlan.h> 36 #include <linux/etherdevice.h> 37 #include <linux/timecounter.h> 38 #include <linux/net_tstamp.h> 39 #include <linux/crash_dump.h> 40 #include <linux/mlx5/driver.h> 41 #include <linux/mlx5/qp.h> 42 #include <linux/mlx5/cq.h> 43 #include <linux/mlx5/port.h> 44 #include <linux/mlx5/vport.h> 45 #include <linux/mlx5/transobj.h> 46 #include <linux/mlx5/fs.h> 47 #include <linux/rhashtable.h> 48 #include <net/udp_tunnel.h> 49 #include <net/switchdev.h> 50 #include <net/xdp.h> 51 #include <linux/dim.h> 52 #include <linux/bits.h> 53 #include "wq.h" 54 #include "mlx5_core.h" 55 #include "en_stats.h" 56 #include "en/dcbnl.h" 57 #include "en/fs.h" 58 #include "en/qos.h" 59 #include "lib/hv_vhca.h" 60 #include "lib/clock.h" 61 #include "en/rx_res.h" 62 #include "en/selq.h" 63 64 extern const struct net_device_ops mlx5e_netdev_ops; 65 struct page_pool; 66 67 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4) 68 #define MLX5E_METADATA_ETHER_LEN 8 69 70 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) 71 72 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu)) 73 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu)) 74 75 #define MLX5E_MAX_NUM_TC 8 76 #define MLX5E_MAX_NUM_MQPRIO_CH_TC TC_QOPT_MAX_QUEUE 77 78 #define MLX5_RX_HEADROOM NET_SKB_PAD 79 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \ 80 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 81 82 #define MLX5E_RX_MAX_HEAD (256) 83 #define MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE (9) 84 #define MLX5E_SHAMPO_WQ_HEADER_PER_PAGE (PAGE_SIZE >> MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE) 85 #define MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE (64) 86 #define MLX5E_SHAMPO_WQ_RESRV_SIZE (64 * 1024) 87 #define MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE (4096) 88 89 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \ 90 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */ 91 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \ 92 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req) 93 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \ 94 MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD)) 95 96 #define MLX5_MPWRQ_LOG_WQE_SZ 18 97 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \ 98 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0) 99 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER) 100 101 #define MLX5_ALIGN_MTTS(mtts) (ALIGN(mtts, 8)) 102 #define MLX5_ALIGNED_MTTS_OCTW(mtts) ((mtts) / 2) 103 #define MLX5_MTT_OCTW(mtts) (MLX5_ALIGNED_MTTS_OCTW(MLX5_ALIGN_MTTS(mtts))) 104 /* Add another page to MLX5E_REQUIRED_WQE_MTTS as a buffer between 105 * WQEs, This page will absorb write overflow by the hardware, when 106 * receiving packets larger than MTU. These oversize packets are 107 * dropped by the driver at a later stage. 108 */ 109 #define MLX5E_REQUIRED_WQE_MTTS (MLX5_ALIGN_MTTS(MLX5_MPWRQ_PAGES_PER_WQE + 1)) 110 #define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS) 111 #define MLX5E_MAX_RQ_NUM_MTTS \ 112 (ALIGN_DOWN(U16_MAX, 4) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */ 113 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024)) 114 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW \ 115 (ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS)) 116 #define MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW \ 117 (MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW + \ 118 (MLX5_MPWRQ_LOG_WQE_SZ - MLX5E_ORDER2_MAX_PACKET_MTU)) 119 120 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM)) 121 #define MLX5E_LOG_MAX_RX_WQE_BULK \ 122 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ))) 123 124 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 125 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa 126 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd 127 128 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK) 129 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa 130 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE min_t(u8, 0xd, \ 131 MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW) 132 133 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2 134 135 #define MLX5E_DEFAULT_LRO_TIMEOUT 32 136 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4 137 138 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 139 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 140 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 141 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 142 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10 143 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 144 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 145 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 146 147 #define MLX5E_MIN_NUM_CHANNELS 0x1 148 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE / 2) 149 #define MLX5E_TX_CQ_POLL_BUDGET 128 150 #define MLX5E_TX_XSK_POLL_BUDGET 64 151 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */ 152 153 #define MLX5E_UMR_WQE_INLINE_SZ \ 154 (sizeof(struct mlx5e_umr_wqe) + \ 155 ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(struct mlx5_mtt), \ 156 MLX5_UMR_MTT_ALIGNMENT)) 157 #define MLX5E_UMR_WQEBBS \ 158 (DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_BB)) 159 160 #define MLX5E_KLM_UMR_WQE_SZ(sgl_len)\ 161 (sizeof(struct mlx5e_umr_wqe) +\ 162 (sizeof(struct mlx5_klm) * (sgl_len))) 163 164 #define MLX5E_KLM_UMR_WQEBBS(klm_entries) \ 165 (DIV_ROUND_UP(MLX5E_KLM_UMR_WQE_SZ(klm_entries), MLX5_SEND_WQE_BB)) 166 167 #define MLX5E_KLM_UMR_DS_CNT(klm_entries)\ 168 (DIV_ROUND_UP(MLX5E_KLM_UMR_WQE_SZ(klm_entries), MLX5_SEND_WQE_DS)) 169 170 #define MLX5E_KLM_MAX_ENTRIES_PER_WQE(wqe_size)\ 171 (((wqe_size) - sizeof(struct mlx5e_umr_wqe)) / sizeof(struct mlx5_klm)) 172 173 #define MLX5E_KLM_ENTRIES_PER_WQE(wqe_size)\ 174 ALIGN_DOWN(MLX5E_KLM_MAX_ENTRIES_PER_WQE(wqe_size), MLX5_UMR_KLM_ALIGNMENT) 175 176 #define MLX5E_MAX_KLM_PER_WQE(mdev) \ 177 MLX5E_KLM_ENTRIES_PER_WQE(MLX5_SEND_WQE_BB * \ 178 mlx5e_get_sw_max_sq_mpw_wqebbs(mlx5e_get_max_sq_wqebbs(mdev))) 179 180 #define MLX5E_MSG_LEVEL NETIF_MSG_LINK 181 182 #define mlx5e_dbg(mlevel, priv, format, ...) \ 183 do { \ 184 if (NETIF_MSG_##mlevel & (priv)->msglevel) \ 185 netdev_warn(priv->netdev, format, \ 186 ##__VA_ARGS__); \ 187 } while (0) 188 189 #define mlx5e_state_dereference(priv, p) \ 190 rcu_dereference_protected((p), lockdep_is_held(&(priv)->state_lock)) 191 192 enum mlx5e_rq_group { 193 MLX5E_RQ_GROUP_REGULAR, 194 MLX5E_RQ_GROUP_XSK, 195 #define MLX5E_NUM_RQ_GROUPS(g) (1 + MLX5E_RQ_GROUP_##g) 196 }; 197 198 static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev) 199 { 200 if (mlx5_lag_is_lacp_owner(mdev)) 201 return 1; 202 203 return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS); 204 } 205 206 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) 207 { 208 switch (wq_type) { 209 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 210 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, 211 wq_size / 2); 212 default: 213 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, 214 wq_size / 2); 215 } 216 } 217 218 /* Use this function to get max num channels (rxqs/txqs) only to create netdev */ 219 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) 220 { 221 return is_kdump_kernel() ? 222 MLX5E_MIN_NUM_CHANNELS : 223 min_t(int, mlx5_comp_vectors_count(mdev), MLX5E_MAX_NUM_CHANNELS); 224 } 225 226 /* The maximum WQE size can be retrieved by max_wqe_sz_sq in 227 * bytes units. Driver hardens the limitation to 1KB (16 228 * WQEBBs), unless firmware capability is stricter. 229 */ 230 static inline u16 mlx5e_get_max_sq_wqebbs(struct mlx5_core_dev *mdev) 231 { 232 return min_t(u16, MLX5_SEND_WQE_MAX_WQEBBS, 233 MLX5_CAP_GEN(mdev, max_wqe_sz_sq) / MLX5_SEND_WQE_BB); 234 } 235 236 static inline u8 mlx5e_get_sw_max_sq_mpw_wqebbs(u8 max_sq_wqebbs) 237 { 238 /* The return value will be multiplied by MLX5_SEND_WQEBB_NUM_DS. 239 * Since max_sq_wqebbs may be up to MLX5_SEND_WQE_MAX_WQEBBS == 16, 240 * see mlx5e_get_max_sq_wqebbs(), the multiplication (16 * 4 == 64) 241 * overflows the 6-bit DS field of Ctrl Segment. Use a bound lower 242 * than MLX5_SEND_WQE_MAX_WQEBBS to let a full-session WQE be 243 * cache-aligned. 244 */ 245 u8 wqebbs = min_t(u8, max_sq_wqebbs, MLX5_SEND_WQE_MAX_WQEBBS - 1); 246 247 #if L1_CACHE_BYTES >= 128 248 wqebbs = ALIGN_DOWN(wqebbs, 2); 249 #endif 250 return wqebbs; 251 } 252 253 struct mlx5e_tx_wqe { 254 struct mlx5_wqe_ctrl_seg ctrl; 255 struct mlx5_wqe_eth_seg eth; 256 struct mlx5_wqe_data_seg data[]; 257 }; 258 259 struct mlx5e_rx_wqe_ll { 260 struct mlx5_wqe_srq_next_seg next; 261 struct mlx5_wqe_data_seg data[]; 262 }; 263 264 struct mlx5e_rx_wqe_cyc { 265 struct mlx5_wqe_data_seg data[0]; 266 }; 267 268 struct mlx5e_umr_wqe { 269 struct mlx5_wqe_ctrl_seg ctrl; 270 struct mlx5_wqe_umr_ctrl_seg uctrl; 271 struct mlx5_mkey_seg mkc; 272 union { 273 DECLARE_FLEX_ARRAY(struct mlx5_mtt, inline_mtts); 274 DECLARE_FLEX_ARRAY(struct mlx5_klm, inline_klms); 275 }; 276 }; 277 278 enum mlx5e_priv_flag { 279 MLX5E_PFLAG_RX_CQE_BASED_MODER, 280 MLX5E_PFLAG_TX_CQE_BASED_MODER, 281 MLX5E_PFLAG_RX_CQE_COMPRESS, 282 MLX5E_PFLAG_RX_STRIDING_RQ, 283 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, 284 MLX5E_PFLAG_XDP_TX_MPWQE, 285 MLX5E_PFLAG_SKB_TX_MPWQE, 286 MLX5E_PFLAG_TX_PORT_TS, 287 MLX5E_NUM_PFLAGS, /* Keep last */ 288 }; 289 290 #define MLX5E_SET_PFLAG(params, pflag, enable) \ 291 do { \ 292 if (enable) \ 293 (params)->pflags |= BIT(pflag); \ 294 else \ 295 (params)->pflags &= ~(BIT(pflag)); \ 296 } while (0) 297 298 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag)))) 299 300 enum packet_merge { 301 MLX5E_PACKET_MERGE_NONE, 302 MLX5E_PACKET_MERGE_LRO, 303 MLX5E_PACKET_MERGE_SHAMPO, 304 }; 305 306 struct mlx5e_packet_merge_param { 307 enum packet_merge type; 308 u32 timeout; 309 struct { 310 u8 match_criteria_type; 311 u8 alignment_granularity; 312 } shampo; 313 }; 314 315 struct mlx5e_params { 316 u8 log_sq_size; 317 u8 rq_wq_type; 318 u8 log_rq_mtu_frames; 319 u16 num_channels; 320 struct { 321 u16 mode; 322 u8 num_tc; 323 struct netdev_tc_txq tc_to_txq[TC_MAX_QUEUE]; 324 struct { 325 u64 max_rate[TC_MAX_QUEUE]; 326 u32 hw_id[TC_MAX_QUEUE]; 327 } channel; 328 } mqprio; 329 bool rx_cqe_compress_def; 330 bool tunneled_offload_en; 331 struct dim_cq_moder rx_cq_moderation; 332 struct dim_cq_moder tx_cq_moderation; 333 struct mlx5e_packet_merge_param packet_merge; 334 u8 tx_min_inline_mode; 335 bool vlan_strip_disable; 336 bool scatter_fcs_en; 337 bool rx_dim_enabled; 338 bool tx_dim_enabled; 339 u32 pflags; 340 struct bpf_prog *xdp_prog; 341 struct mlx5e_xsk *xsk; 342 unsigned int sw_mtu; 343 int hard_mtu; 344 bool ptp_rx; 345 }; 346 347 static inline u8 mlx5e_get_dcb_num_tc(struct mlx5e_params *params) 348 { 349 return params->mqprio.mode == TC_MQPRIO_MODE_DCB ? 350 params->mqprio.num_tc : 1; 351 } 352 353 enum { 354 MLX5E_RQ_STATE_ENABLED, 355 MLX5E_RQ_STATE_RECOVERING, 356 MLX5E_RQ_STATE_AM, 357 MLX5E_RQ_STATE_NO_CSUM_COMPLETE, 358 MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */ 359 MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, /* set when mini_cqe_resp_stride_index cap is used */ 360 MLX5E_RQ_STATE_SHAMPO, /* set when SHAMPO cap is used */ 361 }; 362 363 struct mlx5e_cq { 364 /* data path - accessed per cqe */ 365 struct mlx5_cqwq wq; 366 367 /* data path - accessed per napi poll */ 368 u16 event_ctr; 369 struct napi_struct *napi; 370 struct mlx5_core_cq mcq; 371 struct mlx5e_ch_stats *ch_stats; 372 373 /* control */ 374 struct net_device *netdev; 375 struct mlx5_core_dev *mdev; 376 struct mlx5e_priv *priv; 377 struct mlx5_wq_ctrl wq_ctrl; 378 } ____cacheline_aligned_in_smp; 379 380 struct mlx5e_cq_decomp { 381 /* cqe decompression */ 382 struct mlx5_cqe64 title; 383 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; 384 u8 mini_arr_idx; 385 u16 left; 386 u16 wqe_counter; 387 } ____cacheline_aligned_in_smp; 388 389 enum mlx5e_dma_map_type { 390 MLX5E_DMA_MAP_SINGLE, 391 MLX5E_DMA_MAP_PAGE 392 }; 393 394 struct mlx5e_sq_dma { 395 dma_addr_t addr; 396 u32 size; 397 enum mlx5e_dma_map_type type; 398 }; 399 400 enum { 401 MLX5E_SQ_STATE_ENABLED, 402 MLX5E_SQ_STATE_MPWQE, 403 MLX5E_SQ_STATE_RECOVERING, 404 MLX5E_SQ_STATE_IPSEC, 405 MLX5E_SQ_STATE_AM, 406 MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, 407 MLX5E_SQ_STATE_PENDING_XSK_TX, 408 MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC, 409 MLX5E_SQ_STATE_XDP_MULTIBUF, 410 }; 411 412 struct mlx5e_tx_mpwqe { 413 /* Current MPWQE session */ 414 struct mlx5e_tx_wqe *wqe; 415 u32 bytes_count; 416 u8 ds_count; 417 u8 pkt_count; 418 u8 inline_on; 419 }; 420 421 struct mlx5e_skb_fifo { 422 struct sk_buff **fifo; 423 u16 *pc; 424 u16 *cc; 425 u16 mask; 426 }; 427 428 struct mlx5e_ptpsq; 429 430 struct mlx5e_txqsq { 431 /* data path */ 432 433 /* dirtied @completion */ 434 u16 cc; 435 u16 skb_fifo_cc; 436 u32 dma_fifo_cc; 437 struct dim dim; /* Adaptive Moderation */ 438 439 /* dirtied @xmit */ 440 u16 pc ____cacheline_aligned_in_smp; 441 u16 skb_fifo_pc; 442 u32 dma_fifo_pc; 443 struct mlx5e_tx_mpwqe mpwqe; 444 445 struct mlx5e_cq cq; 446 447 /* read only */ 448 struct mlx5_wq_cyc wq; 449 u32 dma_fifo_mask; 450 struct mlx5e_sq_stats *stats; 451 struct { 452 struct mlx5e_sq_dma *dma_fifo; 453 struct mlx5e_skb_fifo skb_fifo; 454 struct mlx5e_tx_wqe_info *wqe_info; 455 } db; 456 void __iomem *uar_map; 457 struct netdev_queue *txq; 458 u32 sqn; 459 u16 stop_room; 460 u8 max_sq_mpw_wqebbs; 461 u8 min_inline_mode; 462 struct device *pdev; 463 __be32 mkey_be; 464 unsigned long state; 465 unsigned int hw_mtu; 466 struct mlx5_clock *clock; 467 struct net_device *netdev; 468 struct mlx5_core_dev *mdev; 469 struct mlx5e_priv *priv; 470 471 /* control path */ 472 struct mlx5_wq_ctrl wq_ctrl; 473 int ch_ix; 474 int txq_ix; 475 u32 rate_limit; 476 struct work_struct recover_work; 477 struct mlx5e_ptpsq *ptpsq; 478 cqe_ts_to_ns ptp_cyc2time; 479 u16 max_sq_wqebbs; 480 } ____cacheline_aligned_in_smp; 481 482 struct mlx5e_dma_info { 483 dma_addr_t addr; 484 union { 485 struct page *page; 486 struct xdp_buff *xsk; 487 }; 488 }; 489 490 /* XDP packets can be transmitted in different ways. On completion, we need to 491 * distinguish between them to clean up things in a proper way. 492 */ 493 enum mlx5e_xdp_xmit_mode { 494 /* An xdp_frame was transmitted due to either XDP_REDIRECT from another 495 * device or XDP_TX from an XSK RQ. The frame has to be unmapped and 496 * returned. 497 */ 498 MLX5E_XDP_XMIT_MODE_FRAME, 499 500 /* The xdp_frame was created in place as a result of XDP_TX from a 501 * regular RQ. No DMA remapping happened, and the page belongs to us. 502 */ 503 MLX5E_XDP_XMIT_MODE_PAGE, 504 505 /* No xdp_frame was created at all, the transmit happened from a UMEM 506 * page. The UMEM Completion Ring producer pointer has to be increased. 507 */ 508 MLX5E_XDP_XMIT_MODE_XSK, 509 }; 510 511 struct mlx5e_xdp_info { 512 enum mlx5e_xdp_xmit_mode mode; 513 union { 514 struct { 515 struct xdp_frame *xdpf; 516 dma_addr_t dma_addr; 517 } frame; 518 struct { 519 struct mlx5e_rq *rq; 520 struct page *page; 521 } page; 522 }; 523 }; 524 525 struct mlx5e_xmit_data { 526 dma_addr_t dma_addr; 527 void *data; 528 u32 len; 529 }; 530 531 struct mlx5e_xdp_info_fifo { 532 struct mlx5e_xdp_info *xi; 533 u32 *cc; 534 u32 *pc; 535 u32 mask; 536 }; 537 538 struct mlx5e_xdpsq; 539 typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *); 540 typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *, 541 struct mlx5e_xmit_data *, 542 struct skb_shared_info *, 543 int); 544 545 struct mlx5e_xdpsq { 546 /* data path */ 547 548 /* dirtied @completion */ 549 u32 xdpi_fifo_cc; 550 u16 cc; 551 552 /* dirtied @xmit */ 553 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp; 554 u16 pc; 555 struct mlx5_wqe_ctrl_seg *doorbell_cseg; 556 struct mlx5e_tx_mpwqe mpwqe; 557 558 struct mlx5e_cq cq; 559 560 /* read only */ 561 struct xsk_buff_pool *xsk_pool; 562 struct mlx5_wq_cyc wq; 563 struct mlx5e_xdpsq_stats *stats; 564 mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check; 565 mlx5e_fp_xmit_xdp_frame xmit_xdp_frame; 566 struct { 567 struct mlx5e_xdp_wqe_info *wqe_info; 568 struct mlx5e_xdp_info_fifo xdpi_fifo; 569 } db; 570 void __iomem *uar_map; 571 u32 sqn; 572 struct device *pdev; 573 __be32 mkey_be; 574 u16 stop_room; 575 u8 max_sq_mpw_wqebbs; 576 u8 min_inline_mode; 577 unsigned long state; 578 unsigned int hw_mtu; 579 580 /* control path */ 581 struct mlx5_wq_ctrl wq_ctrl; 582 struct mlx5e_channel *channel; 583 u16 max_sq_wqebbs; 584 } ____cacheline_aligned_in_smp; 585 586 struct mlx5e_ktls_resync_resp; 587 588 struct mlx5e_icosq { 589 /* data path */ 590 u16 cc; 591 u16 pc; 592 593 struct mlx5_wqe_ctrl_seg *doorbell_cseg; 594 struct mlx5e_cq cq; 595 596 /* write@xmit, read@completion */ 597 struct { 598 struct mlx5e_icosq_wqe_info *wqe_info; 599 } db; 600 601 /* read only */ 602 struct mlx5_wq_cyc wq; 603 void __iomem *uar_map; 604 u32 sqn; 605 u16 reserved_room; 606 unsigned long state; 607 struct mlx5e_ktls_resync_resp *ktls_resync; 608 609 /* control path */ 610 struct mlx5_wq_ctrl wq_ctrl; 611 struct mlx5e_channel *channel; 612 u16 max_sq_wqebbs; 613 614 struct work_struct recover_work; 615 } ____cacheline_aligned_in_smp; 616 617 struct mlx5e_wqe_frag_info { 618 struct mlx5e_dma_info *di; 619 u32 offset; 620 bool last_in_page; 621 }; 622 623 struct mlx5e_umr_dma_info { 624 struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE]; 625 }; 626 627 struct mlx5e_mpw_info { 628 struct mlx5e_umr_dma_info umr; 629 u16 consumed_strides; 630 DECLARE_BITMAP(xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE); 631 }; 632 633 #define MLX5E_MAX_RX_FRAGS 4 634 635 /* a single cache unit is capable to serve one napi call (for non-striding rq) 636 * or a MPWQE (for striding rq). 637 */ 638 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \ 639 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT) 640 #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT)) 641 struct mlx5e_page_cache { 642 u32 head; 643 u32 tail; 644 struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE]; 645 }; 646 647 struct mlx5e_rq; 648 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*); 649 typedef struct sk_buff * 650 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, 651 u16 cqe_bcnt, u32 head_offset, u32 page_idx); 652 typedef struct sk_buff * 653 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5e_wqe_frag_info *wi, 654 u32 cqe_bcnt); 655 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq); 656 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16); 657 typedef void (*mlx5e_fp_shampo_dealloc_hd)(struct mlx5e_rq*, u16, u16, bool); 658 659 int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk); 660 void mlx5e_rq_set_trap_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params); 661 662 enum mlx5e_rq_flag { 663 MLX5E_RQ_FLAG_XDP_XMIT, 664 MLX5E_RQ_FLAG_XDP_REDIRECT, 665 }; 666 667 struct mlx5e_rq_frag_info { 668 int frag_size; 669 int frag_stride; 670 }; 671 672 struct mlx5e_rq_frags_info { 673 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS]; 674 u8 num_frags; 675 u8 log_num_frags; 676 u8 wqe_bulk; 677 }; 678 679 struct mlx5e_shampo_hd { 680 u32 mkey; 681 struct mlx5e_dma_info *info; 682 struct page *last_page; 683 u16 hd_per_wq; 684 u16 hd_per_wqe; 685 unsigned long *bitmap; 686 u16 pi; 687 u16 ci; 688 __be32 key; 689 u64 last_addr; 690 }; 691 692 struct mlx5e_hw_gro_data { 693 struct sk_buff *skb; 694 struct flow_keys fk; 695 int second_ip_id; 696 }; 697 698 struct mlx5e_rq { 699 /* data path */ 700 union { 701 struct { 702 struct mlx5_wq_cyc wq; 703 struct mlx5e_wqe_frag_info *frags; 704 struct mlx5e_dma_info *di; 705 struct mlx5e_rq_frags_info info; 706 mlx5e_fp_skb_from_cqe skb_from_cqe; 707 } wqe; 708 struct { 709 struct mlx5_wq_ll wq; 710 struct mlx5e_umr_wqe umr_wqe; 711 struct mlx5e_mpw_info *info; 712 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq; 713 u16 num_strides; 714 u16 actual_wq_head; 715 u8 log_stride_sz; 716 u8 umr_in_progress; 717 u8 umr_last_bulk; 718 u8 umr_completed; 719 u8 min_wqe_bulk; 720 struct mlx5e_shampo_hd *shampo; 721 } mpwqe; 722 }; 723 struct { 724 u16 headroom; 725 u32 frame0_sz; 726 u8 map_dir; /* dma map direction */ 727 } buff; 728 729 struct device *pdev; 730 struct net_device *netdev; 731 struct mlx5e_rq_stats *stats; 732 struct mlx5e_cq cq; 733 struct mlx5e_cq_decomp cqd; 734 struct mlx5e_page_cache page_cache; 735 struct hwtstamp_config *tstamp; 736 struct mlx5_clock *clock; 737 struct mlx5e_icosq *icosq; 738 struct mlx5e_priv *priv; 739 740 struct mlx5e_hw_gro_data *hw_gro_data; 741 742 mlx5e_fp_handle_rx_cqe handle_rx_cqe; 743 mlx5e_fp_post_rx_wqes post_wqes; 744 mlx5e_fp_dealloc_wqe dealloc_wqe; 745 746 unsigned long state; 747 int ix; 748 unsigned int hw_mtu; 749 750 struct dim dim; /* Dynamic Interrupt Moderation */ 751 752 /* XDP */ 753 struct bpf_prog __rcu *xdp_prog; 754 struct mlx5e_xdpsq *xdpsq; 755 DECLARE_BITMAP(flags, 8); 756 struct page_pool *page_pool; 757 758 /* AF_XDP zero-copy */ 759 struct xsk_buff_pool *xsk_pool; 760 761 struct work_struct recover_work; 762 763 /* control */ 764 struct mlx5_wq_ctrl wq_ctrl; 765 __be32 mkey_be; 766 u8 wq_type; 767 u32 rqn; 768 struct mlx5_core_dev *mdev; 769 struct mlx5e_channel *channel; 770 u32 umr_mkey; 771 struct mlx5e_dma_info wqe_overflow; 772 773 /* XDP read-mostly */ 774 struct xdp_rxq_info xdp_rxq; 775 cqe_ts_to_ns ptp_cyc2time; 776 } ____cacheline_aligned_in_smp; 777 778 enum mlx5e_channel_state { 779 MLX5E_CHANNEL_STATE_XSK, 780 MLX5E_CHANNEL_NUM_STATES 781 }; 782 783 struct mlx5e_channel { 784 /* data path */ 785 struct mlx5e_rq rq; 786 struct mlx5e_xdpsq rq_xdpsq; 787 struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC]; 788 struct mlx5e_icosq icosq; /* internal control operations */ 789 struct mlx5e_txqsq __rcu * __rcu *qos_sqs; 790 bool xdp; 791 struct napi_struct napi; 792 struct device *pdev; 793 struct net_device *netdev; 794 __be32 mkey_be; 795 u16 qos_sqs_size; 796 u8 num_tc; 797 u8 lag_port; 798 799 /* XDP_REDIRECT */ 800 struct mlx5e_xdpsq xdpsq; 801 802 /* AF_XDP zero-copy */ 803 struct mlx5e_rq xskrq; 804 struct mlx5e_xdpsq xsksq; 805 806 /* Async ICOSQ */ 807 struct mlx5e_icosq async_icosq; 808 /* async_icosq can be accessed from any CPU - the spinlock protects it. */ 809 spinlock_t async_icosq_lock; 810 811 /* data path - accessed per napi poll */ 812 const struct cpumask *aff_mask; 813 struct mlx5e_ch_stats *stats; 814 815 /* control */ 816 struct mlx5e_priv *priv; 817 struct mlx5_core_dev *mdev; 818 struct hwtstamp_config *tstamp; 819 DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES); 820 int ix; 821 int cpu; 822 /* Sync between icosq recovery and XSK enable/disable. */ 823 struct mutex icosq_recovery_lock; 824 }; 825 826 struct mlx5e_ptp; 827 828 struct mlx5e_channels { 829 struct mlx5e_channel **c; 830 struct mlx5e_ptp *ptp; 831 unsigned int num; 832 struct mlx5e_params params; 833 }; 834 835 struct mlx5e_channel_stats { 836 struct mlx5e_ch_stats ch; 837 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC]; 838 struct mlx5e_rq_stats rq; 839 struct mlx5e_rq_stats xskrq; 840 struct mlx5e_xdpsq_stats rq_xdpsq; 841 struct mlx5e_xdpsq_stats xdpsq; 842 struct mlx5e_xdpsq_stats xsksq; 843 } ____cacheline_aligned_in_smp; 844 845 struct mlx5e_ptp_stats { 846 struct mlx5e_ch_stats ch; 847 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC]; 848 struct mlx5e_ptp_cq_stats cq[MLX5E_MAX_NUM_TC]; 849 struct mlx5e_rq_stats rq; 850 } ____cacheline_aligned_in_smp; 851 852 enum { 853 MLX5E_STATE_OPENED, 854 MLX5E_STATE_DESTROYING, 855 MLX5E_STATE_XDP_TX_ENABLED, 856 MLX5E_STATE_XDP_ACTIVE, 857 }; 858 859 enum { 860 MLX5E_TC_PRIO = 0, 861 MLX5E_NIC_PRIO 862 }; 863 864 struct mlx5e_modify_sq_param { 865 int curr_state; 866 int next_state; 867 int rl_update; 868 int rl_index; 869 bool qos_update; 870 u16 qos_queue_group_id; 871 }; 872 873 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE) 874 struct mlx5e_hv_vhca_stats_agent { 875 struct mlx5_hv_vhca_agent *agent; 876 struct delayed_work work; 877 u16 delay; 878 void *buf; 879 }; 880 #endif 881 882 struct mlx5e_xsk { 883 /* XSK buffer pools are stored separately from channels, 884 * because we don't want to lose them when channels are 885 * recreated. The kernel also stores buffer pool, but it doesn't 886 * distinguish between zero-copy and non-zero-copy UMEMs, so 887 * rely on our mechanism. 888 */ 889 struct xsk_buff_pool **pools; 890 u16 refcnt; 891 bool ever_used; 892 }; 893 894 /* Temporary storage for variables that are allocated when struct mlx5e_priv is 895 * initialized, and used where we can't allocate them because that functions 896 * must not fail. Use with care and make sure the same variable is not used 897 * simultaneously by multiple users. 898 */ 899 struct mlx5e_scratchpad { 900 cpumask_var_t cpumask; 901 }; 902 903 struct mlx5e_trap; 904 struct mlx5e_htb; 905 906 struct mlx5e_priv { 907 /* priv data path fields - start */ 908 struct mlx5e_selq selq; 909 struct mlx5e_txqsq **txq2sq; 910 #ifdef CONFIG_MLX5_CORE_EN_DCB 911 struct mlx5e_dcbx_dp dcbx_dp; 912 #endif 913 /* priv data path fields - end */ 914 915 u32 msglevel; 916 unsigned long state; 917 struct mutex state_lock; /* Protects Interface state */ 918 struct mlx5e_rq drop_rq; 919 920 struct mlx5e_channels channels; 921 u32 tisn[MLX5_MAX_PORTS][MLX5E_MAX_NUM_TC]; 922 struct mlx5e_rx_res *rx_res; 923 u32 *tx_rates; 924 925 struct mlx5e_flow_steering *fs; 926 927 struct workqueue_struct *wq; 928 struct work_struct update_carrier_work; 929 struct work_struct set_rx_mode_work; 930 struct work_struct tx_timeout_work; 931 struct work_struct update_stats_work; 932 struct work_struct monitor_counters_work; 933 struct mlx5_nb monitor_counters_nb; 934 935 struct mlx5_core_dev *mdev; 936 struct net_device *netdev; 937 struct mlx5e_trap *en_trap; 938 struct mlx5e_stats stats; 939 struct mlx5e_channel_stats **channel_stats; 940 struct mlx5e_channel_stats trap_stats; 941 struct mlx5e_ptp_stats ptp_stats; 942 struct mlx5e_sq_stats **htb_qos_sq_stats; 943 u16 htb_max_qos_sqs; 944 u16 stats_nch; 945 u16 max_nch; 946 u8 max_opened_tc; 947 bool tx_ptp_opened; 948 bool rx_ptp_opened; 949 struct hwtstamp_config tstamp; 950 u16 q_counter; 951 u16 drop_rq_q_counter; 952 struct notifier_block events_nb; 953 struct notifier_block blocking_events_nb; 954 955 struct udp_tunnel_nic_info nic_info; 956 #ifdef CONFIG_MLX5_CORE_EN_DCB 957 struct mlx5e_dcbx dcbx; 958 #endif 959 960 const struct mlx5e_profile *profile; 961 void *ppriv; 962 #ifdef CONFIG_MLX5_EN_IPSEC 963 struct mlx5e_ipsec *ipsec; 964 #endif 965 #ifdef CONFIG_MLX5_EN_TLS 966 struct mlx5e_tls *tls; 967 #endif 968 struct devlink_health_reporter *tx_reporter; 969 struct devlink_health_reporter *rx_reporter; 970 struct mlx5e_xsk xsk; 971 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE) 972 struct mlx5e_hv_vhca_stats_agent stats_agent; 973 #endif 974 struct mlx5e_scratchpad scratchpad; 975 struct mlx5e_htb *htb; 976 struct mlx5e_mqprio_rl *mqprio_rl; 977 }; 978 979 struct mlx5e_rx_handlers { 980 mlx5e_fp_handle_rx_cqe handle_rx_cqe; 981 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe; 982 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe_shampo; 983 }; 984 985 extern const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic; 986 987 enum mlx5e_profile_feature { 988 MLX5E_PROFILE_FEATURE_PTP_RX, 989 MLX5E_PROFILE_FEATURE_PTP_TX, 990 MLX5E_PROFILE_FEATURE_QOS_HTB, 991 MLX5E_PROFILE_FEATURE_FS_VLAN, 992 MLX5E_PROFILE_FEATURE_FS_TC, 993 }; 994 995 struct mlx5e_profile { 996 int (*init)(struct mlx5_core_dev *mdev, 997 struct net_device *netdev); 998 void (*cleanup)(struct mlx5e_priv *priv); 999 int (*init_rx)(struct mlx5e_priv *priv); 1000 void (*cleanup_rx)(struct mlx5e_priv *priv); 1001 int (*init_tx)(struct mlx5e_priv *priv); 1002 void (*cleanup_tx)(struct mlx5e_priv *priv); 1003 void (*enable)(struct mlx5e_priv *priv); 1004 void (*disable)(struct mlx5e_priv *priv); 1005 int (*update_rx)(struct mlx5e_priv *priv); 1006 void (*update_stats)(struct mlx5e_priv *priv); 1007 void (*update_carrier)(struct mlx5e_priv *priv); 1008 int (*max_nch_limit)(struct mlx5_core_dev *mdev); 1009 unsigned int (*stats_grps_num)(struct mlx5e_priv *priv); 1010 mlx5e_stats_grp_t *stats_grps; 1011 const struct mlx5e_rx_handlers *rx_handlers; 1012 int max_tc; 1013 u8 rq_groups; 1014 u32 features; 1015 }; 1016 1017 #define mlx5e_profile_feature_cap(profile, feature) \ 1018 ((profile)->features & BIT(MLX5E_PROFILE_FEATURE_##feature)) 1019 1020 void mlx5e_build_ptys2ethtool_map(void); 1021 1022 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev); 1023 1024 void mlx5e_shampo_dealloc_hd(struct mlx5e_rq *rq, u16 len, u16 start, bool close); 1025 void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats); 1026 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s); 1027 1028 int mlx5e_self_test_num(struct mlx5e_priv *priv); 1029 int mlx5e_self_test_fill_strings(struct mlx5e_priv *priv, u8 *data); 1030 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest, 1031 u64 *buf); 1032 void mlx5e_set_rx_mode_work(struct work_struct *work); 1033 1034 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr); 1035 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr); 1036 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val, bool rx_filter); 1037 1038 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, 1039 u16 vid); 1040 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, 1041 u16 vid); 1042 void mlx5e_timestamp_init(struct mlx5e_priv *priv); 1043 1044 struct mlx5e_xsk_param; 1045 1046 struct mlx5e_rq_param; 1047 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param, 1048 struct mlx5e_xsk_param *xsk, int node, 1049 struct mlx5e_rq *rq); 1050 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time); 1051 void mlx5e_close_rq(struct mlx5e_rq *rq); 1052 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param); 1053 void mlx5e_destroy_rq(struct mlx5e_rq *rq); 1054 1055 struct mlx5e_sq_param; 1056 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params, 1057 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool, 1058 struct mlx5e_xdpsq *sq, bool is_redirect); 1059 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq); 1060 1061 struct mlx5e_create_cq_param { 1062 struct napi_struct *napi; 1063 struct mlx5e_ch_stats *ch_stats; 1064 int node; 1065 int ix; 1066 }; 1067 1068 struct mlx5e_cq_param; 1069 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder, 1070 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp, 1071 struct mlx5e_cq *cq); 1072 void mlx5e_close_cq(struct mlx5e_cq *cq); 1073 1074 int mlx5e_open_locked(struct net_device *netdev); 1075 int mlx5e_close_locked(struct net_device *netdev); 1076 1077 void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c); 1078 void mlx5e_trigger_napi_sched(struct napi_struct *napi); 1079 1080 int mlx5e_open_channels(struct mlx5e_priv *priv, 1081 struct mlx5e_channels *chs); 1082 void mlx5e_close_channels(struct mlx5e_channels *chs); 1083 1084 /* Function pointer to be used to modify HW or kernel settings while 1085 * switching channels 1086 */ 1087 typedef int (*mlx5e_fp_preactivate)(struct mlx5e_priv *priv, void *context); 1088 #define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \ 1089 int fn##_ctx(struct mlx5e_priv *priv, void *context) \ 1090 { \ 1091 return fn(priv); \ 1092 } 1093 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv); 1094 int mlx5e_safe_switch_params(struct mlx5e_priv *priv, 1095 struct mlx5e_params *new_params, 1096 mlx5e_fp_preactivate preactivate, 1097 void *context, bool reset); 1098 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv); 1099 int mlx5e_num_channels_changed_ctx(struct mlx5e_priv *priv, void *context); 1100 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv); 1101 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv); 1102 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx); 1103 1104 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state); 1105 void mlx5e_activate_rq(struct mlx5e_rq *rq); 1106 void mlx5e_deactivate_rq(struct mlx5e_rq *rq); 1107 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq); 1108 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq); 1109 1110 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn, 1111 struct mlx5e_modify_sq_param *p); 1112 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix, 1113 struct mlx5e_params *params, struct mlx5e_sq_param *param, 1114 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id, 1115 struct mlx5e_sq_stats *sq_stats); 1116 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq); 1117 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq); 1118 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq); 1119 void mlx5e_tx_disable_queue(struct netdev_queue *txq); 1120 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa); 1121 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq); 1122 struct mlx5e_create_sq_param; 1123 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev, 1124 struct mlx5e_sq_param *param, 1125 struct mlx5e_create_sq_param *csp, 1126 u16 qos_queue_group_id, 1127 u32 *sqn); 1128 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work); 1129 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq); 1130 1131 static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev) 1132 { 1133 return MLX5_CAP_ETH(mdev, swp) && 1134 MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso); 1135 } 1136 1137 extern const struct ethtool_ops mlx5e_ethtool_ops; 1138 1139 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev); 1140 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); 1141 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb, 1142 bool enable_mc_lb); 1143 void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc); 1144 1145 /* common netdev helpers */ 1146 void mlx5e_create_q_counters(struct mlx5e_priv *priv); 1147 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv); 1148 int mlx5e_open_drop_rq(struct mlx5e_priv *priv, 1149 struct mlx5e_rq *drop_rq); 1150 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq); 1151 int mlx5e_init_di_list(struct mlx5e_rq *rq, int wq_sz, int node); 1152 void mlx5e_free_di_list(struct mlx5e_rq *rq); 1153 1154 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn); 1155 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn); 1156 1157 int mlx5e_create_tises(struct mlx5e_priv *priv); 1158 void mlx5e_destroy_tises(struct mlx5e_priv *priv); 1159 int mlx5e_update_nic_rx(struct mlx5e_priv *priv); 1160 void mlx5e_update_carrier(struct mlx5e_priv *priv); 1161 int mlx5e_close(struct net_device *netdev); 1162 int mlx5e_open(struct net_device *netdev); 1163 1164 void mlx5e_queue_update_stats(struct mlx5e_priv *priv); 1165 1166 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv); 1167 int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv *priv, void *context); 1168 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu, 1169 mlx5e_fp_preactivate preactivate); 1170 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv); 1171 1172 /* ethtool helpers */ 1173 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv, 1174 struct ethtool_drvinfo *drvinfo); 1175 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, 1176 uint32_t stringset, uint8_t *data); 1177 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset); 1178 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv, 1179 struct ethtool_stats *stats, u64 *data); 1180 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv, 1181 struct ethtool_ringparam *param, 1182 struct kernel_ethtool_ringparam *kernel_param); 1183 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, 1184 struct ethtool_ringparam *param); 1185 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv, 1186 struct ethtool_channels *ch); 1187 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, 1188 struct ethtool_channels *ch); 1189 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv, 1190 struct ethtool_coalesce *coal, 1191 struct kernel_ethtool_coalesce *kernel_coal); 1192 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, 1193 struct ethtool_coalesce *coal, 1194 struct kernel_ethtool_coalesce *kernel_coal, 1195 struct netlink_ext_ack *extack); 1196 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv, 1197 struct ethtool_link_ksettings *link_ksettings); 1198 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv, 1199 const struct ethtool_link_ksettings *link_ksettings); 1200 int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, u8 *hfunc); 1201 int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key, 1202 const u8 hfunc); 1203 int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, 1204 u32 *rule_locs); 1205 int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd); 1206 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv); 1207 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv); 1208 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv, 1209 struct ethtool_ts_info *info); 1210 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv, 1211 struct ethtool_flash *flash); 1212 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv, 1213 struct ethtool_pauseparam *pauseparam); 1214 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv, 1215 struct ethtool_pauseparam *pauseparam); 1216 1217 /* mlx5e generic netdev management API */ 1218 static inline bool 1219 mlx5e_tx_mpwqe_supported(struct mlx5_core_dev *mdev) 1220 { 1221 return !is_kdump_kernel() && 1222 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe); 1223 } 1224 1225 int mlx5e_get_pf_num_tirs(struct mlx5_core_dev *mdev); 1226 int mlx5e_priv_init(struct mlx5e_priv *priv, 1227 const struct mlx5e_profile *profile, 1228 struct net_device *netdev, 1229 struct mlx5_core_dev *mdev); 1230 void mlx5e_priv_cleanup(struct mlx5e_priv *priv); 1231 struct net_device * 1232 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile); 1233 int mlx5e_attach_netdev(struct mlx5e_priv *priv); 1234 void mlx5e_detach_netdev(struct mlx5e_priv *priv); 1235 void mlx5e_destroy_netdev(struct mlx5e_priv *priv); 1236 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv, 1237 const struct mlx5e_profile *new_profile, void *new_ppriv); 1238 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv); 1239 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv); 1240 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu); 1241 void mlx5e_rx_dim_work(struct work_struct *work); 1242 void mlx5e_tx_dim_work(struct work_struct *work); 1243 1244 netdev_features_t mlx5e_features_check(struct sk_buff *skb, 1245 struct net_device *netdev, 1246 netdev_features_t features); 1247 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features); 1248 #ifdef CONFIG_MLX5_ESWITCH 1249 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac); 1250 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate); 1251 int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi); 1252 int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats); 1253 #endif 1254 #endif /* __MLX5_EN_H__ */ 1255