1 /* 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef __MLX5_EN_H__ 33 #define __MLX5_EN_H__ 34 35 #include <linux/if_vlan.h> 36 #include <linux/etherdevice.h> 37 #include <linux/timecounter.h> 38 #include <linux/net_tstamp.h> 39 #include <linux/crash_dump.h> 40 #include <linux/mlx5/driver.h> 41 #include <linux/mlx5/qp.h> 42 #include <linux/mlx5/cq.h> 43 #include <linux/mlx5/port.h> 44 #include <linux/mlx5/vport.h> 45 #include <linux/mlx5/transobj.h> 46 #include <linux/mlx5/fs.h> 47 #include <linux/rhashtable.h> 48 #include <net/udp_tunnel.h> 49 #include <net/switchdev.h> 50 #include <net/xdp.h> 51 #include <linux/dim.h> 52 #include <linux/bits.h> 53 #include "wq.h" 54 #include "mlx5_core.h" 55 #include "en_stats.h" 56 #include "en/dcbnl.h" 57 #include "en/fs.h" 58 #include "en/qos.h" 59 #include "lib/hv_vhca.h" 60 #include "lib/clock.h" 61 #include "en/rx_res.h" 62 #include "en/selq.h" 63 64 extern const struct net_device_ops mlx5e_netdev_ops; 65 struct page_pool; 66 67 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4) 68 #define MLX5E_METADATA_ETHER_LEN 8 69 70 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) 71 72 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu)) 73 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu)) 74 75 #define MLX5E_MAX_NUM_TC 8 76 #define MLX5E_MAX_NUM_MQPRIO_CH_TC TC_QOPT_MAX_QUEUE 77 78 #define MLX5_RX_HEADROOM NET_SKB_PAD 79 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \ 80 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 81 82 #define MLX5E_RX_MAX_HEAD (256) 83 #define MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE (9) 84 #define MLX5E_SHAMPO_WQ_HEADER_PER_PAGE (PAGE_SIZE >> MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE) 85 #define MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE (64) 86 #define MLX5E_SHAMPO_WQ_RESRV_SIZE (64 * 1024) 87 #define MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE (4096) 88 89 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \ 90 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */ 91 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \ 92 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req) 93 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \ 94 MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD)) 95 96 #define MLX5_MPWRQ_MAX_LOG_WQE_SZ 18 97 98 /* Keep in sync with mlx5e_mpwrq_log_wqe_sz. 99 * These are theoretical maximums, which can be further restricted by 100 * capabilities. These values are used for static resource allocations and 101 * sanity checks. 102 * MLX5_SEND_WQE_MAX_SIZE is a bit bigger than the maximum cacheline-aligned WQE 103 * size actually used at runtime, but it's not a problem when calculating static 104 * array sizes. 105 */ 106 #define MLX5_UMR_MAX_FLEX_SPACE \ 107 (ALIGN_DOWN(MLX5_SEND_WQE_MAX_SIZE - sizeof(struct mlx5e_umr_wqe), \ 108 MLX5_UMR_FLEX_ALIGNMENT)) 109 #define MLX5_MPWRQ_MAX_PAGES_PER_WQE \ 110 rounddown_pow_of_two(MLX5_UMR_MAX_FLEX_SPACE / sizeof(struct mlx5_mtt)) 111 112 #define MLX5E_MAX_RQ_NUM_MTTS \ 113 (ALIGN_DOWN(U16_MAX, 4) * 2) /* Fits into u16 and aligned by WQEBB. */ 114 #define MLX5E_MAX_RQ_NUM_KSMS (U16_MAX - 1) /* So that num_ksms fits into u16. */ 115 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024)) 116 117 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM)) 118 #define MLX5E_LOG_MAX_RX_WQE_BULK \ 119 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ))) 120 121 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 122 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa 123 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd 124 125 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK) 126 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa 127 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd 128 129 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2 130 131 #define MLX5E_DEFAULT_LRO_TIMEOUT 32 132 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4 133 134 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 135 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 136 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 137 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 138 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10 139 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 140 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 141 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 142 143 #define MLX5E_MIN_NUM_CHANNELS 0x1 144 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE / 2) 145 #define MLX5E_TX_CQ_POLL_BUDGET 128 146 #define MLX5E_TX_XSK_POLL_BUDGET 64 147 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */ 148 149 #define MLX5E_KLM_UMR_WQE_SZ(sgl_len)\ 150 (sizeof(struct mlx5e_umr_wqe) +\ 151 (sizeof(struct mlx5_klm) * (sgl_len))) 152 153 #define MLX5E_KLM_UMR_WQEBBS(klm_entries) \ 154 (DIV_ROUND_UP(MLX5E_KLM_UMR_WQE_SZ(klm_entries), MLX5_SEND_WQE_BB)) 155 156 #define MLX5E_KLM_UMR_DS_CNT(klm_entries)\ 157 (DIV_ROUND_UP(MLX5E_KLM_UMR_WQE_SZ(klm_entries), MLX5_SEND_WQE_DS)) 158 159 #define MLX5E_KLM_MAX_ENTRIES_PER_WQE(wqe_size)\ 160 (((wqe_size) - sizeof(struct mlx5e_umr_wqe)) / sizeof(struct mlx5_klm)) 161 162 #define MLX5E_KLM_ENTRIES_PER_WQE(wqe_size)\ 163 ALIGN_DOWN(MLX5E_KLM_MAX_ENTRIES_PER_WQE(wqe_size), MLX5_UMR_KLM_NUM_ENTRIES_ALIGNMENT) 164 165 #define MLX5E_MAX_KLM_PER_WQE(mdev) \ 166 MLX5E_KLM_ENTRIES_PER_WQE(MLX5_SEND_WQE_BB * mlx5e_get_max_sq_aligned_wqebbs(mdev)) 167 168 #define MLX5E_MSG_LEVEL NETIF_MSG_LINK 169 170 #define mlx5e_dbg(mlevel, priv, format, ...) \ 171 do { \ 172 if (NETIF_MSG_##mlevel & (priv)->msglevel) \ 173 netdev_warn(priv->netdev, format, \ 174 ##__VA_ARGS__); \ 175 } while (0) 176 177 #define mlx5e_state_dereference(priv, p) \ 178 rcu_dereference_protected((p), lockdep_is_held(&(priv)->state_lock)) 179 180 static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev) 181 { 182 if (mlx5_lag_is_lacp_owner(mdev)) 183 return 1; 184 185 return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS); 186 } 187 188 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) 189 { 190 switch (wq_type) { 191 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: 192 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, 193 wq_size / 2); 194 default: 195 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, 196 wq_size / 2); 197 } 198 } 199 200 /* Use this function to get max num channels (rxqs/txqs) only to create netdev */ 201 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) 202 { 203 return is_kdump_kernel() ? 204 MLX5E_MIN_NUM_CHANNELS : 205 min_t(int, mlx5_comp_vectors_count(mdev), MLX5E_MAX_NUM_CHANNELS); 206 } 207 208 /* The maximum WQE size can be retrieved by max_wqe_sz_sq in 209 * bytes units. Driver hardens the limitation to 1KB (16 210 * WQEBBs), unless firmware capability is stricter. 211 */ 212 static inline u8 mlx5e_get_max_sq_wqebbs(struct mlx5_core_dev *mdev) 213 { 214 BUILD_BUG_ON(MLX5_SEND_WQE_MAX_WQEBBS > U8_MAX); 215 216 return (u8)min_t(u16, MLX5_SEND_WQE_MAX_WQEBBS, 217 MLX5_CAP_GEN(mdev, max_wqe_sz_sq) / MLX5_SEND_WQE_BB); 218 } 219 220 static inline u8 mlx5e_get_max_sq_aligned_wqebbs(struct mlx5_core_dev *mdev) 221 { 222 /* The return value will be multiplied by MLX5_SEND_WQEBB_NUM_DS. 223 * Since max_sq_wqebbs may be up to MLX5_SEND_WQE_MAX_WQEBBS == 16, 224 * see mlx5e_get_max_sq_wqebbs(), the multiplication (16 * 4 == 64) 225 * overflows the 6-bit DS field of Ctrl Segment. Use a bound lower 226 * than MLX5_SEND_WQE_MAX_WQEBBS to let a full-session WQE be 227 * cache-aligned. 228 */ 229 u8 wqebbs = mlx5e_get_max_sq_wqebbs(mdev); 230 231 wqebbs = min_t(u8, wqebbs, MLX5_SEND_WQE_MAX_WQEBBS - 1); 232 #if L1_CACHE_BYTES >= 128 233 wqebbs = ALIGN_DOWN(wqebbs, 2); 234 #endif 235 return wqebbs; 236 } 237 238 struct mlx5e_tx_wqe { 239 struct mlx5_wqe_ctrl_seg ctrl; 240 struct mlx5_wqe_eth_seg eth; 241 struct mlx5_wqe_data_seg data[]; 242 }; 243 244 struct mlx5e_rx_wqe_ll { 245 struct mlx5_wqe_srq_next_seg next; 246 struct mlx5_wqe_data_seg data[]; 247 }; 248 249 struct mlx5e_rx_wqe_cyc { 250 DECLARE_FLEX_ARRAY(struct mlx5_wqe_data_seg, data); 251 }; 252 253 struct mlx5e_umr_wqe { 254 struct mlx5_wqe_ctrl_seg ctrl; 255 struct mlx5_wqe_umr_ctrl_seg uctrl; 256 struct mlx5_mkey_seg mkc; 257 union { 258 DECLARE_FLEX_ARRAY(struct mlx5_mtt, inline_mtts); 259 DECLARE_FLEX_ARRAY(struct mlx5_klm, inline_klms); 260 DECLARE_FLEX_ARRAY(struct mlx5_ksm, inline_ksms); 261 }; 262 }; 263 264 enum mlx5e_priv_flag { 265 MLX5E_PFLAG_RX_CQE_BASED_MODER, 266 MLX5E_PFLAG_TX_CQE_BASED_MODER, 267 MLX5E_PFLAG_RX_CQE_COMPRESS, 268 MLX5E_PFLAG_RX_STRIDING_RQ, 269 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, 270 MLX5E_PFLAG_XDP_TX_MPWQE, 271 MLX5E_PFLAG_SKB_TX_MPWQE, 272 MLX5E_PFLAG_TX_PORT_TS, 273 MLX5E_NUM_PFLAGS, /* Keep last */ 274 }; 275 276 #define MLX5E_SET_PFLAG(params, pflag, enable) \ 277 do { \ 278 if (enable) \ 279 (params)->pflags |= BIT(pflag); \ 280 else \ 281 (params)->pflags &= ~(BIT(pflag)); \ 282 } while (0) 283 284 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag)))) 285 286 enum packet_merge { 287 MLX5E_PACKET_MERGE_NONE, 288 MLX5E_PACKET_MERGE_LRO, 289 MLX5E_PACKET_MERGE_SHAMPO, 290 }; 291 292 struct mlx5e_packet_merge_param { 293 enum packet_merge type; 294 u32 timeout; 295 struct { 296 u8 match_criteria_type; 297 u8 alignment_granularity; 298 } shampo; 299 }; 300 301 struct mlx5e_params { 302 u8 log_sq_size; 303 u8 rq_wq_type; 304 u8 log_rq_mtu_frames; 305 u16 num_channels; 306 struct { 307 u16 mode; 308 u8 num_tc; 309 struct netdev_tc_txq tc_to_txq[TC_MAX_QUEUE]; 310 struct { 311 u64 max_rate[TC_MAX_QUEUE]; 312 u32 hw_id[TC_MAX_QUEUE]; 313 } channel; 314 } mqprio; 315 bool rx_cqe_compress_def; 316 struct dim_cq_moder rx_cq_moderation; 317 struct dim_cq_moder tx_cq_moderation; 318 struct mlx5e_packet_merge_param packet_merge; 319 u8 tx_min_inline_mode; 320 bool vlan_strip_disable; 321 bool scatter_fcs_en; 322 bool rx_dim_enabled; 323 bool tx_dim_enabled; 324 u32 pflags; 325 struct bpf_prog *xdp_prog; 326 struct mlx5e_xsk *xsk; 327 unsigned int sw_mtu; 328 int hard_mtu; 329 bool ptp_rx; 330 }; 331 332 static inline u8 mlx5e_get_dcb_num_tc(struct mlx5e_params *params) 333 { 334 return params->mqprio.mode == TC_MQPRIO_MODE_DCB ? 335 params->mqprio.num_tc : 1; 336 } 337 338 /* Keep this enum consistent with the corresponding strings array 339 * declared in en/reporter_rx.c 340 */ 341 enum { 342 MLX5E_RQ_STATE_ENABLED = 0, 343 MLX5E_RQ_STATE_RECOVERING, 344 MLX5E_RQ_STATE_DIM, 345 MLX5E_RQ_STATE_NO_CSUM_COMPLETE, 346 MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */ 347 MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, /* set when mini_cqe_resp_stride_index cap is used */ 348 MLX5E_RQ_STATE_SHAMPO, /* set when SHAMPO cap is used */ 349 MLX5E_RQ_STATE_MINI_CQE_ENHANCED, /* set when enhanced mini_cqe_cap is used */ 350 MLX5E_RQ_STATE_XSK, /* set to indicate an xsk rq */ 351 MLX5E_NUM_RQ_STATES, /* Must be kept last */ 352 }; 353 354 struct mlx5e_cq { 355 /* data path - accessed per cqe */ 356 struct mlx5_cqwq wq; 357 358 /* data path - accessed per napi poll */ 359 u16 event_ctr; 360 struct napi_struct *napi; 361 struct mlx5_core_cq mcq; 362 struct mlx5e_ch_stats *ch_stats; 363 364 /* control */ 365 struct net_device *netdev; 366 struct mlx5_core_dev *mdev; 367 struct mlx5e_priv *priv; 368 struct mlx5_wq_ctrl wq_ctrl; 369 } ____cacheline_aligned_in_smp; 370 371 struct mlx5e_cq_decomp { 372 /* cqe decompression */ 373 struct mlx5_cqe64 title; 374 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; 375 u8 mini_arr_idx; 376 u16 left; 377 u16 wqe_counter; 378 bool last_cqe_title; 379 } ____cacheline_aligned_in_smp; 380 381 enum mlx5e_dma_map_type { 382 MLX5E_DMA_MAP_SINGLE, 383 MLX5E_DMA_MAP_PAGE 384 }; 385 386 struct mlx5e_sq_dma { 387 dma_addr_t addr; 388 u32 size; 389 enum mlx5e_dma_map_type type; 390 }; 391 392 /* Keep this enum consistent with with the corresponding strings array 393 * declared in en/reporter_tx.c 394 */ 395 enum { 396 MLX5E_SQ_STATE_ENABLED = 0, 397 MLX5E_SQ_STATE_MPWQE, 398 MLX5E_SQ_STATE_RECOVERING, 399 MLX5E_SQ_STATE_IPSEC, 400 MLX5E_SQ_STATE_DIM, 401 MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, 402 MLX5E_SQ_STATE_PENDING_XSK_TX, 403 MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC, 404 MLX5E_SQ_STATE_XDP_MULTIBUF, 405 MLX5E_NUM_SQ_STATES, /* Must be kept last */ 406 }; 407 408 struct mlx5e_tx_mpwqe { 409 /* Current MPWQE session */ 410 struct mlx5e_tx_wqe *wqe; 411 u32 bytes_count; 412 u8 ds_count; 413 u8 pkt_count; 414 u8 inline_on; 415 }; 416 417 struct mlx5e_skb_fifo { 418 struct sk_buff **fifo; 419 u16 *pc; 420 u16 *cc; 421 u16 mask; 422 }; 423 424 struct mlx5e_ptpsq; 425 426 struct mlx5e_txqsq { 427 /* data path */ 428 429 /* dirtied @completion */ 430 u16 cc; 431 u16 skb_fifo_cc; 432 u32 dma_fifo_cc; 433 struct dim dim; /* Adaptive Moderation */ 434 435 /* dirtied @xmit */ 436 u16 pc ____cacheline_aligned_in_smp; 437 u16 skb_fifo_pc; 438 u32 dma_fifo_pc; 439 struct mlx5e_tx_mpwqe mpwqe; 440 441 struct mlx5e_cq cq; 442 443 /* read only */ 444 struct mlx5_wq_cyc wq; 445 u32 dma_fifo_mask; 446 struct mlx5e_sq_stats *stats; 447 struct { 448 struct mlx5e_sq_dma *dma_fifo; 449 struct mlx5e_skb_fifo skb_fifo; 450 struct mlx5e_tx_wqe_info *wqe_info; 451 } db; 452 void __iomem *uar_map; 453 struct netdev_queue *txq; 454 u32 sqn; 455 u16 stop_room; 456 u8 max_sq_mpw_wqebbs; 457 u8 min_inline_mode; 458 struct device *pdev; 459 __be32 mkey_be; 460 unsigned long state; 461 unsigned int hw_mtu; 462 struct mlx5_clock *clock; 463 struct net_device *netdev; 464 struct mlx5_core_dev *mdev; 465 struct mlx5e_channel *channel; 466 struct mlx5e_priv *priv; 467 468 /* control path */ 469 struct mlx5_wq_ctrl wq_ctrl; 470 int ch_ix; 471 int txq_ix; 472 u32 rate_limit; 473 struct work_struct recover_work; 474 struct mlx5e_ptpsq *ptpsq; 475 cqe_ts_to_ns ptp_cyc2time; 476 } ____cacheline_aligned_in_smp; 477 478 struct mlx5e_xdp_info_fifo { 479 union mlx5e_xdp_info *xi; 480 u32 *cc; 481 u32 *pc; 482 u32 mask; 483 }; 484 485 struct mlx5e_xdpsq; 486 struct mlx5e_xmit_data; 487 typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *); 488 typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *, 489 struct mlx5e_xmit_data *, 490 int); 491 492 struct mlx5e_xdpsq { 493 /* data path */ 494 495 /* dirtied @completion */ 496 u32 xdpi_fifo_cc; 497 u16 cc; 498 499 /* dirtied @xmit */ 500 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp; 501 u16 pc; 502 struct mlx5_wqe_ctrl_seg *doorbell_cseg; 503 struct mlx5e_tx_mpwqe mpwqe; 504 505 struct mlx5e_cq cq; 506 507 /* read only */ 508 struct xsk_buff_pool *xsk_pool; 509 struct mlx5_wq_cyc wq; 510 struct mlx5e_xdpsq_stats *stats; 511 mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check; 512 mlx5e_fp_xmit_xdp_frame xmit_xdp_frame; 513 struct { 514 struct mlx5e_xdp_wqe_info *wqe_info; 515 struct mlx5e_xdp_info_fifo xdpi_fifo; 516 } db; 517 void __iomem *uar_map; 518 u32 sqn; 519 struct device *pdev; 520 __be32 mkey_be; 521 u16 stop_room; 522 u8 max_sq_mpw_wqebbs; 523 u8 min_inline_mode; 524 unsigned long state; 525 unsigned int hw_mtu; 526 527 /* control path */ 528 struct mlx5_wq_ctrl wq_ctrl; 529 struct mlx5e_channel *channel; 530 } ____cacheline_aligned_in_smp; 531 532 struct mlx5e_ktls_resync_resp; 533 534 struct mlx5e_icosq { 535 /* data path */ 536 u16 cc; 537 u16 pc; 538 539 struct mlx5_wqe_ctrl_seg *doorbell_cseg; 540 struct mlx5e_cq cq; 541 542 /* write@xmit, read@completion */ 543 struct { 544 struct mlx5e_icosq_wqe_info *wqe_info; 545 } db; 546 547 /* read only */ 548 struct mlx5_wq_cyc wq; 549 void __iomem *uar_map; 550 u32 sqn; 551 u16 reserved_room; 552 unsigned long state; 553 struct mlx5e_ktls_resync_resp *ktls_resync; 554 555 /* control path */ 556 struct mlx5_wq_ctrl wq_ctrl; 557 struct mlx5e_channel *channel; 558 559 struct work_struct recover_work; 560 } ____cacheline_aligned_in_smp; 561 562 struct mlx5e_frag_page { 563 struct page *page; 564 u16 frags; 565 }; 566 567 enum mlx5e_wqe_frag_flag { 568 MLX5E_WQE_FRAG_LAST_IN_PAGE, 569 MLX5E_WQE_FRAG_SKIP_RELEASE, 570 }; 571 572 struct mlx5e_wqe_frag_info { 573 union { 574 struct mlx5e_frag_page *frag_page; 575 struct xdp_buff **xskp; 576 }; 577 u32 offset; 578 u8 flags; 579 }; 580 581 union mlx5e_alloc_units { 582 DECLARE_FLEX_ARRAY(struct mlx5e_frag_page, frag_pages); 583 DECLARE_FLEX_ARRAY(struct page *, pages); 584 DECLARE_FLEX_ARRAY(struct xdp_buff *, xsk_buffs); 585 }; 586 587 struct mlx5e_mpw_info { 588 u16 consumed_strides; 589 DECLARE_BITMAP(skip_release_bitmap, MLX5_MPWRQ_MAX_PAGES_PER_WQE); 590 struct mlx5e_frag_page linear_page; 591 union mlx5e_alloc_units alloc_units; 592 }; 593 594 #define MLX5E_MAX_RX_FRAGS 4 595 596 /* a single cache unit is capable to serve one napi call (for non-striding rq) 597 * or a MPWQE (for striding rq). 598 */ 599 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_MAX_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \ 600 MLX5_MPWRQ_MAX_PAGES_PER_WQE : NAPI_POLL_WEIGHT) 601 #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT)) 602 603 struct mlx5e_rq; 604 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*); 605 typedef struct sk_buff * 606 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, 607 struct mlx5_cqe64 *cqe, u16 cqe_bcnt, 608 u32 head_offset, u32 page_idx); 609 typedef struct sk_buff * 610 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5e_wqe_frag_info *wi, 611 struct mlx5_cqe64 *cqe, u32 cqe_bcnt); 612 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq); 613 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16); 614 typedef void (*mlx5e_fp_shampo_dealloc_hd)(struct mlx5e_rq*, u16, u16, bool); 615 616 int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk); 617 void mlx5e_rq_set_trap_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params); 618 619 enum mlx5e_rq_flag { 620 MLX5E_RQ_FLAG_XDP_XMIT, 621 MLX5E_RQ_FLAG_XDP_REDIRECT, 622 }; 623 624 struct mlx5e_rq_frag_info { 625 int frag_size; 626 int frag_stride; 627 }; 628 629 struct mlx5e_rq_frags_info { 630 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS]; 631 u8 num_frags; 632 u8 log_num_frags; 633 u16 wqe_bulk; 634 u16 refill_unit; 635 u8 wqe_index_mask; 636 }; 637 638 struct mlx5e_dma_info { 639 dma_addr_t addr; 640 union { 641 struct mlx5e_frag_page *frag_page; 642 struct page *page; 643 }; 644 }; 645 646 struct mlx5e_shampo_hd { 647 u32 mkey; 648 struct mlx5e_dma_info *info; 649 struct mlx5e_frag_page *pages; 650 u16 curr_page_index; 651 u16 hd_per_wq; 652 u16 hd_per_wqe; 653 unsigned long *bitmap; 654 u16 pi; 655 u16 ci; 656 __be32 key; 657 u64 last_addr; 658 }; 659 660 struct mlx5e_hw_gro_data { 661 struct sk_buff *skb; 662 struct flow_keys fk; 663 int second_ip_id; 664 }; 665 666 enum mlx5e_mpwrq_umr_mode { 667 MLX5E_MPWRQ_UMR_MODE_ALIGNED, 668 MLX5E_MPWRQ_UMR_MODE_UNALIGNED, 669 MLX5E_MPWRQ_UMR_MODE_OVERSIZED, 670 MLX5E_MPWRQ_UMR_MODE_TRIPLE, 671 }; 672 673 struct mlx5e_rq { 674 /* data path */ 675 union { 676 struct { 677 struct mlx5_wq_cyc wq; 678 struct mlx5e_wqe_frag_info *frags; 679 union mlx5e_alloc_units *alloc_units; 680 struct mlx5e_rq_frags_info info; 681 mlx5e_fp_skb_from_cqe skb_from_cqe; 682 } wqe; 683 struct { 684 struct mlx5_wq_ll wq; 685 struct mlx5e_umr_wqe umr_wqe; 686 struct mlx5e_mpw_info *info; 687 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq; 688 __be32 umr_mkey_be; 689 u16 num_strides; 690 u16 actual_wq_head; 691 u8 log_stride_sz; 692 u8 umr_in_progress; 693 u8 umr_last_bulk; 694 u8 umr_completed; 695 u8 min_wqe_bulk; 696 u8 page_shift; 697 u8 pages_per_wqe; 698 u8 umr_wqebbs; 699 u8 mtts_per_wqe; 700 u8 umr_mode; 701 struct mlx5e_shampo_hd *shampo; 702 } mpwqe; 703 }; 704 struct { 705 u16 headroom; 706 u32 frame0_sz; 707 u8 map_dir; /* dma map direction */ 708 } buff; 709 710 struct device *pdev; 711 struct net_device *netdev; 712 struct mlx5e_rq_stats *stats; 713 struct mlx5e_cq cq; 714 struct mlx5e_cq_decomp cqd; 715 struct hwtstamp_config *tstamp; 716 struct mlx5_clock *clock; 717 struct mlx5e_icosq *icosq; 718 struct mlx5e_priv *priv; 719 720 struct mlx5e_hw_gro_data *hw_gro_data; 721 722 mlx5e_fp_handle_rx_cqe handle_rx_cqe; 723 mlx5e_fp_post_rx_wqes post_wqes; 724 mlx5e_fp_dealloc_wqe dealloc_wqe; 725 726 unsigned long state; 727 int ix; 728 unsigned int hw_mtu; 729 730 struct dim dim; /* Dynamic Interrupt Moderation */ 731 732 /* XDP */ 733 struct bpf_prog __rcu *xdp_prog; 734 struct mlx5e_xdpsq *xdpsq; 735 DECLARE_BITMAP(flags, 8); 736 struct page_pool *page_pool; 737 738 /* AF_XDP zero-copy */ 739 struct xsk_buff_pool *xsk_pool; 740 741 struct work_struct recover_work; 742 743 /* control */ 744 struct mlx5_wq_ctrl wq_ctrl; 745 __be32 mkey_be; 746 u8 wq_type; 747 u32 rqn; 748 struct mlx5_core_dev *mdev; 749 struct mlx5e_channel *channel; 750 struct mlx5e_dma_info wqe_overflow; 751 752 /* XDP read-mostly */ 753 struct xdp_rxq_info xdp_rxq; 754 cqe_ts_to_ns ptp_cyc2time; 755 } ____cacheline_aligned_in_smp; 756 757 enum mlx5e_channel_state { 758 MLX5E_CHANNEL_STATE_XSK, 759 MLX5E_CHANNEL_NUM_STATES 760 }; 761 762 struct mlx5e_channel { 763 /* data path */ 764 struct mlx5e_rq rq; 765 struct mlx5e_xdpsq rq_xdpsq; 766 struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC]; 767 struct mlx5e_icosq icosq; /* internal control operations */ 768 struct mlx5e_txqsq __rcu * __rcu *qos_sqs; 769 bool xdp; 770 struct napi_struct napi; 771 struct device *pdev; 772 struct net_device *netdev; 773 __be32 mkey_be; 774 u16 qos_sqs_size; 775 u8 num_tc; 776 u8 lag_port; 777 778 /* XDP_REDIRECT */ 779 struct mlx5e_xdpsq xdpsq; 780 781 /* AF_XDP zero-copy */ 782 struct mlx5e_rq xskrq; 783 struct mlx5e_xdpsq xsksq; 784 785 /* Async ICOSQ */ 786 struct mlx5e_icosq async_icosq; 787 /* async_icosq can be accessed from any CPU - the spinlock protects it. */ 788 spinlock_t async_icosq_lock; 789 790 /* data path - accessed per napi poll */ 791 const struct cpumask *aff_mask; 792 struct mlx5e_ch_stats *stats; 793 794 /* control */ 795 struct mlx5e_priv *priv; 796 struct mlx5_core_dev *mdev; 797 struct hwtstamp_config *tstamp; 798 DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES); 799 int ix; 800 int cpu; 801 /* Sync between icosq recovery and XSK enable/disable. */ 802 struct mutex icosq_recovery_lock; 803 }; 804 805 struct mlx5e_ptp; 806 807 struct mlx5e_channels { 808 struct mlx5e_channel **c; 809 struct mlx5e_ptp *ptp; 810 unsigned int num; 811 struct mlx5e_params params; 812 }; 813 814 struct mlx5e_channel_stats { 815 struct mlx5e_ch_stats ch; 816 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC]; 817 struct mlx5e_rq_stats rq; 818 struct mlx5e_rq_stats xskrq; 819 struct mlx5e_xdpsq_stats rq_xdpsq; 820 struct mlx5e_xdpsq_stats xdpsq; 821 struct mlx5e_xdpsq_stats xsksq; 822 } ____cacheline_aligned_in_smp; 823 824 struct mlx5e_ptp_stats { 825 struct mlx5e_ch_stats ch; 826 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC]; 827 struct mlx5e_ptp_cq_stats cq[MLX5E_MAX_NUM_TC]; 828 struct mlx5e_rq_stats rq; 829 } ____cacheline_aligned_in_smp; 830 831 enum { 832 MLX5E_STATE_OPENED, 833 MLX5E_STATE_DESTROYING, 834 MLX5E_STATE_XDP_TX_ENABLED, 835 MLX5E_STATE_XDP_ACTIVE, 836 }; 837 838 struct mlx5e_modify_sq_param { 839 int curr_state; 840 int next_state; 841 int rl_update; 842 int rl_index; 843 bool qos_update; 844 u16 qos_queue_group_id; 845 }; 846 847 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE) 848 struct mlx5e_hv_vhca_stats_agent { 849 struct mlx5_hv_vhca_agent *agent; 850 struct delayed_work work; 851 u16 delay; 852 void *buf; 853 }; 854 #endif 855 856 struct mlx5e_xsk { 857 /* XSK buffer pools are stored separately from channels, 858 * because we don't want to lose them when channels are 859 * recreated. The kernel also stores buffer pool, but it doesn't 860 * distinguish between zero-copy and non-zero-copy UMEMs, so 861 * rely on our mechanism. 862 */ 863 struct xsk_buff_pool **pools; 864 u16 refcnt; 865 bool ever_used; 866 }; 867 868 /* Temporary storage for variables that are allocated when struct mlx5e_priv is 869 * initialized, and used where we can't allocate them because that functions 870 * must not fail. Use with care and make sure the same variable is not used 871 * simultaneously by multiple users. 872 */ 873 struct mlx5e_scratchpad { 874 cpumask_var_t cpumask; 875 }; 876 877 struct mlx5e_trap; 878 struct mlx5e_htb; 879 880 struct mlx5e_priv { 881 /* priv data path fields - start */ 882 struct mlx5e_selq selq; 883 struct mlx5e_txqsq **txq2sq; 884 #ifdef CONFIG_MLX5_CORE_EN_DCB 885 struct mlx5e_dcbx_dp dcbx_dp; 886 #endif 887 /* priv data path fields - end */ 888 889 u32 msglevel; 890 unsigned long state; 891 struct mutex state_lock; /* Protects Interface state */ 892 struct mlx5e_rq drop_rq; 893 894 struct mlx5e_channels channels; 895 u32 tisn[MLX5_MAX_PORTS][MLX5E_MAX_NUM_TC]; 896 struct mlx5e_rx_res *rx_res; 897 u32 *tx_rates; 898 899 struct mlx5e_flow_steering *fs; 900 901 struct workqueue_struct *wq; 902 struct work_struct update_carrier_work; 903 struct work_struct set_rx_mode_work; 904 struct work_struct tx_timeout_work; 905 struct work_struct update_stats_work; 906 struct work_struct monitor_counters_work; 907 struct mlx5_nb monitor_counters_nb; 908 909 struct mlx5_core_dev *mdev; 910 struct net_device *netdev; 911 struct mlx5e_trap *en_trap; 912 struct mlx5e_stats stats; 913 struct mlx5e_channel_stats **channel_stats; 914 struct mlx5e_channel_stats trap_stats; 915 struct mlx5e_ptp_stats ptp_stats; 916 struct mlx5e_sq_stats **htb_qos_sq_stats; 917 u16 htb_max_qos_sqs; 918 u16 stats_nch; 919 u16 max_nch; 920 u8 max_opened_tc; 921 bool tx_ptp_opened; 922 bool rx_ptp_opened; 923 struct hwtstamp_config tstamp; 924 u16 q_counter; 925 u16 drop_rq_q_counter; 926 struct notifier_block events_nb; 927 struct notifier_block blocking_events_nb; 928 929 struct udp_tunnel_nic_info nic_info; 930 #ifdef CONFIG_MLX5_CORE_EN_DCB 931 struct mlx5e_dcbx dcbx; 932 #endif 933 934 const struct mlx5e_profile *profile; 935 void *ppriv; 936 #ifdef CONFIG_MLX5_EN_MACSEC 937 struct mlx5e_macsec *macsec; 938 #endif 939 #ifdef CONFIG_MLX5_EN_IPSEC 940 struct mlx5e_ipsec *ipsec; 941 #endif 942 #ifdef CONFIG_MLX5_EN_TLS 943 struct mlx5e_tls *tls; 944 #endif 945 struct devlink_health_reporter *tx_reporter; 946 struct devlink_health_reporter *rx_reporter; 947 struct mlx5e_xsk xsk; 948 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE) 949 struct mlx5e_hv_vhca_stats_agent stats_agent; 950 #endif 951 struct mlx5e_scratchpad scratchpad; 952 struct mlx5e_htb *htb; 953 struct mlx5e_mqprio_rl *mqprio_rl; 954 struct dentry *dfs_root; 955 }; 956 957 struct mlx5e_dev { 958 struct mlx5e_priv *priv; 959 struct devlink_port dl_port; 960 }; 961 962 struct mlx5e_rx_handlers { 963 mlx5e_fp_handle_rx_cqe handle_rx_cqe; 964 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe; 965 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe_shampo; 966 }; 967 968 extern const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic; 969 970 enum mlx5e_profile_feature { 971 MLX5E_PROFILE_FEATURE_PTP_RX, 972 MLX5E_PROFILE_FEATURE_PTP_TX, 973 MLX5E_PROFILE_FEATURE_QOS_HTB, 974 MLX5E_PROFILE_FEATURE_FS_VLAN, 975 MLX5E_PROFILE_FEATURE_FS_TC, 976 }; 977 978 struct mlx5e_profile { 979 int (*init)(struct mlx5_core_dev *mdev, 980 struct net_device *netdev); 981 void (*cleanup)(struct mlx5e_priv *priv); 982 int (*init_rx)(struct mlx5e_priv *priv); 983 void (*cleanup_rx)(struct mlx5e_priv *priv); 984 int (*init_tx)(struct mlx5e_priv *priv); 985 void (*cleanup_tx)(struct mlx5e_priv *priv); 986 void (*enable)(struct mlx5e_priv *priv); 987 void (*disable)(struct mlx5e_priv *priv); 988 int (*update_rx)(struct mlx5e_priv *priv); 989 void (*update_stats)(struct mlx5e_priv *priv); 990 void (*update_carrier)(struct mlx5e_priv *priv); 991 int (*max_nch_limit)(struct mlx5_core_dev *mdev); 992 unsigned int (*stats_grps_num)(struct mlx5e_priv *priv); 993 mlx5e_stats_grp_t *stats_grps; 994 const struct mlx5e_rx_handlers *rx_handlers; 995 int max_tc; 996 u32 features; 997 }; 998 999 #define mlx5e_profile_feature_cap(profile, feature) \ 1000 ((profile)->features & BIT(MLX5E_PROFILE_FEATURE_##feature)) 1001 1002 void mlx5e_build_ptys2ethtool_map(void); 1003 1004 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev, u8 page_shift, 1005 enum mlx5e_mpwrq_umr_mode umr_mode); 1006 1007 void mlx5e_shampo_dealloc_hd(struct mlx5e_rq *rq, u16 len, u16 start, bool close); 1008 void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats); 1009 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s); 1010 1011 int mlx5e_self_test_num(struct mlx5e_priv *priv); 1012 int mlx5e_self_test_fill_strings(struct mlx5e_priv *priv, u8 *data); 1013 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest, 1014 u64 *buf); 1015 void mlx5e_set_rx_mode_work(struct work_struct *work); 1016 1017 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr); 1018 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr); 1019 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val, bool rx_filter); 1020 1021 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, 1022 u16 vid); 1023 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, 1024 u16 vid); 1025 void mlx5e_timestamp_init(struct mlx5e_priv *priv); 1026 1027 struct mlx5e_xsk_param; 1028 1029 struct mlx5e_rq_param; 1030 int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param, 1031 struct mlx5e_xsk_param *xsk, int node, 1032 struct mlx5e_rq *rq); 1033 #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */ 1034 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time); 1035 void mlx5e_close_rq(struct mlx5e_rq *rq); 1036 int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param); 1037 void mlx5e_destroy_rq(struct mlx5e_rq *rq); 1038 1039 struct mlx5e_sq_param; 1040 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params, 1041 struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool, 1042 struct mlx5e_xdpsq *sq, bool is_redirect); 1043 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq); 1044 1045 struct mlx5e_create_cq_param { 1046 struct napi_struct *napi; 1047 struct mlx5e_ch_stats *ch_stats; 1048 int node; 1049 int ix; 1050 }; 1051 1052 struct mlx5e_cq_param; 1053 int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder, 1054 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp, 1055 struct mlx5e_cq *cq); 1056 void mlx5e_close_cq(struct mlx5e_cq *cq); 1057 1058 int mlx5e_open_locked(struct net_device *netdev); 1059 int mlx5e_close_locked(struct net_device *netdev); 1060 1061 void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c); 1062 void mlx5e_trigger_napi_sched(struct napi_struct *napi); 1063 1064 int mlx5e_open_channels(struct mlx5e_priv *priv, 1065 struct mlx5e_channels *chs); 1066 void mlx5e_close_channels(struct mlx5e_channels *chs); 1067 1068 /* Function pointer to be used to modify HW or kernel settings while 1069 * switching channels 1070 */ 1071 typedef int (*mlx5e_fp_preactivate)(struct mlx5e_priv *priv, void *context); 1072 #define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \ 1073 int fn##_ctx(struct mlx5e_priv *priv, void *context) \ 1074 { \ 1075 return fn(priv); \ 1076 } 1077 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv); 1078 int mlx5e_safe_switch_params(struct mlx5e_priv *priv, 1079 struct mlx5e_params *new_params, 1080 mlx5e_fp_preactivate preactivate, 1081 void *context, bool reset); 1082 int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv); 1083 int mlx5e_num_channels_changed_ctx(struct mlx5e_priv *priv, void *context); 1084 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv); 1085 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv); 1086 int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx); 1087 1088 int mlx5e_flush_rq(struct mlx5e_rq *rq, int curr_state); 1089 void mlx5e_activate_rq(struct mlx5e_rq *rq); 1090 void mlx5e_deactivate_rq(struct mlx5e_rq *rq); 1091 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq); 1092 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq); 1093 1094 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn, 1095 struct mlx5e_modify_sq_param *p); 1096 int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix, 1097 struct mlx5e_params *params, struct mlx5e_sq_param *param, 1098 struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id, 1099 struct mlx5e_sq_stats *sq_stats); 1100 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq); 1101 void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq); 1102 void mlx5e_free_txqsq(struct mlx5e_txqsq *sq); 1103 void mlx5e_tx_disable_queue(struct netdev_queue *txq); 1104 int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa); 1105 void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq); 1106 struct mlx5e_create_sq_param; 1107 int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev, 1108 struct mlx5e_sq_param *param, 1109 struct mlx5e_create_sq_param *csp, 1110 u16 qos_queue_group_id, 1111 u32 *sqn); 1112 void mlx5e_tx_err_cqe_work(struct work_struct *recover_work); 1113 void mlx5e_close_txqsq(struct mlx5e_txqsq *sq); 1114 1115 static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev) 1116 { 1117 return MLX5_CAP_ETH(mdev, swp) && 1118 MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso); 1119 } 1120 1121 extern const struct ethtool_ops mlx5e_ethtool_ops; 1122 1123 int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey); 1124 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev); 1125 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); 1126 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb, 1127 bool enable_mc_lb); 1128 void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc); 1129 1130 /* common netdev helpers */ 1131 void mlx5e_create_q_counters(struct mlx5e_priv *priv); 1132 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv); 1133 int mlx5e_open_drop_rq(struct mlx5e_priv *priv, 1134 struct mlx5e_rq *drop_rq); 1135 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq); 1136 1137 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn); 1138 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn); 1139 1140 int mlx5e_create_tises(struct mlx5e_priv *priv); 1141 void mlx5e_destroy_tises(struct mlx5e_priv *priv); 1142 int mlx5e_update_nic_rx(struct mlx5e_priv *priv); 1143 void mlx5e_update_carrier(struct mlx5e_priv *priv); 1144 int mlx5e_close(struct net_device *netdev); 1145 int mlx5e_open(struct net_device *netdev); 1146 1147 void mlx5e_queue_update_stats(struct mlx5e_priv *priv); 1148 1149 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv); 1150 int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv *priv, void *context); 1151 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu, 1152 mlx5e_fp_preactivate preactivate); 1153 void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv); 1154 1155 /* ethtool helpers */ 1156 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv, 1157 struct ethtool_drvinfo *drvinfo); 1158 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, 1159 uint32_t stringset, uint8_t *data); 1160 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset); 1161 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv, 1162 struct ethtool_stats *stats, u64 *data); 1163 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv, 1164 struct ethtool_ringparam *param, 1165 struct kernel_ethtool_ringparam *kernel_param); 1166 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, 1167 struct ethtool_ringparam *param); 1168 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv, 1169 struct ethtool_channels *ch); 1170 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, 1171 struct ethtool_channels *ch); 1172 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv, 1173 struct ethtool_coalesce *coal, 1174 struct kernel_ethtool_coalesce *kernel_coal); 1175 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, 1176 struct ethtool_coalesce *coal, 1177 struct kernel_ethtool_coalesce *kernel_coal, 1178 struct netlink_ext_ack *extack); 1179 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv, 1180 struct ethtool_link_ksettings *link_ksettings); 1181 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv, 1182 const struct ethtool_link_ksettings *link_ksettings); 1183 int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, u8 *hfunc); 1184 int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key, 1185 const u8 hfunc); 1186 int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, 1187 u32 *rule_locs); 1188 int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd); 1189 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv); 1190 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv); 1191 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv, 1192 struct ethtool_ts_info *info); 1193 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv, 1194 struct ethtool_flash *flash); 1195 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv, 1196 struct ethtool_pauseparam *pauseparam); 1197 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv, 1198 struct ethtool_pauseparam *pauseparam); 1199 1200 /* mlx5e generic netdev management API */ 1201 static inline bool 1202 mlx5e_tx_mpwqe_supported(struct mlx5_core_dev *mdev) 1203 { 1204 return !is_kdump_kernel() && 1205 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe); 1206 } 1207 1208 int mlx5e_get_pf_num_tirs(struct mlx5_core_dev *mdev); 1209 int mlx5e_priv_init(struct mlx5e_priv *priv, 1210 const struct mlx5e_profile *profile, 1211 struct net_device *netdev, 1212 struct mlx5_core_dev *mdev); 1213 void mlx5e_priv_cleanup(struct mlx5e_priv *priv); 1214 struct net_device * 1215 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile); 1216 int mlx5e_attach_netdev(struct mlx5e_priv *priv); 1217 void mlx5e_detach_netdev(struct mlx5e_priv *priv); 1218 void mlx5e_destroy_netdev(struct mlx5e_priv *priv); 1219 int mlx5e_netdev_change_profile(struct mlx5e_priv *priv, 1220 const struct mlx5e_profile *new_profile, void *new_ppriv); 1221 void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv); 1222 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv); 1223 void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu); 1224 void mlx5e_rx_dim_work(struct work_struct *work); 1225 void mlx5e_tx_dim_work(struct work_struct *work); 1226 1227 void mlx5e_set_xdp_feature(struct net_device *netdev); 1228 netdev_features_t mlx5e_features_check(struct sk_buff *skb, 1229 struct net_device *netdev, 1230 netdev_features_t features); 1231 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features); 1232 #ifdef CONFIG_MLX5_ESWITCH 1233 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac); 1234 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate); 1235 int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi); 1236 int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats); 1237 #endif 1238 int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey); 1239 #endif /* __MLX5_EN_H__ */ 1240