1 /* 2 * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/highmem.h> 34 #include <linux/module.h> 35 #include <linux/errno.h> 36 #include <linux/pci.h> 37 #include <linux/dma-mapping.h> 38 #include <linux/slab.h> 39 #include <linux/delay.h> 40 #include <linux/random.h> 41 #include <linux/io-mapping.h> 42 #include <linux/mlx5/driver.h> 43 #include <linux/mlx5/eq.h> 44 #include <linux/debugfs.h> 45 46 #include "mlx5_core.h" 47 #include "lib/eq.h" 48 49 enum { 50 CMD_IF_REV = 5, 51 }; 52 53 enum { 54 CMD_MODE_POLLING, 55 CMD_MODE_EVENTS 56 }; 57 58 enum { 59 MLX5_CMD_DELIVERY_STAT_OK = 0x0, 60 MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR = 0x1, 61 MLX5_CMD_DELIVERY_STAT_TOK_ERR = 0x2, 62 MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR = 0x3, 63 MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR = 0x4, 64 MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR = 0x5, 65 MLX5_CMD_DELIVERY_STAT_FW_ERR = 0x6, 66 MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR = 0x7, 67 MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR = 0x8, 68 MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR = 0x9, 69 MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR = 0x10, 70 }; 71 72 static struct mlx5_cmd_work_ent * 73 cmd_alloc_ent(struct mlx5_cmd *cmd, struct mlx5_cmd_msg *in, 74 struct mlx5_cmd_msg *out, void *uout, int uout_size, 75 mlx5_cmd_cbk_t cbk, void *context, int page_queue) 76 { 77 gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL; 78 struct mlx5_cmd_work_ent *ent; 79 80 ent = kzalloc(sizeof(*ent), alloc_flags); 81 if (!ent) 82 return ERR_PTR(-ENOMEM); 83 84 ent->idx = -EINVAL; 85 ent->in = in; 86 ent->out = out; 87 ent->uout = uout; 88 ent->uout_size = uout_size; 89 ent->callback = cbk; 90 ent->context = context; 91 ent->cmd = cmd; 92 ent->page_queue = page_queue; 93 refcount_set(&ent->refcnt, 1); 94 95 return ent; 96 } 97 98 static void cmd_free_ent(struct mlx5_cmd_work_ent *ent) 99 { 100 kfree(ent); 101 } 102 103 static u8 alloc_token(struct mlx5_cmd *cmd) 104 { 105 u8 token; 106 107 spin_lock(&cmd->token_lock); 108 cmd->token++; 109 if (cmd->token == 0) 110 cmd->token++; 111 token = cmd->token; 112 spin_unlock(&cmd->token_lock); 113 114 return token; 115 } 116 117 static int cmd_alloc_index(struct mlx5_cmd *cmd) 118 { 119 unsigned long flags; 120 int ret; 121 122 spin_lock_irqsave(&cmd->alloc_lock, flags); 123 ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds); 124 if (ret < cmd->max_reg_cmds) 125 clear_bit(ret, &cmd->bitmask); 126 spin_unlock_irqrestore(&cmd->alloc_lock, flags); 127 128 return ret < cmd->max_reg_cmds ? ret : -ENOMEM; 129 } 130 131 static void cmd_free_index(struct mlx5_cmd *cmd, int idx) 132 { 133 unsigned long flags; 134 135 spin_lock_irqsave(&cmd->alloc_lock, flags); 136 set_bit(idx, &cmd->bitmask); 137 spin_unlock_irqrestore(&cmd->alloc_lock, flags); 138 } 139 140 static void cmd_ent_get(struct mlx5_cmd_work_ent *ent) 141 { 142 refcount_inc(&ent->refcnt); 143 } 144 145 static void cmd_ent_put(struct mlx5_cmd_work_ent *ent) 146 { 147 if (!refcount_dec_and_test(&ent->refcnt)) 148 return; 149 150 if (ent->idx >= 0) 151 cmd_free_index(ent->cmd, ent->idx); 152 153 cmd_free_ent(ent); 154 } 155 156 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx) 157 { 158 return cmd->cmd_buf + (idx << cmd->log_stride); 159 } 160 161 static int mlx5_calc_cmd_blocks(struct mlx5_cmd_msg *msg) 162 { 163 int size = msg->len; 164 int blen = size - min_t(int, sizeof(msg->first.data), size); 165 166 return DIV_ROUND_UP(blen, MLX5_CMD_DATA_BLOCK_SIZE); 167 } 168 169 static u8 xor8_buf(void *buf, size_t offset, int len) 170 { 171 u8 *ptr = buf; 172 u8 sum = 0; 173 int i; 174 int end = len + offset; 175 176 for (i = offset; i < end; i++) 177 sum ^= ptr[i]; 178 179 return sum; 180 } 181 182 static int verify_block_sig(struct mlx5_cmd_prot_block *block) 183 { 184 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0); 185 int xor_len = sizeof(*block) - sizeof(block->data) - 1; 186 187 if (xor8_buf(block, rsvd0_off, xor_len) != 0xff) 188 return -EINVAL; 189 190 if (xor8_buf(block, 0, sizeof(*block)) != 0xff) 191 return -EINVAL; 192 193 return 0; 194 } 195 196 static void calc_block_sig(struct mlx5_cmd_prot_block *block) 197 { 198 int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2; 199 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0); 200 201 block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len); 202 block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1); 203 } 204 205 static void calc_chain_sig(struct mlx5_cmd_msg *msg) 206 { 207 struct mlx5_cmd_mailbox *next = msg->next; 208 int n = mlx5_calc_cmd_blocks(msg); 209 int i = 0; 210 211 for (i = 0; i < n && next; i++) { 212 calc_block_sig(next->buf); 213 next = next->next; 214 } 215 } 216 217 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum) 218 { 219 ent->lay->sig = ~xor8_buf(ent->lay, 0, sizeof(*ent->lay)); 220 if (csum) { 221 calc_chain_sig(ent->in); 222 calc_chain_sig(ent->out); 223 } 224 } 225 226 static void poll_timeout(struct mlx5_cmd_work_ent *ent) 227 { 228 unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000); 229 u8 own; 230 231 do { 232 own = READ_ONCE(ent->lay->status_own); 233 if (!(own & CMD_OWNER_HW)) { 234 ent->ret = 0; 235 return; 236 } 237 cond_resched(); 238 } while (time_before(jiffies, poll_end)); 239 240 ent->ret = -ETIMEDOUT; 241 } 242 243 static int verify_signature(struct mlx5_cmd_work_ent *ent) 244 { 245 struct mlx5_cmd_mailbox *next = ent->out->next; 246 int n = mlx5_calc_cmd_blocks(ent->out); 247 int err; 248 u8 sig; 249 int i = 0; 250 251 sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay)); 252 if (sig != 0xff) 253 return -EINVAL; 254 255 for (i = 0; i < n && next; i++) { 256 err = verify_block_sig(next->buf); 257 if (err) 258 return err; 259 260 next = next->next; 261 } 262 263 return 0; 264 } 265 266 static void dump_buf(void *buf, int size, int data_only, int offset) 267 { 268 __be32 *p = buf; 269 int i; 270 271 for (i = 0; i < size; i += 16) { 272 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]), 273 be32_to_cpu(p[1]), be32_to_cpu(p[2]), 274 be32_to_cpu(p[3])); 275 p += 4; 276 offset += 16; 277 } 278 if (!data_only) 279 pr_debug("\n"); 280 } 281 282 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op, 283 u32 *synd, u8 *status) 284 { 285 *synd = 0; 286 *status = 0; 287 288 switch (op) { 289 case MLX5_CMD_OP_TEARDOWN_HCA: 290 case MLX5_CMD_OP_DISABLE_HCA: 291 case MLX5_CMD_OP_MANAGE_PAGES: 292 case MLX5_CMD_OP_DESTROY_MKEY: 293 case MLX5_CMD_OP_DESTROY_EQ: 294 case MLX5_CMD_OP_DESTROY_CQ: 295 case MLX5_CMD_OP_DESTROY_QP: 296 case MLX5_CMD_OP_DESTROY_PSV: 297 case MLX5_CMD_OP_DESTROY_SRQ: 298 case MLX5_CMD_OP_DESTROY_XRC_SRQ: 299 case MLX5_CMD_OP_DESTROY_XRQ: 300 case MLX5_CMD_OP_DESTROY_DCT: 301 case MLX5_CMD_OP_DEALLOC_Q_COUNTER: 302 case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT: 303 case MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT: 304 case MLX5_CMD_OP_DEALLOC_PD: 305 case MLX5_CMD_OP_DEALLOC_UAR: 306 case MLX5_CMD_OP_DETACH_FROM_MCG: 307 case MLX5_CMD_OP_DEALLOC_XRCD: 308 case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN: 309 case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT: 310 case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY: 311 case MLX5_CMD_OP_DESTROY_LAG: 312 case MLX5_CMD_OP_DESTROY_VPORT_LAG: 313 case MLX5_CMD_OP_DESTROY_TIR: 314 case MLX5_CMD_OP_DESTROY_SQ: 315 case MLX5_CMD_OP_DESTROY_RQ: 316 case MLX5_CMD_OP_DESTROY_RMP: 317 case MLX5_CMD_OP_DESTROY_TIS: 318 case MLX5_CMD_OP_DESTROY_RQT: 319 case MLX5_CMD_OP_DESTROY_FLOW_TABLE: 320 case MLX5_CMD_OP_DESTROY_FLOW_GROUP: 321 case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY: 322 case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER: 323 case MLX5_CMD_OP_2ERR_QP: 324 case MLX5_CMD_OP_2RST_QP: 325 case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT: 326 case MLX5_CMD_OP_MODIFY_FLOW_TABLE: 327 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY: 328 case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT: 329 case MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT: 330 case MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT: 331 case MLX5_CMD_OP_FPGA_DESTROY_QP: 332 case MLX5_CMD_OP_DESTROY_GENERAL_OBJECT: 333 case MLX5_CMD_OP_DEALLOC_MEMIC: 334 case MLX5_CMD_OP_PAGE_FAULT_RESUME: 335 case MLX5_CMD_OP_QUERY_ESW_FUNCTIONS: 336 case MLX5_CMD_OP_DEALLOC_SF: 337 return MLX5_CMD_STAT_OK; 338 339 case MLX5_CMD_OP_QUERY_HCA_CAP: 340 case MLX5_CMD_OP_QUERY_ADAPTER: 341 case MLX5_CMD_OP_INIT_HCA: 342 case MLX5_CMD_OP_ENABLE_HCA: 343 case MLX5_CMD_OP_QUERY_PAGES: 344 case MLX5_CMD_OP_SET_HCA_CAP: 345 case MLX5_CMD_OP_QUERY_ISSI: 346 case MLX5_CMD_OP_SET_ISSI: 347 case MLX5_CMD_OP_CREATE_MKEY: 348 case MLX5_CMD_OP_QUERY_MKEY: 349 case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS: 350 case MLX5_CMD_OP_CREATE_EQ: 351 case MLX5_CMD_OP_QUERY_EQ: 352 case MLX5_CMD_OP_GEN_EQE: 353 case MLX5_CMD_OP_CREATE_CQ: 354 case MLX5_CMD_OP_QUERY_CQ: 355 case MLX5_CMD_OP_MODIFY_CQ: 356 case MLX5_CMD_OP_CREATE_QP: 357 case MLX5_CMD_OP_RST2INIT_QP: 358 case MLX5_CMD_OP_INIT2RTR_QP: 359 case MLX5_CMD_OP_RTR2RTS_QP: 360 case MLX5_CMD_OP_RTS2RTS_QP: 361 case MLX5_CMD_OP_SQERR2RTS_QP: 362 case MLX5_CMD_OP_QUERY_QP: 363 case MLX5_CMD_OP_SQD_RTS_QP: 364 case MLX5_CMD_OP_INIT2INIT_QP: 365 case MLX5_CMD_OP_CREATE_PSV: 366 case MLX5_CMD_OP_CREATE_SRQ: 367 case MLX5_CMD_OP_QUERY_SRQ: 368 case MLX5_CMD_OP_ARM_RQ: 369 case MLX5_CMD_OP_CREATE_XRC_SRQ: 370 case MLX5_CMD_OP_QUERY_XRC_SRQ: 371 case MLX5_CMD_OP_ARM_XRC_SRQ: 372 case MLX5_CMD_OP_CREATE_XRQ: 373 case MLX5_CMD_OP_QUERY_XRQ: 374 case MLX5_CMD_OP_ARM_XRQ: 375 case MLX5_CMD_OP_CREATE_DCT: 376 case MLX5_CMD_OP_DRAIN_DCT: 377 case MLX5_CMD_OP_QUERY_DCT: 378 case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION: 379 case MLX5_CMD_OP_QUERY_VPORT_STATE: 380 case MLX5_CMD_OP_MODIFY_VPORT_STATE: 381 case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT: 382 case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT: 383 case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT: 384 case MLX5_CMD_OP_QUERY_ROCE_ADDRESS: 385 case MLX5_CMD_OP_SET_ROCE_ADDRESS: 386 case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT: 387 case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT: 388 case MLX5_CMD_OP_QUERY_HCA_VPORT_GID: 389 case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY: 390 case MLX5_CMD_OP_QUERY_VNIC_ENV: 391 case MLX5_CMD_OP_QUERY_VPORT_COUNTER: 392 case MLX5_CMD_OP_ALLOC_Q_COUNTER: 393 case MLX5_CMD_OP_QUERY_Q_COUNTER: 394 case MLX5_CMD_OP_SET_MONITOR_COUNTER: 395 case MLX5_CMD_OP_ARM_MONITOR_COUNTER: 396 case MLX5_CMD_OP_SET_PP_RATE_LIMIT: 397 case MLX5_CMD_OP_QUERY_RATE_LIMIT: 398 case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT: 399 case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT: 400 case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT: 401 case MLX5_CMD_OP_CREATE_QOS_PARA_VPORT: 402 case MLX5_CMD_OP_ALLOC_PD: 403 case MLX5_CMD_OP_ALLOC_UAR: 404 case MLX5_CMD_OP_CONFIG_INT_MODERATION: 405 case MLX5_CMD_OP_ACCESS_REG: 406 case MLX5_CMD_OP_ATTACH_TO_MCG: 407 case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG: 408 case MLX5_CMD_OP_MAD_IFC: 409 case MLX5_CMD_OP_QUERY_MAD_DEMUX: 410 case MLX5_CMD_OP_SET_MAD_DEMUX: 411 case MLX5_CMD_OP_NOP: 412 case MLX5_CMD_OP_ALLOC_XRCD: 413 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN: 414 case MLX5_CMD_OP_QUERY_CONG_STATUS: 415 case MLX5_CMD_OP_MODIFY_CONG_STATUS: 416 case MLX5_CMD_OP_QUERY_CONG_PARAMS: 417 case MLX5_CMD_OP_MODIFY_CONG_PARAMS: 418 case MLX5_CMD_OP_QUERY_CONG_STATISTICS: 419 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT: 420 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY: 421 case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY: 422 case MLX5_CMD_OP_CREATE_LAG: 423 case MLX5_CMD_OP_MODIFY_LAG: 424 case MLX5_CMD_OP_QUERY_LAG: 425 case MLX5_CMD_OP_CREATE_VPORT_LAG: 426 case MLX5_CMD_OP_CREATE_TIR: 427 case MLX5_CMD_OP_MODIFY_TIR: 428 case MLX5_CMD_OP_QUERY_TIR: 429 case MLX5_CMD_OP_CREATE_SQ: 430 case MLX5_CMD_OP_MODIFY_SQ: 431 case MLX5_CMD_OP_QUERY_SQ: 432 case MLX5_CMD_OP_CREATE_RQ: 433 case MLX5_CMD_OP_MODIFY_RQ: 434 case MLX5_CMD_OP_QUERY_RQ: 435 case MLX5_CMD_OP_CREATE_RMP: 436 case MLX5_CMD_OP_MODIFY_RMP: 437 case MLX5_CMD_OP_QUERY_RMP: 438 case MLX5_CMD_OP_CREATE_TIS: 439 case MLX5_CMD_OP_MODIFY_TIS: 440 case MLX5_CMD_OP_QUERY_TIS: 441 case MLX5_CMD_OP_CREATE_RQT: 442 case MLX5_CMD_OP_MODIFY_RQT: 443 case MLX5_CMD_OP_QUERY_RQT: 444 445 case MLX5_CMD_OP_CREATE_FLOW_TABLE: 446 case MLX5_CMD_OP_QUERY_FLOW_TABLE: 447 case MLX5_CMD_OP_CREATE_FLOW_GROUP: 448 case MLX5_CMD_OP_QUERY_FLOW_GROUP: 449 case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY: 450 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER: 451 case MLX5_CMD_OP_QUERY_FLOW_COUNTER: 452 case MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT: 453 case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT: 454 case MLX5_CMD_OP_FPGA_CREATE_QP: 455 case MLX5_CMD_OP_FPGA_MODIFY_QP: 456 case MLX5_CMD_OP_FPGA_QUERY_QP: 457 case MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS: 458 case MLX5_CMD_OP_CREATE_GENERAL_OBJECT: 459 case MLX5_CMD_OP_MODIFY_GENERAL_OBJECT: 460 case MLX5_CMD_OP_QUERY_GENERAL_OBJECT: 461 case MLX5_CMD_OP_CREATE_UCTX: 462 case MLX5_CMD_OP_DESTROY_UCTX: 463 case MLX5_CMD_OP_CREATE_UMEM: 464 case MLX5_CMD_OP_DESTROY_UMEM: 465 case MLX5_CMD_OP_ALLOC_MEMIC: 466 case MLX5_CMD_OP_MODIFY_XRQ: 467 case MLX5_CMD_OP_RELEASE_XRQ_ERROR: 468 case MLX5_CMD_OP_QUERY_VHCA_STATE: 469 case MLX5_CMD_OP_MODIFY_VHCA_STATE: 470 case MLX5_CMD_OP_ALLOC_SF: 471 *status = MLX5_DRIVER_STATUS_ABORTED; 472 *synd = MLX5_DRIVER_SYND; 473 return -EIO; 474 default: 475 mlx5_core_err(dev, "Unknown FW command (%d)\n", op); 476 return -EINVAL; 477 } 478 } 479 480 const char *mlx5_command_str(int command) 481 { 482 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd 483 484 switch (command) { 485 MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP); 486 MLX5_COMMAND_STR_CASE(QUERY_ADAPTER); 487 MLX5_COMMAND_STR_CASE(INIT_HCA); 488 MLX5_COMMAND_STR_CASE(TEARDOWN_HCA); 489 MLX5_COMMAND_STR_CASE(ENABLE_HCA); 490 MLX5_COMMAND_STR_CASE(DISABLE_HCA); 491 MLX5_COMMAND_STR_CASE(QUERY_PAGES); 492 MLX5_COMMAND_STR_CASE(MANAGE_PAGES); 493 MLX5_COMMAND_STR_CASE(SET_HCA_CAP); 494 MLX5_COMMAND_STR_CASE(QUERY_ISSI); 495 MLX5_COMMAND_STR_CASE(SET_ISSI); 496 MLX5_COMMAND_STR_CASE(SET_DRIVER_VERSION); 497 MLX5_COMMAND_STR_CASE(CREATE_MKEY); 498 MLX5_COMMAND_STR_CASE(QUERY_MKEY); 499 MLX5_COMMAND_STR_CASE(DESTROY_MKEY); 500 MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS); 501 MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME); 502 MLX5_COMMAND_STR_CASE(CREATE_EQ); 503 MLX5_COMMAND_STR_CASE(DESTROY_EQ); 504 MLX5_COMMAND_STR_CASE(QUERY_EQ); 505 MLX5_COMMAND_STR_CASE(GEN_EQE); 506 MLX5_COMMAND_STR_CASE(CREATE_CQ); 507 MLX5_COMMAND_STR_CASE(DESTROY_CQ); 508 MLX5_COMMAND_STR_CASE(QUERY_CQ); 509 MLX5_COMMAND_STR_CASE(MODIFY_CQ); 510 MLX5_COMMAND_STR_CASE(CREATE_QP); 511 MLX5_COMMAND_STR_CASE(DESTROY_QP); 512 MLX5_COMMAND_STR_CASE(RST2INIT_QP); 513 MLX5_COMMAND_STR_CASE(INIT2RTR_QP); 514 MLX5_COMMAND_STR_CASE(RTR2RTS_QP); 515 MLX5_COMMAND_STR_CASE(RTS2RTS_QP); 516 MLX5_COMMAND_STR_CASE(SQERR2RTS_QP); 517 MLX5_COMMAND_STR_CASE(2ERR_QP); 518 MLX5_COMMAND_STR_CASE(2RST_QP); 519 MLX5_COMMAND_STR_CASE(QUERY_QP); 520 MLX5_COMMAND_STR_CASE(SQD_RTS_QP); 521 MLX5_COMMAND_STR_CASE(INIT2INIT_QP); 522 MLX5_COMMAND_STR_CASE(CREATE_PSV); 523 MLX5_COMMAND_STR_CASE(DESTROY_PSV); 524 MLX5_COMMAND_STR_CASE(CREATE_SRQ); 525 MLX5_COMMAND_STR_CASE(DESTROY_SRQ); 526 MLX5_COMMAND_STR_CASE(QUERY_SRQ); 527 MLX5_COMMAND_STR_CASE(ARM_RQ); 528 MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ); 529 MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ); 530 MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ); 531 MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ); 532 MLX5_COMMAND_STR_CASE(CREATE_DCT); 533 MLX5_COMMAND_STR_CASE(DESTROY_DCT); 534 MLX5_COMMAND_STR_CASE(DRAIN_DCT); 535 MLX5_COMMAND_STR_CASE(QUERY_DCT); 536 MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION); 537 MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE); 538 MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE); 539 MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT); 540 MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT); 541 MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT); 542 MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT); 543 MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS); 544 MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS); 545 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT); 546 MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT); 547 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID); 548 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY); 549 MLX5_COMMAND_STR_CASE(QUERY_VNIC_ENV); 550 MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER); 551 MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER); 552 MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER); 553 MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER); 554 MLX5_COMMAND_STR_CASE(SET_MONITOR_COUNTER); 555 MLX5_COMMAND_STR_CASE(ARM_MONITOR_COUNTER); 556 MLX5_COMMAND_STR_CASE(SET_PP_RATE_LIMIT); 557 MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT); 558 MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT); 559 MLX5_COMMAND_STR_CASE(DESTROY_SCHEDULING_ELEMENT); 560 MLX5_COMMAND_STR_CASE(QUERY_SCHEDULING_ELEMENT); 561 MLX5_COMMAND_STR_CASE(MODIFY_SCHEDULING_ELEMENT); 562 MLX5_COMMAND_STR_CASE(CREATE_QOS_PARA_VPORT); 563 MLX5_COMMAND_STR_CASE(DESTROY_QOS_PARA_VPORT); 564 MLX5_COMMAND_STR_CASE(ALLOC_PD); 565 MLX5_COMMAND_STR_CASE(DEALLOC_PD); 566 MLX5_COMMAND_STR_CASE(ALLOC_UAR); 567 MLX5_COMMAND_STR_CASE(DEALLOC_UAR); 568 MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION); 569 MLX5_COMMAND_STR_CASE(ACCESS_REG); 570 MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG); 571 MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG); 572 MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG); 573 MLX5_COMMAND_STR_CASE(MAD_IFC); 574 MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX); 575 MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX); 576 MLX5_COMMAND_STR_CASE(NOP); 577 MLX5_COMMAND_STR_CASE(ALLOC_XRCD); 578 MLX5_COMMAND_STR_CASE(DEALLOC_XRCD); 579 MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN); 580 MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN); 581 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS); 582 MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS); 583 MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS); 584 MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS); 585 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS); 586 MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT); 587 MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT); 588 MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY); 589 MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY); 590 MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY); 591 MLX5_COMMAND_STR_CASE(SET_WOL_ROL); 592 MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL); 593 MLX5_COMMAND_STR_CASE(CREATE_LAG); 594 MLX5_COMMAND_STR_CASE(MODIFY_LAG); 595 MLX5_COMMAND_STR_CASE(QUERY_LAG); 596 MLX5_COMMAND_STR_CASE(DESTROY_LAG); 597 MLX5_COMMAND_STR_CASE(CREATE_VPORT_LAG); 598 MLX5_COMMAND_STR_CASE(DESTROY_VPORT_LAG); 599 MLX5_COMMAND_STR_CASE(CREATE_TIR); 600 MLX5_COMMAND_STR_CASE(MODIFY_TIR); 601 MLX5_COMMAND_STR_CASE(DESTROY_TIR); 602 MLX5_COMMAND_STR_CASE(QUERY_TIR); 603 MLX5_COMMAND_STR_CASE(CREATE_SQ); 604 MLX5_COMMAND_STR_CASE(MODIFY_SQ); 605 MLX5_COMMAND_STR_CASE(DESTROY_SQ); 606 MLX5_COMMAND_STR_CASE(QUERY_SQ); 607 MLX5_COMMAND_STR_CASE(CREATE_RQ); 608 MLX5_COMMAND_STR_CASE(MODIFY_RQ); 609 MLX5_COMMAND_STR_CASE(DESTROY_RQ); 610 MLX5_COMMAND_STR_CASE(QUERY_RQ); 611 MLX5_COMMAND_STR_CASE(CREATE_RMP); 612 MLX5_COMMAND_STR_CASE(MODIFY_RMP); 613 MLX5_COMMAND_STR_CASE(DESTROY_RMP); 614 MLX5_COMMAND_STR_CASE(QUERY_RMP); 615 MLX5_COMMAND_STR_CASE(CREATE_TIS); 616 MLX5_COMMAND_STR_CASE(MODIFY_TIS); 617 MLX5_COMMAND_STR_CASE(DESTROY_TIS); 618 MLX5_COMMAND_STR_CASE(QUERY_TIS); 619 MLX5_COMMAND_STR_CASE(CREATE_RQT); 620 MLX5_COMMAND_STR_CASE(MODIFY_RQT); 621 MLX5_COMMAND_STR_CASE(DESTROY_RQT); 622 MLX5_COMMAND_STR_CASE(QUERY_RQT); 623 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT); 624 MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE); 625 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE); 626 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE); 627 MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP); 628 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP); 629 MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP); 630 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY); 631 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY); 632 MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY); 633 MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER); 634 MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER); 635 MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER); 636 MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE); 637 MLX5_COMMAND_STR_CASE(ALLOC_PACKET_REFORMAT_CONTEXT); 638 MLX5_COMMAND_STR_CASE(DEALLOC_PACKET_REFORMAT_CONTEXT); 639 MLX5_COMMAND_STR_CASE(ALLOC_MODIFY_HEADER_CONTEXT); 640 MLX5_COMMAND_STR_CASE(DEALLOC_MODIFY_HEADER_CONTEXT); 641 MLX5_COMMAND_STR_CASE(FPGA_CREATE_QP); 642 MLX5_COMMAND_STR_CASE(FPGA_MODIFY_QP); 643 MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP); 644 MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS); 645 MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP); 646 MLX5_COMMAND_STR_CASE(CREATE_XRQ); 647 MLX5_COMMAND_STR_CASE(DESTROY_XRQ); 648 MLX5_COMMAND_STR_CASE(QUERY_XRQ); 649 MLX5_COMMAND_STR_CASE(ARM_XRQ); 650 MLX5_COMMAND_STR_CASE(CREATE_GENERAL_OBJECT); 651 MLX5_COMMAND_STR_CASE(DESTROY_GENERAL_OBJECT); 652 MLX5_COMMAND_STR_CASE(MODIFY_GENERAL_OBJECT); 653 MLX5_COMMAND_STR_CASE(QUERY_GENERAL_OBJECT); 654 MLX5_COMMAND_STR_CASE(QUERY_MODIFY_HEADER_CONTEXT); 655 MLX5_COMMAND_STR_CASE(ALLOC_MEMIC); 656 MLX5_COMMAND_STR_CASE(DEALLOC_MEMIC); 657 MLX5_COMMAND_STR_CASE(QUERY_ESW_FUNCTIONS); 658 MLX5_COMMAND_STR_CASE(CREATE_UCTX); 659 MLX5_COMMAND_STR_CASE(DESTROY_UCTX); 660 MLX5_COMMAND_STR_CASE(CREATE_UMEM); 661 MLX5_COMMAND_STR_CASE(DESTROY_UMEM); 662 MLX5_COMMAND_STR_CASE(RELEASE_XRQ_ERROR); 663 MLX5_COMMAND_STR_CASE(MODIFY_XRQ); 664 MLX5_COMMAND_STR_CASE(QUERY_VHCA_STATE); 665 MLX5_COMMAND_STR_CASE(MODIFY_VHCA_STATE); 666 MLX5_COMMAND_STR_CASE(ALLOC_SF); 667 MLX5_COMMAND_STR_CASE(DEALLOC_SF); 668 default: return "unknown command opcode"; 669 } 670 } 671 672 static const char *cmd_status_str(u8 status) 673 { 674 switch (status) { 675 case MLX5_CMD_STAT_OK: 676 return "OK"; 677 case MLX5_CMD_STAT_INT_ERR: 678 return "internal error"; 679 case MLX5_CMD_STAT_BAD_OP_ERR: 680 return "bad operation"; 681 case MLX5_CMD_STAT_BAD_PARAM_ERR: 682 return "bad parameter"; 683 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR: 684 return "bad system state"; 685 case MLX5_CMD_STAT_BAD_RES_ERR: 686 return "bad resource"; 687 case MLX5_CMD_STAT_RES_BUSY: 688 return "resource busy"; 689 case MLX5_CMD_STAT_LIM_ERR: 690 return "limits exceeded"; 691 case MLX5_CMD_STAT_BAD_RES_STATE_ERR: 692 return "bad resource state"; 693 case MLX5_CMD_STAT_IX_ERR: 694 return "bad index"; 695 case MLX5_CMD_STAT_NO_RES_ERR: 696 return "no resources"; 697 case MLX5_CMD_STAT_BAD_INP_LEN_ERR: 698 return "bad input length"; 699 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR: 700 return "bad output length"; 701 case MLX5_CMD_STAT_BAD_QP_STATE_ERR: 702 return "bad QP state"; 703 case MLX5_CMD_STAT_BAD_PKT_ERR: 704 return "bad packet (discarded)"; 705 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR: 706 return "bad size too many outstanding CQEs"; 707 default: 708 return "unknown status"; 709 } 710 } 711 712 static int cmd_status_to_err(u8 status) 713 { 714 switch (status) { 715 case MLX5_CMD_STAT_OK: return 0; 716 case MLX5_CMD_STAT_INT_ERR: return -EIO; 717 case MLX5_CMD_STAT_BAD_OP_ERR: return -EINVAL; 718 case MLX5_CMD_STAT_BAD_PARAM_ERR: return -EINVAL; 719 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR: return -EIO; 720 case MLX5_CMD_STAT_BAD_RES_ERR: return -EINVAL; 721 case MLX5_CMD_STAT_RES_BUSY: return -EBUSY; 722 case MLX5_CMD_STAT_LIM_ERR: return -ENOMEM; 723 case MLX5_CMD_STAT_BAD_RES_STATE_ERR: return -EINVAL; 724 case MLX5_CMD_STAT_IX_ERR: return -EINVAL; 725 case MLX5_CMD_STAT_NO_RES_ERR: return -EAGAIN; 726 case MLX5_CMD_STAT_BAD_INP_LEN_ERR: return -EIO; 727 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR: return -EIO; 728 case MLX5_CMD_STAT_BAD_QP_STATE_ERR: return -EINVAL; 729 case MLX5_CMD_STAT_BAD_PKT_ERR: return -EINVAL; 730 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR: return -EINVAL; 731 default: return -EIO; 732 } 733 } 734 735 struct mlx5_ifc_mbox_out_bits { 736 u8 status[0x8]; 737 u8 reserved_at_8[0x18]; 738 739 u8 syndrome[0x20]; 740 741 u8 reserved_at_40[0x40]; 742 }; 743 744 struct mlx5_ifc_mbox_in_bits { 745 u8 opcode[0x10]; 746 u8 uid[0x10]; 747 748 u8 reserved_at_20[0x10]; 749 u8 op_mod[0x10]; 750 751 u8 reserved_at_40[0x40]; 752 }; 753 754 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome) 755 { 756 *status = MLX5_GET(mbox_out, out, status); 757 *syndrome = MLX5_GET(mbox_out, out, syndrome); 758 } 759 760 static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out) 761 { 762 u32 syndrome; 763 u8 status; 764 u16 opcode; 765 u16 op_mod; 766 u16 uid; 767 768 mlx5_cmd_mbox_status(out, &status, &syndrome); 769 if (!status) 770 return 0; 771 772 opcode = MLX5_GET(mbox_in, in, opcode); 773 op_mod = MLX5_GET(mbox_in, in, op_mod); 774 uid = MLX5_GET(mbox_in, in, uid); 775 776 if (!uid && opcode != MLX5_CMD_OP_DESTROY_MKEY) 777 mlx5_core_err_rl(dev, 778 "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n", 779 mlx5_command_str(opcode), opcode, op_mod, 780 cmd_status_str(status), status, syndrome); 781 else 782 mlx5_core_dbg(dev, 783 "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n", 784 mlx5_command_str(opcode), 785 opcode, op_mod, 786 cmd_status_str(status), 787 status, 788 syndrome); 789 790 return cmd_status_to_err(status); 791 } 792 793 static void dump_command(struct mlx5_core_dev *dev, 794 struct mlx5_cmd_work_ent *ent, int input) 795 { 796 struct mlx5_cmd_msg *msg = input ? ent->in : ent->out; 797 u16 op = MLX5_GET(mbox_in, ent->lay->in, opcode); 798 struct mlx5_cmd_mailbox *next = msg->next; 799 int n = mlx5_calc_cmd_blocks(msg); 800 int data_only; 801 u32 offset = 0; 802 int dump_len; 803 int i; 804 805 data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA)); 806 807 if (data_only) 808 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA, 809 "dump command data %s(0x%x) %s\n", 810 mlx5_command_str(op), op, 811 input ? "INPUT" : "OUTPUT"); 812 else 813 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n", 814 mlx5_command_str(op), op, 815 input ? "INPUT" : "OUTPUT"); 816 817 if (data_only) { 818 if (input) { 819 dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset); 820 offset += sizeof(ent->lay->in); 821 } else { 822 dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset); 823 offset += sizeof(ent->lay->out); 824 } 825 } else { 826 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset); 827 offset += sizeof(*ent->lay); 828 } 829 830 for (i = 0; i < n && next; i++) { 831 if (data_only) { 832 dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset); 833 dump_buf(next->buf, dump_len, 1, offset); 834 offset += MLX5_CMD_DATA_BLOCK_SIZE; 835 } else { 836 mlx5_core_dbg(dev, "command block:\n"); 837 dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset); 838 offset += sizeof(struct mlx5_cmd_prot_block); 839 } 840 next = next->next; 841 } 842 843 if (data_only) 844 pr_debug("\n"); 845 } 846 847 static u16 msg_to_opcode(struct mlx5_cmd_msg *in) 848 { 849 return MLX5_GET(mbox_in, in->first.data, opcode); 850 } 851 852 static void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced); 853 854 static void cb_timeout_handler(struct work_struct *work) 855 { 856 struct delayed_work *dwork = container_of(work, struct delayed_work, 857 work); 858 struct mlx5_cmd_work_ent *ent = container_of(dwork, 859 struct mlx5_cmd_work_ent, 860 cb_timeout_work); 861 struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev, 862 cmd); 863 864 mlx5_cmd_eq_recover(dev); 865 866 /* Maybe got handled by eq recover ? */ 867 if (!test_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state)) { 868 mlx5_core_warn(dev, "cmd[%d]: %s(0x%x) Async, recovered after timeout\n", ent->idx, 869 mlx5_command_str(msg_to_opcode(ent->in)), msg_to_opcode(ent->in)); 870 goto out; /* phew, already handled */ 871 } 872 873 ent->ret = -ETIMEDOUT; 874 mlx5_core_warn(dev, "cmd[%d]: %s(0x%x) Async, timeout. Will cause a leak of a command resource\n", 875 ent->idx, mlx5_command_str(msg_to_opcode(ent->in)), msg_to_opcode(ent->in)); 876 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true); 877 878 out: 879 cmd_ent_put(ent); /* for the cmd_ent_get() took on schedule delayed work */ 880 } 881 882 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg); 883 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev, 884 struct mlx5_cmd_msg *msg); 885 886 static bool opcode_allowed(struct mlx5_cmd *cmd, u16 opcode) 887 { 888 if (cmd->allowed_opcode == CMD_ALLOWED_OPCODE_ALL) 889 return true; 890 891 return cmd->allowed_opcode == opcode; 892 } 893 894 static int cmd_alloc_index_retry(struct mlx5_cmd *cmd) 895 { 896 unsigned long alloc_end = jiffies + msecs_to_jiffies(1000); 897 int idx; 898 899 retry: 900 idx = cmd_alloc_index(cmd); 901 if (idx < 0 && time_before(jiffies, alloc_end)) { 902 /* Index allocation can fail on heavy load of commands. This is a temporary 903 * situation as the current command already holds the semaphore, meaning that 904 * another command completion is being handled and it is expected to release 905 * the entry index soon. 906 */ 907 cpu_relax(); 908 goto retry; 909 } 910 return idx; 911 } 912 913 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev) 914 { 915 return pci_channel_offline(dev->pdev) || 916 dev->cmd.state != MLX5_CMDIF_STATE_UP || 917 dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR; 918 } 919 920 static void cmd_work_handler(struct work_struct *work) 921 { 922 struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work); 923 struct mlx5_cmd *cmd = ent->cmd; 924 struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd); 925 unsigned long cb_timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC); 926 struct mlx5_cmd_layout *lay; 927 struct semaphore *sem; 928 unsigned long flags; 929 bool poll_cmd = ent->polling; 930 int alloc_ret; 931 int cmd_mode; 932 933 complete(&ent->handling); 934 sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem; 935 down(sem); 936 if (!ent->page_queue) { 937 alloc_ret = cmd_alloc_index_retry(cmd); 938 if (alloc_ret < 0) { 939 mlx5_core_err_rl(dev, "failed to allocate command entry\n"); 940 if (ent->callback) { 941 ent->callback(-EAGAIN, ent->context); 942 mlx5_free_cmd_msg(dev, ent->out); 943 free_msg(dev, ent->in); 944 cmd_ent_put(ent); 945 } else { 946 ent->ret = -EAGAIN; 947 complete(&ent->done); 948 } 949 up(sem); 950 return; 951 } 952 ent->idx = alloc_ret; 953 } else { 954 ent->idx = cmd->max_reg_cmds; 955 spin_lock_irqsave(&cmd->alloc_lock, flags); 956 clear_bit(ent->idx, &cmd->bitmask); 957 spin_unlock_irqrestore(&cmd->alloc_lock, flags); 958 } 959 960 cmd->ent_arr[ent->idx] = ent; 961 lay = get_inst(cmd, ent->idx); 962 ent->lay = lay; 963 memset(lay, 0, sizeof(*lay)); 964 memcpy(lay->in, ent->in->first.data, sizeof(lay->in)); 965 ent->op = be32_to_cpu(lay->in[0]) >> 16; 966 if (ent->in->next) 967 lay->in_ptr = cpu_to_be64(ent->in->next->dma); 968 lay->inlen = cpu_to_be32(ent->in->len); 969 if (ent->out->next) 970 lay->out_ptr = cpu_to_be64(ent->out->next->dma); 971 lay->outlen = cpu_to_be32(ent->out->len); 972 lay->type = MLX5_PCI_CMD_XPORT; 973 lay->token = ent->token; 974 lay->status_own = CMD_OWNER_HW; 975 set_signature(ent, !cmd->checksum_disabled); 976 dump_command(dev, ent, 1); 977 ent->ts1 = ktime_get_ns(); 978 cmd_mode = cmd->mode; 979 980 if (ent->callback && schedule_delayed_work(&ent->cb_timeout_work, cb_timeout)) 981 cmd_ent_get(ent); 982 set_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state); 983 984 /* Skip sending command to fw if internal error */ 985 if (mlx5_cmd_is_down(dev) || !opcode_allowed(&dev->cmd, ent->op)) { 986 u8 status = 0; 987 u32 drv_synd; 988 989 ent->ret = mlx5_internal_err_ret_value(dev, msg_to_opcode(ent->in), &drv_synd, &status); 990 MLX5_SET(mbox_out, ent->out, status, status); 991 MLX5_SET(mbox_out, ent->out, syndrome, drv_synd); 992 993 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true); 994 return; 995 } 996 997 cmd_ent_get(ent); /* for the _real_ FW event on completion */ 998 /* ring doorbell after the descriptor is valid */ 999 mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx); 1000 wmb(); 1001 iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell); 1002 /* if not in polling don't use ent after this point */ 1003 if (cmd_mode == CMD_MODE_POLLING || poll_cmd) { 1004 poll_timeout(ent); 1005 /* make sure we read the descriptor after ownership is SW */ 1006 rmb(); 1007 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, (ent->ret == -ETIMEDOUT)); 1008 } 1009 } 1010 1011 static const char *deliv_status_to_str(u8 status) 1012 { 1013 switch (status) { 1014 case MLX5_CMD_DELIVERY_STAT_OK: 1015 return "no errors"; 1016 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR: 1017 return "signature error"; 1018 case MLX5_CMD_DELIVERY_STAT_TOK_ERR: 1019 return "token error"; 1020 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR: 1021 return "bad block number"; 1022 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR: 1023 return "output pointer not aligned to block size"; 1024 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR: 1025 return "input pointer not aligned to block size"; 1026 case MLX5_CMD_DELIVERY_STAT_FW_ERR: 1027 return "firmware internal error"; 1028 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR: 1029 return "command input length error"; 1030 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR: 1031 return "command output length error"; 1032 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR: 1033 return "reserved fields not cleared"; 1034 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR: 1035 return "bad command descriptor type"; 1036 default: 1037 return "unknown status code"; 1038 } 1039 } 1040 1041 enum { 1042 MLX5_CMD_TIMEOUT_RECOVER_MSEC = 5 * 1000, 1043 }; 1044 1045 static void wait_func_handle_exec_timeout(struct mlx5_core_dev *dev, 1046 struct mlx5_cmd_work_ent *ent) 1047 { 1048 unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_RECOVER_MSEC); 1049 1050 mlx5_cmd_eq_recover(dev); 1051 1052 /* Re-wait on the ent->done after executing the recovery flow. If the 1053 * recovery flow (or any other recovery flow running simultaneously) 1054 * has recovered an EQE, it should cause the entry to be completed by 1055 * the command interface. 1056 */ 1057 if (wait_for_completion_timeout(&ent->done, timeout)) { 1058 mlx5_core_warn(dev, "cmd[%d]: %s(0x%x) recovered after timeout\n", ent->idx, 1059 mlx5_command_str(msg_to_opcode(ent->in)), msg_to_opcode(ent->in)); 1060 return; 1061 } 1062 1063 mlx5_core_warn(dev, "cmd[%d]: %s(0x%x) No done completion\n", ent->idx, 1064 mlx5_command_str(msg_to_opcode(ent->in)), msg_to_opcode(ent->in)); 1065 1066 ent->ret = -ETIMEDOUT; 1067 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true); 1068 } 1069 1070 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent) 1071 { 1072 unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC); 1073 struct mlx5_cmd *cmd = &dev->cmd; 1074 int err; 1075 1076 if (!wait_for_completion_timeout(&ent->handling, timeout) && 1077 cancel_work_sync(&ent->work)) { 1078 ent->ret = -ECANCELED; 1079 goto out_err; 1080 } 1081 if (cmd->mode == CMD_MODE_POLLING || ent->polling) 1082 wait_for_completion(&ent->done); 1083 else if (!wait_for_completion_timeout(&ent->done, timeout)) 1084 wait_func_handle_exec_timeout(dev, ent); 1085 1086 out_err: 1087 err = ent->ret; 1088 1089 if (err == -ETIMEDOUT) { 1090 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n", 1091 mlx5_command_str(msg_to_opcode(ent->in)), 1092 msg_to_opcode(ent->in)); 1093 } else if (err == -ECANCELED) { 1094 mlx5_core_warn(dev, "%s(0x%x) canceled on out of queue timeout.\n", 1095 mlx5_command_str(msg_to_opcode(ent->in)), 1096 msg_to_opcode(ent->in)); 1097 } 1098 mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n", 1099 err, deliv_status_to_str(ent->status), ent->status); 1100 1101 return err; 1102 } 1103 1104 /* Notes: 1105 * 1. Callback functions may not sleep 1106 * 2. page queue commands do not support asynchrous completion 1107 */ 1108 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in, 1109 struct mlx5_cmd_msg *out, void *uout, int uout_size, 1110 mlx5_cmd_cbk_t callback, 1111 void *context, int page_queue, u8 *status, 1112 u8 token, bool force_polling) 1113 { 1114 struct mlx5_cmd *cmd = &dev->cmd; 1115 struct mlx5_cmd_work_ent *ent; 1116 struct mlx5_cmd_stats *stats; 1117 int err = 0; 1118 s64 ds; 1119 u16 op; 1120 1121 if (callback && page_queue) 1122 return -EINVAL; 1123 1124 ent = cmd_alloc_ent(cmd, in, out, uout, uout_size, 1125 callback, context, page_queue); 1126 if (IS_ERR(ent)) 1127 return PTR_ERR(ent); 1128 1129 /* put for this ent is when consumed, depending on the use case 1130 * 1) (!callback) blocking flow: by caller after wait_func completes 1131 * 2) (callback) flow: by mlx5_cmd_comp_handler() when ent is handled 1132 */ 1133 1134 ent->token = token; 1135 ent->polling = force_polling; 1136 1137 init_completion(&ent->handling); 1138 if (!callback) 1139 init_completion(&ent->done); 1140 1141 INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler); 1142 INIT_WORK(&ent->work, cmd_work_handler); 1143 if (page_queue) { 1144 cmd_work_handler(&ent->work); 1145 } else if (!queue_work(cmd->wq, &ent->work)) { 1146 mlx5_core_warn(dev, "failed to queue work\n"); 1147 err = -ENOMEM; 1148 goto out_free; 1149 } 1150 1151 if (callback) 1152 goto out; /* mlx5_cmd_comp_handler() will put(ent) */ 1153 1154 err = wait_func(dev, ent); 1155 if (err == -ETIMEDOUT || err == -ECANCELED) 1156 goto out_free; 1157 1158 ds = ent->ts2 - ent->ts1; 1159 op = MLX5_GET(mbox_in, in->first.data, opcode); 1160 if (op < MLX5_CMD_OP_MAX) { 1161 stats = &cmd->stats[op]; 1162 spin_lock_irq(&stats->lock); 1163 stats->sum += ds; 1164 ++stats->n; 1165 spin_unlock_irq(&stats->lock); 1166 } 1167 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME, 1168 "fw exec time for %s is %lld nsec\n", 1169 mlx5_command_str(op), ds); 1170 *status = ent->status; 1171 1172 out_free: 1173 cmd_ent_put(ent); 1174 out: 1175 return err; 1176 } 1177 1178 static ssize_t dbg_write(struct file *filp, const char __user *buf, 1179 size_t count, loff_t *pos) 1180 { 1181 struct mlx5_core_dev *dev = filp->private_data; 1182 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg; 1183 char lbuf[3]; 1184 int err; 1185 1186 if (!dbg->in_msg || !dbg->out_msg) 1187 return -ENOMEM; 1188 1189 if (count < sizeof(lbuf) - 1) 1190 return -EINVAL; 1191 1192 if (copy_from_user(lbuf, buf, sizeof(lbuf) - 1)) 1193 return -EFAULT; 1194 1195 lbuf[sizeof(lbuf) - 1] = 0; 1196 1197 if (strcmp(lbuf, "go")) 1198 return -EINVAL; 1199 1200 err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen); 1201 1202 return err ? err : count; 1203 } 1204 1205 static const struct file_operations fops = { 1206 .owner = THIS_MODULE, 1207 .open = simple_open, 1208 .write = dbg_write, 1209 }; 1210 1211 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size, 1212 u8 token) 1213 { 1214 struct mlx5_cmd_prot_block *block; 1215 struct mlx5_cmd_mailbox *next; 1216 int copy; 1217 1218 if (!to || !from) 1219 return -ENOMEM; 1220 1221 copy = min_t(int, size, sizeof(to->first.data)); 1222 memcpy(to->first.data, from, copy); 1223 size -= copy; 1224 from += copy; 1225 1226 next = to->next; 1227 while (size) { 1228 if (!next) { 1229 /* this is a BUG */ 1230 return -ENOMEM; 1231 } 1232 1233 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE); 1234 block = next->buf; 1235 memcpy(block->data, from, copy); 1236 from += copy; 1237 size -= copy; 1238 block->token = token; 1239 next = next->next; 1240 } 1241 1242 return 0; 1243 } 1244 1245 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size) 1246 { 1247 struct mlx5_cmd_prot_block *block; 1248 struct mlx5_cmd_mailbox *next; 1249 int copy; 1250 1251 if (!to || !from) 1252 return -ENOMEM; 1253 1254 copy = min_t(int, size, sizeof(from->first.data)); 1255 memcpy(to, from->first.data, copy); 1256 size -= copy; 1257 to += copy; 1258 1259 next = from->next; 1260 while (size) { 1261 if (!next) { 1262 /* this is a BUG */ 1263 return -ENOMEM; 1264 } 1265 1266 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE); 1267 block = next->buf; 1268 1269 memcpy(to, block->data, copy); 1270 to += copy; 1271 size -= copy; 1272 next = next->next; 1273 } 1274 1275 return 0; 1276 } 1277 1278 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev, 1279 gfp_t flags) 1280 { 1281 struct mlx5_cmd_mailbox *mailbox; 1282 1283 mailbox = kmalloc(sizeof(*mailbox), flags); 1284 if (!mailbox) 1285 return ERR_PTR(-ENOMEM); 1286 1287 mailbox->buf = dma_pool_zalloc(dev->cmd.pool, flags, 1288 &mailbox->dma); 1289 if (!mailbox->buf) { 1290 mlx5_core_dbg(dev, "failed allocation\n"); 1291 kfree(mailbox); 1292 return ERR_PTR(-ENOMEM); 1293 } 1294 mailbox->next = NULL; 1295 1296 return mailbox; 1297 } 1298 1299 static void free_cmd_box(struct mlx5_core_dev *dev, 1300 struct mlx5_cmd_mailbox *mailbox) 1301 { 1302 dma_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma); 1303 kfree(mailbox); 1304 } 1305 1306 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev, 1307 gfp_t flags, int size, 1308 u8 token) 1309 { 1310 struct mlx5_cmd_mailbox *tmp, *head = NULL; 1311 struct mlx5_cmd_prot_block *block; 1312 struct mlx5_cmd_msg *msg; 1313 int err; 1314 int n; 1315 int i; 1316 1317 msg = kzalloc(sizeof(*msg), flags); 1318 if (!msg) 1319 return ERR_PTR(-ENOMEM); 1320 1321 msg->len = size; 1322 n = mlx5_calc_cmd_blocks(msg); 1323 1324 for (i = 0; i < n; i++) { 1325 tmp = alloc_cmd_box(dev, flags); 1326 if (IS_ERR(tmp)) { 1327 mlx5_core_warn(dev, "failed allocating block\n"); 1328 err = PTR_ERR(tmp); 1329 goto err_alloc; 1330 } 1331 1332 block = tmp->buf; 1333 tmp->next = head; 1334 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0); 1335 block->block_num = cpu_to_be32(n - i - 1); 1336 block->token = token; 1337 head = tmp; 1338 } 1339 msg->next = head; 1340 return msg; 1341 1342 err_alloc: 1343 while (head) { 1344 tmp = head->next; 1345 free_cmd_box(dev, head); 1346 head = tmp; 1347 } 1348 kfree(msg); 1349 1350 return ERR_PTR(err); 1351 } 1352 1353 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev, 1354 struct mlx5_cmd_msg *msg) 1355 { 1356 struct mlx5_cmd_mailbox *head = msg->next; 1357 struct mlx5_cmd_mailbox *next; 1358 1359 while (head) { 1360 next = head->next; 1361 free_cmd_box(dev, head); 1362 head = next; 1363 } 1364 kfree(msg); 1365 } 1366 1367 static ssize_t data_write(struct file *filp, const char __user *buf, 1368 size_t count, loff_t *pos) 1369 { 1370 struct mlx5_core_dev *dev = filp->private_data; 1371 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg; 1372 void *ptr; 1373 1374 if (*pos != 0) 1375 return -EINVAL; 1376 1377 kfree(dbg->in_msg); 1378 dbg->in_msg = NULL; 1379 dbg->inlen = 0; 1380 ptr = memdup_user(buf, count); 1381 if (IS_ERR(ptr)) 1382 return PTR_ERR(ptr); 1383 dbg->in_msg = ptr; 1384 dbg->inlen = count; 1385 1386 *pos = count; 1387 1388 return count; 1389 } 1390 1391 static ssize_t data_read(struct file *filp, char __user *buf, size_t count, 1392 loff_t *pos) 1393 { 1394 struct mlx5_core_dev *dev = filp->private_data; 1395 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg; 1396 1397 if (!dbg->out_msg) 1398 return -ENOMEM; 1399 1400 return simple_read_from_buffer(buf, count, pos, dbg->out_msg, 1401 dbg->outlen); 1402 } 1403 1404 static const struct file_operations dfops = { 1405 .owner = THIS_MODULE, 1406 .open = simple_open, 1407 .write = data_write, 1408 .read = data_read, 1409 }; 1410 1411 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count, 1412 loff_t *pos) 1413 { 1414 struct mlx5_core_dev *dev = filp->private_data; 1415 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg; 1416 char outlen[8]; 1417 int err; 1418 1419 err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen); 1420 if (err < 0) 1421 return err; 1422 1423 return simple_read_from_buffer(buf, count, pos, outlen, err); 1424 } 1425 1426 static ssize_t outlen_write(struct file *filp, const char __user *buf, 1427 size_t count, loff_t *pos) 1428 { 1429 struct mlx5_core_dev *dev = filp->private_data; 1430 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg; 1431 char outlen_str[8] = {0}; 1432 int outlen; 1433 void *ptr; 1434 int err; 1435 1436 if (*pos != 0 || count > 6) 1437 return -EINVAL; 1438 1439 kfree(dbg->out_msg); 1440 dbg->out_msg = NULL; 1441 dbg->outlen = 0; 1442 1443 if (copy_from_user(outlen_str, buf, count)) 1444 return -EFAULT; 1445 1446 err = sscanf(outlen_str, "%d", &outlen); 1447 if (err < 0) 1448 return err; 1449 1450 ptr = kzalloc(outlen, GFP_KERNEL); 1451 if (!ptr) 1452 return -ENOMEM; 1453 1454 dbg->out_msg = ptr; 1455 dbg->outlen = outlen; 1456 1457 *pos = count; 1458 1459 return count; 1460 } 1461 1462 static const struct file_operations olfops = { 1463 .owner = THIS_MODULE, 1464 .open = simple_open, 1465 .write = outlen_write, 1466 .read = outlen_read, 1467 }; 1468 1469 static void set_wqname(struct mlx5_core_dev *dev) 1470 { 1471 struct mlx5_cmd *cmd = &dev->cmd; 1472 1473 snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s", 1474 dev_name(dev->device)); 1475 } 1476 1477 static void clean_debug_files(struct mlx5_core_dev *dev) 1478 { 1479 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg; 1480 1481 if (!mlx5_debugfs_root) 1482 return; 1483 1484 mlx5_cmdif_debugfs_cleanup(dev); 1485 debugfs_remove_recursive(dbg->dbg_root); 1486 } 1487 1488 static void create_debugfs_files(struct mlx5_core_dev *dev) 1489 { 1490 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg; 1491 1492 dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root); 1493 1494 debugfs_create_file("in", 0400, dbg->dbg_root, dev, &dfops); 1495 debugfs_create_file("out", 0200, dbg->dbg_root, dev, &dfops); 1496 debugfs_create_file("out_len", 0600, dbg->dbg_root, dev, &olfops); 1497 debugfs_create_u8("status", 0600, dbg->dbg_root, &dbg->status); 1498 debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops); 1499 1500 mlx5_cmdif_debugfs_init(dev); 1501 } 1502 1503 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode) 1504 { 1505 struct mlx5_cmd *cmd = &dev->cmd; 1506 int i; 1507 1508 for (i = 0; i < cmd->max_reg_cmds; i++) 1509 down(&cmd->sem); 1510 down(&cmd->pages_sem); 1511 1512 cmd->allowed_opcode = opcode; 1513 1514 up(&cmd->pages_sem); 1515 for (i = 0; i < cmd->max_reg_cmds; i++) 1516 up(&cmd->sem); 1517 } 1518 1519 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode) 1520 { 1521 struct mlx5_cmd *cmd = &dev->cmd; 1522 int i; 1523 1524 for (i = 0; i < cmd->max_reg_cmds; i++) 1525 down(&cmd->sem); 1526 down(&cmd->pages_sem); 1527 1528 cmd->mode = mode; 1529 1530 up(&cmd->pages_sem); 1531 for (i = 0; i < cmd->max_reg_cmds; i++) 1532 up(&cmd->sem); 1533 } 1534 1535 static int cmd_comp_notifier(struct notifier_block *nb, 1536 unsigned long type, void *data) 1537 { 1538 struct mlx5_core_dev *dev; 1539 struct mlx5_cmd *cmd; 1540 struct mlx5_eqe *eqe; 1541 1542 cmd = mlx5_nb_cof(nb, struct mlx5_cmd, nb); 1543 dev = container_of(cmd, struct mlx5_core_dev, cmd); 1544 eqe = data; 1545 1546 mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector), false); 1547 1548 return NOTIFY_OK; 1549 } 1550 void mlx5_cmd_use_events(struct mlx5_core_dev *dev) 1551 { 1552 MLX5_NB_INIT(&dev->cmd.nb, cmd_comp_notifier, CMD); 1553 mlx5_eq_notifier_register(dev, &dev->cmd.nb); 1554 mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS); 1555 } 1556 1557 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev) 1558 { 1559 mlx5_cmd_change_mod(dev, CMD_MODE_POLLING); 1560 mlx5_eq_notifier_unregister(dev, &dev->cmd.nb); 1561 } 1562 1563 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg) 1564 { 1565 unsigned long flags; 1566 1567 if (msg->parent) { 1568 spin_lock_irqsave(&msg->parent->lock, flags); 1569 list_add_tail(&msg->list, &msg->parent->head); 1570 spin_unlock_irqrestore(&msg->parent->lock, flags); 1571 } else { 1572 mlx5_free_cmd_msg(dev, msg); 1573 } 1574 } 1575 1576 static void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced) 1577 { 1578 struct mlx5_cmd *cmd = &dev->cmd; 1579 struct mlx5_cmd_work_ent *ent; 1580 mlx5_cmd_cbk_t callback; 1581 void *context; 1582 int err; 1583 int i; 1584 s64 ds; 1585 struct mlx5_cmd_stats *stats; 1586 unsigned long flags; 1587 unsigned long vector; 1588 1589 /* there can be at most 32 command queues */ 1590 vector = vec & 0xffffffff; 1591 for (i = 0; i < (1 << cmd->log_sz); i++) { 1592 if (test_bit(i, &vector)) { 1593 struct semaphore *sem; 1594 1595 ent = cmd->ent_arr[i]; 1596 1597 /* if we already completed the command, ignore it */ 1598 if (!test_and_clear_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, 1599 &ent->state)) { 1600 /* only real completion can free the cmd slot */ 1601 if (!forced) { 1602 mlx5_core_err(dev, "Command completion arrived after timeout (entry idx = %d).\n", 1603 ent->idx); 1604 cmd_ent_put(ent); 1605 } 1606 continue; 1607 } 1608 1609 if (ent->callback && cancel_delayed_work(&ent->cb_timeout_work)) 1610 cmd_ent_put(ent); /* timeout work was canceled */ 1611 1612 if (!forced || /* Real FW completion */ 1613 pci_channel_offline(dev->pdev) || /* FW is inaccessible */ 1614 dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) 1615 cmd_ent_put(ent); 1616 1617 if (ent->page_queue) 1618 sem = &cmd->pages_sem; 1619 else 1620 sem = &cmd->sem; 1621 ent->ts2 = ktime_get_ns(); 1622 memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out)); 1623 dump_command(dev, ent, 0); 1624 if (!ent->ret) { 1625 if (!cmd->checksum_disabled) 1626 ent->ret = verify_signature(ent); 1627 else 1628 ent->ret = 0; 1629 if (vec & MLX5_TRIGGERED_CMD_COMP) 1630 ent->status = MLX5_DRIVER_STATUS_ABORTED; 1631 else 1632 ent->status = ent->lay->status_own >> 1; 1633 1634 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n", 1635 ent->ret, deliv_status_to_str(ent->status), ent->status); 1636 } 1637 1638 if (ent->callback) { 1639 ds = ent->ts2 - ent->ts1; 1640 if (ent->op < MLX5_CMD_OP_MAX) { 1641 stats = &cmd->stats[ent->op]; 1642 spin_lock_irqsave(&stats->lock, flags); 1643 stats->sum += ds; 1644 ++stats->n; 1645 spin_unlock_irqrestore(&stats->lock, flags); 1646 } 1647 1648 callback = ent->callback; 1649 context = ent->context; 1650 err = ent->ret; 1651 if (!err) { 1652 err = mlx5_copy_from_msg(ent->uout, 1653 ent->out, 1654 ent->uout_size); 1655 1656 err = err ? err : mlx5_cmd_check(dev, 1657 ent->in->first.data, 1658 ent->uout); 1659 } 1660 1661 mlx5_free_cmd_msg(dev, ent->out); 1662 free_msg(dev, ent->in); 1663 1664 err = err ? err : ent->status; 1665 /* final consumer is done, release ent */ 1666 cmd_ent_put(ent); 1667 callback(err, context); 1668 } else { 1669 /* release wait_func() so mlx5_cmd_invoke() 1670 * can make the final ent_put() 1671 */ 1672 complete(&ent->done); 1673 } 1674 up(sem); 1675 } 1676 } 1677 } 1678 1679 void mlx5_cmd_trigger_completions(struct mlx5_core_dev *dev) 1680 { 1681 struct mlx5_cmd *cmd = &dev->cmd; 1682 unsigned long bitmask; 1683 unsigned long flags; 1684 u64 vector; 1685 int i; 1686 1687 /* wait for pending handlers to complete */ 1688 mlx5_eq_synchronize_cmd_irq(dev); 1689 spin_lock_irqsave(&dev->cmd.alloc_lock, flags); 1690 vector = ~dev->cmd.bitmask & ((1ul << (1 << dev->cmd.log_sz)) - 1); 1691 if (!vector) 1692 goto no_trig; 1693 1694 bitmask = vector; 1695 /* we must increment the allocated entries refcount before triggering the completions 1696 * to guarantee pending commands will not get freed in the meanwhile. 1697 * For that reason, it also has to be done inside the alloc_lock. 1698 */ 1699 for_each_set_bit(i, &bitmask, (1 << cmd->log_sz)) 1700 cmd_ent_get(cmd->ent_arr[i]); 1701 vector |= MLX5_TRIGGERED_CMD_COMP; 1702 spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags); 1703 1704 mlx5_core_dbg(dev, "vector 0x%llx\n", vector); 1705 mlx5_cmd_comp_handler(dev, vector, true); 1706 for_each_set_bit(i, &bitmask, (1 << cmd->log_sz)) 1707 cmd_ent_put(cmd->ent_arr[i]); 1708 return; 1709 1710 no_trig: 1711 spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags); 1712 } 1713 1714 void mlx5_cmd_flush(struct mlx5_core_dev *dev) 1715 { 1716 struct mlx5_cmd *cmd = &dev->cmd; 1717 int i; 1718 1719 for (i = 0; i < cmd->max_reg_cmds; i++) 1720 while (down_trylock(&cmd->sem)) 1721 mlx5_cmd_trigger_completions(dev); 1722 1723 while (down_trylock(&cmd->pages_sem)) 1724 mlx5_cmd_trigger_completions(dev); 1725 1726 /* Unlock cmdif */ 1727 up(&cmd->pages_sem); 1728 for (i = 0; i < cmd->max_reg_cmds; i++) 1729 up(&cmd->sem); 1730 } 1731 1732 static int status_to_err(u8 status) 1733 { 1734 switch (status) { 1735 case MLX5_CMD_DELIVERY_STAT_OK: 1736 case MLX5_DRIVER_STATUS_ABORTED: 1737 return 0; 1738 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR: 1739 case MLX5_CMD_DELIVERY_STAT_TOK_ERR: 1740 return -EBADR; 1741 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR: 1742 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR: 1743 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR: 1744 return -EFAULT; /* Bad address */ 1745 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR: 1746 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR: 1747 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR: 1748 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR: 1749 return -ENOMSG; 1750 case MLX5_CMD_DELIVERY_STAT_FW_ERR: 1751 return -EIO; 1752 default: 1753 return -EINVAL; 1754 } 1755 } 1756 1757 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size, 1758 gfp_t gfp) 1759 { 1760 struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM); 1761 struct cmd_msg_cache *ch = NULL; 1762 struct mlx5_cmd *cmd = &dev->cmd; 1763 int i; 1764 1765 if (in_size <= 16) 1766 goto cache_miss; 1767 1768 for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) { 1769 ch = &cmd->cache[i]; 1770 if (in_size > ch->max_inbox_size) 1771 continue; 1772 spin_lock_irq(&ch->lock); 1773 if (list_empty(&ch->head)) { 1774 spin_unlock_irq(&ch->lock); 1775 continue; 1776 } 1777 msg = list_entry(ch->head.next, typeof(*msg), list); 1778 /* For cached lists, we must explicitly state what is 1779 * the real size 1780 */ 1781 msg->len = in_size; 1782 list_del(&msg->list); 1783 spin_unlock_irq(&ch->lock); 1784 break; 1785 } 1786 1787 if (!IS_ERR(msg)) 1788 return msg; 1789 1790 cache_miss: 1791 msg = mlx5_alloc_cmd_msg(dev, gfp, in_size, 0); 1792 return msg; 1793 } 1794 1795 static int is_manage_pages(void *in) 1796 { 1797 return MLX5_GET(mbox_in, in, opcode) == MLX5_CMD_OP_MANAGE_PAGES; 1798 } 1799 1800 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 1801 int out_size, mlx5_cmd_cbk_t callback, void *context, 1802 bool force_polling) 1803 { 1804 struct mlx5_cmd_msg *inb; 1805 struct mlx5_cmd_msg *outb; 1806 int pages_queue; 1807 gfp_t gfp; 1808 int err; 1809 u8 status = 0; 1810 u32 drv_synd; 1811 u16 opcode; 1812 u8 token; 1813 1814 opcode = MLX5_GET(mbox_in, in, opcode); 1815 if (mlx5_cmd_is_down(dev) || !opcode_allowed(&dev->cmd, opcode)) { 1816 err = mlx5_internal_err_ret_value(dev, opcode, &drv_synd, &status); 1817 MLX5_SET(mbox_out, out, status, status); 1818 MLX5_SET(mbox_out, out, syndrome, drv_synd); 1819 return err; 1820 } 1821 1822 pages_queue = is_manage_pages(in); 1823 gfp = callback ? GFP_ATOMIC : GFP_KERNEL; 1824 1825 inb = alloc_msg(dev, in_size, gfp); 1826 if (IS_ERR(inb)) { 1827 err = PTR_ERR(inb); 1828 return err; 1829 } 1830 1831 token = alloc_token(&dev->cmd); 1832 1833 err = mlx5_copy_to_msg(inb, in, in_size, token); 1834 if (err) { 1835 mlx5_core_warn(dev, "err %d\n", err); 1836 goto out_in; 1837 } 1838 1839 outb = mlx5_alloc_cmd_msg(dev, gfp, out_size, token); 1840 if (IS_ERR(outb)) { 1841 err = PTR_ERR(outb); 1842 goto out_in; 1843 } 1844 1845 err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context, 1846 pages_queue, &status, token, force_polling); 1847 if (err) 1848 goto out_out; 1849 1850 mlx5_core_dbg(dev, "err %d, status %d\n", err, status); 1851 if (status) { 1852 err = status_to_err(status); 1853 goto out_out; 1854 } 1855 1856 if (!callback) 1857 err = mlx5_copy_from_msg(out, outb, out_size); 1858 1859 out_out: 1860 if (!callback) 1861 mlx5_free_cmd_msg(dev, outb); 1862 1863 out_in: 1864 if (!callback) 1865 free_msg(dev, inb); 1866 return err; 1867 } 1868 1869 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 1870 int out_size) 1871 { 1872 int err; 1873 1874 err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, false); 1875 return err ? : mlx5_cmd_check(dev, in, out); 1876 } 1877 EXPORT_SYMBOL(mlx5_cmd_exec); 1878 1879 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev, 1880 struct mlx5_async_ctx *ctx) 1881 { 1882 ctx->dev = dev; 1883 /* Starts at 1 to avoid doing wake_up if we are not cleaning up */ 1884 atomic_set(&ctx->num_inflight, 1); 1885 init_waitqueue_head(&ctx->wait); 1886 } 1887 EXPORT_SYMBOL(mlx5_cmd_init_async_ctx); 1888 1889 /** 1890 * mlx5_cmd_cleanup_async_ctx - Clean up an async_ctx 1891 * @ctx: The ctx to clean 1892 * 1893 * Upon return all callbacks given to mlx5_cmd_exec_cb() have been called. The 1894 * caller must ensure that mlx5_cmd_exec_cb() is not called during or after 1895 * the call mlx5_cleanup_async_ctx(). 1896 */ 1897 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx) 1898 { 1899 atomic_dec(&ctx->num_inflight); 1900 wait_event(ctx->wait, atomic_read(&ctx->num_inflight) == 0); 1901 } 1902 EXPORT_SYMBOL(mlx5_cmd_cleanup_async_ctx); 1903 1904 static void mlx5_cmd_exec_cb_handler(int status, void *_work) 1905 { 1906 struct mlx5_async_work *work = _work; 1907 struct mlx5_async_ctx *ctx = work->ctx; 1908 1909 work->user_callback(status, work); 1910 if (atomic_dec_and_test(&ctx->num_inflight)) 1911 wake_up(&ctx->wait); 1912 } 1913 1914 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size, 1915 void *out, int out_size, mlx5_async_cbk_t callback, 1916 struct mlx5_async_work *work) 1917 { 1918 int ret; 1919 1920 work->ctx = ctx; 1921 work->user_callback = callback; 1922 if (WARN_ON(!atomic_inc_not_zero(&ctx->num_inflight))) 1923 return -EIO; 1924 ret = cmd_exec(ctx->dev, in, in_size, out, out_size, 1925 mlx5_cmd_exec_cb_handler, work, false); 1926 if (ret && atomic_dec_and_test(&ctx->num_inflight)) 1927 wake_up(&ctx->wait); 1928 1929 return ret; 1930 } 1931 EXPORT_SYMBOL(mlx5_cmd_exec_cb); 1932 1933 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, 1934 void *out, int out_size) 1935 { 1936 int err; 1937 1938 err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, true); 1939 1940 return err ? : mlx5_cmd_check(dev, in, out); 1941 } 1942 EXPORT_SYMBOL(mlx5_cmd_exec_polling); 1943 1944 static void destroy_msg_cache(struct mlx5_core_dev *dev) 1945 { 1946 struct cmd_msg_cache *ch; 1947 struct mlx5_cmd_msg *msg; 1948 struct mlx5_cmd_msg *n; 1949 int i; 1950 1951 for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) { 1952 ch = &dev->cmd.cache[i]; 1953 list_for_each_entry_safe(msg, n, &ch->head, list) { 1954 list_del(&msg->list); 1955 mlx5_free_cmd_msg(dev, msg); 1956 } 1957 } 1958 } 1959 1960 static unsigned cmd_cache_num_ent[MLX5_NUM_COMMAND_CACHES] = { 1961 512, 32, 16, 8, 2 1962 }; 1963 1964 static unsigned cmd_cache_ent_size[MLX5_NUM_COMMAND_CACHES] = { 1965 16 + MLX5_CMD_DATA_BLOCK_SIZE, 1966 16 + MLX5_CMD_DATA_BLOCK_SIZE * 2, 1967 16 + MLX5_CMD_DATA_BLOCK_SIZE * 16, 1968 16 + MLX5_CMD_DATA_BLOCK_SIZE * 256, 1969 16 + MLX5_CMD_DATA_BLOCK_SIZE * 512, 1970 }; 1971 1972 static void create_msg_cache(struct mlx5_core_dev *dev) 1973 { 1974 struct mlx5_cmd *cmd = &dev->cmd; 1975 struct cmd_msg_cache *ch; 1976 struct mlx5_cmd_msg *msg; 1977 int i; 1978 int k; 1979 1980 /* Initialize and fill the caches with initial entries */ 1981 for (k = 0; k < MLX5_NUM_COMMAND_CACHES; k++) { 1982 ch = &cmd->cache[k]; 1983 spin_lock_init(&ch->lock); 1984 INIT_LIST_HEAD(&ch->head); 1985 ch->num_ent = cmd_cache_num_ent[k]; 1986 ch->max_inbox_size = cmd_cache_ent_size[k]; 1987 for (i = 0; i < ch->num_ent; i++) { 1988 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL | __GFP_NOWARN, 1989 ch->max_inbox_size, 0); 1990 if (IS_ERR(msg)) 1991 break; 1992 msg->parent = ch; 1993 list_add_tail(&msg->list, &ch->head); 1994 } 1995 } 1996 } 1997 1998 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd) 1999 { 2000 cmd->cmd_alloc_buf = dma_alloc_coherent(mlx5_core_dma_dev(dev), MLX5_ADAPTER_PAGE_SIZE, 2001 &cmd->alloc_dma, GFP_KERNEL); 2002 if (!cmd->cmd_alloc_buf) 2003 return -ENOMEM; 2004 2005 /* make sure it is aligned to 4K */ 2006 if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) { 2007 cmd->cmd_buf = cmd->cmd_alloc_buf; 2008 cmd->dma = cmd->alloc_dma; 2009 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE; 2010 return 0; 2011 } 2012 2013 dma_free_coherent(mlx5_core_dma_dev(dev), MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf, 2014 cmd->alloc_dma); 2015 cmd->cmd_alloc_buf = dma_alloc_coherent(mlx5_core_dma_dev(dev), 2016 2 * MLX5_ADAPTER_PAGE_SIZE - 1, 2017 &cmd->alloc_dma, GFP_KERNEL); 2018 if (!cmd->cmd_alloc_buf) 2019 return -ENOMEM; 2020 2021 cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE); 2022 cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE); 2023 cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1; 2024 return 0; 2025 } 2026 2027 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd) 2028 { 2029 dma_free_coherent(mlx5_core_dma_dev(dev), cmd->alloc_size, cmd->cmd_alloc_buf, 2030 cmd->alloc_dma); 2031 } 2032 2033 static u16 cmdif_rev(struct mlx5_core_dev *dev) 2034 { 2035 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 2036 } 2037 2038 int mlx5_cmd_init(struct mlx5_core_dev *dev) 2039 { 2040 int size = sizeof(struct mlx5_cmd_prot_block); 2041 int align = roundup_pow_of_two(size); 2042 struct mlx5_cmd *cmd = &dev->cmd; 2043 u32 cmd_h, cmd_l; 2044 u16 cmd_if_rev; 2045 int err; 2046 int i; 2047 2048 memset(cmd, 0, sizeof(*cmd)); 2049 cmd_if_rev = cmdif_rev(dev); 2050 if (cmd_if_rev != CMD_IF_REV) { 2051 mlx5_core_err(dev, 2052 "Driver cmdif rev(%d) differs from firmware's(%d)\n", 2053 CMD_IF_REV, cmd_if_rev); 2054 return -EINVAL; 2055 } 2056 2057 cmd->stats = kvzalloc(MLX5_CMD_OP_MAX * sizeof(*cmd->stats), GFP_KERNEL); 2058 if (!cmd->stats) 2059 return -ENOMEM; 2060 2061 cmd->pool = dma_pool_create("mlx5_cmd", mlx5_core_dma_dev(dev), size, align, 0); 2062 if (!cmd->pool) { 2063 err = -ENOMEM; 2064 goto dma_pool_err; 2065 } 2066 2067 err = alloc_cmd_page(dev, cmd); 2068 if (err) 2069 goto err_free_pool; 2070 2071 cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff; 2072 cmd->log_sz = cmd_l >> 4 & 0xf; 2073 cmd->log_stride = cmd_l & 0xf; 2074 if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) { 2075 mlx5_core_err(dev, "firmware reports too many outstanding commands %d\n", 2076 1 << cmd->log_sz); 2077 err = -EINVAL; 2078 goto err_free_page; 2079 } 2080 2081 if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) { 2082 mlx5_core_err(dev, "command queue size overflow\n"); 2083 err = -EINVAL; 2084 goto err_free_page; 2085 } 2086 2087 cmd->state = MLX5_CMDIF_STATE_DOWN; 2088 cmd->checksum_disabled = 1; 2089 cmd->max_reg_cmds = (1 << cmd->log_sz) - 1; 2090 cmd->bitmask = (1UL << cmd->max_reg_cmds) - 1; 2091 2092 cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 2093 if (cmd->cmdif_rev > CMD_IF_REV) { 2094 mlx5_core_err(dev, "driver does not support command interface version. driver %d, firmware %d\n", 2095 CMD_IF_REV, cmd->cmdif_rev); 2096 err = -EOPNOTSUPP; 2097 goto err_free_page; 2098 } 2099 2100 spin_lock_init(&cmd->alloc_lock); 2101 spin_lock_init(&cmd->token_lock); 2102 for (i = 0; i < MLX5_CMD_OP_MAX; i++) 2103 spin_lock_init(&cmd->stats[i].lock); 2104 2105 sema_init(&cmd->sem, cmd->max_reg_cmds); 2106 sema_init(&cmd->pages_sem, 1); 2107 2108 cmd_h = (u32)((u64)(cmd->dma) >> 32); 2109 cmd_l = (u32)(cmd->dma); 2110 if (cmd_l & 0xfff) { 2111 mlx5_core_err(dev, "invalid command queue address\n"); 2112 err = -ENOMEM; 2113 goto err_free_page; 2114 } 2115 2116 iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h); 2117 iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz); 2118 2119 /* Make sure firmware sees the complete address before we proceed */ 2120 wmb(); 2121 2122 mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma)); 2123 2124 cmd->mode = CMD_MODE_POLLING; 2125 cmd->allowed_opcode = CMD_ALLOWED_OPCODE_ALL; 2126 2127 create_msg_cache(dev); 2128 2129 set_wqname(dev); 2130 cmd->wq = create_singlethread_workqueue(cmd->wq_name); 2131 if (!cmd->wq) { 2132 mlx5_core_err(dev, "failed to create command workqueue\n"); 2133 err = -ENOMEM; 2134 goto err_cache; 2135 } 2136 2137 create_debugfs_files(dev); 2138 2139 return 0; 2140 2141 err_cache: 2142 destroy_msg_cache(dev); 2143 2144 err_free_page: 2145 free_cmd_page(dev, cmd); 2146 2147 err_free_pool: 2148 dma_pool_destroy(cmd->pool); 2149 dma_pool_err: 2150 kvfree(cmd->stats); 2151 return err; 2152 } 2153 2154 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev) 2155 { 2156 struct mlx5_cmd *cmd = &dev->cmd; 2157 2158 clean_debug_files(dev); 2159 destroy_workqueue(cmd->wq); 2160 destroy_msg_cache(dev); 2161 free_cmd_page(dev, cmd); 2162 dma_pool_destroy(cmd->pool); 2163 kvfree(cmd->stats); 2164 } 2165 2166 void mlx5_cmd_set_state(struct mlx5_core_dev *dev, 2167 enum mlx5_cmdif_state cmdif_state) 2168 { 2169 dev->cmd.state = cmdif_state; 2170 } 2171