1 /* 2 * Copyright (c) 2004 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 5 * Copyright (c) 2004 Voltaire, Inc. All rights reserved. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * OpenIB.org BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or 14 * without modification, are permitted provided that the following 15 * conditions are met: 16 * 17 * - Redistributions of source code must retain the above 18 * copyright notice, this list of conditions and the following 19 * disclaimer. 20 * 21 * - Redistributions in binary form must reproduce the above 22 * copyright notice, this list of conditions and the following 23 * disclaimer in the documentation and/or other materials 24 * provided with the distribution. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 33 * SOFTWARE. 34 */ 35 36 #include <linux/gfp.h> 37 #include <linux/export.h> 38 #include <linux/init.h> 39 40 #include <linux/mlx4/cmd.h> 41 #include <linux/mlx4/qp.h> 42 43 #include "mlx4.h" 44 #include "icm.h" 45 46 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type) 47 { 48 struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table; 49 struct mlx4_qp *qp; 50 51 spin_lock(&qp_table->lock); 52 53 qp = __mlx4_qp_lookup(dev, qpn); 54 if (qp) 55 atomic_inc(&qp->refcount); 56 57 spin_unlock(&qp_table->lock); 58 59 if (!qp) { 60 mlx4_dbg(dev, "Async event for none existent QP %08x\n", qpn); 61 return; 62 } 63 64 qp->event(qp, event_type); 65 66 if (atomic_dec_and_test(&qp->refcount)) 67 complete(&qp->free); 68 } 69 70 static int is_qp0(struct mlx4_dev *dev, struct mlx4_qp *qp) 71 { 72 return qp->qpn >= dev->caps.sqp_start && 73 qp->qpn <= dev->caps.sqp_start + 1; 74 } 75 76 static int __mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 77 enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state, 78 struct mlx4_qp_context *context, 79 enum mlx4_qp_optpar optpar, 80 int sqd_event, struct mlx4_qp *qp, int native) 81 { 82 static const u16 op[MLX4_QP_NUM_STATE][MLX4_QP_NUM_STATE] = { 83 [MLX4_QP_STATE_RST] = { 84 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP, 85 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP, 86 [MLX4_QP_STATE_INIT] = MLX4_CMD_RST2INIT_QP, 87 }, 88 [MLX4_QP_STATE_INIT] = { 89 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP, 90 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP, 91 [MLX4_QP_STATE_INIT] = MLX4_CMD_INIT2INIT_QP, 92 [MLX4_QP_STATE_RTR] = MLX4_CMD_INIT2RTR_QP, 93 }, 94 [MLX4_QP_STATE_RTR] = { 95 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP, 96 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP, 97 [MLX4_QP_STATE_RTS] = MLX4_CMD_RTR2RTS_QP, 98 }, 99 [MLX4_QP_STATE_RTS] = { 100 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP, 101 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP, 102 [MLX4_QP_STATE_RTS] = MLX4_CMD_RTS2RTS_QP, 103 [MLX4_QP_STATE_SQD] = MLX4_CMD_RTS2SQD_QP, 104 }, 105 [MLX4_QP_STATE_SQD] = { 106 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP, 107 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP, 108 [MLX4_QP_STATE_RTS] = MLX4_CMD_SQD2RTS_QP, 109 [MLX4_QP_STATE_SQD] = MLX4_CMD_SQD2SQD_QP, 110 }, 111 [MLX4_QP_STATE_SQER] = { 112 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP, 113 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP, 114 [MLX4_QP_STATE_RTS] = MLX4_CMD_SQERR2RTS_QP, 115 }, 116 [MLX4_QP_STATE_ERR] = { 117 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP, 118 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP, 119 } 120 }; 121 122 struct mlx4_priv *priv = mlx4_priv(dev); 123 struct mlx4_cmd_mailbox *mailbox; 124 int ret = 0; 125 u8 port; 126 127 if (cur_state >= MLX4_QP_NUM_STATE || new_state >= MLX4_QP_NUM_STATE || 128 !op[cur_state][new_state]) 129 return -EINVAL; 130 131 if (op[cur_state][new_state] == MLX4_CMD_2RST_QP) { 132 ret = mlx4_cmd(dev, 0, qp->qpn, 2, 133 MLX4_CMD_2RST_QP, MLX4_CMD_TIME_CLASS_A, native); 134 if (mlx4_is_master(dev) && cur_state != MLX4_QP_STATE_ERR && 135 cur_state != MLX4_QP_STATE_RST && 136 is_qp0(dev, qp)) { 137 port = (qp->qpn & 1) + 1; 138 priv->mfunc.master.qp0_state[port].qp0_active = 0; 139 } 140 return ret; 141 } 142 143 mailbox = mlx4_alloc_cmd_mailbox(dev); 144 if (IS_ERR(mailbox)) 145 return PTR_ERR(mailbox); 146 147 if (cur_state == MLX4_QP_STATE_RST && new_state == MLX4_QP_STATE_INIT) { 148 u64 mtt_addr = mlx4_mtt_addr(dev, mtt); 149 context->mtt_base_addr_h = mtt_addr >> 32; 150 context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff); 151 context->log_page_size = mtt->page_shift - MLX4_ICM_PAGE_SHIFT; 152 } 153 154 *(__be32 *) mailbox->buf = cpu_to_be32(optpar); 155 memcpy(mailbox->buf + 8, context, sizeof *context); 156 157 ((struct mlx4_qp_context *) (mailbox->buf + 8))->local_qpn = 158 cpu_to_be32(qp->qpn); 159 160 ret = mlx4_cmd(dev, mailbox->dma, 161 qp->qpn | (!!sqd_event << 31), 162 new_state == MLX4_QP_STATE_RST ? 2 : 0, 163 op[cur_state][new_state], MLX4_CMD_TIME_CLASS_C, native); 164 165 mlx4_free_cmd_mailbox(dev, mailbox); 166 return ret; 167 } 168 169 int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 170 enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state, 171 struct mlx4_qp_context *context, 172 enum mlx4_qp_optpar optpar, 173 int sqd_event, struct mlx4_qp *qp) 174 { 175 return __mlx4_qp_modify(dev, mtt, cur_state, new_state, context, 176 optpar, sqd_event, qp, 0); 177 } 178 EXPORT_SYMBOL_GPL(mlx4_qp_modify); 179 180 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 181 int *base) 182 { 183 struct mlx4_priv *priv = mlx4_priv(dev); 184 struct mlx4_qp_table *qp_table = &priv->qp_table; 185 186 *base = mlx4_bitmap_alloc_range(&qp_table->bitmap, cnt, align); 187 if (*base == -1) 188 return -ENOMEM; 189 190 return 0; 191 } 192 193 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base) 194 { 195 u64 in_param; 196 u64 out_param; 197 int err; 198 199 if (mlx4_is_mfunc(dev)) { 200 set_param_l(&in_param, cnt); 201 set_param_h(&in_param, align); 202 err = mlx4_cmd_imm(dev, in_param, &out_param, 203 RES_QP, RES_OP_RESERVE, 204 MLX4_CMD_ALLOC_RES, 205 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 206 if (err) 207 return err; 208 209 *base = get_param_l(&out_param); 210 return 0; 211 } 212 return __mlx4_qp_reserve_range(dev, cnt, align, base); 213 } 214 EXPORT_SYMBOL_GPL(mlx4_qp_reserve_range); 215 216 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt) 217 { 218 struct mlx4_priv *priv = mlx4_priv(dev); 219 struct mlx4_qp_table *qp_table = &priv->qp_table; 220 221 if (mlx4_is_qp_reserved(dev, (u32) base_qpn)) 222 return; 223 mlx4_bitmap_free_range(&qp_table->bitmap, base_qpn, cnt); 224 } 225 226 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt) 227 { 228 u64 in_param; 229 int err; 230 231 if (mlx4_is_mfunc(dev)) { 232 set_param_l(&in_param, base_qpn); 233 set_param_h(&in_param, cnt); 234 err = mlx4_cmd(dev, in_param, RES_QP, RES_OP_RESERVE, 235 MLX4_CMD_FREE_RES, 236 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 237 if (err) { 238 mlx4_warn(dev, "Failed to release qp range" 239 " base:%d cnt:%d\n", base_qpn, cnt); 240 } 241 } else 242 __mlx4_qp_release_range(dev, base_qpn, cnt); 243 } 244 EXPORT_SYMBOL_GPL(mlx4_qp_release_range); 245 246 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn) 247 { 248 struct mlx4_priv *priv = mlx4_priv(dev); 249 struct mlx4_qp_table *qp_table = &priv->qp_table; 250 int err; 251 252 err = mlx4_table_get(dev, &qp_table->qp_table, qpn); 253 if (err) 254 goto err_out; 255 256 err = mlx4_table_get(dev, &qp_table->auxc_table, qpn); 257 if (err) 258 goto err_put_qp; 259 260 err = mlx4_table_get(dev, &qp_table->altc_table, qpn); 261 if (err) 262 goto err_put_auxc; 263 264 err = mlx4_table_get(dev, &qp_table->rdmarc_table, qpn); 265 if (err) 266 goto err_put_altc; 267 268 err = mlx4_table_get(dev, &qp_table->cmpt_table, qpn); 269 if (err) 270 goto err_put_rdmarc; 271 272 return 0; 273 274 err_put_rdmarc: 275 mlx4_table_put(dev, &qp_table->rdmarc_table, qpn); 276 277 err_put_altc: 278 mlx4_table_put(dev, &qp_table->altc_table, qpn); 279 280 err_put_auxc: 281 mlx4_table_put(dev, &qp_table->auxc_table, qpn); 282 283 err_put_qp: 284 mlx4_table_put(dev, &qp_table->qp_table, qpn); 285 286 err_out: 287 return err; 288 } 289 290 static int mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn) 291 { 292 u64 param; 293 294 if (mlx4_is_mfunc(dev)) { 295 set_param_l(¶m, qpn); 296 return mlx4_cmd_imm(dev, param, ¶m, RES_QP, RES_OP_MAP_ICM, 297 MLX4_CMD_ALLOC_RES, MLX4_CMD_TIME_CLASS_A, 298 MLX4_CMD_WRAPPED); 299 } 300 return __mlx4_qp_alloc_icm(dev, qpn); 301 } 302 303 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn) 304 { 305 struct mlx4_priv *priv = mlx4_priv(dev); 306 struct mlx4_qp_table *qp_table = &priv->qp_table; 307 308 mlx4_table_put(dev, &qp_table->cmpt_table, qpn); 309 mlx4_table_put(dev, &qp_table->rdmarc_table, qpn); 310 mlx4_table_put(dev, &qp_table->altc_table, qpn); 311 mlx4_table_put(dev, &qp_table->auxc_table, qpn); 312 mlx4_table_put(dev, &qp_table->qp_table, qpn); 313 } 314 315 static void mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn) 316 { 317 u64 in_param; 318 319 if (mlx4_is_mfunc(dev)) { 320 set_param_l(&in_param, qpn); 321 if (mlx4_cmd(dev, in_param, RES_QP, RES_OP_MAP_ICM, 322 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A, 323 MLX4_CMD_WRAPPED)) 324 mlx4_warn(dev, "Failed to free icm of qp:%d\n", qpn); 325 } else 326 __mlx4_qp_free_icm(dev, qpn); 327 } 328 329 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp) 330 { 331 struct mlx4_priv *priv = mlx4_priv(dev); 332 struct mlx4_qp_table *qp_table = &priv->qp_table; 333 int err; 334 335 if (!qpn) 336 return -EINVAL; 337 338 qp->qpn = qpn; 339 340 err = mlx4_qp_alloc_icm(dev, qpn); 341 if (err) 342 return err; 343 344 spin_lock_irq(&qp_table->lock); 345 err = radix_tree_insert(&dev->qp_table_tree, qp->qpn & 346 (dev->caps.num_qps - 1), qp); 347 spin_unlock_irq(&qp_table->lock); 348 if (err) 349 goto err_icm; 350 351 atomic_set(&qp->refcount, 1); 352 init_completion(&qp->free); 353 354 return 0; 355 356 err_icm: 357 mlx4_qp_free_icm(dev, qpn); 358 return err; 359 } 360 361 EXPORT_SYMBOL_GPL(mlx4_qp_alloc); 362 363 void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp) 364 { 365 struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table; 366 unsigned long flags; 367 368 spin_lock_irqsave(&qp_table->lock, flags); 369 radix_tree_delete(&dev->qp_table_tree, qp->qpn & (dev->caps.num_qps - 1)); 370 spin_unlock_irqrestore(&qp_table->lock, flags); 371 } 372 EXPORT_SYMBOL_GPL(mlx4_qp_remove); 373 374 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp) 375 { 376 if (atomic_dec_and_test(&qp->refcount)) 377 complete(&qp->free); 378 wait_for_completion(&qp->free); 379 380 mlx4_qp_free_icm(dev, qp->qpn); 381 } 382 EXPORT_SYMBOL_GPL(mlx4_qp_free); 383 384 static int mlx4_CONF_SPECIAL_QP(struct mlx4_dev *dev, u32 base_qpn) 385 { 386 return mlx4_cmd(dev, 0, base_qpn, 0, MLX4_CMD_CONF_SPECIAL_QP, 387 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); 388 } 389 390 int mlx4_init_qp_table(struct mlx4_dev *dev) 391 { 392 struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table; 393 int err; 394 int reserved_from_top = 0; 395 396 spin_lock_init(&qp_table->lock); 397 INIT_RADIX_TREE(&dev->qp_table_tree, GFP_ATOMIC); 398 if (mlx4_is_slave(dev)) 399 return 0; 400 401 /* 402 * We reserve 2 extra QPs per port for the special QPs. The 403 * block of special QPs must be aligned to a multiple of 8, so 404 * round up. 405 * 406 * We also reserve the MSB of the 24-bit QP number to indicate 407 * that a QP is an XRC QP. 408 */ 409 dev->caps.sqp_start = 410 ALIGN(dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 8); 411 412 { 413 int sort[MLX4_NUM_QP_REGION]; 414 int i, j, tmp; 415 int last_base = dev->caps.num_qps; 416 417 for (i = 1; i < MLX4_NUM_QP_REGION; ++i) 418 sort[i] = i; 419 420 for (i = MLX4_NUM_QP_REGION; i > 0; --i) { 421 for (j = 2; j < i; ++j) { 422 if (dev->caps.reserved_qps_cnt[sort[j]] > 423 dev->caps.reserved_qps_cnt[sort[j - 1]]) { 424 tmp = sort[j]; 425 sort[j] = sort[j - 1]; 426 sort[j - 1] = tmp; 427 } 428 } 429 } 430 431 for (i = 1; i < MLX4_NUM_QP_REGION; ++i) { 432 last_base -= dev->caps.reserved_qps_cnt[sort[i]]; 433 dev->caps.reserved_qps_base[sort[i]] = last_base; 434 reserved_from_top += 435 dev->caps.reserved_qps_cnt[sort[i]]; 436 } 437 438 } 439 440 err = mlx4_bitmap_init(&qp_table->bitmap, dev->caps.num_qps, 441 (1 << 23) - 1, dev->caps.sqp_start + 8, 442 reserved_from_top); 443 if (err) 444 return err; 445 446 return mlx4_CONF_SPECIAL_QP(dev, dev->caps.sqp_start); 447 } 448 449 void mlx4_cleanup_qp_table(struct mlx4_dev *dev) 450 { 451 if (mlx4_is_slave(dev)) 452 return; 453 454 mlx4_CONF_SPECIAL_QP(dev, 0); 455 mlx4_bitmap_cleanup(&mlx4_priv(dev)->qp_table.bitmap); 456 } 457 458 int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp, 459 struct mlx4_qp_context *context) 460 { 461 struct mlx4_cmd_mailbox *mailbox; 462 int err; 463 464 mailbox = mlx4_alloc_cmd_mailbox(dev); 465 if (IS_ERR(mailbox)) 466 return PTR_ERR(mailbox); 467 468 err = mlx4_cmd_box(dev, 0, mailbox->dma, qp->qpn, 0, 469 MLX4_CMD_QUERY_QP, MLX4_CMD_TIME_CLASS_A, 470 MLX4_CMD_WRAPPED); 471 if (!err) 472 memcpy(context, mailbox->buf + 8, sizeof *context); 473 474 mlx4_free_cmd_mailbox(dev, mailbox); 475 return err; 476 } 477 EXPORT_SYMBOL_GPL(mlx4_qp_query); 478 479 int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 480 struct mlx4_qp_context *context, 481 struct mlx4_qp *qp, enum mlx4_qp_state *qp_state) 482 { 483 int err; 484 int i; 485 enum mlx4_qp_state states[] = { 486 MLX4_QP_STATE_RST, 487 MLX4_QP_STATE_INIT, 488 MLX4_QP_STATE_RTR, 489 MLX4_QP_STATE_RTS 490 }; 491 492 for (i = 0; i < ARRAY_SIZE(states) - 1; i++) { 493 context->flags &= cpu_to_be32(~(0xf << 28)); 494 context->flags |= cpu_to_be32(states[i + 1] << 28); 495 err = mlx4_qp_modify(dev, mtt, states[i], states[i + 1], 496 context, 0, 0, qp); 497 if (err) { 498 mlx4_err(dev, "Failed to bring QP to state: " 499 "%d with error: %d\n", 500 states[i + 1], err); 501 return err; 502 } 503 504 *qp_state = states[i + 1]; 505 } 506 507 return 0; 508 } 509 EXPORT_SYMBOL_GPL(mlx4_qp_to_ready); 510