1 /*
2  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
3  * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
4  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
6  *
7  * This software is available to you under a choice of one of two
8  * licenses.  You may choose to be licensed under the terms of the GNU
9  * General Public License (GPL) Version 2, available from the file
10  * COPYING in the main directory of this source tree, or the
11  * OpenIB.org BSD license below:
12  *
13  *     Redistribution and use in source and binary forms, with or
14  *     without modification, are permitted provided that the following
15  *     conditions are met:
16  *
17  *      - Redistributions of source code must retain the above
18  *        copyright notice, this list of conditions and the following
19  *        disclaimer.
20  *
21  *      - Redistributions in binary form must reproduce the above
22  *        copyright notice, this list of conditions and the following
23  *        disclaimer in the documentation and/or other materials
24  *        provided with the distribution.
25  *
26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33  * SOFTWARE.
34  */
35 
36 #include <linux/gfp.h>
37 #include <linux/export.h>
38 
39 #include <linux/mlx4/cmd.h>
40 #include <linux/mlx4/qp.h>
41 
42 #include "mlx4.h"
43 #include "icm.h"
44 
45 /* QP to support BF should have bits 6,7 cleared */
46 #define MLX4_BF_QP_SKIP_MASK	0xc0
47 #define MLX4_MAX_BF_QP_RANGE	0x40
48 
49 void mlx4_put_qp(struct mlx4_qp *qp)
50 {
51 	if (refcount_dec_and_test(&qp->refcount))
52 		complete(&qp->free);
53 }
54 EXPORT_SYMBOL_GPL(mlx4_put_qp);
55 
56 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type)
57 {
58 	struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
59 	struct mlx4_qp *qp;
60 
61 	spin_lock(&qp_table->lock);
62 
63 	qp = __mlx4_qp_lookup(dev, qpn);
64 	if (qp)
65 		refcount_inc(&qp->refcount);
66 
67 	spin_unlock(&qp_table->lock);
68 
69 	if (!qp) {
70 		mlx4_dbg(dev, "Async event for none existent QP %08x\n", qpn);
71 		return;
72 	}
73 
74 	/* Need to call mlx4_put_qp() in event handler */
75 	qp->event(qp, event_type);
76 }
77 
78 /* used for INIT/CLOSE port logic */
79 static int is_master_qp0(struct mlx4_dev *dev, struct mlx4_qp *qp, int *real_qp0, int *proxy_qp0)
80 {
81 	/* this procedure is called after we already know we are on the master */
82 	/* qp0 is either the proxy qp0, or the real qp0 */
83 	u32 pf_proxy_offset = dev->phys_caps.base_proxy_sqpn + 8 * mlx4_master_func_num(dev);
84 	*proxy_qp0 = qp->qpn >= pf_proxy_offset && qp->qpn <= pf_proxy_offset + 1;
85 
86 	*real_qp0 = qp->qpn >= dev->phys_caps.base_sqpn &&
87 		qp->qpn <= dev->phys_caps.base_sqpn + 1;
88 
89 	return *real_qp0 || *proxy_qp0;
90 }
91 
92 static int __mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
93 		     enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
94 		     struct mlx4_qp_context *context,
95 		     enum mlx4_qp_optpar optpar,
96 		     int sqd_event, struct mlx4_qp *qp, int native)
97 {
98 	static const u16 op[MLX4_QP_NUM_STATE][MLX4_QP_NUM_STATE] = {
99 		[MLX4_QP_STATE_RST] = {
100 			[MLX4_QP_STATE_RST]	= MLX4_CMD_2RST_QP,
101 			[MLX4_QP_STATE_ERR]	= MLX4_CMD_2ERR_QP,
102 			[MLX4_QP_STATE_INIT]	= MLX4_CMD_RST2INIT_QP,
103 		},
104 		[MLX4_QP_STATE_INIT]  = {
105 			[MLX4_QP_STATE_RST]	= MLX4_CMD_2RST_QP,
106 			[MLX4_QP_STATE_ERR]	= MLX4_CMD_2ERR_QP,
107 			[MLX4_QP_STATE_INIT]	= MLX4_CMD_INIT2INIT_QP,
108 			[MLX4_QP_STATE_RTR]	= MLX4_CMD_INIT2RTR_QP,
109 		},
110 		[MLX4_QP_STATE_RTR]   = {
111 			[MLX4_QP_STATE_RST]	= MLX4_CMD_2RST_QP,
112 			[MLX4_QP_STATE_ERR]	= MLX4_CMD_2ERR_QP,
113 			[MLX4_QP_STATE_RTS]	= MLX4_CMD_RTR2RTS_QP,
114 		},
115 		[MLX4_QP_STATE_RTS]   = {
116 			[MLX4_QP_STATE_RST]	= MLX4_CMD_2RST_QP,
117 			[MLX4_QP_STATE_ERR]	= MLX4_CMD_2ERR_QP,
118 			[MLX4_QP_STATE_RTS]	= MLX4_CMD_RTS2RTS_QP,
119 			[MLX4_QP_STATE_SQD]	= MLX4_CMD_RTS2SQD_QP,
120 		},
121 		[MLX4_QP_STATE_SQD] = {
122 			[MLX4_QP_STATE_RST]	= MLX4_CMD_2RST_QP,
123 			[MLX4_QP_STATE_ERR]	= MLX4_CMD_2ERR_QP,
124 			[MLX4_QP_STATE_RTS]	= MLX4_CMD_SQD2RTS_QP,
125 			[MLX4_QP_STATE_SQD]	= MLX4_CMD_SQD2SQD_QP,
126 		},
127 		[MLX4_QP_STATE_SQER] = {
128 			[MLX4_QP_STATE_RST]	= MLX4_CMD_2RST_QP,
129 			[MLX4_QP_STATE_ERR]	= MLX4_CMD_2ERR_QP,
130 			[MLX4_QP_STATE_RTS]	= MLX4_CMD_SQERR2RTS_QP,
131 		},
132 		[MLX4_QP_STATE_ERR] = {
133 			[MLX4_QP_STATE_RST]	= MLX4_CMD_2RST_QP,
134 			[MLX4_QP_STATE_ERR]	= MLX4_CMD_2ERR_QP,
135 		}
136 	};
137 
138 	struct mlx4_priv *priv = mlx4_priv(dev);
139 	struct mlx4_cmd_mailbox *mailbox;
140 	int ret = 0;
141 	int real_qp0 = 0;
142 	int proxy_qp0 = 0;
143 	u8 port;
144 
145 	if (cur_state >= MLX4_QP_NUM_STATE || new_state >= MLX4_QP_NUM_STATE ||
146 	    !op[cur_state][new_state])
147 		return -EINVAL;
148 
149 	if (op[cur_state][new_state] == MLX4_CMD_2RST_QP) {
150 		ret = mlx4_cmd(dev, 0, qp->qpn, 2,
151 			MLX4_CMD_2RST_QP, MLX4_CMD_TIME_CLASS_A, native);
152 		if (mlx4_is_master(dev) && cur_state != MLX4_QP_STATE_ERR &&
153 		    cur_state != MLX4_QP_STATE_RST &&
154 		    is_master_qp0(dev, qp, &real_qp0, &proxy_qp0)) {
155 			port = (qp->qpn & 1) + 1;
156 			if (proxy_qp0)
157 				priv->mfunc.master.qp0_state[port].proxy_qp0_active = 0;
158 			else
159 				priv->mfunc.master.qp0_state[port].qp0_active = 0;
160 		}
161 		return ret;
162 	}
163 
164 	mailbox = mlx4_alloc_cmd_mailbox(dev);
165 	if (IS_ERR(mailbox))
166 		return PTR_ERR(mailbox);
167 
168 	if (cur_state == MLX4_QP_STATE_RST && new_state == MLX4_QP_STATE_INIT) {
169 		u64 mtt_addr = mlx4_mtt_addr(dev, mtt);
170 		context->mtt_base_addr_h = mtt_addr >> 32;
171 		context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
172 		context->log_page_size   = mtt->page_shift - MLX4_ICM_PAGE_SHIFT;
173 	}
174 
175 	if ((cur_state == MLX4_QP_STATE_RTR) &&
176 	    (new_state == MLX4_QP_STATE_RTS) &&
177 	    dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
178 		context->roce_entropy =
179 			cpu_to_be16(mlx4_qp_roce_entropy(dev, qp->qpn));
180 
181 	*(__be32 *) mailbox->buf = cpu_to_be32(optpar);
182 	memcpy(mailbox->buf + 8, context, sizeof(*context));
183 
184 	((struct mlx4_qp_context *) (mailbox->buf + 8))->local_qpn =
185 		cpu_to_be32(qp->qpn);
186 
187 	ret = mlx4_cmd(dev, mailbox->dma,
188 		       qp->qpn | (!!sqd_event << 31),
189 		       new_state == MLX4_QP_STATE_RST ? 2 : 0,
190 		       op[cur_state][new_state], MLX4_CMD_TIME_CLASS_C, native);
191 
192 	if (mlx4_is_master(dev) && is_master_qp0(dev, qp, &real_qp0, &proxy_qp0)) {
193 		port = (qp->qpn & 1) + 1;
194 		if (cur_state != MLX4_QP_STATE_ERR &&
195 		    cur_state != MLX4_QP_STATE_RST &&
196 		    new_state == MLX4_QP_STATE_ERR) {
197 			if (proxy_qp0)
198 				priv->mfunc.master.qp0_state[port].proxy_qp0_active = 0;
199 			else
200 				priv->mfunc.master.qp0_state[port].qp0_active = 0;
201 		} else if (new_state == MLX4_QP_STATE_RTR) {
202 			if (proxy_qp0)
203 				priv->mfunc.master.qp0_state[port].proxy_qp0_active = 1;
204 			else
205 				priv->mfunc.master.qp0_state[port].qp0_active = 1;
206 		}
207 	}
208 
209 	mlx4_free_cmd_mailbox(dev, mailbox);
210 	return ret;
211 }
212 
213 int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
214 		   enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
215 		   struct mlx4_qp_context *context,
216 		   enum mlx4_qp_optpar optpar,
217 		   int sqd_event, struct mlx4_qp *qp)
218 {
219 	return __mlx4_qp_modify(dev, mtt, cur_state, new_state, context,
220 				optpar, sqd_event, qp, 0);
221 }
222 EXPORT_SYMBOL_GPL(mlx4_qp_modify);
223 
224 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
225 			    int *base, u8 flags)
226 {
227 	u32 uid;
228 	int bf_qp = !!(flags & (u8)MLX4_RESERVE_ETH_BF_QP);
229 
230 	struct mlx4_priv *priv = mlx4_priv(dev);
231 	struct mlx4_qp_table *qp_table = &priv->qp_table;
232 
233 	if (cnt > MLX4_MAX_BF_QP_RANGE && bf_qp)
234 		return -ENOMEM;
235 
236 	uid = MLX4_QP_TABLE_ZONE_GENERAL;
237 	if (flags & (u8)MLX4_RESERVE_A0_QP) {
238 		if (bf_qp)
239 			uid = MLX4_QP_TABLE_ZONE_RAW_ETH;
240 		else
241 			uid = MLX4_QP_TABLE_ZONE_RSS;
242 	}
243 
244 	*base = mlx4_zone_alloc_entries(qp_table->zones, uid, cnt, align,
245 					bf_qp ? MLX4_BF_QP_SKIP_MASK : 0, NULL);
246 	if (*base == -1)
247 		return -ENOMEM;
248 
249 	return 0;
250 }
251 
252 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
253 			  int *base, u8 flags, u8 usage)
254 {
255 	u32 in_modifier = RES_QP | (((u32)usage & 3) << 30);
256 	u64 in_param = 0;
257 	u64 out_param;
258 	int err;
259 
260 	/* Turn off all unsupported QP allocation flags */
261 	flags &= dev->caps.alloc_res_qp_mask;
262 
263 	if (mlx4_is_mfunc(dev)) {
264 		set_param_l(&in_param, (((u32)flags) << 24) | (u32)cnt);
265 		set_param_h(&in_param, align);
266 		err = mlx4_cmd_imm(dev, in_param, &out_param,
267 				   in_modifier, RES_OP_RESERVE,
268 				   MLX4_CMD_ALLOC_RES,
269 				   MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
270 		if (err)
271 			return err;
272 
273 		*base = get_param_l(&out_param);
274 		return 0;
275 	}
276 	return __mlx4_qp_reserve_range(dev, cnt, align, base, flags);
277 }
278 EXPORT_SYMBOL_GPL(mlx4_qp_reserve_range);
279 
280 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt)
281 {
282 	struct mlx4_priv *priv = mlx4_priv(dev);
283 	struct mlx4_qp_table *qp_table = &priv->qp_table;
284 
285 	if (mlx4_is_qp_reserved(dev, (u32) base_qpn))
286 		return;
287 	mlx4_zone_free_entries_unique(qp_table->zones, base_qpn, cnt);
288 }
289 
290 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt)
291 {
292 	u64 in_param = 0;
293 	int err;
294 
295 	if (!cnt)
296 		return;
297 
298 	if (mlx4_is_mfunc(dev)) {
299 		set_param_l(&in_param, base_qpn);
300 		set_param_h(&in_param, cnt);
301 		err = mlx4_cmd(dev, in_param, RES_QP, RES_OP_RESERVE,
302 			       MLX4_CMD_FREE_RES,
303 			       MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
304 		if (err) {
305 			mlx4_warn(dev, "Failed to release qp range base:%d cnt:%d\n",
306 				  base_qpn, cnt);
307 		}
308 	} else
309 		 __mlx4_qp_release_range(dev, base_qpn, cnt);
310 }
311 EXPORT_SYMBOL_GPL(mlx4_qp_release_range);
312 
313 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn)
314 {
315 	struct mlx4_priv *priv = mlx4_priv(dev);
316 	struct mlx4_qp_table *qp_table = &priv->qp_table;
317 	int err;
318 
319 	err = mlx4_table_get(dev, &qp_table->qp_table, qpn);
320 	if (err)
321 		goto err_out;
322 
323 	err = mlx4_table_get(dev, &qp_table->auxc_table, qpn);
324 	if (err)
325 		goto err_put_qp;
326 
327 	err = mlx4_table_get(dev, &qp_table->altc_table, qpn);
328 	if (err)
329 		goto err_put_auxc;
330 
331 	err = mlx4_table_get(dev, &qp_table->rdmarc_table, qpn);
332 	if (err)
333 		goto err_put_altc;
334 
335 	err = mlx4_table_get(dev, &qp_table->cmpt_table, qpn);
336 	if (err)
337 		goto err_put_rdmarc;
338 
339 	return 0;
340 
341 err_put_rdmarc:
342 	mlx4_table_put(dev, &qp_table->rdmarc_table, qpn);
343 
344 err_put_altc:
345 	mlx4_table_put(dev, &qp_table->altc_table, qpn);
346 
347 err_put_auxc:
348 	mlx4_table_put(dev, &qp_table->auxc_table, qpn);
349 
350 err_put_qp:
351 	mlx4_table_put(dev, &qp_table->qp_table, qpn);
352 
353 err_out:
354 	return err;
355 }
356 
357 static int mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn)
358 {
359 	u64 param = 0;
360 
361 	if (mlx4_is_mfunc(dev)) {
362 		set_param_l(&param, qpn);
363 		return mlx4_cmd_imm(dev, param, &param, RES_QP, RES_OP_MAP_ICM,
364 				    MLX4_CMD_ALLOC_RES, MLX4_CMD_TIME_CLASS_A,
365 				    MLX4_CMD_WRAPPED);
366 	}
367 	return __mlx4_qp_alloc_icm(dev, qpn);
368 }
369 
370 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn)
371 {
372 	struct mlx4_priv *priv = mlx4_priv(dev);
373 	struct mlx4_qp_table *qp_table = &priv->qp_table;
374 
375 	mlx4_table_put(dev, &qp_table->cmpt_table, qpn);
376 	mlx4_table_put(dev, &qp_table->rdmarc_table, qpn);
377 	mlx4_table_put(dev, &qp_table->altc_table, qpn);
378 	mlx4_table_put(dev, &qp_table->auxc_table, qpn);
379 	mlx4_table_put(dev, &qp_table->qp_table, qpn);
380 }
381 
382 static void mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn)
383 {
384 	u64 in_param = 0;
385 
386 	if (mlx4_is_mfunc(dev)) {
387 		set_param_l(&in_param, qpn);
388 		if (mlx4_cmd(dev, in_param, RES_QP, RES_OP_MAP_ICM,
389 			     MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
390 			     MLX4_CMD_WRAPPED))
391 			mlx4_warn(dev, "Failed to free icm of qp:%d\n", qpn);
392 	} else
393 		__mlx4_qp_free_icm(dev, qpn);
394 }
395 
396 struct mlx4_qp *mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn)
397 {
398 	struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
399 	struct mlx4_qp *qp;
400 
401 	spin_lock_irq(&qp_table->lock);
402 
403 	qp = __mlx4_qp_lookup(dev, qpn);
404 
405 	spin_unlock_irq(&qp_table->lock);
406 	return qp;
407 }
408 
409 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp)
410 {
411 	struct mlx4_priv *priv = mlx4_priv(dev);
412 	struct mlx4_qp_table *qp_table = &priv->qp_table;
413 	int err;
414 
415 	if (!qpn)
416 		return -EINVAL;
417 
418 	qp->qpn = qpn;
419 
420 	err = mlx4_qp_alloc_icm(dev, qpn);
421 	if (err)
422 		return err;
423 
424 	spin_lock_irq(&qp_table->lock);
425 	err = radix_tree_insert(&dev->qp_table_tree, qp->qpn &
426 				(dev->caps.num_qps - 1), qp);
427 	spin_unlock_irq(&qp_table->lock);
428 	if (err)
429 		goto err_icm;
430 
431 	refcount_set(&qp->refcount, 1);
432 	init_completion(&qp->free);
433 
434 	return 0;
435 
436 err_icm:
437 	mlx4_qp_free_icm(dev, qpn);
438 	return err;
439 }
440 
441 EXPORT_SYMBOL_GPL(mlx4_qp_alloc);
442 
443 int mlx4_update_qp(struct mlx4_dev *dev, u32 qpn,
444 		   enum mlx4_update_qp_attr attr,
445 		   struct mlx4_update_qp_params *params)
446 {
447 	struct mlx4_cmd_mailbox *mailbox;
448 	struct mlx4_update_qp_context *cmd;
449 	u64 pri_addr_path_mask = 0;
450 	u64 qp_mask = 0;
451 	int err = 0;
452 
453 	if (!attr || (attr & ~MLX4_UPDATE_QP_SUPPORTED_ATTRS))
454 		return -EINVAL;
455 
456 	mailbox = mlx4_alloc_cmd_mailbox(dev);
457 	if (IS_ERR(mailbox))
458 		return PTR_ERR(mailbox);
459 
460 	cmd = (struct mlx4_update_qp_context *)mailbox->buf;
461 
462 	if (attr & MLX4_UPDATE_QP_SMAC) {
463 		pri_addr_path_mask |= 1ULL << MLX4_UPD_QP_PATH_MASK_MAC_INDEX;
464 		cmd->qp_context.pri_path.grh_mylmc = params->smac_index;
465 	}
466 
467 	if (attr & MLX4_UPDATE_QP_ETH_SRC_CHECK_MC_LB) {
468 		if (!(dev->caps.flags2
469 		      & MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB)) {
470 			mlx4_warn(dev,
471 				  "Trying to set src check LB, but it isn't supported\n");
472 			err = -EOPNOTSUPP;
473 			goto out;
474 		}
475 		pri_addr_path_mask |=
476 			1ULL << MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB;
477 		if (params->flags &
478 		    MLX4_UPDATE_QP_PARAMS_FLAGS_ETH_CHECK_MC_LB) {
479 			cmd->qp_context.pri_path.fl |=
480 				MLX4_FL_ETH_SRC_CHECK_MC_LB;
481 		}
482 	}
483 
484 	if (attr & MLX4_UPDATE_QP_VSD) {
485 		qp_mask |= 1ULL << MLX4_UPD_QP_MASK_VSD;
486 		if (params->flags & MLX4_UPDATE_QP_PARAMS_FLAGS_VSD_ENABLE)
487 			cmd->qp_context.param3 |= cpu_to_be32(MLX4_STRIP_VLAN);
488 	}
489 
490 	if (attr & MLX4_UPDATE_QP_RATE_LIMIT) {
491 		qp_mask |= 1ULL << MLX4_UPD_QP_MASK_RATE_LIMIT;
492 		cmd->qp_context.rate_limit_params = cpu_to_be16((params->rate_unit << 14) | params->rate_val);
493 	}
494 
495 	if (attr & MLX4_UPDATE_QP_QOS_VPORT) {
496 		if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QOS_VPP)) {
497 			mlx4_warn(dev, "Granular QoS per VF is not enabled\n");
498 			err = -EOPNOTSUPP;
499 			goto out;
500 		}
501 
502 		qp_mask |= 1ULL << MLX4_UPD_QP_MASK_QOS_VPP;
503 		cmd->qp_context.qos_vport = params->qos_vport;
504 	}
505 
506 	cmd->primary_addr_path_mask = cpu_to_be64(pri_addr_path_mask);
507 	cmd->qp_mask = cpu_to_be64(qp_mask);
508 
509 	err = mlx4_cmd(dev, mailbox->dma, qpn & 0xffffff, 0,
510 		       MLX4_CMD_UPDATE_QP, MLX4_CMD_TIME_CLASS_A,
511 		       MLX4_CMD_NATIVE);
512 out:
513 	mlx4_free_cmd_mailbox(dev, mailbox);
514 	return err;
515 }
516 EXPORT_SYMBOL_GPL(mlx4_update_qp);
517 
518 void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp)
519 {
520 	struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
521 	unsigned long flags;
522 
523 	spin_lock_irqsave(&qp_table->lock, flags);
524 	radix_tree_delete(&dev->qp_table_tree, qp->qpn & (dev->caps.num_qps - 1));
525 	spin_unlock_irqrestore(&qp_table->lock, flags);
526 }
527 EXPORT_SYMBOL_GPL(mlx4_qp_remove);
528 
529 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp)
530 {
531 	mlx4_put_qp(qp);
532 	wait_for_completion(&qp->free);
533 
534 	mlx4_qp_free_icm(dev, qp->qpn);
535 }
536 EXPORT_SYMBOL_GPL(mlx4_qp_free);
537 
538 static int mlx4_CONF_SPECIAL_QP(struct mlx4_dev *dev, u32 base_qpn)
539 {
540 	return mlx4_cmd(dev, 0, base_qpn, 0, MLX4_CMD_CONF_SPECIAL_QP,
541 			MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
542 }
543 
544 #define MLX4_QP_TABLE_RSS_ETH_PRIORITY 2
545 #define MLX4_QP_TABLE_RAW_ETH_PRIORITY 1
546 #define MLX4_QP_TABLE_RAW_ETH_SIZE     256
547 
548 static int mlx4_create_zones(struct mlx4_dev *dev,
549 			     u32 reserved_bottom_general,
550 			     u32 reserved_top_general,
551 			     u32 reserved_bottom_rss,
552 			     u32 start_offset_rss,
553 			     u32 max_table_offset)
554 {
555 	struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
556 	struct mlx4_bitmap (*bitmap)[MLX4_QP_TABLE_ZONE_NUM] = NULL;
557 	int bitmap_initialized = 0;
558 	u32 last_offset;
559 	int k;
560 	int err;
561 
562 	qp_table->zones = mlx4_zone_allocator_create(MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP);
563 
564 	if (NULL == qp_table->zones)
565 		return -ENOMEM;
566 
567 	bitmap = kmalloc(sizeof(*bitmap), GFP_KERNEL);
568 
569 	if (NULL == bitmap) {
570 		err = -ENOMEM;
571 		goto free_zone;
572 	}
573 
574 	err = mlx4_bitmap_init(*bitmap + MLX4_QP_TABLE_ZONE_GENERAL, dev->caps.num_qps,
575 			       (1 << 23) - 1, reserved_bottom_general,
576 			       reserved_top_general);
577 
578 	if (err)
579 		goto free_bitmap;
580 
581 	++bitmap_initialized;
582 
583 	err = mlx4_zone_add_one(qp_table->zones, *bitmap + MLX4_QP_TABLE_ZONE_GENERAL,
584 				MLX4_ZONE_FALLBACK_TO_HIGHER_PRIO |
585 				MLX4_ZONE_USE_RR, 0,
586 				0, qp_table->zones_uids + MLX4_QP_TABLE_ZONE_GENERAL);
587 
588 	if (err)
589 		goto free_bitmap;
590 
591 	err = mlx4_bitmap_init(*bitmap + MLX4_QP_TABLE_ZONE_RSS,
592 			       reserved_bottom_rss,
593 			       reserved_bottom_rss - 1,
594 			       dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
595 			       reserved_bottom_rss - start_offset_rss);
596 
597 	if (err)
598 		goto free_bitmap;
599 
600 	++bitmap_initialized;
601 
602 	err = mlx4_zone_add_one(qp_table->zones, *bitmap + MLX4_QP_TABLE_ZONE_RSS,
603 				MLX4_ZONE_ALLOW_ALLOC_FROM_LOWER_PRIO |
604 				MLX4_ZONE_ALLOW_ALLOC_FROM_EQ_PRIO |
605 				MLX4_ZONE_USE_RR, MLX4_QP_TABLE_RSS_ETH_PRIORITY,
606 				0, qp_table->zones_uids + MLX4_QP_TABLE_ZONE_RSS);
607 
608 	if (err)
609 		goto free_bitmap;
610 
611 	last_offset = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
612 	/*  We have a single zone for the A0 steering QPs area of the FW. This area
613 	 *  needs to be split into subareas. One set of subareas is for RSS QPs
614 	 *  (in which qp number bits 6 and/or 7 are set); the other set of subareas
615 	 *  is for RAW_ETH QPs, which require that both bits 6 and 7 are zero.
616 	 *  Currently, the values returned by the FW (A0 steering area starting qp number
617 	 *  and A0 steering area size) are such that there are only two subareas -- one
618 	 *  for RSS and one for RAW_ETH.
619 	 */
620 	for (k = MLX4_QP_TABLE_ZONE_RSS + 1; k < sizeof(*bitmap)/sizeof((*bitmap)[0]);
621 	     k++) {
622 		int size;
623 		u32 offset = start_offset_rss;
624 		u32 bf_mask;
625 		u32 requested_size;
626 
627 		/* Assuming MLX4_BF_QP_SKIP_MASK is consecutive ones, this calculates
628 		 * a mask of all LSB bits set until (and not including) the first
629 		 * set bit of  MLX4_BF_QP_SKIP_MASK. For example, if MLX4_BF_QP_SKIP_MASK
630 		 * is 0xc0, bf_mask will be 0x3f.
631 		 */
632 		bf_mask = (MLX4_BF_QP_SKIP_MASK & ~(MLX4_BF_QP_SKIP_MASK - 1)) - 1;
633 		requested_size = min((u32)MLX4_QP_TABLE_RAW_ETH_SIZE, bf_mask + 1);
634 
635 		if (((last_offset & MLX4_BF_QP_SKIP_MASK) &&
636 		     ((int)(max_table_offset - last_offset)) >=
637 		     roundup_pow_of_two(MLX4_BF_QP_SKIP_MASK)) ||
638 		    (!(last_offset & MLX4_BF_QP_SKIP_MASK) &&
639 		     !((last_offset + requested_size - 1) &
640 		       MLX4_BF_QP_SKIP_MASK)))
641 			size = requested_size;
642 		else {
643 			u32 candidate_offset =
644 				(last_offset | MLX4_BF_QP_SKIP_MASK | bf_mask) + 1;
645 
646 			if (last_offset & MLX4_BF_QP_SKIP_MASK)
647 				last_offset = candidate_offset;
648 
649 			/* From this point, the BF bits are 0 */
650 
651 			if (last_offset > max_table_offset) {
652 				/* need to skip */
653 				size = -1;
654 			} else {
655 				size = min3(max_table_offset - last_offset,
656 					    bf_mask - (last_offset & bf_mask),
657 					    requested_size);
658 				if (size < requested_size) {
659 					int candidate_size;
660 
661 					candidate_size = min3(
662 						max_table_offset - candidate_offset,
663 						bf_mask - (last_offset & bf_mask),
664 						requested_size);
665 
666 					/*  We will not take this path if last_offset was
667 					 *  already set above to candidate_offset
668 					 */
669 					if (candidate_size > size) {
670 						last_offset = candidate_offset;
671 						size = candidate_size;
672 					}
673 				}
674 			}
675 		}
676 
677 		if (size > 0) {
678 			/* mlx4_bitmap_alloc_range will find a contiguous range of "size"
679 			 * QPs in which both bits 6 and 7 are zero, because we pass it the
680 			 * MLX4_BF_SKIP_MASK).
681 			 */
682 			offset = mlx4_bitmap_alloc_range(
683 					*bitmap + MLX4_QP_TABLE_ZONE_RSS,
684 					size, 1,
685 					MLX4_BF_QP_SKIP_MASK);
686 
687 			if (offset == (u32)-1) {
688 				err = -ENOMEM;
689 				break;
690 			}
691 
692 			last_offset = offset + size;
693 
694 			err = mlx4_bitmap_init(*bitmap + k, roundup_pow_of_two(size),
695 					       roundup_pow_of_two(size) - 1, 0,
696 					       roundup_pow_of_two(size) - size);
697 		} else {
698 			/* Add an empty bitmap, we'll allocate from different zones (since
699 			 * at least one is reserved)
700 			 */
701 			err = mlx4_bitmap_init(*bitmap + k, 1,
702 					       MLX4_QP_TABLE_RAW_ETH_SIZE - 1, 0,
703 					       0);
704 			if (!err)
705 				mlx4_bitmap_alloc_range(*bitmap + k, 1, 1, 0);
706 		}
707 
708 		if (err)
709 			break;
710 
711 		++bitmap_initialized;
712 
713 		err = mlx4_zone_add_one(qp_table->zones, *bitmap + k,
714 					MLX4_ZONE_ALLOW_ALLOC_FROM_LOWER_PRIO |
715 					MLX4_ZONE_ALLOW_ALLOC_FROM_EQ_PRIO |
716 					MLX4_ZONE_USE_RR, MLX4_QP_TABLE_RAW_ETH_PRIORITY,
717 					offset, qp_table->zones_uids + k);
718 
719 		if (err)
720 			break;
721 	}
722 
723 	if (err)
724 		goto free_bitmap;
725 
726 	qp_table->bitmap_gen = *bitmap;
727 
728 	return err;
729 
730 free_bitmap:
731 	for (k = 0; k < bitmap_initialized; k++)
732 		mlx4_bitmap_cleanup(*bitmap + k);
733 	kfree(bitmap);
734 free_zone:
735 	mlx4_zone_allocator_destroy(qp_table->zones);
736 	return err;
737 }
738 
739 static void mlx4_cleanup_qp_zones(struct mlx4_dev *dev)
740 {
741 	struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
742 
743 	if (qp_table->zones) {
744 		int i;
745 
746 		for (i = 0;
747 		     i < ARRAY_SIZE(qp_table->zones_uids);
748 		     i++) {
749 			struct mlx4_bitmap *bitmap =
750 				mlx4_zone_get_bitmap(qp_table->zones,
751 						     qp_table->zones_uids[i]);
752 
753 			mlx4_zone_remove_one(qp_table->zones, qp_table->zones_uids[i]);
754 			if (NULL == bitmap)
755 				continue;
756 
757 			mlx4_bitmap_cleanup(bitmap);
758 		}
759 		mlx4_zone_allocator_destroy(qp_table->zones);
760 		kfree(qp_table->bitmap_gen);
761 		qp_table->bitmap_gen = NULL;
762 		qp_table->zones = NULL;
763 	}
764 }
765 
766 int mlx4_init_qp_table(struct mlx4_dev *dev)
767 {
768 	struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
769 	int err;
770 	int reserved_from_top = 0;
771 	int reserved_from_bot;
772 	int k;
773 	int fixed_reserved_from_bot_rv = 0;
774 	int bottom_reserved_for_rss_bitmap;
775 	u32 max_table_offset = dev->caps.dmfs_high_rate_qpn_base +
776 			dev->caps.dmfs_high_rate_qpn_range;
777 
778 	spin_lock_init(&qp_table->lock);
779 	INIT_RADIX_TREE(&dev->qp_table_tree, GFP_ATOMIC);
780 	if (mlx4_is_slave(dev))
781 		return 0;
782 
783 	/* We reserve 2 extra QPs per port for the special QPs.  The
784 	 * block of special QPs must be aligned to a multiple of 8, so
785 	 * round up.
786 	 *
787 	 * We also reserve the MSB of the 24-bit QP number to indicate
788 	 * that a QP is an XRC QP.
789 	 */
790 	for (k = 0; k <= MLX4_QP_REGION_BOTTOM; k++)
791 		fixed_reserved_from_bot_rv += dev->caps.reserved_qps_cnt[k];
792 
793 	if (fixed_reserved_from_bot_rv < max_table_offset)
794 		fixed_reserved_from_bot_rv = max_table_offset;
795 
796 	/* We reserve at least 1 extra for bitmaps that we don't have enough space for*/
797 	bottom_reserved_for_rss_bitmap =
798 		roundup_pow_of_two(fixed_reserved_from_bot_rv + 1);
799 	dev->phys_caps.base_sqpn = ALIGN(bottom_reserved_for_rss_bitmap, 8);
800 
801 	{
802 		int sort[MLX4_NUM_QP_REGION];
803 		int i, j;
804 		int last_base = dev->caps.num_qps;
805 
806 		for (i = 1; i < MLX4_NUM_QP_REGION; ++i)
807 			sort[i] = i;
808 
809 		for (i = MLX4_NUM_QP_REGION; i > MLX4_QP_REGION_BOTTOM; --i) {
810 			for (j = MLX4_QP_REGION_BOTTOM + 2; j < i; ++j) {
811 				if (dev->caps.reserved_qps_cnt[sort[j]] >
812 				    dev->caps.reserved_qps_cnt[sort[j - 1]])
813 					swap(sort[j], sort[j - 1]);
814 			}
815 		}
816 
817 		for (i = MLX4_QP_REGION_BOTTOM + 1; i < MLX4_NUM_QP_REGION; ++i) {
818 			last_base -= dev->caps.reserved_qps_cnt[sort[i]];
819 			dev->caps.reserved_qps_base[sort[i]] = last_base;
820 			reserved_from_top +=
821 				dev->caps.reserved_qps_cnt[sort[i]];
822 		}
823 	}
824 
825        /* Reserve 8 real SQPs in both native and SRIOV modes.
826 	* In addition, in SRIOV mode, reserve 8 proxy SQPs per function
827 	* (for all PFs and VFs), and 8 corresponding tunnel QPs.
828 	* Each proxy SQP works opposite its own tunnel QP.
829 	*
830 	* The QPs are arranged as follows:
831 	* a. 8 real SQPs
832 	* b. All the proxy SQPs (8 per function)
833 	* c. All the tunnel QPs (8 per function)
834 	*/
835 	reserved_from_bot = mlx4_num_reserved_sqps(dev);
836 	if (reserved_from_bot + reserved_from_top > dev->caps.num_qps) {
837 		mlx4_err(dev, "Number of reserved QPs is higher than number of QPs\n");
838 		return -EINVAL;
839 	}
840 
841 	err = mlx4_create_zones(dev, reserved_from_bot, reserved_from_bot,
842 				bottom_reserved_for_rss_bitmap,
843 				fixed_reserved_from_bot_rv,
844 				max_table_offset);
845 
846 	if (err)
847 		return err;
848 
849 	if (mlx4_is_mfunc(dev)) {
850 		/* for PPF use */
851 		dev->phys_caps.base_proxy_sqpn = dev->phys_caps.base_sqpn + 8;
852 		dev->phys_caps.base_tunnel_sqpn = dev->phys_caps.base_sqpn + 8 + 8 * MLX4_MFUNC_MAX;
853 
854 		/* In mfunc, calculate proxy and tunnel qp offsets for the PF here,
855 		 * since the PF does not call mlx4_slave_caps */
856 		dev->caps.spec_qps = kcalloc(dev->caps.num_ports,
857 					     sizeof(*dev->caps.spec_qps),
858 					     GFP_KERNEL);
859 		if (!dev->caps.spec_qps) {
860 			err = -ENOMEM;
861 			goto err_mem;
862 		}
863 
864 		for (k = 0; k < dev->caps.num_ports; k++) {
865 			dev->caps.spec_qps[k].qp0_proxy = dev->phys_caps.base_proxy_sqpn +
866 				8 * mlx4_master_func_num(dev) + k;
867 			dev->caps.spec_qps[k].qp0_tunnel = dev->caps.spec_qps[k].qp0_proxy + 8 * MLX4_MFUNC_MAX;
868 			dev->caps.spec_qps[k].qp1_proxy = dev->phys_caps.base_proxy_sqpn +
869 				8 * mlx4_master_func_num(dev) + MLX4_MAX_PORTS + k;
870 			dev->caps.spec_qps[k].qp1_tunnel = dev->caps.spec_qps[k].qp1_proxy + 8 * MLX4_MFUNC_MAX;
871 		}
872 	}
873 
874 
875 	err = mlx4_CONF_SPECIAL_QP(dev, dev->phys_caps.base_sqpn);
876 	if (err)
877 		goto err_mem;
878 
879 	return err;
880 
881 err_mem:
882 	kfree(dev->caps.spec_qps);
883 	dev->caps.spec_qps = NULL;
884 	mlx4_cleanup_qp_zones(dev);
885 	return err;
886 }
887 
888 void mlx4_cleanup_qp_table(struct mlx4_dev *dev)
889 {
890 	if (mlx4_is_slave(dev))
891 		return;
892 
893 	mlx4_CONF_SPECIAL_QP(dev, 0);
894 
895 	mlx4_cleanup_qp_zones(dev);
896 }
897 
898 int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp,
899 		  struct mlx4_qp_context *context)
900 {
901 	struct mlx4_cmd_mailbox *mailbox;
902 	int err;
903 
904 	mailbox = mlx4_alloc_cmd_mailbox(dev);
905 	if (IS_ERR(mailbox))
906 		return PTR_ERR(mailbox);
907 
908 	err = mlx4_cmd_box(dev, 0, mailbox->dma, qp->qpn, 0,
909 			   MLX4_CMD_QUERY_QP, MLX4_CMD_TIME_CLASS_A,
910 			   MLX4_CMD_WRAPPED);
911 	if (!err)
912 		memcpy(context, mailbox->buf + 8, sizeof(*context));
913 
914 	mlx4_free_cmd_mailbox(dev, mailbox);
915 	return err;
916 }
917 EXPORT_SYMBOL_GPL(mlx4_qp_query);
918 
919 int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
920 		     struct mlx4_qp_context *context,
921 		     struct mlx4_qp *qp, enum mlx4_qp_state *qp_state)
922 {
923 	int err;
924 	int i;
925 	static const enum mlx4_qp_state states[] = {
926 		MLX4_QP_STATE_RST,
927 		MLX4_QP_STATE_INIT,
928 		MLX4_QP_STATE_RTR,
929 		MLX4_QP_STATE_RTS
930 	};
931 
932 	for (i = 0; i < ARRAY_SIZE(states) - 1; i++) {
933 		context->flags &= cpu_to_be32(~(0xf << 28));
934 		context->flags |= cpu_to_be32(states[i + 1] << 28);
935 		if (states[i + 1] != MLX4_QP_STATE_RTR)
936 			context->params2 &= ~cpu_to_be32(MLX4_QP_BIT_FPP);
937 		err = mlx4_qp_modify(dev, mtt, states[i], states[i + 1],
938 				     context, 0, 0, qp);
939 		if (err) {
940 			mlx4_err(dev, "Failed to bring QP to state: %d with error: %d\n",
941 				 states[i + 1], err);
942 			return err;
943 		}
944 
945 		*qp_state = states[i + 1];
946 	}
947 
948 	return 0;
949 }
950 EXPORT_SYMBOL_GPL(mlx4_qp_to_ready);
951 
952 u16 mlx4_qp_roce_entropy(struct mlx4_dev *dev, u32 qpn)
953 {
954 	struct mlx4_qp_context context;
955 	struct mlx4_qp qp;
956 	int err;
957 
958 	qp.qpn = qpn;
959 	err = mlx4_qp_query(dev, &qp, &context);
960 	if (!err) {
961 		u32 dest_qpn = be32_to_cpu(context.remote_qpn) & 0xffffff;
962 		u16 folded_dst = folded_qp(dest_qpn);
963 		u16 folded_src = folded_qp(qpn);
964 
965 		return (dest_qpn != qpn) ?
966 			((folded_dst ^ folded_src) | 0xC000) :
967 			folded_src | 0xC000;
968 	}
969 	return 0xdead;
970 }
971