1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
2b4b6e842SEran Ben Elisha #ifndef _MLX4_STATS_
3b4b6e842SEran Ben Elisha #define _MLX4_STATS_
4b4b6e842SEran Ben Elisha 
5b4b6e842SEran Ben Elisha #ifdef MLX4_EN_PERF_STAT
6b4b6e842SEran Ben Elisha #define NUM_PERF_STATS			NUM_PERF_COUNTERS
7b4b6e842SEran Ben Elisha #else
8b4b6e842SEran Ben Elisha #define NUM_PERF_STATS			0
9b4b6e842SEran Ben Elisha #endif
10b4b6e842SEran Ben Elisha 
11b4b6e842SEran Ben Elisha #define NUM_PRIORITIES	9
12b4b6e842SEran Ben Elisha #define NUM_PRIORITY_STATS 2
13b4b6e842SEran Ben Elisha 
14b4b6e842SEran Ben Elisha struct mlx4_en_pkt_stats {
15a3333b35SEran Ben Elisha 	unsigned long rx_multicast_packets;
16a3333b35SEran Ben Elisha 	unsigned long rx_broadcast_packets;
17a3333b35SEran Ben Elisha 	unsigned long rx_jabbers;
18a3333b35SEran Ben Elisha 	unsigned long rx_in_range_length_error;
19a3333b35SEran Ben Elisha 	unsigned long rx_out_range_length_error;
20a3333b35SEran Ben Elisha 	unsigned long tx_multicast_packets;
21a3333b35SEran Ben Elisha 	unsigned long tx_broadcast_packets;
22a3333b35SEran Ben Elisha 	unsigned long rx_prio[NUM_PRIORITIES][NUM_PRIORITY_STATS];
23a3333b35SEran Ben Elisha 	unsigned long tx_prio[NUM_PRIORITIES][NUM_PRIORITY_STATS];
24a3333b35SEran Ben Elisha #define NUM_PKT_STATS		43
25b4b6e842SEran Ben Elisha };
26b4b6e842SEran Ben Elisha 
27b42de4d0SEran Ben Elisha struct mlx4_en_counter_stats {
28b42de4d0SEran Ben Elisha 	unsigned long rx_packets;
29b42de4d0SEran Ben Elisha 	unsigned long rx_bytes;
30b42de4d0SEran Ben Elisha 	unsigned long tx_packets;
31b42de4d0SEran Ben Elisha 	unsigned long tx_bytes;
32b42de4d0SEran Ben Elisha #define NUM_PF_STATS      4
33b42de4d0SEran Ben Elisha };
34b42de4d0SEran Ben Elisha 
35b4b6e842SEran Ben Elisha struct mlx4_en_port_stats {
36b4b6e842SEran Ben Elisha 	unsigned long tso_packets;
37b4b6e842SEran Ben Elisha 	unsigned long xmit_more;
38b4b6e842SEran Ben Elisha 	unsigned long queue_stopped;
39b4b6e842SEran Ben Elisha 	unsigned long wake_queue;
40b4b6e842SEran Ben Elisha 	unsigned long tx_timeout;
417d7bfc6aSEric Dumazet 	unsigned long rx_alloc_pages;
42b4b6e842SEran Ben Elisha 	unsigned long rx_chksum_good;
43b4b6e842SEran Ben Elisha 	unsigned long rx_chksum_none;
44b4b6e842SEran Ben Elisha 	unsigned long rx_chksum_complete;
45b4b6e842SEran Ben Elisha 	unsigned long tx_chksum_offload;
46b4b6e842SEran Ben Elisha #define NUM_PORT_STATS		10
47b4b6e842SEran Ben Elisha };
48b4b6e842SEran Ben Elisha 
49b4b6e842SEran Ben Elisha struct mlx4_en_perf_stats {
50b4b6e842SEran Ben Elisha 	u32 tx_poll;
51b4b6e842SEran Ben Elisha 	u64 tx_pktsz_avg;
52b4b6e842SEran Ben Elisha 	u32 inflight_avg;
53b4b6e842SEran Ben Elisha 	u16 tx_coal_avg;
54b4b6e842SEran Ben Elisha 	u16 rx_coal_avg;
55b4b6e842SEran Ben Elisha 	u32 napi_quota;
56b4b6e842SEran Ben Elisha #define NUM_PERF_COUNTERS		6
57b4b6e842SEran Ben Elisha };
58b4b6e842SEran Ben Elisha 
5915fca2c8STariq Toukan struct mlx4_en_xdp_stats {
6015fca2c8STariq Toukan 	unsigned long rx_xdp_drop;
6115fca2c8STariq Toukan 	unsigned long rx_xdp_tx;
6215fca2c8STariq Toukan 	unsigned long rx_xdp_tx_full;
6315fca2c8STariq Toukan #define NUM_XDP_STATS		3
6415fca2c8STariq Toukan };
6515fca2c8STariq Toukan 
66f26d0d25SEran Ben Elisha struct mlx4_en_phy_stats {
67f26d0d25SEran Ben Elisha 	unsigned long rx_packets_phy;
68f26d0d25SEran Ben Elisha 	unsigned long rx_bytes_phy;
69f26d0d25SEran Ben Elisha 	unsigned long tx_packets_phy;
70f26d0d25SEran Ben Elisha 	unsigned long tx_bytes_phy;
71f26d0d25SEran Ben Elisha #define NUM_PHY_STATS		4
72f26d0d25SEran Ben Elisha };
73f26d0d25SEran Ben Elisha 
74b4b6e842SEran Ben Elisha #define NUM_MAIN_STATS	21
750b131561SMatan Barak 
760b131561SMatan Barak #define MLX4_NUM_PRIORITIES	8
770b131561SMatan Barak 
780b131561SMatan Barak struct mlx4_en_flow_stats_rx {
790b131561SMatan Barak 	u64 rx_pause;
800b131561SMatan Barak 	u64 rx_pause_duration;
810b131561SMatan Barak 	u64 rx_pause_transition;
820b131561SMatan Barak #define NUM_FLOW_STATS_RX	3
830b131561SMatan Barak #define NUM_FLOW_PRIORITY_STATS_RX	(NUM_FLOW_STATS_RX * \
840b131561SMatan Barak 					 MLX4_NUM_PRIORITIES)
850b131561SMatan Barak };
860b131561SMatan Barak 
870b131561SMatan Barak struct mlx4_en_flow_stats_tx {
880b131561SMatan Barak 	u64 tx_pause;
890b131561SMatan Barak 	u64 tx_pause_duration;
900b131561SMatan Barak 	u64 tx_pause_transition;
910b131561SMatan Barak #define NUM_FLOW_STATS_TX	3
920b131561SMatan Barak #define NUM_FLOW_PRIORITY_STATS_TX	(NUM_FLOW_STATS_TX * \
930b131561SMatan Barak 					 MLX4_NUM_PRIORITIES)
940b131561SMatan Barak };
950b131561SMatan Barak 
960b131561SMatan Barak #define NUM_FLOW_STATS (NUM_FLOW_STATS_RX + NUM_FLOW_STATS_TX + \
970b131561SMatan Barak 			NUM_FLOW_PRIORITY_STATS_TX + \
989a2abf5aSEran Ben Elisha 			NUM_FLOW_PRIORITY_STATS_RX)
990b131561SMatan Barak 
1000b131561SMatan Barak struct mlx4_en_stat_out_flow_control_mbox {
1010b131561SMatan Barak 	/* Total number of PAUSE frames received from the far-end port */
1020b131561SMatan Barak 	__be64 rx_pause;
1030b131561SMatan Barak 	/* Total number of microseconds that far-end port requested to pause
1040b131561SMatan Barak 	* transmission of packets
1050b131561SMatan Barak 	*/
1060b131561SMatan Barak 	__be64 rx_pause_duration;
1070b131561SMatan Barak 	/* Number of received transmission from XOFF state to XON state */
1080b131561SMatan Barak 	__be64 rx_pause_transition;
1090b131561SMatan Barak 	/* Total number of PAUSE frames sent from the far-end port */
1100b131561SMatan Barak 	__be64 tx_pause;
1110b131561SMatan Barak 	/* Total time in microseconds that transmission of packets has been
1120b131561SMatan Barak 	* paused
1130b131561SMatan Barak 	*/
1140b131561SMatan Barak 	__be64 tx_pause_duration;
1150b131561SMatan Barak 	/* Number of transmitter transitions from XOFF state to XON state */
1160b131561SMatan Barak 	__be64 tx_pause_transition;
1170b131561SMatan Barak 	/* Reserverd */
1180b131561SMatan Barak 	__be64 reserved[2];
1190b131561SMatan Barak };
1200b131561SMatan Barak 
1210b131561SMatan Barak enum {
1220b131561SMatan Barak 	MLX4_DUMP_ETH_STATS_FLOW_CONTROL = 1 << 12
1230b131561SMatan Barak };
1240b131561SMatan Barak 
125b4b6e842SEran Ben Elisha #define NUM_ALL_STATS	(NUM_MAIN_STATS + NUM_PORT_STATS + NUM_PKT_STATS + \
12615fca2c8STariq Toukan 			 NUM_FLOW_STATS + NUM_PERF_STATS + NUM_PF_STATS + \
127f26d0d25SEran Ben Elisha 			 NUM_XDP_STATS + NUM_PHY_STATS)
1286fcd2735SEran Ben Elisha 
1296fcd2735SEran Ben Elisha #define MLX4_FIND_NETDEV_STAT(n) (offsetof(struct net_device_stats, n) / \
1306fcd2735SEran Ben Elisha 				  sizeof(((struct net_device_stats *)0)->n))
1316fcd2735SEran Ben Elisha 
132b4b6e842SEran Ben Elisha #endif
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