1b4b6e842SEran Ben Elisha #ifndef _MLX4_STATS_ 2b4b6e842SEran Ben Elisha #define _MLX4_STATS_ 3b4b6e842SEran Ben Elisha 4b4b6e842SEran Ben Elisha #ifdef MLX4_EN_PERF_STAT 5b4b6e842SEran Ben Elisha #define NUM_PERF_STATS NUM_PERF_COUNTERS 6b4b6e842SEran Ben Elisha #else 7b4b6e842SEran Ben Elisha #define NUM_PERF_STATS 0 8b4b6e842SEran Ben Elisha #endif 9b4b6e842SEran Ben Elisha 10b4b6e842SEran Ben Elisha #define NUM_PRIORITIES 9 11b4b6e842SEran Ben Elisha #define NUM_PRIORITY_STATS 2 12b4b6e842SEran Ben Elisha 13b4b6e842SEran Ben Elisha struct mlx4_en_pkt_stats { 14a3333b35SEran Ben Elisha unsigned long rx_multicast_packets; 15a3333b35SEran Ben Elisha unsigned long rx_broadcast_packets; 16a3333b35SEran Ben Elisha unsigned long rx_jabbers; 17a3333b35SEran Ben Elisha unsigned long rx_in_range_length_error; 18a3333b35SEran Ben Elisha unsigned long rx_out_range_length_error; 19a3333b35SEran Ben Elisha unsigned long tx_multicast_packets; 20a3333b35SEran Ben Elisha unsigned long tx_broadcast_packets; 21a3333b35SEran Ben Elisha unsigned long rx_prio[NUM_PRIORITIES][NUM_PRIORITY_STATS]; 22a3333b35SEran Ben Elisha unsigned long tx_prio[NUM_PRIORITIES][NUM_PRIORITY_STATS]; 23a3333b35SEran Ben Elisha #define NUM_PKT_STATS 43 24b4b6e842SEran Ben Elisha }; 25b4b6e842SEran Ben Elisha 26b42de4d0SEran Ben Elisha struct mlx4_en_counter_stats { 27b42de4d0SEran Ben Elisha unsigned long rx_packets; 28b42de4d0SEran Ben Elisha unsigned long rx_bytes; 29b42de4d0SEran Ben Elisha unsigned long tx_packets; 30b42de4d0SEran Ben Elisha unsigned long tx_bytes; 31b42de4d0SEran Ben Elisha #define NUM_PF_STATS 4 32b42de4d0SEran Ben Elisha }; 33b42de4d0SEran Ben Elisha 34b4b6e842SEran Ben Elisha struct mlx4_en_port_stats { 35b4b6e842SEran Ben Elisha unsigned long tso_packets; 36b4b6e842SEran Ben Elisha unsigned long xmit_more; 37b4b6e842SEran Ben Elisha unsigned long queue_stopped; 38b4b6e842SEran Ben Elisha unsigned long wake_queue; 39b4b6e842SEran Ben Elisha unsigned long tx_timeout; 40b4b6e842SEran Ben Elisha unsigned long rx_alloc_failed; 41b4b6e842SEran Ben Elisha unsigned long rx_chksum_good; 42b4b6e842SEran Ben Elisha unsigned long rx_chksum_none; 43b4b6e842SEran Ben Elisha unsigned long rx_chksum_complete; 44b4b6e842SEran Ben Elisha unsigned long tx_chksum_offload; 45b4b6e842SEran Ben Elisha #define NUM_PORT_STATS 10 46b4b6e842SEran Ben Elisha }; 47b4b6e842SEran Ben Elisha 48b4b6e842SEran Ben Elisha struct mlx4_en_perf_stats { 49b4b6e842SEran Ben Elisha u32 tx_poll; 50b4b6e842SEran Ben Elisha u64 tx_pktsz_avg; 51b4b6e842SEran Ben Elisha u32 inflight_avg; 52b4b6e842SEran Ben Elisha u16 tx_coal_avg; 53b4b6e842SEran Ben Elisha u16 rx_coal_avg; 54b4b6e842SEran Ben Elisha u32 napi_quota; 55b4b6e842SEran Ben Elisha #define NUM_PERF_COUNTERS 6 56b4b6e842SEran Ben Elisha }; 57b4b6e842SEran Ben Elisha 58b4b6e842SEran Ben Elisha #define NUM_MAIN_STATS 21 590b131561SMatan Barak 600b131561SMatan Barak #define MLX4_NUM_PRIORITIES 8 610b131561SMatan Barak 620b131561SMatan Barak struct mlx4_en_flow_stats_rx { 630b131561SMatan Barak u64 rx_pause; 640b131561SMatan Barak u64 rx_pause_duration; 650b131561SMatan Barak u64 rx_pause_transition; 660b131561SMatan Barak #define NUM_FLOW_STATS_RX 3 670b131561SMatan Barak #define NUM_FLOW_PRIORITY_STATS_RX (NUM_FLOW_STATS_RX * \ 680b131561SMatan Barak MLX4_NUM_PRIORITIES) 690b131561SMatan Barak }; 700b131561SMatan Barak 710b131561SMatan Barak struct mlx4_en_flow_stats_tx { 720b131561SMatan Barak u64 tx_pause; 730b131561SMatan Barak u64 tx_pause_duration; 740b131561SMatan Barak u64 tx_pause_transition; 750b131561SMatan Barak #define NUM_FLOW_STATS_TX 3 760b131561SMatan Barak #define NUM_FLOW_PRIORITY_STATS_TX (NUM_FLOW_STATS_TX * \ 770b131561SMatan Barak MLX4_NUM_PRIORITIES) 780b131561SMatan Barak }; 790b131561SMatan Barak 800b131561SMatan Barak #define NUM_FLOW_STATS (NUM_FLOW_STATS_RX + NUM_FLOW_STATS_TX + \ 810b131561SMatan Barak NUM_FLOW_PRIORITY_STATS_TX + \ 82b42de4d0SEran Ben Elisha NUM_FLOW_PRIORITY_STATS_RX + \ 83b42de4d0SEran Ben Elisha NUM_PF_STATS) 840b131561SMatan Barak 850b131561SMatan Barak struct mlx4_en_stat_out_flow_control_mbox { 860b131561SMatan Barak /* Total number of PAUSE frames received from the far-end port */ 870b131561SMatan Barak __be64 rx_pause; 880b131561SMatan Barak /* Total number of microseconds that far-end port requested to pause 890b131561SMatan Barak * transmission of packets 900b131561SMatan Barak */ 910b131561SMatan Barak __be64 rx_pause_duration; 920b131561SMatan Barak /* Number of received transmission from XOFF state to XON state */ 930b131561SMatan Barak __be64 rx_pause_transition; 940b131561SMatan Barak /* Total number of PAUSE frames sent from the far-end port */ 950b131561SMatan Barak __be64 tx_pause; 960b131561SMatan Barak /* Total time in microseconds that transmission of packets has been 970b131561SMatan Barak * paused 980b131561SMatan Barak */ 990b131561SMatan Barak __be64 tx_pause_duration; 1000b131561SMatan Barak /* Number of transmitter transitions from XOFF state to XON state */ 1010b131561SMatan Barak __be64 tx_pause_transition; 1020b131561SMatan Barak /* Reserverd */ 1030b131561SMatan Barak __be64 reserved[2]; 1040b131561SMatan Barak }; 1050b131561SMatan Barak 1060b131561SMatan Barak enum { 1070b131561SMatan Barak MLX4_DUMP_ETH_STATS_FLOW_CONTROL = 1 << 12 1080b131561SMatan Barak }; 1090b131561SMatan Barak 110b4b6e842SEran Ben Elisha #define NUM_ALL_STATS (NUM_MAIN_STATS + NUM_PORT_STATS + NUM_PKT_STATS + \ 1110b131561SMatan Barak NUM_FLOW_STATS + NUM_PERF_STATS) 1126fcd2735SEran Ben Elisha 1136fcd2735SEran Ben Elisha #define MLX4_FIND_NETDEV_STAT(n) (offsetof(struct net_device_stats, n) / \ 1146fcd2735SEran Ben Elisha sizeof(((struct net_device_stats *)0)->n)) 1156fcd2735SEran Ben Elisha 116b4b6e842SEran Ben Elisha #endif 117