1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #ifndef _MLX4_EN_H_ 35 #define _MLX4_EN_H_ 36 37 #include <linux/bitops.h> 38 #include <linux/compiler.h> 39 #include <linux/ethtool.h> 40 #include <linux/list.h> 41 #include <linux/mutex.h> 42 #include <linux/netdevice.h> 43 #include <linux/if_vlan.h> 44 #include <linux/net_tstamp.h> 45 #ifdef CONFIG_MLX4_EN_DCB 46 #include <linux/dcbnl.h> 47 #endif 48 #include <linux/cpu_rmap.h> 49 #include <linux/ptp_clock_kernel.h> 50 #include <net/xdp.h> 51 52 #include <linux/mlx4/device.h> 53 #include <linux/mlx4/qp.h> 54 #include <linux/mlx4/cq.h> 55 #include <linux/mlx4/srq.h> 56 #include <linux/mlx4/doorbell.h> 57 #include <linux/mlx4/cmd.h> 58 59 #include "en_port.h" 60 #include "mlx4_stats.h" 61 62 #define DRV_NAME "mlx4_en" 63 #define DRV_VERSION "4.0-0" 64 65 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN) 66 67 /* 68 * Device constants 69 */ 70 71 72 #define MLX4_EN_PAGE_SHIFT 12 73 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT) 74 #define DEF_RX_RINGS 16 75 #define MAX_RX_RINGS 128 76 #define MIN_RX_RINGS 1 77 #define LOG_TXBB_SIZE 6 78 #define TXBB_SIZE BIT(LOG_TXBB_SIZE) 79 #define HEADROOM (2048 / TXBB_SIZE + 1) 80 #define STAMP_STRIDE 64 81 #define STAMP_DWORDS (STAMP_STRIDE / 4) 82 #define STAMP_SHIFT 31 83 #define STAMP_VAL 0x7fffffff 84 #define STATS_DELAY (HZ / 4) 85 #define SERVICE_TASK_DELAY (HZ / 4) 86 #define MAX_NUM_OF_FS_RULES 256 87 88 #define MLX4_EN_FILTER_HASH_SHIFT 4 89 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60 90 91 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */ 92 #define MAX_DESC_SIZE 512 93 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE) 94 95 /* 96 * OS related constants and tunables 97 */ 98 99 #define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1 100 #define MLX4_EN_PRIV_FLAGS_PHV 2 101 102 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ) 103 104 /* Use the maximum between 16384 and a single page */ 105 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384) 106 107 #define MLX4_EN_MAX_RX_FRAGS 4 108 109 /* Maximum ring sizes */ 110 #define MLX4_EN_MAX_TX_SIZE 8192 111 #define MLX4_EN_MAX_RX_SIZE 8192 112 113 /* Minimum ring size for our page-allocation scheme to work */ 114 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES) 115 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE) 116 117 #define MLX4_EN_SMALL_PKT_SIZE 64 118 #define MLX4_EN_MIN_TX_RING_P_UP 1 119 #define MLX4_EN_MAX_TX_RING_P_UP 32 120 #define MLX4_EN_NUM_UP_LOW 1 121 #define MLX4_EN_NUM_UP_HIGH 8 122 #define MLX4_EN_DEF_RX_RING_SIZE 1024 123 #define MLX4_EN_DEF_TX_RING_SIZE MLX4_EN_DEF_RX_RING_SIZE 124 #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \ 125 MLX4_EN_NUM_UP_HIGH) 126 127 #define MLX4_EN_DEFAULT_TX_WORK 256 128 129 /* Target number of packets to coalesce with interrupt moderation */ 130 #define MLX4_EN_RX_COAL_TARGET 44 131 #define MLX4_EN_RX_COAL_TIME 0x10 132 133 #define MLX4_EN_TX_COAL_PKTS 16 134 #define MLX4_EN_TX_COAL_TIME 0x10 135 136 #define MLX4_EN_MAX_COAL_PKTS U16_MAX 137 #define MLX4_EN_MAX_COAL_TIME U16_MAX 138 139 #define MLX4_EN_RX_RATE_LOW 400000 140 #define MLX4_EN_RX_COAL_TIME_LOW 0 141 #define MLX4_EN_RX_RATE_HIGH 450000 142 #define MLX4_EN_RX_COAL_TIME_HIGH 128 143 #define MLX4_EN_RX_SIZE_THRESH 1024 144 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH) 145 #define MLX4_EN_SAMPLE_INTERVAL 0 146 #define MLX4_EN_AVG_PKT_SMALL 256 147 148 #define MLX4_EN_AUTO_CONF 0xffff 149 150 #define MLX4_EN_DEF_RX_PAUSE 1 151 #define MLX4_EN_DEF_TX_PAUSE 1 152 153 /* Interval between successive polls in the Tx routine when polling is used 154 instead of interrupts (in per-core Tx rings) - should be power of 2 */ 155 #define MLX4_EN_TX_POLL_MODER 16 156 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4) 157 158 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN) 159 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN) 160 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN) 161 #define PREAMBLE_LEN 8 162 #define MLX4_SELFTEST_LB_MIN_MTU (MLX4_LOOPBACK_TEST_PAYLOAD + NET_IP_ALIGN + \ 163 ETH_HLEN + PREAMBLE_LEN) 164 165 /* VLAN_HLEN is added twice,to support skb vlan tagged with multiple 166 * headers. (For example: ETH_P_8021Q and ETH_P_8021AD). 167 */ 168 #define MLX4_EN_EFF_MTU(mtu) ((mtu) + ETH_HLEN + (2 * VLAN_HLEN)) 169 #define ETH_BCAST 0xffffffffffffULL 170 171 #define MLX4_EN_LOOPBACK_RETRIES 5 172 #define MLX4_EN_LOOPBACK_TIMEOUT 100 173 174 /* Constants for TX flow */ 175 enum { 176 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */ 177 MAX_BF = 256, 178 MIN_PKT_LEN = 17, 179 }; 180 181 /* 182 * Configurables 183 */ 184 185 enum cq_type { 186 /* keep tx types first */ 187 TX, 188 TX_XDP, 189 #define MLX4_EN_NUM_TX_TYPES (TX_XDP + 1) 190 RX, 191 }; 192 193 194 /* 195 * Useful macros 196 */ 197 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x)) 198 #define XNOR(x, y) (!(x) == !(y)) 199 200 201 struct mlx4_en_tx_info { 202 union { 203 struct sk_buff *skb; 204 struct page *page; 205 }; 206 dma_addr_t map0_dma; 207 u32 map0_byte_count; 208 u32 nr_txbb; 209 u32 nr_bytes; 210 u8 linear; 211 u8 data_offset; 212 u8 inl; 213 u8 ts_requested; 214 u8 nr_maps; 215 } ____cacheline_aligned_in_smp; 216 217 218 #define MLX4_EN_BIT_DESC_OWN 0x80000000 219 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg) 220 #define MLX4_EN_MEMTYPE_PAD 0x100 221 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg) 222 223 224 struct mlx4_en_tx_desc { 225 struct mlx4_wqe_ctrl_seg ctrl; 226 union { 227 struct mlx4_wqe_data_seg data; /* at least one data segment */ 228 struct mlx4_wqe_lso_seg lso; 229 struct mlx4_wqe_inline_seg inl; 230 }; 231 }; 232 233 #define MLX4_EN_USE_SRQ 0x01000000 234 235 #define MLX4_EN_CX3_LOW_ID 0x1000 236 #define MLX4_EN_CX3_HIGH_ID 0x1005 237 238 struct mlx4_en_rx_alloc { 239 struct page *page; 240 dma_addr_t dma; 241 u32 page_offset; 242 }; 243 244 #define MLX4_EN_CACHE_SIZE (2 * NAPI_POLL_WEIGHT) 245 246 struct mlx4_en_page_cache { 247 u32 index; 248 struct { 249 struct page *page; 250 dma_addr_t dma; 251 } buf[MLX4_EN_CACHE_SIZE]; 252 }; 253 254 enum { 255 MLX4_EN_TX_RING_STATE_RECOVERING, 256 }; 257 258 struct mlx4_en_priv; 259 260 struct mlx4_en_tx_ring { 261 /* cache line used and dirtied in tx completion 262 * (mlx4_en_free_tx_buf()) 263 */ 264 u32 last_nr_txbb; 265 u32 cons; 266 unsigned long wake_queue; 267 struct netdev_queue *tx_queue; 268 u32 (*free_tx_desc)(struct mlx4_en_priv *priv, 269 struct mlx4_en_tx_ring *ring, 270 int index, 271 u64 timestamp, int napi_mode); 272 struct mlx4_en_rx_ring *recycle_ring; 273 274 /* cache line used and dirtied in mlx4_en_xmit() */ 275 u32 prod ____cacheline_aligned_in_smp; 276 unsigned int tx_dropped; 277 unsigned long bytes; 278 unsigned long packets; 279 unsigned long tx_csum; 280 unsigned long tso_packets; 281 unsigned long xmit_more; 282 struct mlx4_bf bf; 283 284 /* Following part should be mostly read */ 285 __be32 doorbell_qpn; 286 __be32 mr_key; 287 u32 size; /* number of TXBBs */ 288 u32 size_mask; 289 u32 full_size; 290 u32 buf_size; 291 void *buf; 292 struct mlx4_en_tx_info *tx_info; 293 int qpn; 294 u8 queue_index; 295 bool bf_enabled; 296 bool bf_alloced; 297 u8 hwtstamp_tx_type; 298 u8 *bounce_buf; 299 300 /* Not used in fast path 301 * Only queue_stopped might be used if BQL is not properly working. 302 */ 303 unsigned long queue_stopped; 304 unsigned long state; 305 struct mlx4_hwq_resources sp_wqres; 306 struct mlx4_qp sp_qp; 307 struct mlx4_qp_context sp_context; 308 cpumask_t sp_affinity_mask; 309 enum mlx4_qp_state sp_qp_state; 310 u16 sp_stride; 311 u16 sp_cqn; /* index of port CQ associated with this ring */ 312 } ____cacheline_aligned_in_smp; 313 314 struct mlx4_en_rx_desc { 315 /* actual number of entries depends on rx ring stride */ 316 struct mlx4_wqe_data_seg data[0]; 317 }; 318 319 struct mlx4_en_rx_ring { 320 struct mlx4_hwq_resources wqres; 321 u32 size ; /* number of Rx descs*/ 322 u32 actual_size; 323 u32 size_mask; 324 u16 stride; 325 u16 log_stride; 326 u16 cqn; /* index of port CQ associated with this ring */ 327 u32 prod; 328 u32 cons; 329 u32 buf_size; 330 u8 fcs_del; 331 void *buf; 332 void *rx_info; 333 struct bpf_prog __rcu *xdp_prog; 334 struct mlx4_en_page_cache page_cache; 335 unsigned long bytes; 336 unsigned long packets; 337 unsigned long csum_ok; 338 unsigned long csum_none; 339 unsigned long csum_complete; 340 unsigned long rx_alloc_pages; 341 unsigned long xdp_drop; 342 unsigned long xdp_tx; 343 unsigned long xdp_tx_full; 344 unsigned long dropped; 345 int hwtstamp_rx_filter; 346 cpumask_var_t affinity_mask; 347 struct xdp_rxq_info xdp_rxq; 348 }; 349 350 struct mlx4_en_cq { 351 struct mlx4_cq mcq; 352 struct mlx4_hwq_resources wqres; 353 int ring; 354 struct net_device *dev; 355 union { 356 struct napi_struct napi; 357 bool xdp_busy; 358 }; 359 int size; 360 int buf_size; 361 int vector; 362 enum cq_type type; 363 u16 moder_time; 364 u16 moder_cnt; 365 struct mlx4_cqe *buf; 366 #define MLX4_EN_OPCODE_ERROR 0x1e 367 368 struct irq_desc *irq_desc; 369 }; 370 371 struct mlx4_en_port_profile { 372 u32 flags; 373 u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES]; 374 u32 rx_ring_num; 375 u32 tx_ring_size; 376 u32 rx_ring_size; 377 u8 num_tx_rings_p_up; 378 u8 rx_pause; 379 u8 rx_ppp; 380 u8 tx_pause; 381 u8 tx_ppp; 382 u8 num_up; 383 int rss_rings; 384 int inline_thold; 385 struct hwtstamp_config hwtstamp_config; 386 }; 387 388 struct mlx4_en_profile { 389 int udp_rss; 390 u8 rss_mask; 391 u32 active_ports; 392 u32 small_pkt_int; 393 u8 no_reset; 394 u8 max_num_tx_rings_p_up; 395 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1]; 396 }; 397 398 struct mlx4_en_dev { 399 struct mlx4_dev *dev; 400 struct pci_dev *pdev; 401 struct mutex state_lock; 402 struct net_device *pndev[MLX4_MAX_PORTS + 1]; 403 struct net_device *upper[MLX4_MAX_PORTS + 1]; 404 u32 port_cnt; 405 bool device_up; 406 struct mlx4_en_profile profile; 407 u32 LSO_support; 408 struct workqueue_struct *workqueue; 409 struct device *dma_device; 410 void __iomem *uar_map; 411 struct mlx4_uar priv_uar; 412 struct mlx4_mr mr; 413 u32 priv_pdn; 414 spinlock_t uar_lock; 415 u8 mac_removed[MLX4_MAX_PORTS + 1]; 416 u32 nominal_c_mult; 417 struct cyclecounter cycles; 418 seqlock_t clock_lock; 419 struct timecounter clock; 420 unsigned long last_overflow_check; 421 struct ptp_clock *ptp_clock; 422 struct ptp_clock_info ptp_clock_info; 423 struct notifier_block nb; 424 }; 425 426 427 struct mlx4_en_rss_map { 428 int base_qpn; 429 struct mlx4_qp qps[MAX_RX_RINGS]; 430 enum mlx4_qp_state state[MAX_RX_RINGS]; 431 struct mlx4_qp *indir_qp; 432 enum mlx4_qp_state indir_state; 433 }; 434 435 enum mlx4_en_port_flag { 436 MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */ 437 MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */ 438 }; 439 440 struct mlx4_en_port_state { 441 int link_state; 442 int link_speed; 443 int transceiver; 444 u32 flags; 445 }; 446 447 enum mlx4_en_mclist_act { 448 MCLIST_NONE, 449 MCLIST_REM, 450 MCLIST_ADD, 451 }; 452 453 struct mlx4_en_mc_list { 454 struct list_head list; 455 enum mlx4_en_mclist_act action; 456 u8 addr[ETH_ALEN]; 457 u64 reg_id; 458 u64 tunnel_reg_id; 459 }; 460 461 struct mlx4_en_frag_info { 462 u16 frag_size; 463 u32 frag_stride; 464 }; 465 466 #ifdef CONFIG_MLX4_EN_DCB 467 /* Minimal TC BW - setting to 0 will block traffic */ 468 #define MLX4_EN_BW_MIN 1 469 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */ 470 471 #define MLX4_EN_TC_VENDOR 0 472 #define MLX4_EN_TC_ETS 7 473 474 enum dcb_pfc_type { 475 pfc_disabled = 0, 476 pfc_enabled_full, 477 pfc_enabled_tx, 478 pfc_enabled_rx 479 }; 480 481 struct mlx4_en_cee_config { 482 bool pfc_state; 483 enum dcb_pfc_type dcb_pfc[MLX4_EN_NUM_UP_HIGH]; 484 }; 485 #endif 486 487 struct ethtool_flow_id { 488 struct list_head list; 489 struct ethtool_rx_flow_spec flow_spec; 490 u64 id; 491 }; 492 493 enum { 494 MLX4_EN_FLAG_PROMISC = (1 << 0), 495 MLX4_EN_FLAG_MC_PROMISC = (1 << 1), 496 /* whether we need to enable hardware loopback by putting dmac 497 * in Tx WQE 498 */ 499 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2), 500 /* whether we need to drop packets that hardware loopback-ed */ 501 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3), 502 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4), 503 MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP = (1 << 5), 504 #ifdef CONFIG_MLX4_EN_DCB 505 MLX4_EN_FLAG_DCB_ENABLED = (1 << 6), 506 #endif 507 }; 508 509 #define PORT_BEACON_MAX_LIMIT (65535) 510 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE) 511 #define MLX4_EN_MAC_HASH_IDX 5 512 513 struct mlx4_en_stats_bitmap { 514 DECLARE_BITMAP(bitmap, NUM_ALL_STATS); 515 struct mutex mutex; /* for mutual access to stats bitmap */ 516 }; 517 518 enum { 519 MLX4_EN_STATE_FLAG_RESTARTING, 520 }; 521 522 struct mlx4_en_priv { 523 struct mlx4_en_dev *mdev; 524 struct mlx4_en_port_profile *prof; 525 struct net_device *dev; 526 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 527 struct mlx4_en_port_state port_state; 528 spinlock_t stats_lock; 529 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES]; 530 /* To allow rules removal while port is going down */ 531 struct list_head ethtool_list; 532 533 unsigned long last_moder_packets[MAX_RX_RINGS]; 534 unsigned long last_moder_tx_packets; 535 unsigned long last_moder_bytes[MAX_RX_RINGS]; 536 unsigned long last_moder_jiffies; 537 int last_moder_time[MAX_RX_RINGS]; 538 u16 rx_usecs; 539 u16 rx_frames; 540 u16 tx_usecs; 541 u16 tx_frames; 542 u32 pkt_rate_low; 543 u16 rx_usecs_low; 544 u32 pkt_rate_high; 545 u16 rx_usecs_high; 546 u32 sample_interval; 547 u32 adaptive_rx_coal; 548 u32 msg_enable; 549 u32 loopback_ok; 550 u32 validate_loopback; 551 552 struct mlx4_hwq_resources res; 553 int link_state; 554 int last_link_state; 555 bool port_up; 556 int port; 557 int registered; 558 int allocated; 559 int stride; 560 unsigned char current_mac[ETH_ALEN + 2]; 561 int mac_index; 562 unsigned max_mtu; 563 int base_qpn; 564 int cqe_factor; 565 int cqe_size; 566 567 struct mlx4_en_rss_map rss_map; 568 __be32 ctrl_flags; 569 u32 flags; 570 u8 num_tx_rings_p_up; 571 u32 tx_work_limit; 572 u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES]; 573 u32 rx_ring_num; 574 u32 rx_skb_size; 575 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS]; 576 u8 num_frags; 577 u8 log_rx_info; 578 u8 dma_dir; 579 u16 rx_headroom; 580 581 struct mlx4_en_tx_ring **tx_ring[MLX4_EN_NUM_TX_TYPES]; 582 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS]; 583 struct mlx4_en_cq **tx_cq[MLX4_EN_NUM_TX_TYPES]; 584 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS]; 585 struct mlx4_qp drop_qp; 586 struct work_struct rx_mode_task; 587 struct work_struct restart_task; 588 struct work_struct linkstate_task; 589 struct delayed_work stats_task; 590 struct delayed_work service_task; 591 struct mlx4_en_pkt_stats pkstats; 592 struct mlx4_en_counter_stats pf_stats; 593 struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES]; 594 struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES]; 595 struct mlx4_en_flow_stats_rx rx_flowstats; 596 struct mlx4_en_flow_stats_tx tx_flowstats; 597 struct mlx4_en_port_stats port_stats; 598 struct mlx4_en_xdp_stats xdp_stats; 599 struct mlx4_en_phy_stats phy_stats; 600 struct mlx4_en_stats_bitmap stats_bitmap; 601 struct list_head mc_list; 602 struct list_head curr_list; 603 u64 broadcast_id; 604 struct mlx4_en_stat_out_mbox hw_stats; 605 int vids[128]; 606 bool wol; 607 struct device *ddev; 608 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE]; 609 struct hwtstamp_config hwtstamp_config; 610 u32 counter_index; 611 612 #ifdef CONFIG_MLX4_EN_DCB 613 #define MLX4_EN_DCB_ENABLED 0x3 614 struct ieee_ets ets; 615 u16 maxrate[IEEE_8021QAZ_MAX_TCS]; 616 enum dcbnl_cndd_states cndd_state[IEEE_8021QAZ_MAX_TCS]; 617 struct mlx4_en_cee_config cee_config; 618 u8 dcbx_cap; 619 #endif 620 #ifdef CONFIG_RFS_ACCEL 621 spinlock_t filters_lock; 622 int last_filter_id; 623 struct list_head filters; 624 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT]; 625 #endif 626 u64 tunnel_reg_id; 627 __be16 vxlan_port; 628 629 u32 pflags; 630 u8 rss_key[MLX4_EN_RSS_KEY_SIZE]; 631 u8 rss_hash_fn; 632 unsigned long state; 633 }; 634 635 enum mlx4_en_wol { 636 MLX4_EN_WOL_MAGIC = (1ULL << 61), 637 MLX4_EN_WOL_ENABLED = (1ULL << 62), 638 }; 639 640 struct mlx4_mac_entry { 641 struct hlist_node hlist; 642 unsigned char mac[ETH_ALEN + 2]; 643 u64 reg_id; 644 struct rcu_head rcu; 645 }; 646 647 static inline struct mlx4_cqe *mlx4_en_get_cqe(void *buf, int idx, int cqe_sz) 648 { 649 return buf + idx * cqe_sz; 650 } 651 652 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63) 653 654 void mlx4_en_init_ptys2ethtool_map(void); 655 void mlx4_en_update_loopback_state(struct net_device *dev, 656 netdev_features_t features); 657 658 void mlx4_en_destroy_netdev(struct net_device *dev); 659 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, 660 struct mlx4_en_port_profile *prof); 661 662 int mlx4_en_start_port(struct net_device *dev); 663 void mlx4_en_stop_port(struct net_device *dev, int detach); 664 665 void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev, 666 struct mlx4_en_stats_bitmap *stats_bitmap, 667 u8 rx_ppp, u8 rx_pause, 668 u8 tx_ppp, u8 tx_pause); 669 670 int mlx4_en_try_alloc_resources(struct mlx4_en_priv *priv, 671 struct mlx4_en_priv *tmp, 672 struct mlx4_en_port_profile *prof, 673 bool carry_xdp_prog); 674 void mlx4_en_safe_replace_resources(struct mlx4_en_priv *priv, 675 struct mlx4_en_priv *tmp); 676 677 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq, 678 int entries, int ring, enum cq_type mode, int node); 679 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq); 680 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq, 681 int cq_idx); 682 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 683 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 684 void mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 685 686 void mlx4_en_tx_irq(struct mlx4_cq *mcq); 687 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, 688 struct net_device *sb_dev); 689 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev); 690 netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring, 691 struct mlx4_en_rx_alloc *frame, 692 struct mlx4_en_priv *priv, unsigned int length, 693 int tx_ind, bool *doorbell_pending); 694 void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring); 695 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring, 696 struct mlx4_en_rx_alloc *frame); 697 698 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 699 struct mlx4_en_tx_ring **pring, 700 u32 size, u16 stride, 701 int node, int queue_index); 702 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 703 struct mlx4_en_tx_ring **pring); 704 void mlx4_en_init_tx_xdp_ring_descs(struct mlx4_en_priv *priv, 705 struct mlx4_en_tx_ring *ring); 706 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 707 struct mlx4_en_tx_ring *ring, 708 int cq, int user_prio); 709 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 710 struct mlx4_en_tx_ring *ring); 711 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev); 712 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv); 713 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 714 struct mlx4_en_rx_ring **pring, 715 u32 size, u16 stride, int node, int queue_index); 716 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 717 struct mlx4_en_rx_ring **pring, 718 u32 size, u16 stride); 719 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv); 720 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, 721 struct mlx4_en_rx_ring *ring); 722 int mlx4_en_process_rx_cq(struct net_device *dev, 723 struct mlx4_en_cq *cq, 724 int budget); 725 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget); 726 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget); 727 int mlx4_en_process_tx_cq(struct net_device *dev, 728 struct mlx4_en_cq *cq, int napi_budget); 729 u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, 730 struct mlx4_en_tx_ring *ring, 731 int index, u64 timestamp, 732 int napi_mode); 733 u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv, 734 struct mlx4_en_tx_ring *ring, 735 int index, u64 timestamp, 736 int napi_mode); 737 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, 738 int is_tx, int rss, int qpn, int cqn, int user_prio, 739 struct mlx4_qp_context *context); 740 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event); 741 int mlx4_en_change_mcast_lb(struct mlx4_en_priv *priv, struct mlx4_qp *qp, 742 int loopback); 743 void mlx4_en_calc_rx_buf(struct net_device *dev); 744 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv); 745 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv); 746 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv); 747 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv); 748 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring); 749 void mlx4_en_rx_irq(struct mlx4_cq *mcq); 750 751 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 752 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv); 753 754 void mlx4_en_fold_software_stats(struct net_device *dev); 755 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset); 756 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port); 757 758 #ifdef CONFIG_MLX4_EN_DCB 759 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops; 760 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops; 761 #endif 762 763 int mlx4_en_setup_tc(struct net_device *dev, u8 up); 764 int mlx4_en_alloc_tx_queue_per_tc(struct net_device *dev, u8 tc); 765 766 #ifdef CONFIG_RFS_ACCEL 767 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv); 768 #endif 769 770 #define MLX4_EN_NUM_SELF_TEST 5 771 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf); 772 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev); 773 774 #define DEV_FEATURE_CHANGED(dev, new_features, feature) \ 775 ((dev->features & feature) ^ (new_features & feature)) 776 777 int mlx4_en_reset_config(struct net_device *dev, 778 struct hwtstamp_config ts_config, 779 netdev_features_t new_features); 780 void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev, 781 struct mlx4_en_stats_bitmap *stats_bitmap, 782 u8 rx_ppp, u8 rx_pause, 783 u8 tx_ppp, u8 tx_pause); 784 int mlx4_en_netdev_event(struct notifier_block *this, 785 unsigned long event, void *ptr); 786 787 /* 788 * Functions for time stamping 789 */ 790 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe); 791 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev, 792 struct skb_shared_hwtstamps *hwts, 793 u64 timestamp); 794 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev); 795 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev); 796 797 /* Globals 798 */ 799 extern const struct ethtool_ops mlx4_en_ethtool_ops; 800 801 802 803 /* 804 * printk / logging functions 805 */ 806 807 __printf(3, 4) 808 void en_print(const char *level, const struct mlx4_en_priv *priv, 809 const char *format, ...); 810 811 #define en_dbg(mlevel, priv, format, ...) \ 812 do { \ 813 if (NETIF_MSG_##mlevel & (priv)->msg_enable) \ 814 en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__); \ 815 } while (0) 816 #define en_warn(priv, format, ...) \ 817 en_print(KERN_WARNING, priv, format, ##__VA_ARGS__) 818 #define en_err(priv, format, ...) \ 819 en_print(KERN_ERR, priv, format, ##__VA_ARGS__) 820 #define en_info(priv, format, ...) \ 821 en_print(KERN_INFO, priv, format, ##__VA_ARGS__) 822 823 #define mlx4_err(mdev, format, ...) \ 824 pr_err(DRV_NAME " %s: " format, \ 825 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 826 #define mlx4_info(mdev, format, ...) \ 827 pr_info(DRV_NAME " %s: " format, \ 828 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 829 #define mlx4_warn(mdev, format, ...) \ 830 pr_warn(DRV_NAME " %s: " format, \ 831 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 832 833 #endif 834