1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #ifndef _MLX4_EN_H_ 35 #define _MLX4_EN_H_ 36 37 #include <linux/bitops.h> 38 #include <linux/compiler.h> 39 #include <linux/ethtool.h> 40 #include <linux/list.h> 41 #include <linux/mutex.h> 42 #include <linux/netdevice.h> 43 #include <linux/if_vlan.h> 44 #include <linux/net_tstamp.h> 45 #ifdef CONFIG_MLX4_EN_DCB 46 #include <linux/dcbnl.h> 47 #endif 48 #include <linux/cpu_rmap.h> 49 #include <linux/ptp_clock_kernel.h> 50 #include <linux/irq.h> 51 #include <net/xdp.h> 52 53 #include <linux/mlx4/device.h> 54 #include <linux/mlx4/qp.h> 55 #include <linux/mlx4/cq.h> 56 #include <linux/mlx4/srq.h> 57 #include <linux/mlx4/doorbell.h> 58 #include <linux/mlx4/cmd.h> 59 60 #include "en_port.h" 61 #include "mlx4_stats.h" 62 63 #define DRV_NAME "mlx4_en" 64 #define DRV_VERSION "4.0-0" 65 66 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN) 67 68 /* 69 * Device constants 70 */ 71 72 73 #define MLX4_EN_PAGE_SHIFT 12 74 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT) 75 #define DEF_RX_RINGS 16 76 #define MAX_RX_RINGS 128 77 #define MIN_RX_RINGS 1 78 #define LOG_TXBB_SIZE 6 79 #define TXBB_SIZE BIT(LOG_TXBB_SIZE) 80 #define HEADROOM (2048 / TXBB_SIZE + 1) 81 #define STAMP_STRIDE 64 82 #define STAMP_DWORDS (STAMP_STRIDE / 4) 83 #define STAMP_SHIFT 31 84 #define STAMP_VAL 0x7fffffff 85 #define STATS_DELAY (HZ / 4) 86 #define SERVICE_TASK_DELAY (HZ / 4) 87 #define MAX_NUM_OF_FS_RULES 256 88 89 #define MLX4_EN_FILTER_HASH_SHIFT 4 90 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60 91 92 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */ 93 #define MAX_DESC_SIZE 512 94 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE) 95 96 /* 97 * OS related constants and tunables 98 */ 99 100 #define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1 101 #define MLX4_EN_PRIV_FLAGS_PHV 2 102 103 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ) 104 105 /* Use the maximum between 16384 and a single page */ 106 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384) 107 108 #define MLX4_EN_MAX_RX_FRAGS 4 109 110 /* Maximum ring sizes */ 111 #define MLX4_EN_MAX_TX_SIZE 8192 112 #define MLX4_EN_MAX_RX_SIZE 8192 113 114 /* Minimum ring size for our page-allocation scheme to work */ 115 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES) 116 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE) 117 118 #define MLX4_EN_SMALL_PKT_SIZE 64 119 #define MLX4_EN_MIN_TX_RING_P_UP 1 120 #define MLX4_EN_MAX_TX_RING_P_UP 32 121 #define MLX4_EN_NUM_UP_LOW 1 122 #define MLX4_EN_NUM_UP_HIGH 8 123 #define MLX4_EN_DEF_RX_RING_SIZE 1024 124 #define MLX4_EN_DEF_TX_RING_SIZE MLX4_EN_DEF_RX_RING_SIZE 125 #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \ 126 MLX4_EN_NUM_UP_HIGH) 127 128 #define MLX4_EN_DEFAULT_TX_WORK 256 129 130 /* Target number of packets to coalesce with interrupt moderation */ 131 #define MLX4_EN_RX_COAL_TARGET 44 132 #define MLX4_EN_RX_COAL_TIME 0x10 133 134 #define MLX4_EN_TX_COAL_PKTS 16 135 #define MLX4_EN_TX_COAL_TIME 0x10 136 137 #define MLX4_EN_MAX_COAL_PKTS U16_MAX 138 #define MLX4_EN_MAX_COAL_TIME U16_MAX 139 140 #define MLX4_EN_RX_RATE_LOW 400000 141 #define MLX4_EN_RX_COAL_TIME_LOW 0 142 #define MLX4_EN_RX_RATE_HIGH 450000 143 #define MLX4_EN_RX_COAL_TIME_HIGH 128 144 #define MLX4_EN_RX_SIZE_THRESH 1024 145 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH) 146 #define MLX4_EN_SAMPLE_INTERVAL 0 147 #define MLX4_EN_AVG_PKT_SMALL 256 148 149 #define MLX4_EN_AUTO_CONF 0xffff 150 151 #define MLX4_EN_DEF_RX_PAUSE 1 152 #define MLX4_EN_DEF_TX_PAUSE 1 153 154 /* Interval between successive polls in the Tx routine when polling is used 155 instead of interrupts (in per-core Tx rings) - should be power of 2 */ 156 #define MLX4_EN_TX_POLL_MODER 16 157 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4) 158 159 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN) 160 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN) 161 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN) 162 #define PREAMBLE_LEN 8 163 #define MLX4_SELFTEST_LB_MIN_MTU (MLX4_LOOPBACK_TEST_PAYLOAD + NET_IP_ALIGN + \ 164 ETH_HLEN + PREAMBLE_LEN) 165 166 /* VLAN_HLEN is added twice,to support skb vlan tagged with multiple 167 * headers. (For example: ETH_P_8021Q and ETH_P_8021AD). 168 */ 169 #define MLX4_EN_EFF_MTU(mtu) ((mtu) + ETH_HLEN + (2 * VLAN_HLEN)) 170 #define ETH_BCAST 0xffffffffffffULL 171 172 #define MLX4_EN_LOOPBACK_RETRIES 5 173 #define MLX4_EN_LOOPBACK_TIMEOUT 100 174 175 /* Constants for TX flow */ 176 enum { 177 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */ 178 MAX_BF = 256, 179 MIN_PKT_LEN = 17, 180 }; 181 182 /* 183 * Configurables 184 */ 185 186 enum cq_type { 187 /* keep tx types first */ 188 TX, 189 TX_XDP, 190 #define MLX4_EN_NUM_TX_TYPES (TX_XDP + 1) 191 RX, 192 }; 193 194 195 /* 196 * Useful macros 197 */ 198 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x)) 199 #define XNOR(x, y) (!(x) == !(y)) 200 201 202 struct mlx4_en_tx_info { 203 union { 204 struct sk_buff *skb; 205 struct page *page; 206 }; 207 dma_addr_t map0_dma; 208 u32 map0_byte_count; 209 u32 nr_txbb; 210 u32 nr_bytes; 211 u8 linear; 212 u8 data_offset; 213 u8 inl; 214 u8 ts_requested; 215 u8 nr_maps; 216 } ____cacheline_aligned_in_smp; 217 218 219 #define MLX4_EN_BIT_DESC_OWN 0x80000000 220 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg) 221 #define MLX4_EN_MEMTYPE_PAD 0x100 222 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg) 223 224 225 struct mlx4_en_tx_desc { 226 struct mlx4_wqe_ctrl_seg ctrl; 227 union { 228 struct mlx4_wqe_data_seg data; /* at least one data segment */ 229 struct mlx4_wqe_lso_seg lso; 230 struct mlx4_wqe_inline_seg inl; 231 }; 232 }; 233 234 #define MLX4_EN_USE_SRQ 0x01000000 235 236 #define MLX4_EN_CX3_LOW_ID 0x1000 237 #define MLX4_EN_CX3_HIGH_ID 0x1005 238 239 struct mlx4_en_rx_alloc { 240 struct page *page; 241 dma_addr_t dma; 242 u32 page_offset; 243 }; 244 245 #define MLX4_EN_CACHE_SIZE (2 * NAPI_POLL_WEIGHT) 246 247 struct mlx4_en_page_cache { 248 u32 index; 249 struct { 250 struct page *page; 251 dma_addr_t dma; 252 } buf[MLX4_EN_CACHE_SIZE]; 253 }; 254 255 enum { 256 MLX4_EN_TX_RING_STATE_RECOVERING, 257 }; 258 259 struct mlx4_en_priv; 260 261 struct mlx4_en_tx_ring { 262 /* cache line used and dirtied in tx completion 263 * (mlx4_en_free_tx_buf()) 264 */ 265 u32 last_nr_txbb; 266 u32 cons; 267 unsigned long wake_queue; 268 struct netdev_queue *tx_queue; 269 u32 (*free_tx_desc)(struct mlx4_en_priv *priv, 270 struct mlx4_en_tx_ring *ring, 271 int index, 272 u64 timestamp, int napi_mode); 273 struct mlx4_en_rx_ring *recycle_ring; 274 275 /* cache line used and dirtied in mlx4_en_xmit() */ 276 u32 prod ____cacheline_aligned_in_smp; 277 unsigned int tx_dropped; 278 unsigned long bytes; 279 unsigned long packets; 280 unsigned long tx_csum; 281 unsigned long tso_packets; 282 unsigned long xmit_more; 283 struct mlx4_bf bf; 284 285 /* Following part should be mostly read */ 286 __be32 doorbell_qpn; 287 __be32 mr_key; 288 u32 size; /* number of TXBBs */ 289 u32 size_mask; 290 u32 full_size; 291 u32 buf_size; 292 void *buf; 293 struct mlx4_en_tx_info *tx_info; 294 int qpn; 295 u8 queue_index; 296 bool bf_enabled; 297 bool bf_alloced; 298 u8 hwtstamp_tx_type; 299 u8 *bounce_buf; 300 301 /* Not used in fast path 302 * Only queue_stopped might be used if BQL is not properly working. 303 */ 304 unsigned long queue_stopped; 305 unsigned long state; 306 struct mlx4_hwq_resources sp_wqres; 307 struct mlx4_qp sp_qp; 308 struct mlx4_qp_context sp_context; 309 cpumask_t sp_affinity_mask; 310 enum mlx4_qp_state sp_qp_state; 311 u16 sp_stride; 312 u16 sp_cqn; /* index of port CQ associated with this ring */ 313 } ____cacheline_aligned_in_smp; 314 315 struct mlx4_en_rx_desc { 316 /* actual number of entries depends on rx ring stride */ 317 struct mlx4_wqe_data_seg data[0]; 318 }; 319 320 struct mlx4_en_rx_ring { 321 struct mlx4_hwq_resources wqres; 322 u32 size ; /* number of Rx descs*/ 323 u32 actual_size; 324 u32 size_mask; 325 u16 stride; 326 u16 log_stride; 327 u16 cqn; /* index of port CQ associated with this ring */ 328 u32 prod; 329 u32 cons; 330 u32 buf_size; 331 u8 fcs_del; 332 void *buf; 333 void *rx_info; 334 struct bpf_prog __rcu *xdp_prog; 335 struct mlx4_en_page_cache page_cache; 336 unsigned long bytes; 337 unsigned long packets; 338 unsigned long csum_ok; 339 unsigned long csum_none; 340 unsigned long csum_complete; 341 unsigned long rx_alloc_pages; 342 unsigned long xdp_drop; 343 unsigned long xdp_tx; 344 unsigned long xdp_tx_full; 345 unsigned long dropped; 346 int hwtstamp_rx_filter; 347 cpumask_var_t affinity_mask; 348 struct xdp_rxq_info xdp_rxq; 349 }; 350 351 struct mlx4_en_cq { 352 struct mlx4_cq mcq; 353 struct mlx4_hwq_resources wqres; 354 int ring; 355 struct net_device *dev; 356 union { 357 struct napi_struct napi; 358 bool xdp_busy; 359 }; 360 int size; 361 int buf_size; 362 int vector; 363 enum cq_type type; 364 u16 moder_time; 365 u16 moder_cnt; 366 struct mlx4_cqe *buf; 367 #define MLX4_EN_OPCODE_ERROR 0x1e 368 369 const struct cpumask *aff_mask; 370 }; 371 372 struct mlx4_en_port_profile { 373 u32 flags; 374 u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES]; 375 u32 rx_ring_num; 376 u32 tx_ring_size; 377 u32 rx_ring_size; 378 u8 num_tx_rings_p_up; 379 u8 rx_pause; 380 u8 rx_ppp; 381 u8 tx_pause; 382 u8 tx_ppp; 383 u8 num_up; 384 int rss_rings; 385 int inline_thold; 386 struct hwtstamp_config hwtstamp_config; 387 }; 388 389 struct mlx4_en_profile { 390 int udp_rss; 391 u8 rss_mask; 392 u32 active_ports; 393 u32 small_pkt_int; 394 u8 no_reset; 395 u8 max_num_tx_rings_p_up; 396 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1]; 397 }; 398 399 struct mlx4_en_dev { 400 struct mlx4_dev *dev; 401 struct pci_dev *pdev; 402 struct mutex state_lock; 403 struct net_device *pndev[MLX4_MAX_PORTS + 1]; 404 struct net_device *upper[MLX4_MAX_PORTS + 1]; 405 u32 port_cnt; 406 bool device_up; 407 struct mlx4_en_profile profile; 408 u32 LSO_support; 409 struct workqueue_struct *workqueue; 410 struct device *dma_device; 411 void __iomem *uar_map; 412 struct mlx4_uar priv_uar; 413 struct mlx4_mr mr; 414 u32 priv_pdn; 415 spinlock_t uar_lock; 416 u8 mac_removed[MLX4_MAX_PORTS + 1]; 417 u32 nominal_c_mult; 418 struct cyclecounter cycles; 419 seqlock_t clock_lock; 420 struct timecounter clock; 421 unsigned long last_overflow_check; 422 struct ptp_clock *ptp_clock; 423 struct ptp_clock_info ptp_clock_info; 424 struct notifier_block nb; 425 }; 426 427 428 struct mlx4_en_rss_map { 429 int base_qpn; 430 struct mlx4_qp qps[MAX_RX_RINGS]; 431 enum mlx4_qp_state state[MAX_RX_RINGS]; 432 struct mlx4_qp *indir_qp; 433 enum mlx4_qp_state indir_state; 434 }; 435 436 enum mlx4_en_port_flag { 437 MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */ 438 MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */ 439 }; 440 441 struct mlx4_en_port_state { 442 int link_state; 443 int link_speed; 444 int transceiver; 445 u32 flags; 446 }; 447 448 enum mlx4_en_mclist_act { 449 MCLIST_NONE, 450 MCLIST_REM, 451 MCLIST_ADD, 452 }; 453 454 struct mlx4_en_mc_list { 455 struct list_head list; 456 enum mlx4_en_mclist_act action; 457 u8 addr[ETH_ALEN]; 458 u64 reg_id; 459 u64 tunnel_reg_id; 460 }; 461 462 struct mlx4_en_frag_info { 463 u16 frag_size; 464 u32 frag_stride; 465 }; 466 467 #ifdef CONFIG_MLX4_EN_DCB 468 /* Minimal TC BW - setting to 0 will block traffic */ 469 #define MLX4_EN_BW_MIN 1 470 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */ 471 472 #define MLX4_EN_TC_VENDOR 0 473 #define MLX4_EN_TC_ETS 7 474 475 enum dcb_pfc_type { 476 pfc_disabled = 0, 477 pfc_enabled_full, 478 pfc_enabled_tx, 479 pfc_enabled_rx 480 }; 481 482 struct mlx4_en_cee_config { 483 bool pfc_state; 484 enum dcb_pfc_type dcb_pfc[MLX4_EN_NUM_UP_HIGH]; 485 }; 486 #endif 487 488 struct ethtool_flow_id { 489 struct list_head list; 490 struct ethtool_rx_flow_spec flow_spec; 491 u64 id; 492 }; 493 494 enum { 495 MLX4_EN_FLAG_PROMISC = (1 << 0), 496 MLX4_EN_FLAG_MC_PROMISC = (1 << 1), 497 /* whether we need to enable hardware loopback by putting dmac 498 * in Tx WQE 499 */ 500 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2), 501 /* whether we need to drop packets that hardware loopback-ed */ 502 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3), 503 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4), 504 MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP = (1 << 5), 505 #ifdef CONFIG_MLX4_EN_DCB 506 MLX4_EN_FLAG_DCB_ENABLED = (1 << 6), 507 #endif 508 }; 509 510 #define PORT_BEACON_MAX_LIMIT (65535) 511 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE) 512 #define MLX4_EN_MAC_HASH_IDX 5 513 514 struct mlx4_en_stats_bitmap { 515 DECLARE_BITMAP(bitmap, NUM_ALL_STATS); 516 struct mutex mutex; /* for mutual access to stats bitmap */ 517 }; 518 519 enum { 520 MLX4_EN_STATE_FLAG_RESTARTING, 521 }; 522 523 struct mlx4_en_priv { 524 struct mlx4_en_dev *mdev; 525 struct mlx4_en_port_profile *prof; 526 struct net_device *dev; 527 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 528 struct mlx4_en_port_state port_state; 529 spinlock_t stats_lock; 530 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES]; 531 /* To allow rules removal while port is going down */ 532 struct list_head ethtool_list; 533 534 unsigned long last_moder_packets[MAX_RX_RINGS]; 535 unsigned long last_moder_tx_packets; 536 unsigned long last_moder_bytes[MAX_RX_RINGS]; 537 unsigned long last_moder_jiffies; 538 int last_moder_time[MAX_RX_RINGS]; 539 u16 rx_usecs; 540 u16 rx_frames; 541 u16 tx_usecs; 542 u16 tx_frames; 543 u32 pkt_rate_low; 544 u16 rx_usecs_low; 545 u32 pkt_rate_high; 546 u16 rx_usecs_high; 547 u32 sample_interval; 548 u32 adaptive_rx_coal; 549 u32 msg_enable; 550 u32 loopback_ok; 551 u32 validate_loopback; 552 553 struct mlx4_hwq_resources res; 554 int link_state; 555 int last_link_state; 556 bool port_up; 557 int port; 558 int registered; 559 int allocated; 560 int stride; 561 unsigned char current_mac[ETH_ALEN + 2]; 562 int mac_index; 563 unsigned max_mtu; 564 int base_qpn; 565 int cqe_factor; 566 int cqe_size; 567 568 struct mlx4_en_rss_map rss_map; 569 __be32 ctrl_flags; 570 u32 flags; 571 u8 num_tx_rings_p_up; 572 u32 tx_work_limit; 573 u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES]; 574 u32 rx_ring_num; 575 u32 rx_skb_size; 576 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS]; 577 u8 num_frags; 578 u8 log_rx_info; 579 u8 dma_dir; 580 u16 rx_headroom; 581 582 struct mlx4_en_tx_ring **tx_ring[MLX4_EN_NUM_TX_TYPES]; 583 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS]; 584 struct mlx4_en_cq **tx_cq[MLX4_EN_NUM_TX_TYPES]; 585 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS]; 586 struct mlx4_qp drop_qp; 587 struct work_struct rx_mode_task; 588 struct work_struct restart_task; 589 struct work_struct linkstate_task; 590 struct delayed_work stats_task; 591 struct delayed_work service_task; 592 struct mlx4_en_pkt_stats pkstats; 593 struct mlx4_en_counter_stats pf_stats; 594 struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES]; 595 struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES]; 596 struct mlx4_en_flow_stats_rx rx_flowstats; 597 struct mlx4_en_flow_stats_tx tx_flowstats; 598 struct mlx4_en_port_stats port_stats; 599 struct mlx4_en_xdp_stats xdp_stats; 600 struct mlx4_en_phy_stats phy_stats; 601 struct mlx4_en_stats_bitmap stats_bitmap; 602 struct list_head mc_list; 603 struct list_head curr_list; 604 u64 broadcast_id; 605 struct mlx4_en_stat_out_mbox hw_stats; 606 int vids[128]; 607 bool wol; 608 struct device *ddev; 609 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE]; 610 struct hwtstamp_config hwtstamp_config; 611 u32 counter_index; 612 613 #ifdef CONFIG_MLX4_EN_DCB 614 #define MLX4_EN_DCB_ENABLED 0x3 615 struct ieee_ets ets; 616 u16 maxrate[IEEE_8021QAZ_MAX_TCS]; 617 enum dcbnl_cndd_states cndd_state[IEEE_8021QAZ_MAX_TCS]; 618 struct mlx4_en_cee_config cee_config; 619 u8 dcbx_cap; 620 #endif 621 #ifdef CONFIG_RFS_ACCEL 622 spinlock_t filters_lock; 623 int last_filter_id; 624 struct list_head filters; 625 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT]; 626 #endif 627 u64 tunnel_reg_id; 628 __be16 vxlan_port; 629 630 u32 pflags; 631 u8 rss_key[MLX4_EN_RSS_KEY_SIZE]; 632 u8 rss_hash_fn; 633 unsigned long state; 634 }; 635 636 enum mlx4_en_wol { 637 MLX4_EN_WOL_MAGIC = (1ULL << 61), 638 MLX4_EN_WOL_ENABLED = (1ULL << 62), 639 }; 640 641 struct mlx4_mac_entry { 642 struct hlist_node hlist; 643 unsigned char mac[ETH_ALEN + 2]; 644 u64 reg_id; 645 struct rcu_head rcu; 646 }; 647 648 static inline struct mlx4_cqe *mlx4_en_get_cqe(void *buf, int idx, int cqe_sz) 649 { 650 return buf + idx * cqe_sz; 651 } 652 653 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63) 654 655 void mlx4_en_init_ptys2ethtool_map(void); 656 void mlx4_en_update_loopback_state(struct net_device *dev, 657 netdev_features_t features); 658 659 void mlx4_en_destroy_netdev(struct net_device *dev); 660 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, 661 struct mlx4_en_port_profile *prof); 662 663 int mlx4_en_start_port(struct net_device *dev); 664 void mlx4_en_stop_port(struct net_device *dev, int detach); 665 666 void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev, 667 struct mlx4_en_stats_bitmap *stats_bitmap, 668 u8 rx_ppp, u8 rx_pause, 669 u8 tx_ppp, u8 tx_pause); 670 671 int mlx4_en_try_alloc_resources(struct mlx4_en_priv *priv, 672 struct mlx4_en_priv *tmp, 673 struct mlx4_en_port_profile *prof, 674 bool carry_xdp_prog); 675 void mlx4_en_safe_replace_resources(struct mlx4_en_priv *priv, 676 struct mlx4_en_priv *tmp); 677 678 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq, 679 int entries, int ring, enum cq_type mode, int node); 680 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq); 681 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq, 682 int cq_idx); 683 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 684 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 685 void mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 686 687 void mlx4_en_tx_irq(struct mlx4_cq *mcq); 688 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, 689 struct net_device *sb_dev); 690 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev); 691 netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring, 692 struct mlx4_en_rx_alloc *frame, 693 struct mlx4_en_priv *priv, unsigned int length, 694 int tx_ind, bool *doorbell_pending); 695 void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring); 696 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring, 697 struct mlx4_en_rx_alloc *frame); 698 699 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 700 struct mlx4_en_tx_ring **pring, 701 u32 size, u16 stride, 702 int node, int queue_index); 703 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 704 struct mlx4_en_tx_ring **pring); 705 void mlx4_en_init_tx_xdp_ring_descs(struct mlx4_en_priv *priv, 706 struct mlx4_en_tx_ring *ring); 707 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 708 struct mlx4_en_tx_ring *ring, 709 int cq, int user_prio); 710 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 711 struct mlx4_en_tx_ring *ring); 712 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev); 713 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv); 714 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 715 struct mlx4_en_rx_ring **pring, 716 u32 size, u16 stride, int node, int queue_index); 717 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 718 struct mlx4_en_rx_ring **pring, 719 u32 size, u16 stride); 720 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv); 721 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, 722 struct mlx4_en_rx_ring *ring); 723 int mlx4_en_process_rx_cq(struct net_device *dev, 724 struct mlx4_en_cq *cq, 725 int budget); 726 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget); 727 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget); 728 int mlx4_en_process_tx_cq(struct net_device *dev, 729 struct mlx4_en_cq *cq, int napi_budget); 730 u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, 731 struct mlx4_en_tx_ring *ring, 732 int index, u64 timestamp, 733 int napi_mode); 734 u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv, 735 struct mlx4_en_tx_ring *ring, 736 int index, u64 timestamp, 737 int napi_mode); 738 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, 739 int is_tx, int rss, int qpn, int cqn, int user_prio, 740 struct mlx4_qp_context *context); 741 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event); 742 int mlx4_en_change_mcast_lb(struct mlx4_en_priv *priv, struct mlx4_qp *qp, 743 int loopback); 744 void mlx4_en_calc_rx_buf(struct net_device *dev); 745 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv); 746 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv); 747 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv); 748 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv); 749 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring); 750 void mlx4_en_rx_irq(struct mlx4_cq *mcq); 751 752 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 753 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv); 754 755 void mlx4_en_fold_software_stats(struct net_device *dev); 756 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset); 757 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port); 758 759 #ifdef CONFIG_MLX4_EN_DCB 760 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops; 761 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops; 762 #endif 763 764 int mlx4_en_setup_tc(struct net_device *dev, u8 up); 765 int mlx4_en_alloc_tx_queue_per_tc(struct net_device *dev, u8 tc); 766 767 #ifdef CONFIG_RFS_ACCEL 768 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv); 769 #endif 770 771 #define MLX4_EN_NUM_SELF_TEST 5 772 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf); 773 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev); 774 775 #define DEV_FEATURE_CHANGED(dev, new_features, feature) \ 776 ((dev->features & feature) ^ (new_features & feature)) 777 778 int mlx4_en_reset_config(struct net_device *dev, 779 struct hwtstamp_config ts_config, 780 netdev_features_t new_features); 781 void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev, 782 struct mlx4_en_stats_bitmap *stats_bitmap, 783 u8 rx_ppp, u8 rx_pause, 784 u8 tx_ppp, u8 tx_pause); 785 int mlx4_en_netdev_event(struct notifier_block *this, 786 unsigned long event, void *ptr); 787 788 /* 789 * Functions for time stamping 790 */ 791 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe); 792 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev, 793 struct skb_shared_hwtstamps *hwts, 794 u64 timestamp); 795 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev); 796 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev); 797 798 /* Globals 799 */ 800 extern const struct ethtool_ops mlx4_en_ethtool_ops; 801 802 803 804 /* 805 * printk / logging functions 806 */ 807 808 __printf(3, 4) 809 void en_print(const char *level, const struct mlx4_en_priv *priv, 810 const char *format, ...); 811 812 #define en_dbg(mlevel, priv, format, ...) \ 813 do { \ 814 if (NETIF_MSG_##mlevel & (priv)->msg_enable) \ 815 en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__); \ 816 } while (0) 817 #define en_warn(priv, format, ...) \ 818 en_print(KERN_WARNING, priv, format, ##__VA_ARGS__) 819 #define en_err(priv, format, ...) \ 820 en_print(KERN_ERR, priv, format, ##__VA_ARGS__) 821 #define en_info(priv, format, ...) \ 822 en_print(KERN_INFO, priv, format, ##__VA_ARGS__) 823 824 #define mlx4_err(mdev, format, ...) \ 825 pr_err(DRV_NAME " %s: " format, \ 826 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 827 #define mlx4_info(mdev, format, ...) \ 828 pr_info(DRV_NAME " %s: " format, \ 829 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 830 #define mlx4_warn(mdev, format, ...) \ 831 pr_warn(DRV_NAME " %s: " format, \ 832 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 833 834 #endif 835