1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #ifndef _MLX4_EN_H_ 35 #define _MLX4_EN_H_ 36 37 #include <linux/bitops.h> 38 #include <linux/compiler.h> 39 #include <linux/list.h> 40 #include <linux/mutex.h> 41 #include <linux/netdevice.h> 42 #include <linux/if_vlan.h> 43 #include <linux/net_tstamp.h> 44 #ifdef CONFIG_MLX4_EN_DCB 45 #include <linux/dcbnl.h> 46 #endif 47 #include <linux/cpu_rmap.h> 48 #include <linux/ptp_clock_kernel.h> 49 50 #include <linux/mlx4/device.h> 51 #include <linux/mlx4/qp.h> 52 #include <linux/mlx4/cq.h> 53 #include <linux/mlx4/srq.h> 54 #include <linux/mlx4/doorbell.h> 55 #include <linux/mlx4/cmd.h> 56 57 #include "en_port.h" 58 59 #define DRV_NAME "mlx4_en" 60 #define DRV_VERSION "2.2-1" 61 #define DRV_RELDATE "Feb 2014" 62 63 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN) 64 65 /* 66 * Device constants 67 */ 68 69 70 #define MLX4_EN_PAGE_SHIFT 12 71 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT) 72 #define DEF_RX_RINGS 16 73 #define MAX_RX_RINGS 128 74 #define MIN_RX_RINGS 4 75 #define TXBB_SIZE 64 76 #define HEADROOM (2048 / TXBB_SIZE + 1) 77 #define STAMP_STRIDE 64 78 #define STAMP_DWORDS (STAMP_STRIDE / 4) 79 #define STAMP_SHIFT 31 80 #define STAMP_VAL 0x7fffffff 81 #define STATS_DELAY (HZ / 4) 82 #define SERVICE_TASK_DELAY (HZ / 4) 83 #define MAX_NUM_OF_FS_RULES 256 84 85 #define MLX4_EN_FILTER_HASH_SHIFT 4 86 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60 87 88 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */ 89 #define MAX_DESC_SIZE 512 90 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE) 91 92 /* 93 * OS related constants and tunables 94 */ 95 96 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ) 97 98 /* Use the maximum between 16384 and a single page */ 99 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384) 100 101 #define MLX4_EN_ALLOC_PREFER_ORDER PAGE_ALLOC_COSTLY_ORDER 102 103 /* Receive fragment sizes; we use at most 3 fragments (for 9600 byte MTU 104 * and 4K allocations) */ 105 enum { 106 FRAG_SZ0 = 1536 - NET_IP_ALIGN, 107 FRAG_SZ1 = 4096, 108 FRAG_SZ2 = 4096, 109 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE 110 }; 111 #define MLX4_EN_MAX_RX_FRAGS 4 112 113 /* Maximum ring sizes */ 114 #define MLX4_EN_MAX_TX_SIZE 8192 115 #define MLX4_EN_MAX_RX_SIZE 8192 116 117 /* Minimum ring size for our page-allocation scheme to work */ 118 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES) 119 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE) 120 121 #define MLX4_EN_SMALL_PKT_SIZE 64 122 #define MLX4_EN_MAX_TX_RING_P_UP 32 123 #define MLX4_EN_NUM_UP 8 124 #define MLX4_EN_DEF_TX_RING_SIZE 512 125 #define MLX4_EN_DEF_RX_RING_SIZE 1024 126 #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \ 127 MLX4_EN_NUM_UP) 128 129 #define MLX4_EN_DEFAULT_TX_WORK 256 130 131 /* Target number of packets to coalesce with interrupt moderation */ 132 #define MLX4_EN_RX_COAL_TARGET 44 133 #define MLX4_EN_RX_COAL_TIME 0x10 134 135 #define MLX4_EN_TX_COAL_PKTS 16 136 #define MLX4_EN_TX_COAL_TIME 0x10 137 138 #define MLX4_EN_RX_RATE_LOW 400000 139 #define MLX4_EN_RX_COAL_TIME_LOW 0 140 #define MLX4_EN_RX_RATE_HIGH 450000 141 #define MLX4_EN_RX_COAL_TIME_HIGH 128 142 #define MLX4_EN_RX_SIZE_THRESH 1024 143 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH) 144 #define MLX4_EN_SAMPLE_INTERVAL 0 145 #define MLX4_EN_AVG_PKT_SMALL 256 146 147 #define MLX4_EN_AUTO_CONF 0xffff 148 149 #define MLX4_EN_DEF_RX_PAUSE 1 150 #define MLX4_EN_DEF_TX_PAUSE 1 151 152 /* Interval between successive polls in the Tx routine when polling is used 153 instead of interrupts (in per-core Tx rings) - should be power of 2 */ 154 #define MLX4_EN_TX_POLL_MODER 16 155 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4) 156 157 #define ETH_LLC_SNAP_SIZE 8 158 159 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN) 160 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN) 161 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN) 162 163 #define MLX4_EN_MIN_MTU 46 164 #define ETH_BCAST 0xffffffffffffULL 165 166 #define MLX4_EN_LOOPBACK_RETRIES 5 167 #define MLX4_EN_LOOPBACK_TIMEOUT 100 168 169 #ifdef MLX4_EN_PERF_STAT 170 /* Number of samples to 'average' */ 171 #define AVG_SIZE 128 172 #define AVG_FACTOR 1024 173 #define NUM_PERF_STATS NUM_PERF_COUNTERS 174 175 #define INC_PERF_COUNTER(cnt) (++(cnt)) 176 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add)) 177 #define AVG_PERF_COUNTER(cnt, sample) \ 178 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE) 179 #define GET_PERF_COUNTER(cnt) (cnt) 180 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR) 181 182 #else 183 184 #define NUM_PERF_STATS 0 185 #define INC_PERF_COUNTER(cnt) do {} while (0) 186 #define ADD_PERF_COUNTER(cnt, add) do {} while (0) 187 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0) 188 #define GET_PERF_COUNTER(cnt) (0) 189 #define GET_AVG_PERF_COUNTER(cnt) (0) 190 #endif /* MLX4_EN_PERF_STAT */ 191 192 /* Constants for TX flow */ 193 enum { 194 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */ 195 MAX_BF = 256, 196 MIN_PKT_LEN = 17, 197 }; 198 199 /* 200 * Configurables 201 */ 202 203 enum cq_type { 204 RX = 0, 205 TX = 1, 206 }; 207 208 209 /* 210 * Useful macros 211 */ 212 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x)) 213 #define XNOR(x, y) (!(x) == !(y)) 214 215 216 struct mlx4_en_tx_info { 217 struct sk_buff *skb; 218 u32 nr_txbb; 219 u32 nr_bytes; 220 u8 linear; 221 u8 data_offset; 222 u8 inl; 223 u8 ts_requested; 224 }; 225 226 227 #define MLX4_EN_BIT_DESC_OWN 0x80000000 228 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg) 229 #define MLX4_EN_MEMTYPE_PAD 0x100 230 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg) 231 232 233 struct mlx4_en_tx_desc { 234 struct mlx4_wqe_ctrl_seg ctrl; 235 union { 236 struct mlx4_wqe_data_seg data; /* at least one data segment */ 237 struct mlx4_wqe_lso_seg lso; 238 struct mlx4_wqe_inline_seg inl; 239 }; 240 }; 241 242 #define MLX4_EN_USE_SRQ 0x01000000 243 244 #define MLX4_EN_CX3_LOW_ID 0x1000 245 #define MLX4_EN_CX3_HIGH_ID 0x1005 246 247 struct mlx4_en_rx_alloc { 248 struct page *page; 249 dma_addr_t dma; 250 u32 page_offset; 251 u32 page_size; 252 }; 253 254 struct mlx4_en_tx_ring { 255 struct mlx4_hwq_resources wqres; 256 u32 size ; /* number of TXBBs */ 257 u32 size_mask; 258 u16 stride; 259 u16 cqn; /* index of port CQ associated with this ring */ 260 u32 prod; 261 u32 cons; 262 u32 buf_size; 263 u32 doorbell_qpn; 264 void *buf; 265 u16 poll_cnt; 266 struct mlx4_en_tx_info *tx_info; 267 u8 *bounce_buf; 268 u8 queue_index; 269 cpumask_t affinity_mask; 270 u32 last_nr_txbb; 271 struct mlx4_qp qp; 272 struct mlx4_qp_context context; 273 int qpn; 274 enum mlx4_qp_state qp_state; 275 struct mlx4_srq dummy; 276 unsigned long bytes; 277 unsigned long packets; 278 unsigned long tx_csum; 279 unsigned long queue_stopped; 280 unsigned long wake_queue; 281 struct mlx4_bf bf; 282 bool bf_enabled; 283 struct netdev_queue *tx_queue; 284 int hwtstamp_tx_type; 285 int inline_thold; 286 }; 287 288 struct mlx4_en_rx_desc { 289 /* actual number of entries depends on rx ring stride */ 290 struct mlx4_wqe_data_seg data[0]; 291 }; 292 293 struct mlx4_en_rx_ring { 294 struct mlx4_hwq_resources wqres; 295 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS]; 296 u32 size ; /* number of Rx descs*/ 297 u32 actual_size; 298 u32 size_mask; 299 u16 stride; 300 u16 log_stride; 301 u16 cqn; /* index of port CQ associated with this ring */ 302 u32 prod; 303 u32 cons; 304 u32 buf_size; 305 u8 fcs_del; 306 void *buf; 307 void *rx_info; 308 unsigned long bytes; 309 unsigned long packets; 310 #ifdef CONFIG_NET_RX_BUSY_POLL 311 unsigned long yields; 312 unsigned long misses; 313 unsigned long cleaned; 314 #endif 315 unsigned long csum_ok; 316 unsigned long csum_none; 317 int hwtstamp_rx_filter; 318 cpumask_var_t affinity_mask; 319 }; 320 321 struct mlx4_en_cq { 322 struct mlx4_cq mcq; 323 struct mlx4_hwq_resources wqres; 324 int ring; 325 struct net_device *dev; 326 struct napi_struct napi; 327 int size; 328 int buf_size; 329 unsigned vector; 330 enum cq_type is_tx; 331 u16 moder_time; 332 u16 moder_cnt; 333 struct mlx4_cqe *buf; 334 #define MLX4_EN_OPCODE_ERROR 0x1e 335 336 #ifdef CONFIG_NET_RX_BUSY_POLL 337 unsigned int state; 338 #define MLX4_EN_CQ_STATE_IDLE 0 339 #define MLX4_EN_CQ_STATE_NAPI 1 /* NAPI owns this CQ */ 340 #define MLX4_EN_CQ_STATE_POLL 2 /* poll owns this CQ */ 341 #define MLX4_CQ_LOCKED (MLX4_EN_CQ_STATE_NAPI | MLX4_EN_CQ_STATE_POLL) 342 #define MLX4_EN_CQ_STATE_NAPI_YIELD 4 /* NAPI yielded this CQ */ 343 #define MLX4_EN_CQ_STATE_POLL_YIELD 8 /* poll yielded this CQ */ 344 #define CQ_YIELD (MLX4_EN_CQ_STATE_NAPI_YIELD | MLX4_EN_CQ_STATE_POLL_YIELD) 345 #define CQ_USER_PEND (MLX4_EN_CQ_STATE_POLL | MLX4_EN_CQ_STATE_POLL_YIELD) 346 spinlock_t poll_lock; /* protects from LLS/napi conflicts */ 347 #endif /* CONFIG_NET_RX_BUSY_POLL */ 348 struct irq_desc *irq_desc; 349 }; 350 351 struct mlx4_en_port_profile { 352 u32 flags; 353 u32 tx_ring_num; 354 u32 rx_ring_num; 355 u32 tx_ring_size; 356 u32 rx_ring_size; 357 u8 rx_pause; 358 u8 rx_ppp; 359 u8 tx_pause; 360 u8 tx_ppp; 361 int rss_rings; 362 int inline_thold; 363 }; 364 365 struct mlx4_en_profile { 366 int rss_xor; 367 int udp_rss; 368 u8 rss_mask; 369 u32 active_ports; 370 u32 small_pkt_int; 371 u8 no_reset; 372 u8 num_tx_rings_p_up; 373 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1]; 374 }; 375 376 struct mlx4_en_dev { 377 struct mlx4_dev *dev; 378 struct pci_dev *pdev; 379 struct mutex state_lock; 380 struct net_device *pndev[MLX4_MAX_PORTS + 1]; 381 u32 port_cnt; 382 bool device_up; 383 struct mlx4_en_profile profile; 384 u32 LSO_support; 385 struct workqueue_struct *workqueue; 386 struct device *dma_device; 387 void __iomem *uar_map; 388 struct mlx4_uar priv_uar; 389 struct mlx4_mr mr; 390 u32 priv_pdn; 391 spinlock_t uar_lock; 392 u8 mac_removed[MLX4_MAX_PORTS + 1]; 393 rwlock_t clock_lock; 394 u32 nominal_c_mult; 395 struct cyclecounter cycles; 396 struct timecounter clock; 397 unsigned long last_overflow_check; 398 unsigned long overflow_period; 399 struct ptp_clock *ptp_clock; 400 struct ptp_clock_info ptp_clock_info; 401 }; 402 403 404 struct mlx4_en_rss_map { 405 int base_qpn; 406 struct mlx4_qp qps[MAX_RX_RINGS]; 407 enum mlx4_qp_state state[MAX_RX_RINGS]; 408 struct mlx4_qp indir_qp; 409 enum mlx4_qp_state indir_state; 410 }; 411 412 struct mlx4_en_port_state { 413 int link_state; 414 int link_speed; 415 int transciver; 416 }; 417 418 struct mlx4_en_pkt_stats { 419 unsigned long broadcast; 420 unsigned long rx_prio[8]; 421 unsigned long tx_prio[8]; 422 #define NUM_PKT_STATS 17 423 }; 424 425 struct mlx4_en_port_stats { 426 unsigned long tso_packets; 427 unsigned long queue_stopped; 428 unsigned long wake_queue; 429 unsigned long tx_timeout; 430 unsigned long rx_alloc_failed; 431 unsigned long rx_chksum_good; 432 unsigned long rx_chksum_none; 433 unsigned long tx_chksum_offload; 434 #define NUM_PORT_STATS 8 435 }; 436 437 struct mlx4_en_perf_stats { 438 u32 tx_poll; 439 u64 tx_pktsz_avg; 440 u32 inflight_avg; 441 u16 tx_coal_avg; 442 u16 rx_coal_avg; 443 u32 napi_quota; 444 #define NUM_PERF_COUNTERS 6 445 }; 446 447 enum mlx4_en_mclist_act { 448 MCLIST_NONE, 449 MCLIST_REM, 450 MCLIST_ADD, 451 }; 452 453 struct mlx4_en_mc_list { 454 struct list_head list; 455 enum mlx4_en_mclist_act action; 456 u8 addr[ETH_ALEN]; 457 u64 reg_id; 458 u64 tunnel_reg_id; 459 }; 460 461 struct mlx4_en_frag_info { 462 u16 frag_size; 463 u16 frag_prefix_size; 464 u16 frag_stride; 465 u16 frag_align; 466 }; 467 468 #ifdef CONFIG_MLX4_EN_DCB 469 /* Minimal TC BW - setting to 0 will block traffic */ 470 #define MLX4_EN_BW_MIN 1 471 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */ 472 473 #define MLX4_EN_TC_ETS 7 474 475 #endif 476 477 struct ethtool_flow_id { 478 struct list_head list; 479 struct ethtool_rx_flow_spec flow_spec; 480 u64 id; 481 }; 482 483 enum { 484 MLX4_EN_FLAG_PROMISC = (1 << 0), 485 MLX4_EN_FLAG_MC_PROMISC = (1 << 1), 486 /* whether we need to enable hardware loopback by putting dmac 487 * in Tx WQE 488 */ 489 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2), 490 /* whether we need to drop packets that hardware loopback-ed */ 491 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3), 492 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4) 493 }; 494 495 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE) 496 #define MLX4_EN_MAC_HASH_IDX 5 497 498 struct mlx4_en_priv { 499 struct mlx4_en_dev *mdev; 500 struct mlx4_en_port_profile *prof; 501 struct net_device *dev; 502 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 503 struct net_device_stats stats; 504 struct net_device_stats ret_stats; 505 struct mlx4_en_port_state port_state; 506 spinlock_t stats_lock; 507 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES]; 508 /* To allow rules removal while port is going down */ 509 struct list_head ethtool_list; 510 511 unsigned long last_moder_packets[MAX_RX_RINGS]; 512 unsigned long last_moder_tx_packets; 513 unsigned long last_moder_bytes[MAX_RX_RINGS]; 514 unsigned long last_moder_jiffies; 515 int last_moder_time[MAX_RX_RINGS]; 516 u16 rx_usecs; 517 u16 rx_frames; 518 u16 tx_usecs; 519 u16 tx_frames; 520 u32 pkt_rate_low; 521 u16 rx_usecs_low; 522 u32 pkt_rate_high; 523 u16 rx_usecs_high; 524 u16 sample_interval; 525 u16 adaptive_rx_coal; 526 u32 msg_enable; 527 u32 loopback_ok; 528 u32 validate_loopback; 529 530 struct mlx4_hwq_resources res; 531 int link_state; 532 int last_link_state; 533 bool port_up; 534 int port; 535 int registered; 536 int allocated; 537 int stride; 538 unsigned char prev_mac[ETH_ALEN + 2]; 539 int mac_index; 540 unsigned max_mtu; 541 int base_qpn; 542 int cqe_factor; 543 544 struct mlx4_en_rss_map rss_map; 545 __be32 ctrl_flags; 546 u32 flags; 547 u8 num_tx_rings_p_up; 548 u32 tx_work_limit; 549 u32 tx_ring_num; 550 u32 rx_ring_num; 551 u32 rx_skb_size; 552 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS]; 553 u16 num_frags; 554 u16 log_rx_info; 555 556 struct mlx4_en_tx_ring **tx_ring; 557 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS]; 558 struct mlx4_en_cq **tx_cq; 559 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS]; 560 struct mlx4_qp drop_qp; 561 struct work_struct rx_mode_task; 562 struct work_struct watchdog_task; 563 struct work_struct linkstate_task; 564 struct delayed_work stats_task; 565 struct delayed_work service_task; 566 #ifdef CONFIG_MLX4_EN_VXLAN 567 struct work_struct vxlan_add_task; 568 struct work_struct vxlan_del_task; 569 #endif 570 struct mlx4_en_perf_stats pstats; 571 struct mlx4_en_pkt_stats pkstats; 572 struct mlx4_en_port_stats port_stats; 573 u64 stats_bitmap; 574 struct list_head mc_list; 575 struct list_head curr_list; 576 u64 broadcast_id; 577 struct mlx4_en_stat_out_mbox hw_stats; 578 int vids[128]; 579 bool wol; 580 struct device *ddev; 581 int base_tx_qpn; 582 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE]; 583 struct hwtstamp_config hwtstamp_config; 584 585 #ifdef CONFIG_MLX4_EN_DCB 586 struct ieee_ets ets; 587 u16 maxrate[IEEE_8021QAZ_MAX_TCS]; 588 #endif 589 #ifdef CONFIG_RFS_ACCEL 590 spinlock_t filters_lock; 591 int last_filter_id; 592 struct list_head filters; 593 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT]; 594 #endif 595 u64 tunnel_reg_id; 596 __be16 vxlan_port; 597 }; 598 599 enum mlx4_en_wol { 600 MLX4_EN_WOL_MAGIC = (1ULL << 61), 601 MLX4_EN_WOL_ENABLED = (1ULL << 62), 602 }; 603 604 struct mlx4_mac_entry { 605 struct hlist_node hlist; 606 unsigned char mac[ETH_ALEN + 2]; 607 u64 reg_id; 608 struct rcu_head rcu; 609 }; 610 611 #ifdef CONFIG_NET_RX_BUSY_POLL 612 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq) 613 { 614 spin_lock_init(&cq->poll_lock); 615 cq->state = MLX4_EN_CQ_STATE_IDLE; 616 } 617 618 /* called from the device poll rutine to get ownership of a cq */ 619 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq) 620 { 621 int rc = true; 622 spin_lock(&cq->poll_lock); 623 if (cq->state & MLX4_CQ_LOCKED) { 624 WARN_ON(cq->state & MLX4_EN_CQ_STATE_NAPI); 625 cq->state |= MLX4_EN_CQ_STATE_NAPI_YIELD; 626 rc = false; 627 } else 628 /* we don't care if someone yielded */ 629 cq->state = MLX4_EN_CQ_STATE_NAPI; 630 spin_unlock(&cq->poll_lock); 631 return rc; 632 } 633 634 /* returns true is someone tried to get the cq while napi had it */ 635 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq) 636 { 637 int rc = false; 638 spin_lock(&cq->poll_lock); 639 WARN_ON(cq->state & (MLX4_EN_CQ_STATE_POLL | 640 MLX4_EN_CQ_STATE_NAPI_YIELD)); 641 642 if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD) 643 rc = true; 644 cq->state = MLX4_EN_CQ_STATE_IDLE; 645 spin_unlock(&cq->poll_lock); 646 return rc; 647 } 648 649 /* called from mlx4_en_low_latency_poll() */ 650 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq) 651 { 652 int rc = true; 653 spin_lock_bh(&cq->poll_lock); 654 if ((cq->state & MLX4_CQ_LOCKED)) { 655 struct net_device *dev = cq->dev; 656 struct mlx4_en_priv *priv = netdev_priv(dev); 657 struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring]; 658 659 cq->state |= MLX4_EN_CQ_STATE_POLL_YIELD; 660 rc = false; 661 rx_ring->yields++; 662 } else 663 /* preserve yield marks */ 664 cq->state |= MLX4_EN_CQ_STATE_POLL; 665 spin_unlock_bh(&cq->poll_lock); 666 return rc; 667 } 668 669 /* returns true if someone tried to get the cq while it was locked */ 670 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq) 671 { 672 int rc = false; 673 spin_lock_bh(&cq->poll_lock); 674 WARN_ON(cq->state & (MLX4_EN_CQ_STATE_NAPI)); 675 676 if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD) 677 rc = true; 678 cq->state = MLX4_EN_CQ_STATE_IDLE; 679 spin_unlock_bh(&cq->poll_lock); 680 return rc; 681 } 682 683 /* true if a socket is polling, even if it did not get the lock */ 684 static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq) 685 { 686 WARN_ON(!(cq->state & MLX4_CQ_LOCKED)); 687 return cq->state & CQ_USER_PEND; 688 } 689 #else 690 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq) 691 { 692 } 693 694 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq) 695 { 696 return true; 697 } 698 699 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq) 700 { 701 return false; 702 } 703 704 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq) 705 { 706 return false; 707 } 708 709 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq) 710 { 711 return false; 712 } 713 714 static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq) 715 { 716 return false; 717 } 718 #endif /* CONFIG_NET_RX_BUSY_POLL */ 719 720 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63) 721 722 void mlx4_en_update_loopback_state(struct net_device *dev, 723 netdev_features_t features); 724 725 void mlx4_en_destroy_netdev(struct net_device *dev); 726 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, 727 struct mlx4_en_port_profile *prof); 728 729 int mlx4_en_start_port(struct net_device *dev); 730 void mlx4_en_stop_port(struct net_device *dev, int detach); 731 732 void mlx4_en_free_resources(struct mlx4_en_priv *priv); 733 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv); 734 735 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq, 736 int entries, int ring, enum cq_type mode, int node); 737 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq); 738 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq, 739 int cq_idx); 740 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 741 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 742 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 743 744 void mlx4_en_tx_irq(struct mlx4_cq *mcq); 745 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, 746 void *accel_priv, select_queue_fallback_t fallback); 747 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev); 748 749 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 750 struct mlx4_en_tx_ring **pring, 751 int qpn, u32 size, u16 stride, 752 int node, int queue_index); 753 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 754 struct mlx4_en_tx_ring **pring); 755 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 756 struct mlx4_en_tx_ring *ring, 757 int cq, int user_prio); 758 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 759 struct mlx4_en_tx_ring *ring); 760 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev); 761 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 762 struct mlx4_en_rx_ring **pring, 763 u32 size, u16 stride, int node); 764 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 765 struct mlx4_en_rx_ring **pring, 766 u32 size, u16 stride); 767 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv); 768 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, 769 struct mlx4_en_rx_ring *ring); 770 int mlx4_en_process_rx_cq(struct net_device *dev, 771 struct mlx4_en_cq *cq, 772 int budget); 773 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget); 774 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget); 775 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, 776 int is_tx, int rss, int qpn, int cqn, int user_prio, 777 struct mlx4_qp_context *context); 778 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event); 779 int mlx4_en_map_buffer(struct mlx4_buf *buf); 780 void mlx4_en_unmap_buffer(struct mlx4_buf *buf); 781 782 void mlx4_en_calc_rx_buf(struct net_device *dev); 783 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv); 784 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv); 785 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv); 786 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv); 787 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring); 788 void mlx4_en_rx_irq(struct mlx4_cq *mcq); 789 790 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 791 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv); 792 793 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset); 794 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port); 795 796 #ifdef CONFIG_MLX4_EN_DCB 797 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops; 798 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops; 799 #endif 800 801 int mlx4_en_setup_tc(struct net_device *dev, u8 up); 802 803 #ifdef CONFIG_RFS_ACCEL 804 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv); 805 #endif 806 807 #define MLX4_EN_NUM_SELF_TEST 5 808 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf); 809 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev); 810 811 /* 812 * Functions for time stamping 813 */ 814 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe); 815 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev, 816 struct skb_shared_hwtstamps *hwts, 817 u64 timestamp); 818 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev); 819 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev); 820 int mlx4_en_timestamp_config(struct net_device *dev, 821 int tx_type, 822 int rx_filter); 823 824 /* Globals 825 */ 826 extern const struct ethtool_ops mlx4_en_ethtool_ops; 827 828 829 830 /* 831 * printk / logging functions 832 */ 833 834 __printf(3, 4) 835 int en_print(const char *level, const struct mlx4_en_priv *priv, 836 const char *format, ...); 837 838 #define en_dbg(mlevel, priv, format, ...) \ 839 do { \ 840 if (NETIF_MSG_##mlevel & (priv)->msg_enable) \ 841 en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__); \ 842 } while (0) 843 #define en_warn(priv, format, ...) \ 844 en_print(KERN_WARNING, priv, format, ##__VA_ARGS__) 845 #define en_err(priv, format, ...) \ 846 en_print(KERN_ERR, priv, format, ##__VA_ARGS__) 847 #define en_info(priv, format, ...) \ 848 en_print(KERN_INFO, priv, format, ##__VA_ARGS__) 849 850 #define mlx4_err(mdev, format, ...) \ 851 pr_err(DRV_NAME " %s: " format, \ 852 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 853 #define mlx4_info(mdev, format, ...) \ 854 pr_info(DRV_NAME " %s: " format, \ 855 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 856 #define mlx4_warn(mdev, format, ...) \ 857 pr_warn(DRV_NAME " %s: " format, \ 858 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 859 860 #endif 861