1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #ifndef _MLX4_EN_H_ 35 #define _MLX4_EN_H_ 36 37 #include <linux/bitops.h> 38 #include <linux/compiler.h> 39 #include <linux/list.h> 40 #include <linux/mutex.h> 41 #include <linux/netdevice.h> 42 #include <linux/if_vlan.h> 43 #include <linux/net_tstamp.h> 44 #ifdef CONFIG_MLX4_EN_DCB 45 #include <linux/dcbnl.h> 46 #endif 47 #include <linux/cpu_rmap.h> 48 #include <linux/ptp_clock_kernel.h> 49 50 #include <linux/mlx4/device.h> 51 #include <linux/mlx4/qp.h> 52 #include <linux/mlx4/cq.h> 53 #include <linux/mlx4/srq.h> 54 #include <linux/mlx4/doorbell.h> 55 #include <linux/mlx4/cmd.h> 56 57 #include "en_port.h" 58 59 #define DRV_NAME "mlx4_en" 60 #define DRV_VERSION "2.2-1" 61 #define DRV_RELDATE "Feb 2014" 62 63 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN) 64 65 /* 66 * Device constants 67 */ 68 69 70 #define MLX4_EN_PAGE_SHIFT 12 71 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT) 72 #define DEF_RX_RINGS 16 73 #define MAX_RX_RINGS 128 74 #define MIN_RX_RINGS 4 75 #define TXBB_SIZE 64 76 #define HEADROOM (2048 / TXBB_SIZE + 1) 77 #define STAMP_STRIDE 64 78 #define STAMP_DWORDS (STAMP_STRIDE / 4) 79 #define STAMP_SHIFT 31 80 #define STAMP_VAL 0x7fffffff 81 #define STATS_DELAY (HZ / 4) 82 #define SERVICE_TASK_DELAY (HZ / 4) 83 #define MAX_NUM_OF_FS_RULES 256 84 85 #define MLX4_EN_FILTER_HASH_SHIFT 4 86 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60 87 88 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */ 89 #define MAX_DESC_SIZE 512 90 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE) 91 92 /* 93 * OS related constants and tunables 94 */ 95 96 #define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1 97 98 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ) 99 100 /* Use the maximum between 16384 and a single page */ 101 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384) 102 103 #define MLX4_EN_ALLOC_PREFER_ORDER PAGE_ALLOC_COSTLY_ORDER 104 105 /* Receive fragment sizes; we use at most 3 fragments (for 9600 byte MTU 106 * and 4K allocations) */ 107 enum { 108 FRAG_SZ0 = 1536 - NET_IP_ALIGN, 109 FRAG_SZ1 = 4096, 110 FRAG_SZ2 = 4096, 111 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE 112 }; 113 #define MLX4_EN_MAX_RX_FRAGS 4 114 115 /* Maximum ring sizes */ 116 #define MLX4_EN_MAX_TX_SIZE 8192 117 #define MLX4_EN_MAX_RX_SIZE 8192 118 119 /* Minimum ring size for our page-allocation scheme to work */ 120 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES) 121 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE) 122 123 #define MLX4_EN_SMALL_PKT_SIZE 64 124 #define MLX4_EN_MIN_TX_RING_P_UP 1 125 #define MLX4_EN_MAX_TX_RING_P_UP 32 126 #define MLX4_EN_NUM_UP 8 127 #define MLX4_EN_DEF_TX_RING_SIZE 512 128 #define MLX4_EN_DEF_RX_RING_SIZE 1024 129 #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \ 130 MLX4_EN_NUM_UP) 131 132 #define MLX4_EN_DEFAULT_TX_WORK 256 133 134 /* Target number of packets to coalesce with interrupt moderation */ 135 #define MLX4_EN_RX_COAL_TARGET 44 136 #define MLX4_EN_RX_COAL_TIME 0x10 137 138 #define MLX4_EN_TX_COAL_PKTS 16 139 #define MLX4_EN_TX_COAL_TIME 0x10 140 141 #define MLX4_EN_RX_RATE_LOW 400000 142 #define MLX4_EN_RX_COAL_TIME_LOW 0 143 #define MLX4_EN_RX_RATE_HIGH 450000 144 #define MLX4_EN_RX_COAL_TIME_HIGH 128 145 #define MLX4_EN_RX_SIZE_THRESH 1024 146 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH) 147 #define MLX4_EN_SAMPLE_INTERVAL 0 148 #define MLX4_EN_AVG_PKT_SMALL 256 149 150 #define MLX4_EN_AUTO_CONF 0xffff 151 152 #define MLX4_EN_DEF_RX_PAUSE 1 153 #define MLX4_EN_DEF_TX_PAUSE 1 154 155 /* Interval between successive polls in the Tx routine when polling is used 156 instead of interrupts (in per-core Tx rings) - should be power of 2 */ 157 #define MLX4_EN_TX_POLL_MODER 16 158 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4) 159 160 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN) 161 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN) 162 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN) 163 164 #define MLX4_EN_MIN_MTU 46 165 #define ETH_BCAST 0xffffffffffffULL 166 167 #define MLX4_EN_LOOPBACK_RETRIES 5 168 #define MLX4_EN_LOOPBACK_TIMEOUT 100 169 170 #ifdef MLX4_EN_PERF_STAT 171 /* Number of samples to 'average' */ 172 #define AVG_SIZE 128 173 #define AVG_FACTOR 1024 174 #define NUM_PERF_STATS NUM_PERF_COUNTERS 175 176 #define INC_PERF_COUNTER(cnt) (++(cnt)) 177 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add)) 178 #define AVG_PERF_COUNTER(cnt, sample) \ 179 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE) 180 #define GET_PERF_COUNTER(cnt) (cnt) 181 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR) 182 183 #else 184 185 #define NUM_PERF_STATS 0 186 #define INC_PERF_COUNTER(cnt) do {} while (0) 187 #define ADD_PERF_COUNTER(cnt, add) do {} while (0) 188 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0) 189 #define GET_PERF_COUNTER(cnt) (0) 190 #define GET_AVG_PERF_COUNTER(cnt) (0) 191 #endif /* MLX4_EN_PERF_STAT */ 192 193 /* Constants for TX flow */ 194 enum { 195 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */ 196 MAX_BF = 256, 197 MIN_PKT_LEN = 17, 198 }; 199 200 /* 201 * Configurables 202 */ 203 204 enum cq_type { 205 RX = 0, 206 TX = 1, 207 }; 208 209 210 /* 211 * Useful macros 212 */ 213 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x)) 214 #define XNOR(x, y) (!(x) == !(y)) 215 216 217 struct mlx4_en_tx_info { 218 struct sk_buff *skb; 219 dma_addr_t map0_dma; 220 u32 map0_byte_count; 221 u32 nr_txbb; 222 u32 nr_bytes; 223 u8 linear; 224 u8 data_offset; 225 u8 inl; 226 u8 ts_requested; 227 u8 nr_maps; 228 } ____cacheline_aligned_in_smp; 229 230 231 #define MLX4_EN_BIT_DESC_OWN 0x80000000 232 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg) 233 #define MLX4_EN_MEMTYPE_PAD 0x100 234 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg) 235 236 237 struct mlx4_en_tx_desc { 238 struct mlx4_wqe_ctrl_seg ctrl; 239 union { 240 struct mlx4_wqe_data_seg data; /* at least one data segment */ 241 struct mlx4_wqe_lso_seg lso; 242 struct mlx4_wqe_inline_seg inl; 243 }; 244 }; 245 246 #define MLX4_EN_USE_SRQ 0x01000000 247 248 #define MLX4_EN_CX3_LOW_ID 0x1000 249 #define MLX4_EN_CX3_HIGH_ID 0x1005 250 251 struct mlx4_en_rx_alloc { 252 struct page *page; 253 dma_addr_t dma; 254 u32 page_offset; 255 u32 page_size; 256 }; 257 258 struct mlx4_en_tx_ring { 259 /* cache line used and dirtied in tx completion 260 * (mlx4_en_free_tx_buf()) 261 */ 262 u32 last_nr_txbb; 263 u32 cons; 264 unsigned long wake_queue; 265 266 /* cache line used and dirtied in mlx4_en_xmit() */ 267 u32 prod ____cacheline_aligned_in_smp; 268 unsigned long bytes; 269 unsigned long packets; 270 unsigned long tx_csum; 271 unsigned long tso_packets; 272 unsigned long xmit_more; 273 struct mlx4_bf bf; 274 unsigned long queue_stopped; 275 276 /* Following part should be mostly read */ 277 cpumask_t affinity_mask; 278 struct mlx4_qp qp; 279 struct mlx4_hwq_resources wqres; 280 u32 size; /* number of TXBBs */ 281 u32 size_mask; 282 u16 stride; 283 u16 cqn; /* index of port CQ associated with this ring */ 284 u32 buf_size; 285 __be32 doorbell_qpn; 286 __be32 mr_key; 287 void *buf; 288 struct mlx4_en_tx_info *tx_info; 289 u8 *bounce_buf; 290 struct mlx4_qp_context context; 291 int qpn; 292 enum mlx4_qp_state qp_state; 293 u8 queue_index; 294 bool bf_enabled; 295 bool bf_alloced; 296 struct netdev_queue *tx_queue; 297 int hwtstamp_tx_type; 298 } ____cacheline_aligned_in_smp; 299 300 struct mlx4_en_rx_desc { 301 /* actual number of entries depends on rx ring stride */ 302 struct mlx4_wqe_data_seg data[0]; 303 }; 304 305 struct mlx4_en_rx_ring { 306 struct mlx4_hwq_resources wqres; 307 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS]; 308 u32 size ; /* number of Rx descs*/ 309 u32 actual_size; 310 u32 size_mask; 311 u16 stride; 312 u16 log_stride; 313 u16 cqn; /* index of port CQ associated with this ring */ 314 u32 prod; 315 u32 cons; 316 u32 buf_size; 317 u8 fcs_del; 318 void *buf; 319 void *rx_info; 320 unsigned long bytes; 321 unsigned long packets; 322 #ifdef CONFIG_NET_RX_BUSY_POLL 323 unsigned long yields; 324 unsigned long misses; 325 unsigned long cleaned; 326 #endif 327 unsigned long csum_ok; 328 unsigned long csum_none; 329 unsigned long csum_complete; 330 int hwtstamp_rx_filter; 331 cpumask_var_t affinity_mask; 332 }; 333 334 struct mlx4_en_cq { 335 struct mlx4_cq mcq; 336 struct mlx4_hwq_resources wqres; 337 int ring; 338 struct net_device *dev; 339 struct napi_struct napi; 340 int size; 341 int buf_size; 342 unsigned vector; 343 enum cq_type is_tx; 344 u16 moder_time; 345 u16 moder_cnt; 346 struct mlx4_cqe *buf; 347 #define MLX4_EN_OPCODE_ERROR 0x1e 348 349 #ifdef CONFIG_NET_RX_BUSY_POLL 350 unsigned int state; 351 #define MLX4_EN_CQ_STATE_IDLE 0 352 #define MLX4_EN_CQ_STATE_NAPI 1 /* NAPI owns this CQ */ 353 #define MLX4_EN_CQ_STATE_POLL 2 /* poll owns this CQ */ 354 #define MLX4_CQ_LOCKED (MLX4_EN_CQ_STATE_NAPI | MLX4_EN_CQ_STATE_POLL) 355 #define MLX4_EN_CQ_STATE_NAPI_YIELD 4 /* NAPI yielded this CQ */ 356 #define MLX4_EN_CQ_STATE_POLL_YIELD 8 /* poll yielded this CQ */ 357 #define CQ_YIELD (MLX4_EN_CQ_STATE_NAPI_YIELD | MLX4_EN_CQ_STATE_POLL_YIELD) 358 #define CQ_USER_PEND (MLX4_EN_CQ_STATE_POLL | MLX4_EN_CQ_STATE_POLL_YIELD) 359 spinlock_t poll_lock; /* protects from LLS/napi conflicts */ 360 #endif /* CONFIG_NET_RX_BUSY_POLL */ 361 struct irq_desc *irq_desc; 362 }; 363 364 struct mlx4_en_port_profile { 365 u32 flags; 366 u32 tx_ring_num; 367 u32 rx_ring_num; 368 u32 tx_ring_size; 369 u32 rx_ring_size; 370 u8 rx_pause; 371 u8 rx_ppp; 372 u8 tx_pause; 373 u8 tx_ppp; 374 int rss_rings; 375 int inline_thold; 376 }; 377 378 struct mlx4_en_profile { 379 int udp_rss; 380 u8 rss_mask; 381 u32 active_ports; 382 u32 small_pkt_int; 383 u8 no_reset; 384 u8 num_tx_rings_p_up; 385 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1]; 386 }; 387 388 struct mlx4_en_dev { 389 struct mlx4_dev *dev; 390 struct pci_dev *pdev; 391 struct mutex state_lock; 392 struct net_device *pndev[MLX4_MAX_PORTS + 1]; 393 u32 port_cnt; 394 bool device_up; 395 struct mlx4_en_profile profile; 396 u32 LSO_support; 397 struct workqueue_struct *workqueue; 398 struct device *dma_device; 399 void __iomem *uar_map; 400 struct mlx4_uar priv_uar; 401 struct mlx4_mr mr; 402 u32 priv_pdn; 403 spinlock_t uar_lock; 404 u8 mac_removed[MLX4_MAX_PORTS + 1]; 405 rwlock_t clock_lock; 406 u32 nominal_c_mult; 407 struct cyclecounter cycles; 408 struct timecounter clock; 409 unsigned long last_overflow_check; 410 unsigned long overflow_period; 411 struct ptp_clock *ptp_clock; 412 struct ptp_clock_info ptp_clock_info; 413 }; 414 415 416 struct mlx4_en_rss_map { 417 int base_qpn; 418 struct mlx4_qp qps[MAX_RX_RINGS]; 419 enum mlx4_qp_state state[MAX_RX_RINGS]; 420 struct mlx4_qp indir_qp; 421 enum mlx4_qp_state indir_state; 422 }; 423 424 enum mlx4_en_port_flag { 425 MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */ 426 MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */ 427 }; 428 429 struct mlx4_en_port_state { 430 int link_state; 431 int link_speed; 432 int transceiver; 433 u32 flags; 434 }; 435 436 struct mlx4_en_pkt_stats { 437 unsigned long broadcast; 438 unsigned long rx_prio[8]; 439 unsigned long tx_prio[8]; 440 #define NUM_PKT_STATS 17 441 }; 442 443 struct mlx4_en_port_stats { 444 unsigned long tso_packets; 445 unsigned long xmit_more; 446 unsigned long queue_stopped; 447 unsigned long wake_queue; 448 unsigned long tx_timeout; 449 unsigned long rx_alloc_failed; 450 unsigned long rx_chksum_good; 451 unsigned long rx_chksum_none; 452 unsigned long rx_chksum_complete; 453 unsigned long tx_chksum_offload; 454 #define NUM_PORT_STATS 9 455 }; 456 457 struct mlx4_en_perf_stats { 458 u32 tx_poll; 459 u64 tx_pktsz_avg; 460 u32 inflight_avg; 461 u16 tx_coal_avg; 462 u16 rx_coal_avg; 463 u32 napi_quota; 464 #define NUM_PERF_COUNTERS 6 465 }; 466 467 enum mlx4_en_mclist_act { 468 MCLIST_NONE, 469 MCLIST_REM, 470 MCLIST_ADD, 471 }; 472 473 struct mlx4_en_mc_list { 474 struct list_head list; 475 enum mlx4_en_mclist_act action; 476 u8 addr[ETH_ALEN]; 477 u64 reg_id; 478 u64 tunnel_reg_id; 479 }; 480 481 struct mlx4_en_frag_info { 482 u16 frag_size; 483 u16 frag_prefix_size; 484 u16 frag_stride; 485 }; 486 487 #ifdef CONFIG_MLX4_EN_DCB 488 /* Minimal TC BW - setting to 0 will block traffic */ 489 #define MLX4_EN_BW_MIN 1 490 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */ 491 492 #define MLX4_EN_TC_ETS 7 493 494 #endif 495 496 struct ethtool_flow_id { 497 struct list_head list; 498 struct ethtool_rx_flow_spec flow_spec; 499 u64 id; 500 }; 501 502 enum { 503 MLX4_EN_FLAG_PROMISC = (1 << 0), 504 MLX4_EN_FLAG_MC_PROMISC = (1 << 1), 505 /* whether we need to enable hardware loopback by putting dmac 506 * in Tx WQE 507 */ 508 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2), 509 /* whether we need to drop packets that hardware loopback-ed */ 510 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3), 511 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4), 512 MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP = (1 << 5), 513 }; 514 515 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE) 516 #define MLX4_EN_MAC_HASH_IDX 5 517 518 struct mlx4_en_priv { 519 struct mlx4_en_dev *mdev; 520 struct mlx4_en_port_profile *prof; 521 struct net_device *dev; 522 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 523 struct net_device_stats stats; 524 struct net_device_stats ret_stats; 525 struct mlx4_en_port_state port_state; 526 spinlock_t stats_lock; 527 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES]; 528 /* To allow rules removal while port is going down */ 529 struct list_head ethtool_list; 530 531 unsigned long last_moder_packets[MAX_RX_RINGS]; 532 unsigned long last_moder_tx_packets; 533 unsigned long last_moder_bytes[MAX_RX_RINGS]; 534 unsigned long last_moder_jiffies; 535 int last_moder_time[MAX_RX_RINGS]; 536 u16 rx_usecs; 537 u16 rx_frames; 538 u16 tx_usecs; 539 u16 tx_frames; 540 u32 pkt_rate_low; 541 u16 rx_usecs_low; 542 u32 pkt_rate_high; 543 u16 rx_usecs_high; 544 u16 sample_interval; 545 u16 adaptive_rx_coal; 546 u32 msg_enable; 547 u32 loopback_ok; 548 u32 validate_loopback; 549 550 struct mlx4_hwq_resources res; 551 int link_state; 552 int last_link_state; 553 bool port_up; 554 int port; 555 int registered; 556 int allocated; 557 int stride; 558 unsigned char current_mac[ETH_ALEN + 2]; 559 int mac_index; 560 unsigned max_mtu; 561 int base_qpn; 562 int cqe_factor; 563 int cqe_size; 564 565 struct mlx4_en_rss_map rss_map; 566 __be32 ctrl_flags; 567 u32 flags; 568 u8 num_tx_rings_p_up; 569 u32 tx_work_limit; 570 u32 tx_ring_num; 571 u32 rx_ring_num; 572 u32 rx_skb_size; 573 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS]; 574 u16 num_frags; 575 u16 log_rx_info; 576 577 struct mlx4_en_tx_ring **tx_ring; 578 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS]; 579 struct mlx4_en_cq **tx_cq; 580 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS]; 581 struct mlx4_qp drop_qp; 582 struct work_struct rx_mode_task; 583 struct work_struct watchdog_task; 584 struct work_struct linkstate_task; 585 struct delayed_work stats_task; 586 struct delayed_work service_task; 587 #ifdef CONFIG_MLX4_EN_VXLAN 588 struct work_struct vxlan_add_task; 589 struct work_struct vxlan_del_task; 590 #endif 591 struct mlx4_en_perf_stats pstats; 592 struct mlx4_en_pkt_stats pkstats; 593 struct mlx4_en_port_stats port_stats; 594 u64 stats_bitmap; 595 struct list_head mc_list; 596 struct list_head curr_list; 597 u64 broadcast_id; 598 struct mlx4_en_stat_out_mbox hw_stats; 599 int vids[128]; 600 bool wol; 601 struct device *ddev; 602 int base_tx_qpn; 603 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE]; 604 struct hwtstamp_config hwtstamp_config; 605 606 #ifdef CONFIG_MLX4_EN_DCB 607 struct ieee_ets ets; 608 u16 maxrate[IEEE_8021QAZ_MAX_TCS]; 609 #endif 610 #ifdef CONFIG_RFS_ACCEL 611 spinlock_t filters_lock; 612 int last_filter_id; 613 struct list_head filters; 614 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT]; 615 #endif 616 u64 tunnel_reg_id; 617 __be16 vxlan_port; 618 619 u32 pflags; 620 u8 rss_key[MLX4_EN_RSS_KEY_SIZE]; 621 u8 rss_hash_fn; 622 }; 623 624 enum mlx4_en_wol { 625 MLX4_EN_WOL_MAGIC = (1ULL << 61), 626 MLX4_EN_WOL_ENABLED = (1ULL << 62), 627 }; 628 629 struct mlx4_mac_entry { 630 struct hlist_node hlist; 631 unsigned char mac[ETH_ALEN + 2]; 632 u64 reg_id; 633 struct rcu_head rcu; 634 }; 635 636 static inline struct mlx4_cqe *mlx4_en_get_cqe(void *buf, int idx, int cqe_sz) 637 { 638 return buf + idx * cqe_sz; 639 } 640 641 #ifdef CONFIG_NET_RX_BUSY_POLL 642 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq) 643 { 644 spin_lock_init(&cq->poll_lock); 645 cq->state = MLX4_EN_CQ_STATE_IDLE; 646 } 647 648 /* called from the device poll rutine to get ownership of a cq */ 649 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq) 650 { 651 int rc = true; 652 spin_lock(&cq->poll_lock); 653 if (cq->state & MLX4_CQ_LOCKED) { 654 WARN_ON(cq->state & MLX4_EN_CQ_STATE_NAPI); 655 cq->state |= MLX4_EN_CQ_STATE_NAPI_YIELD; 656 rc = false; 657 } else 658 /* we don't care if someone yielded */ 659 cq->state = MLX4_EN_CQ_STATE_NAPI; 660 spin_unlock(&cq->poll_lock); 661 return rc; 662 } 663 664 /* returns true is someone tried to get the cq while napi had it */ 665 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq) 666 { 667 int rc = false; 668 spin_lock(&cq->poll_lock); 669 WARN_ON(cq->state & (MLX4_EN_CQ_STATE_POLL | 670 MLX4_EN_CQ_STATE_NAPI_YIELD)); 671 672 if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD) 673 rc = true; 674 cq->state = MLX4_EN_CQ_STATE_IDLE; 675 spin_unlock(&cq->poll_lock); 676 return rc; 677 } 678 679 /* called from mlx4_en_low_latency_poll() */ 680 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq) 681 { 682 int rc = true; 683 spin_lock_bh(&cq->poll_lock); 684 if ((cq->state & MLX4_CQ_LOCKED)) { 685 struct net_device *dev = cq->dev; 686 struct mlx4_en_priv *priv = netdev_priv(dev); 687 struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring]; 688 689 cq->state |= MLX4_EN_CQ_STATE_POLL_YIELD; 690 rc = false; 691 rx_ring->yields++; 692 } else 693 /* preserve yield marks */ 694 cq->state |= MLX4_EN_CQ_STATE_POLL; 695 spin_unlock_bh(&cq->poll_lock); 696 return rc; 697 } 698 699 /* returns true if someone tried to get the cq while it was locked */ 700 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq) 701 { 702 int rc = false; 703 spin_lock_bh(&cq->poll_lock); 704 WARN_ON(cq->state & (MLX4_EN_CQ_STATE_NAPI)); 705 706 if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD) 707 rc = true; 708 cq->state = MLX4_EN_CQ_STATE_IDLE; 709 spin_unlock_bh(&cq->poll_lock); 710 return rc; 711 } 712 713 /* true if a socket is polling, even if it did not get the lock */ 714 static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq) 715 { 716 WARN_ON(!(cq->state & MLX4_CQ_LOCKED)); 717 return cq->state & CQ_USER_PEND; 718 } 719 #else 720 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq) 721 { 722 } 723 724 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq) 725 { 726 return true; 727 } 728 729 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq) 730 { 731 return false; 732 } 733 734 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq) 735 { 736 return false; 737 } 738 739 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq) 740 { 741 return false; 742 } 743 744 static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq) 745 { 746 return false; 747 } 748 #endif /* CONFIG_NET_RX_BUSY_POLL */ 749 750 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63) 751 752 void mlx4_en_update_loopback_state(struct net_device *dev, 753 netdev_features_t features); 754 755 void mlx4_en_destroy_netdev(struct net_device *dev); 756 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, 757 struct mlx4_en_port_profile *prof); 758 759 int mlx4_en_start_port(struct net_device *dev); 760 void mlx4_en_stop_port(struct net_device *dev, int detach); 761 762 void mlx4_en_free_resources(struct mlx4_en_priv *priv); 763 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv); 764 765 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq, 766 int entries, int ring, enum cq_type mode, int node); 767 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq); 768 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq, 769 int cq_idx); 770 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 771 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 772 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 773 774 void mlx4_en_tx_irq(struct mlx4_cq *mcq); 775 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, 776 void *accel_priv, select_queue_fallback_t fallback); 777 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev); 778 779 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 780 struct mlx4_en_tx_ring **pring, 781 u32 size, u16 stride, 782 int node, int queue_index); 783 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 784 struct mlx4_en_tx_ring **pring); 785 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 786 struct mlx4_en_tx_ring *ring, 787 int cq, int user_prio); 788 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 789 struct mlx4_en_tx_ring *ring); 790 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev); 791 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 792 struct mlx4_en_rx_ring **pring, 793 u32 size, u16 stride, int node); 794 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 795 struct mlx4_en_rx_ring **pring, 796 u32 size, u16 stride); 797 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv); 798 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, 799 struct mlx4_en_rx_ring *ring); 800 int mlx4_en_process_rx_cq(struct net_device *dev, 801 struct mlx4_en_cq *cq, 802 int budget); 803 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget); 804 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget); 805 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, 806 int is_tx, int rss, int qpn, int cqn, int user_prio, 807 struct mlx4_qp_context *context); 808 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event); 809 int mlx4_en_map_buffer(struct mlx4_buf *buf); 810 void mlx4_en_unmap_buffer(struct mlx4_buf *buf); 811 812 void mlx4_en_calc_rx_buf(struct net_device *dev); 813 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv); 814 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv); 815 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv); 816 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv); 817 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring); 818 void mlx4_en_rx_irq(struct mlx4_cq *mcq); 819 820 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 821 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv); 822 823 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset); 824 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port); 825 826 #ifdef CONFIG_MLX4_EN_DCB 827 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops; 828 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops; 829 #endif 830 831 int mlx4_en_setup_tc(struct net_device *dev, u8 up); 832 833 #ifdef CONFIG_RFS_ACCEL 834 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv); 835 #endif 836 837 #define MLX4_EN_NUM_SELF_TEST 5 838 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf); 839 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev); 840 841 #define DEV_FEATURE_CHANGED(dev, new_features, feature) \ 842 ((dev->features & feature) ^ (new_features & feature)) 843 844 int mlx4_en_reset_config(struct net_device *dev, 845 struct hwtstamp_config ts_config, 846 netdev_features_t new_features); 847 848 /* 849 * Functions for time stamping 850 */ 851 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe); 852 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev, 853 struct skb_shared_hwtstamps *hwts, 854 u64 timestamp); 855 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev); 856 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev); 857 858 /* Globals 859 */ 860 extern const struct ethtool_ops mlx4_en_ethtool_ops; 861 862 863 864 /* 865 * printk / logging functions 866 */ 867 868 __printf(3, 4) 869 void en_print(const char *level, const struct mlx4_en_priv *priv, 870 const char *format, ...); 871 872 #define en_dbg(mlevel, priv, format, ...) \ 873 do { \ 874 if (NETIF_MSG_##mlevel & (priv)->msg_enable) \ 875 en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__); \ 876 } while (0) 877 #define en_warn(priv, format, ...) \ 878 en_print(KERN_WARNING, priv, format, ##__VA_ARGS__) 879 #define en_err(priv, format, ...) \ 880 en_print(KERN_ERR, priv, format, ##__VA_ARGS__) 881 #define en_info(priv, format, ...) \ 882 en_print(KERN_INFO, priv, format, ##__VA_ARGS__) 883 884 #define mlx4_err(mdev, format, ...) \ 885 pr_err(DRV_NAME " %s: " format, \ 886 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 887 #define mlx4_info(mdev, format, ...) \ 888 pr_info(DRV_NAME " %s: " format, \ 889 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 890 #define mlx4_warn(mdev, format, ...) \ 891 pr_warn(DRV_NAME " %s: " format, \ 892 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 893 894 #endif 895