1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #ifndef _MLX4_EN_H_ 35 #define _MLX4_EN_H_ 36 37 #include <linux/bitops.h> 38 #include <linux/compiler.h> 39 #include <linux/list.h> 40 #include <linux/mutex.h> 41 #include <linux/netdevice.h> 42 #include <linux/if_vlan.h> 43 #include <linux/net_tstamp.h> 44 #ifdef CONFIG_MLX4_EN_DCB 45 #include <linux/dcbnl.h> 46 #endif 47 #include <linux/cpu_rmap.h> 48 #include <linux/ptp_clock_kernel.h> 49 50 #include <linux/mlx4/device.h> 51 #include <linux/mlx4/qp.h> 52 #include <linux/mlx4/cq.h> 53 #include <linux/mlx4/srq.h> 54 #include <linux/mlx4/doorbell.h> 55 #include <linux/mlx4/cmd.h> 56 57 #include "en_port.h" 58 #include "mlx4_stats.h" 59 60 #define DRV_NAME "mlx4_en" 61 #define DRV_VERSION "2.2-1" 62 #define DRV_RELDATE "Feb 2014" 63 64 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN) 65 66 /* 67 * Device constants 68 */ 69 70 71 #define MLX4_EN_PAGE_SHIFT 12 72 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT) 73 #define DEF_RX_RINGS 16 74 #define MAX_RX_RINGS 128 75 #define MIN_RX_RINGS 4 76 #define TXBB_SIZE 64 77 #define HEADROOM (2048 / TXBB_SIZE + 1) 78 #define STAMP_STRIDE 64 79 #define STAMP_DWORDS (STAMP_STRIDE / 4) 80 #define STAMP_SHIFT 31 81 #define STAMP_VAL 0x7fffffff 82 #define STATS_DELAY (HZ / 4) 83 #define SERVICE_TASK_DELAY (HZ / 4) 84 #define MAX_NUM_OF_FS_RULES 256 85 86 #define MLX4_EN_FILTER_HASH_SHIFT 4 87 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60 88 89 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */ 90 #define MAX_DESC_SIZE 512 91 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE) 92 93 /* 94 * OS related constants and tunables 95 */ 96 97 #define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1 98 #define MLX4_EN_PRIV_FLAGS_PHV 2 99 100 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ) 101 102 /* Use the maximum between 16384 and a single page */ 103 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384) 104 105 #define MLX4_EN_ALLOC_PREFER_ORDER PAGE_ALLOC_COSTLY_ORDER 106 107 /* Receive fragment sizes; we use at most 3 fragments (for 9600 byte MTU 108 * and 4K allocations) */ 109 enum { 110 FRAG_SZ0 = 1536 - NET_IP_ALIGN, 111 FRAG_SZ1 = 4096, 112 FRAG_SZ2 = 4096, 113 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE 114 }; 115 #define MLX4_EN_MAX_RX_FRAGS 4 116 117 /* Maximum ring sizes */ 118 #define MLX4_EN_MAX_TX_SIZE 8192 119 #define MLX4_EN_MAX_RX_SIZE 8192 120 121 /* Minimum ring size for our page-allocation scheme to work */ 122 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES) 123 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE) 124 125 #define MLX4_EN_SMALL_PKT_SIZE 64 126 #define MLX4_EN_MIN_TX_RING_P_UP 1 127 #define MLX4_EN_MAX_TX_RING_P_UP 32 128 #define MLX4_EN_NUM_UP 8 129 #define MLX4_EN_DEF_TX_RING_SIZE 512 130 #define MLX4_EN_DEF_RX_RING_SIZE 1024 131 #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \ 132 MLX4_EN_NUM_UP) 133 134 #define MLX4_EN_DEFAULT_TX_WORK 256 135 #define MLX4_EN_DOORBELL_BUDGET 8 136 137 /* Target number of packets to coalesce with interrupt moderation */ 138 #define MLX4_EN_RX_COAL_TARGET 44 139 #define MLX4_EN_RX_COAL_TIME 0x10 140 141 #define MLX4_EN_TX_COAL_PKTS 16 142 #define MLX4_EN_TX_COAL_TIME 0x10 143 144 #define MLX4_EN_RX_RATE_LOW 400000 145 #define MLX4_EN_RX_COAL_TIME_LOW 0 146 #define MLX4_EN_RX_RATE_HIGH 450000 147 #define MLX4_EN_RX_COAL_TIME_HIGH 128 148 #define MLX4_EN_RX_SIZE_THRESH 1024 149 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH) 150 #define MLX4_EN_SAMPLE_INTERVAL 0 151 #define MLX4_EN_AVG_PKT_SMALL 256 152 153 #define MLX4_EN_AUTO_CONF 0xffff 154 155 #define MLX4_EN_DEF_RX_PAUSE 1 156 #define MLX4_EN_DEF_TX_PAUSE 1 157 158 /* Interval between successive polls in the Tx routine when polling is used 159 instead of interrupts (in per-core Tx rings) - should be power of 2 */ 160 #define MLX4_EN_TX_POLL_MODER 16 161 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4) 162 163 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN) 164 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN) 165 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN) 166 167 #define MLX4_EN_MIN_MTU 46 168 /* VLAN_HLEN is added twice,to support skb vlan tagged with multiple 169 * headers. (For example: ETH_P_8021Q and ETH_P_8021AD). 170 */ 171 #define MLX4_EN_EFF_MTU(mtu) ((mtu) + ETH_HLEN + (2 * VLAN_HLEN)) 172 #define ETH_BCAST 0xffffffffffffULL 173 174 #define MLX4_EN_LOOPBACK_RETRIES 5 175 #define MLX4_EN_LOOPBACK_TIMEOUT 100 176 177 #ifdef MLX4_EN_PERF_STAT 178 /* Number of samples to 'average' */ 179 #define AVG_SIZE 128 180 #define AVG_FACTOR 1024 181 182 #define INC_PERF_COUNTER(cnt) (++(cnt)) 183 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add)) 184 #define AVG_PERF_COUNTER(cnt, sample) \ 185 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE) 186 #define GET_PERF_COUNTER(cnt) (cnt) 187 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR) 188 189 #else 190 191 #define INC_PERF_COUNTER(cnt) do {} while (0) 192 #define ADD_PERF_COUNTER(cnt, add) do {} while (0) 193 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0) 194 #define GET_PERF_COUNTER(cnt) (0) 195 #define GET_AVG_PERF_COUNTER(cnt) (0) 196 #endif /* MLX4_EN_PERF_STAT */ 197 198 /* Constants for TX flow */ 199 enum { 200 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */ 201 MAX_BF = 256, 202 MIN_PKT_LEN = 17, 203 }; 204 205 /* 206 * Configurables 207 */ 208 209 enum cq_type { 210 /* keep tx types first */ 211 TX, 212 TX_XDP, 213 #define MLX4_EN_NUM_TX_TYPES (TX_XDP + 1) 214 RX, 215 }; 216 217 218 /* 219 * Useful macros 220 */ 221 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x)) 222 #define XNOR(x, y) (!(x) == !(y)) 223 224 225 struct mlx4_en_tx_info { 226 union { 227 struct sk_buff *skb; 228 struct page *page; 229 }; 230 dma_addr_t map0_dma; 231 u32 map0_byte_count; 232 u32 nr_txbb; 233 u32 nr_bytes; 234 u8 linear; 235 u8 data_offset; 236 u8 inl; 237 u8 ts_requested; 238 u8 nr_maps; 239 } ____cacheline_aligned_in_smp; 240 241 242 #define MLX4_EN_BIT_DESC_OWN 0x80000000 243 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg) 244 #define MLX4_EN_MEMTYPE_PAD 0x100 245 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg) 246 247 248 struct mlx4_en_tx_desc { 249 struct mlx4_wqe_ctrl_seg ctrl; 250 union { 251 struct mlx4_wqe_data_seg data; /* at least one data segment */ 252 struct mlx4_wqe_lso_seg lso; 253 struct mlx4_wqe_inline_seg inl; 254 }; 255 }; 256 257 #define MLX4_EN_USE_SRQ 0x01000000 258 259 #define MLX4_EN_CX3_LOW_ID 0x1000 260 #define MLX4_EN_CX3_HIGH_ID 0x1005 261 262 struct mlx4_en_rx_alloc { 263 struct page *page; 264 dma_addr_t dma; 265 u32 page_offset; 266 u32 page_size; 267 }; 268 269 #define MLX4_EN_CACHE_SIZE (2 * NAPI_POLL_WEIGHT) 270 struct mlx4_en_page_cache { 271 u32 index; 272 struct mlx4_en_rx_alloc buf[MLX4_EN_CACHE_SIZE]; 273 }; 274 275 struct mlx4_en_priv; 276 277 struct mlx4_en_tx_ring { 278 /* cache line used and dirtied in tx completion 279 * (mlx4_en_free_tx_buf()) 280 */ 281 u32 last_nr_txbb; 282 u32 cons; 283 unsigned long wake_queue; 284 struct netdev_queue *tx_queue; 285 u32 (*free_tx_desc)(struct mlx4_en_priv *priv, 286 struct mlx4_en_tx_ring *ring, 287 int index, u8 owner, 288 u64 timestamp, int napi_mode); 289 struct mlx4_en_rx_ring *recycle_ring; 290 291 /* cache line used and dirtied in mlx4_en_xmit() */ 292 u32 prod ____cacheline_aligned_in_smp; 293 unsigned int tx_dropped; 294 unsigned long bytes; 295 unsigned long packets; 296 unsigned long tx_csum; 297 unsigned long tso_packets; 298 unsigned long xmit_more; 299 struct mlx4_bf bf; 300 301 /* Following part should be mostly read */ 302 __be32 doorbell_qpn; 303 __be32 mr_key; 304 u32 size; /* number of TXBBs */ 305 u32 size_mask; 306 u32 full_size; 307 u32 buf_size; 308 void *buf; 309 struct mlx4_en_tx_info *tx_info; 310 int qpn; 311 u8 queue_index; 312 bool bf_enabled; 313 bool bf_alloced; 314 u8 hwtstamp_tx_type; 315 u8 *bounce_buf; 316 317 /* Not used in fast path 318 * Only queue_stopped might be used if BQL is not properly working. 319 */ 320 unsigned long queue_stopped; 321 struct mlx4_hwq_resources sp_wqres; 322 struct mlx4_qp sp_qp; 323 struct mlx4_qp_context sp_context; 324 cpumask_t sp_affinity_mask; 325 enum mlx4_qp_state sp_qp_state; 326 u16 sp_stride; 327 u16 sp_cqn; /* index of port CQ associated with this ring */ 328 } ____cacheline_aligned_in_smp; 329 330 struct mlx4_en_rx_desc { 331 /* actual number of entries depends on rx ring stride */ 332 struct mlx4_wqe_data_seg data[0]; 333 }; 334 335 struct mlx4_en_rx_ring { 336 struct mlx4_hwq_resources wqres; 337 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS]; 338 u32 size ; /* number of Rx descs*/ 339 u32 actual_size; 340 u32 size_mask; 341 u16 stride; 342 u16 log_stride; 343 u16 cqn; /* index of port CQ associated with this ring */ 344 u32 prod; 345 u32 cons; 346 u32 buf_size; 347 u8 fcs_del; 348 void *buf; 349 void *rx_info; 350 struct bpf_prog __rcu *xdp_prog; 351 struct mlx4_en_page_cache page_cache; 352 unsigned long bytes; 353 unsigned long packets; 354 unsigned long csum_ok; 355 unsigned long csum_none; 356 unsigned long csum_complete; 357 unsigned long xdp_drop; 358 unsigned long xdp_tx; 359 unsigned long xdp_tx_full; 360 unsigned long dropped; 361 int hwtstamp_rx_filter; 362 cpumask_var_t affinity_mask; 363 }; 364 365 struct mlx4_en_cq { 366 struct mlx4_cq mcq; 367 struct mlx4_hwq_resources wqres; 368 int ring; 369 struct net_device *dev; 370 struct napi_struct napi; 371 int size; 372 int buf_size; 373 int vector; 374 enum cq_type type; 375 u16 moder_time; 376 u16 moder_cnt; 377 struct mlx4_cqe *buf; 378 #define MLX4_EN_OPCODE_ERROR 0x1e 379 380 struct irq_desc *irq_desc; 381 }; 382 383 struct mlx4_en_port_profile { 384 u32 flags; 385 u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES]; 386 u32 rx_ring_num; 387 u32 tx_ring_size; 388 u32 rx_ring_size; 389 u8 num_tx_rings_p_up; 390 u8 rx_pause; 391 u8 rx_ppp; 392 u8 tx_pause; 393 u8 tx_ppp; 394 int rss_rings; 395 int inline_thold; 396 struct hwtstamp_config hwtstamp_config; 397 }; 398 399 struct mlx4_en_profile { 400 int udp_rss; 401 u8 rss_mask; 402 u32 active_ports; 403 u32 small_pkt_int; 404 u8 no_reset; 405 u8 num_tx_rings_p_up; 406 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1]; 407 }; 408 409 struct mlx4_en_dev { 410 struct mlx4_dev *dev; 411 struct pci_dev *pdev; 412 struct mutex state_lock; 413 struct net_device *pndev[MLX4_MAX_PORTS + 1]; 414 struct net_device *upper[MLX4_MAX_PORTS + 1]; 415 u32 port_cnt; 416 bool device_up; 417 struct mlx4_en_profile profile; 418 u32 LSO_support; 419 struct workqueue_struct *workqueue; 420 struct device *dma_device; 421 void __iomem *uar_map; 422 struct mlx4_uar priv_uar; 423 struct mlx4_mr mr; 424 u32 priv_pdn; 425 spinlock_t uar_lock; 426 u8 mac_removed[MLX4_MAX_PORTS + 1]; 427 rwlock_t clock_lock; 428 u32 nominal_c_mult; 429 struct cyclecounter cycles; 430 struct timecounter clock; 431 unsigned long last_overflow_check; 432 unsigned long overflow_period; 433 struct ptp_clock *ptp_clock; 434 struct ptp_clock_info ptp_clock_info; 435 struct notifier_block nb; 436 }; 437 438 439 struct mlx4_en_rss_map { 440 int base_qpn; 441 struct mlx4_qp qps[MAX_RX_RINGS]; 442 enum mlx4_qp_state state[MAX_RX_RINGS]; 443 struct mlx4_qp indir_qp; 444 enum mlx4_qp_state indir_state; 445 }; 446 447 enum mlx4_en_port_flag { 448 MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */ 449 MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */ 450 }; 451 452 struct mlx4_en_port_state { 453 int link_state; 454 int link_speed; 455 int transceiver; 456 u32 flags; 457 }; 458 459 enum mlx4_en_mclist_act { 460 MCLIST_NONE, 461 MCLIST_REM, 462 MCLIST_ADD, 463 }; 464 465 struct mlx4_en_mc_list { 466 struct list_head list; 467 enum mlx4_en_mclist_act action; 468 u8 addr[ETH_ALEN]; 469 u64 reg_id; 470 u64 tunnel_reg_id; 471 }; 472 473 struct mlx4_en_frag_info { 474 u16 frag_size; 475 u16 frag_prefix_size; 476 u32 frag_stride; 477 enum dma_data_direction dma_dir; 478 int order; 479 }; 480 481 #ifdef CONFIG_MLX4_EN_DCB 482 /* Minimal TC BW - setting to 0 will block traffic */ 483 #define MLX4_EN_BW_MIN 1 484 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */ 485 486 #define MLX4_EN_TC_ETS 7 487 488 enum dcb_pfc_type { 489 pfc_disabled = 0, 490 pfc_enabled_full, 491 pfc_enabled_tx, 492 pfc_enabled_rx 493 }; 494 495 struct mlx4_en_cee_config { 496 bool pfc_state; 497 enum dcb_pfc_type dcb_pfc[MLX4_EN_NUM_UP]; 498 }; 499 #endif 500 501 struct ethtool_flow_id { 502 struct list_head list; 503 struct ethtool_rx_flow_spec flow_spec; 504 u64 id; 505 }; 506 507 enum { 508 MLX4_EN_FLAG_PROMISC = (1 << 0), 509 MLX4_EN_FLAG_MC_PROMISC = (1 << 1), 510 /* whether we need to enable hardware loopback by putting dmac 511 * in Tx WQE 512 */ 513 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2), 514 /* whether we need to drop packets that hardware loopback-ed */ 515 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3), 516 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4), 517 MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP = (1 << 5), 518 #ifdef CONFIG_MLX4_EN_DCB 519 MLX4_EN_FLAG_DCB_ENABLED = (1 << 6), 520 #endif 521 }; 522 523 #define PORT_BEACON_MAX_LIMIT (65535) 524 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE) 525 #define MLX4_EN_MAC_HASH_IDX 5 526 527 struct mlx4_en_stats_bitmap { 528 DECLARE_BITMAP(bitmap, NUM_ALL_STATS); 529 struct mutex mutex; /* for mutual access to stats bitmap */ 530 }; 531 532 struct mlx4_en_priv { 533 struct mlx4_en_dev *mdev; 534 struct mlx4_en_port_profile *prof; 535 struct net_device *dev; 536 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 537 struct mlx4_en_port_state port_state; 538 spinlock_t stats_lock; 539 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES]; 540 /* To allow rules removal while port is going down */ 541 struct list_head ethtool_list; 542 543 unsigned long last_moder_packets[MAX_RX_RINGS]; 544 unsigned long last_moder_tx_packets; 545 unsigned long last_moder_bytes[MAX_RX_RINGS]; 546 unsigned long last_moder_jiffies; 547 int last_moder_time[MAX_RX_RINGS]; 548 u16 rx_usecs; 549 u16 rx_frames; 550 u16 tx_usecs; 551 u16 tx_frames; 552 u32 pkt_rate_low; 553 u16 rx_usecs_low; 554 u32 pkt_rate_high; 555 u16 rx_usecs_high; 556 u16 sample_interval; 557 u16 adaptive_rx_coal; 558 u32 msg_enable; 559 u32 loopback_ok; 560 u32 validate_loopback; 561 562 struct mlx4_hwq_resources res; 563 int link_state; 564 int last_link_state; 565 bool port_up; 566 int port; 567 int registered; 568 int allocated; 569 int stride; 570 unsigned char current_mac[ETH_ALEN + 2]; 571 int mac_index; 572 unsigned max_mtu; 573 int base_qpn; 574 int cqe_factor; 575 int cqe_size; 576 577 struct mlx4_en_rss_map rss_map; 578 __be32 ctrl_flags; 579 u32 flags; 580 u8 num_tx_rings_p_up; 581 u32 tx_work_limit; 582 u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES]; 583 u32 rx_ring_num; 584 u32 rx_skb_size; 585 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS]; 586 u16 num_frags; 587 u16 log_rx_info; 588 589 struct mlx4_en_tx_ring **tx_ring[MLX4_EN_NUM_TX_TYPES]; 590 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS]; 591 struct mlx4_en_cq **tx_cq[MLX4_EN_NUM_TX_TYPES]; 592 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS]; 593 struct mlx4_qp drop_qp; 594 struct work_struct rx_mode_task; 595 struct work_struct watchdog_task; 596 struct work_struct linkstate_task; 597 struct delayed_work stats_task; 598 struct delayed_work service_task; 599 struct work_struct vxlan_add_task; 600 struct work_struct vxlan_del_task; 601 struct mlx4_en_perf_stats pstats; 602 struct mlx4_en_pkt_stats pkstats; 603 struct mlx4_en_counter_stats pf_stats; 604 struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES]; 605 struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES]; 606 struct mlx4_en_flow_stats_rx rx_flowstats; 607 struct mlx4_en_flow_stats_tx tx_flowstats; 608 struct mlx4_en_port_stats port_stats; 609 struct mlx4_en_xdp_stats xdp_stats; 610 struct mlx4_en_stats_bitmap stats_bitmap; 611 struct list_head mc_list; 612 struct list_head curr_list; 613 u64 broadcast_id; 614 struct mlx4_en_stat_out_mbox hw_stats; 615 int vids[128]; 616 bool wol; 617 struct device *ddev; 618 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE]; 619 struct hwtstamp_config hwtstamp_config; 620 u32 counter_index; 621 622 #ifdef CONFIG_MLX4_EN_DCB 623 #define MLX4_EN_DCB_ENABLED 0x3 624 struct ieee_ets ets; 625 u16 maxrate[IEEE_8021QAZ_MAX_TCS]; 626 enum dcbnl_cndd_states cndd_state[IEEE_8021QAZ_MAX_TCS]; 627 struct mlx4_en_cee_config cee_config; 628 u8 dcbx_cap; 629 #endif 630 #ifdef CONFIG_RFS_ACCEL 631 spinlock_t filters_lock; 632 int last_filter_id; 633 struct list_head filters; 634 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT]; 635 #endif 636 u64 tunnel_reg_id; 637 __be16 vxlan_port; 638 639 u32 pflags; 640 u8 rss_key[MLX4_EN_RSS_KEY_SIZE]; 641 u8 rss_hash_fn; 642 }; 643 644 enum mlx4_en_wol { 645 MLX4_EN_WOL_MAGIC = (1ULL << 61), 646 MLX4_EN_WOL_ENABLED = (1ULL << 62), 647 }; 648 649 struct mlx4_mac_entry { 650 struct hlist_node hlist; 651 unsigned char mac[ETH_ALEN + 2]; 652 u64 reg_id; 653 struct rcu_head rcu; 654 }; 655 656 static inline struct mlx4_cqe *mlx4_en_get_cqe(void *buf, int idx, int cqe_sz) 657 { 658 return buf + idx * cqe_sz; 659 } 660 661 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63) 662 663 void mlx4_en_init_ptys2ethtool_map(void); 664 void mlx4_en_update_loopback_state(struct net_device *dev, 665 netdev_features_t features); 666 667 void mlx4_en_destroy_netdev(struct net_device *dev); 668 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, 669 struct mlx4_en_port_profile *prof); 670 671 int mlx4_en_start_port(struct net_device *dev); 672 void mlx4_en_stop_port(struct net_device *dev, int detach); 673 674 void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev, 675 struct mlx4_en_stats_bitmap *stats_bitmap, 676 u8 rx_ppp, u8 rx_pause, 677 u8 tx_ppp, u8 tx_pause); 678 679 int mlx4_en_try_alloc_resources(struct mlx4_en_priv *priv, 680 struct mlx4_en_priv *tmp, 681 struct mlx4_en_port_profile *prof); 682 void mlx4_en_safe_replace_resources(struct mlx4_en_priv *priv, 683 struct mlx4_en_priv *tmp); 684 685 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq, 686 int entries, int ring, enum cq_type mode, int node); 687 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq); 688 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq, 689 int cq_idx); 690 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 691 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 692 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 693 694 void mlx4_en_tx_irq(struct mlx4_cq *mcq); 695 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, 696 void *accel_priv, select_queue_fallback_t fallback); 697 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev); 698 netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring, 699 struct mlx4_en_rx_alloc *frame, 700 struct net_device *dev, unsigned int length, 701 int tx_ind, int *doorbell_pending); 702 void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring); 703 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring, 704 struct mlx4_en_rx_alloc *frame); 705 706 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 707 struct mlx4_en_tx_ring **pring, 708 u32 size, u16 stride, 709 int node, int queue_index); 710 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 711 struct mlx4_en_tx_ring **pring); 712 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 713 struct mlx4_en_tx_ring *ring, 714 int cq, int user_prio); 715 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 716 struct mlx4_en_tx_ring *ring); 717 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev); 718 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv); 719 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 720 struct mlx4_en_rx_ring **pring, 721 u32 size, u16 stride, int node); 722 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 723 struct mlx4_en_rx_ring **pring, 724 u32 size, u16 stride); 725 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv); 726 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, 727 struct mlx4_en_rx_ring *ring); 728 int mlx4_en_process_rx_cq(struct net_device *dev, 729 struct mlx4_en_cq *cq, 730 int budget); 731 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget); 732 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget); 733 u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, 734 struct mlx4_en_tx_ring *ring, 735 int index, u8 owner, u64 timestamp, 736 int napi_mode); 737 u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv, 738 struct mlx4_en_tx_ring *ring, 739 int index, u8 owner, u64 timestamp, 740 int napi_mode); 741 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, 742 int is_tx, int rss, int qpn, int cqn, int user_prio, 743 struct mlx4_qp_context *context); 744 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event); 745 int mlx4_en_change_mcast_lb(struct mlx4_en_priv *priv, struct mlx4_qp *qp, 746 int loopback); 747 void mlx4_en_calc_rx_buf(struct net_device *dev); 748 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv); 749 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv); 750 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv); 751 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv); 752 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring); 753 void mlx4_en_rx_irq(struct mlx4_cq *mcq); 754 755 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 756 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv); 757 758 void mlx4_en_fold_software_stats(struct net_device *dev); 759 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset); 760 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port); 761 762 #ifdef CONFIG_MLX4_EN_DCB 763 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops; 764 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops; 765 #endif 766 767 int mlx4_en_setup_tc(struct net_device *dev, u8 up); 768 769 #ifdef CONFIG_RFS_ACCEL 770 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv); 771 #endif 772 773 #define MLX4_EN_NUM_SELF_TEST 5 774 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf); 775 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev); 776 777 #define DEV_FEATURE_CHANGED(dev, new_features, feature) \ 778 ((dev->features & feature) ^ (new_features & feature)) 779 780 int mlx4_en_reset_config(struct net_device *dev, 781 struct hwtstamp_config ts_config, 782 netdev_features_t new_features); 783 void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev, 784 struct mlx4_en_stats_bitmap *stats_bitmap, 785 u8 rx_ppp, u8 rx_pause, 786 u8 tx_ppp, u8 tx_pause); 787 int mlx4_en_netdev_event(struct notifier_block *this, 788 unsigned long event, void *ptr); 789 790 /* 791 * Functions for time stamping 792 */ 793 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe); 794 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev, 795 struct skb_shared_hwtstamps *hwts, 796 u64 timestamp); 797 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev); 798 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev); 799 800 /* Globals 801 */ 802 extern const struct ethtool_ops mlx4_en_ethtool_ops; 803 804 805 806 /* 807 * printk / logging functions 808 */ 809 810 __printf(3, 4) 811 void en_print(const char *level, const struct mlx4_en_priv *priv, 812 const char *format, ...); 813 814 #define en_dbg(mlevel, priv, format, ...) \ 815 do { \ 816 if (NETIF_MSG_##mlevel & (priv)->msg_enable) \ 817 en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__); \ 818 } while (0) 819 #define en_warn(priv, format, ...) \ 820 en_print(KERN_WARNING, priv, format, ##__VA_ARGS__) 821 #define en_err(priv, format, ...) \ 822 en_print(KERN_ERR, priv, format, ##__VA_ARGS__) 823 #define en_info(priv, format, ...) \ 824 en_print(KERN_INFO, priv, format, ##__VA_ARGS__) 825 826 #define mlx4_err(mdev, format, ...) \ 827 pr_err(DRV_NAME " %s: " format, \ 828 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 829 #define mlx4_info(mdev, format, ...) \ 830 pr_info(DRV_NAME " %s: " format, \ 831 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 832 #define mlx4_warn(mdev, format, ...) \ 833 pr_warn(DRV_NAME " %s: " format, \ 834 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 835 836 #endif 837