1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #ifndef _MLX4_EN_H_ 35 #define _MLX4_EN_H_ 36 37 #include <linux/bitops.h> 38 #include <linux/compiler.h> 39 #include <linux/list.h> 40 #include <linux/mutex.h> 41 #include <linux/netdevice.h> 42 #include <linux/if_vlan.h> 43 #include <linux/net_tstamp.h> 44 #ifdef CONFIG_MLX4_EN_DCB 45 #include <linux/dcbnl.h> 46 #endif 47 #include <linux/cpu_rmap.h> 48 #include <linux/ptp_clock_kernel.h> 49 50 #include <linux/mlx4/device.h> 51 #include <linux/mlx4/qp.h> 52 #include <linux/mlx4/cq.h> 53 #include <linux/mlx4/srq.h> 54 #include <linux/mlx4/doorbell.h> 55 #include <linux/mlx4/cmd.h> 56 57 #include "en_port.h" 58 #include "mlx4_stats.h" 59 60 #define DRV_NAME "mlx4_en" 61 #define DRV_VERSION "2.2-1" 62 #define DRV_RELDATE "Feb 2014" 63 64 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN) 65 66 /* 67 * Device constants 68 */ 69 70 71 #define MLX4_EN_PAGE_SHIFT 12 72 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT) 73 #define DEF_RX_RINGS 16 74 #define MAX_RX_RINGS 128 75 #define MIN_RX_RINGS 4 76 #define TXBB_SIZE 64 77 #define HEADROOM (2048 / TXBB_SIZE + 1) 78 #define STAMP_STRIDE 64 79 #define STAMP_DWORDS (STAMP_STRIDE / 4) 80 #define STAMP_SHIFT 31 81 #define STAMP_VAL 0x7fffffff 82 #define STATS_DELAY (HZ / 4) 83 #define SERVICE_TASK_DELAY (HZ / 4) 84 #define MAX_NUM_OF_FS_RULES 256 85 86 #define MLX4_EN_FILTER_HASH_SHIFT 4 87 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60 88 89 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */ 90 #define MAX_DESC_SIZE 512 91 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE) 92 93 /* 94 * OS related constants and tunables 95 */ 96 97 #define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1 98 #define MLX4_EN_PRIV_FLAGS_PHV 2 99 100 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ) 101 102 /* Use the maximum between 16384 and a single page */ 103 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384) 104 105 #define MLX4_EN_ALLOC_PREFER_ORDER PAGE_ALLOC_COSTLY_ORDER 106 107 /* Receive fragment sizes; we use at most 3 fragments (for 9600 byte MTU 108 * and 4K allocations) */ 109 enum { 110 FRAG_SZ0 = 1536 - NET_IP_ALIGN, 111 FRAG_SZ1 = 4096, 112 FRAG_SZ2 = 4096, 113 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE 114 }; 115 #define MLX4_EN_MAX_RX_FRAGS 4 116 117 /* Maximum ring sizes */ 118 #define MLX4_EN_MAX_TX_SIZE 8192 119 #define MLX4_EN_MAX_RX_SIZE 8192 120 121 /* Minimum ring size for our page-allocation scheme to work */ 122 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES) 123 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE) 124 125 #define MLX4_EN_SMALL_PKT_SIZE 64 126 #define MLX4_EN_MIN_TX_RING_P_UP 1 127 #define MLX4_EN_MAX_TX_RING_P_UP 32 128 #define MLX4_EN_NUM_UP 8 129 #define MLX4_EN_DEF_TX_RING_SIZE 512 130 #define MLX4_EN_DEF_RX_RING_SIZE 1024 131 #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \ 132 MLX4_EN_NUM_UP) 133 134 #define MLX4_EN_DEFAULT_TX_WORK 256 135 #define MLX4_EN_DOORBELL_BUDGET 8 136 137 /* Target number of packets to coalesce with interrupt moderation */ 138 #define MLX4_EN_RX_COAL_TARGET 44 139 #define MLX4_EN_RX_COAL_TIME 0x10 140 141 #define MLX4_EN_TX_COAL_PKTS 16 142 #define MLX4_EN_TX_COAL_TIME 0x10 143 144 #define MLX4_EN_RX_RATE_LOW 400000 145 #define MLX4_EN_RX_COAL_TIME_LOW 0 146 #define MLX4_EN_RX_RATE_HIGH 450000 147 #define MLX4_EN_RX_COAL_TIME_HIGH 128 148 #define MLX4_EN_RX_SIZE_THRESH 1024 149 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH) 150 #define MLX4_EN_SAMPLE_INTERVAL 0 151 #define MLX4_EN_AVG_PKT_SMALL 256 152 153 #define MLX4_EN_AUTO_CONF 0xffff 154 155 #define MLX4_EN_DEF_RX_PAUSE 1 156 #define MLX4_EN_DEF_TX_PAUSE 1 157 158 /* Interval between successive polls in the Tx routine when polling is used 159 instead of interrupts (in per-core Tx rings) - should be power of 2 */ 160 #define MLX4_EN_TX_POLL_MODER 16 161 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4) 162 163 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN) 164 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN) 165 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN) 166 167 #define MLX4_EN_MIN_MTU 46 168 /* VLAN_HLEN is added twice,to support skb vlan tagged with multiple 169 * headers. (For example: ETH_P_8021Q and ETH_P_8021AD). 170 */ 171 #define MLX4_EN_EFF_MTU(mtu) ((mtu) + ETH_HLEN + (2 * VLAN_HLEN)) 172 #define ETH_BCAST 0xffffffffffffULL 173 174 #define MLX4_EN_LOOPBACK_RETRIES 5 175 #define MLX4_EN_LOOPBACK_TIMEOUT 100 176 177 #ifdef MLX4_EN_PERF_STAT 178 /* Number of samples to 'average' */ 179 #define AVG_SIZE 128 180 #define AVG_FACTOR 1024 181 182 #define INC_PERF_COUNTER(cnt) (++(cnt)) 183 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add)) 184 #define AVG_PERF_COUNTER(cnt, sample) \ 185 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE) 186 #define GET_PERF_COUNTER(cnt) (cnt) 187 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR) 188 189 #else 190 191 #define INC_PERF_COUNTER(cnt) do {} while (0) 192 #define ADD_PERF_COUNTER(cnt, add) do {} while (0) 193 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0) 194 #define GET_PERF_COUNTER(cnt) (0) 195 #define GET_AVG_PERF_COUNTER(cnt) (0) 196 #endif /* MLX4_EN_PERF_STAT */ 197 198 /* Constants for TX flow */ 199 enum { 200 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */ 201 MAX_BF = 256, 202 MIN_PKT_LEN = 17, 203 }; 204 205 /* 206 * Configurables 207 */ 208 209 enum cq_type { 210 RX = 0, 211 TX = 1, 212 }; 213 214 215 /* 216 * Useful macros 217 */ 218 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x)) 219 #define XNOR(x, y) (!(x) == !(y)) 220 221 222 struct mlx4_en_tx_info { 223 union { 224 struct sk_buff *skb; 225 struct page *page; 226 }; 227 dma_addr_t map0_dma; 228 u32 map0_byte_count; 229 u32 nr_txbb; 230 u32 nr_bytes; 231 u8 linear; 232 u8 data_offset; 233 u8 inl; 234 u8 ts_requested; 235 u8 nr_maps; 236 } ____cacheline_aligned_in_smp; 237 238 239 #define MLX4_EN_BIT_DESC_OWN 0x80000000 240 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg) 241 #define MLX4_EN_MEMTYPE_PAD 0x100 242 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg) 243 244 245 struct mlx4_en_tx_desc { 246 struct mlx4_wqe_ctrl_seg ctrl; 247 union { 248 struct mlx4_wqe_data_seg data; /* at least one data segment */ 249 struct mlx4_wqe_lso_seg lso; 250 struct mlx4_wqe_inline_seg inl; 251 }; 252 }; 253 254 #define MLX4_EN_USE_SRQ 0x01000000 255 256 #define MLX4_EN_CX3_LOW_ID 0x1000 257 #define MLX4_EN_CX3_HIGH_ID 0x1005 258 259 struct mlx4_en_rx_alloc { 260 struct page *page; 261 dma_addr_t dma; 262 u32 page_offset; 263 u32 page_size; 264 }; 265 266 #define MLX4_EN_CACHE_SIZE (2 * NAPI_POLL_WEIGHT) 267 struct mlx4_en_page_cache { 268 u32 index; 269 struct mlx4_en_rx_alloc buf[MLX4_EN_CACHE_SIZE]; 270 }; 271 272 struct mlx4_en_priv; 273 274 struct mlx4_en_tx_ring { 275 /* cache line used and dirtied in tx completion 276 * (mlx4_en_free_tx_buf()) 277 */ 278 u32 last_nr_txbb; 279 u32 cons; 280 unsigned long wake_queue; 281 282 /* cache line used and dirtied in mlx4_en_xmit() */ 283 u32 prod ____cacheline_aligned_in_smp; 284 unsigned long bytes; 285 unsigned long packets; 286 unsigned long tx_csum; 287 unsigned long tso_packets; 288 unsigned long xmit_more; 289 unsigned int tx_dropped; 290 struct mlx4_bf bf; 291 unsigned long queue_stopped; 292 293 /* Following part should be mostly read */ 294 cpumask_t affinity_mask; 295 struct mlx4_qp qp; 296 struct mlx4_hwq_resources wqres; 297 u32 size; /* number of TXBBs */ 298 u32 size_mask; 299 u16 stride; 300 u32 full_size; 301 u16 cqn; /* index of port CQ associated with this ring */ 302 u32 buf_size; 303 __be32 doorbell_qpn; 304 __be32 mr_key; 305 void *buf; 306 struct mlx4_en_tx_info *tx_info; 307 struct mlx4_en_rx_ring *recycle_ring; 308 u32 (*free_tx_desc)(struct mlx4_en_priv *priv, 309 struct mlx4_en_tx_ring *ring, 310 int index, u8 owner, 311 u64 timestamp, int napi_mode); 312 u8 *bounce_buf; 313 struct mlx4_qp_context context; 314 int qpn; 315 enum mlx4_qp_state qp_state; 316 u8 queue_index; 317 bool bf_enabled; 318 bool bf_alloced; 319 struct netdev_queue *tx_queue; 320 int hwtstamp_tx_type; 321 } ____cacheline_aligned_in_smp; 322 323 struct mlx4_en_rx_desc { 324 /* actual number of entries depends on rx ring stride */ 325 struct mlx4_wqe_data_seg data[0]; 326 }; 327 328 struct mlx4_en_rx_ring { 329 struct mlx4_hwq_resources wqres; 330 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS]; 331 u32 size ; /* number of Rx descs*/ 332 u32 actual_size; 333 u32 size_mask; 334 u16 stride; 335 u16 log_stride; 336 u16 cqn; /* index of port CQ associated with this ring */ 337 u32 prod; 338 u32 cons; 339 u32 buf_size; 340 u8 fcs_del; 341 void *buf; 342 void *rx_info; 343 struct bpf_prog *xdp_prog; 344 struct mlx4_en_page_cache page_cache; 345 unsigned long bytes; 346 unsigned long packets; 347 unsigned long csum_ok; 348 unsigned long csum_none; 349 unsigned long csum_complete; 350 unsigned long dropped; 351 int hwtstamp_rx_filter; 352 cpumask_var_t affinity_mask; 353 }; 354 355 struct mlx4_en_cq { 356 struct mlx4_cq mcq; 357 struct mlx4_hwq_resources wqres; 358 int ring; 359 struct net_device *dev; 360 struct napi_struct napi; 361 int size; 362 int buf_size; 363 int vector; 364 enum cq_type is_tx; 365 u16 moder_time; 366 u16 moder_cnt; 367 struct mlx4_cqe *buf; 368 #define MLX4_EN_OPCODE_ERROR 0x1e 369 370 struct irq_desc *irq_desc; 371 }; 372 373 struct mlx4_en_port_profile { 374 u32 flags; 375 u32 tx_ring_num; 376 u32 rx_ring_num; 377 u32 tx_ring_size; 378 u32 rx_ring_size; 379 u8 num_tx_rings_p_up; 380 u8 rx_pause; 381 u8 rx_ppp; 382 u8 tx_pause; 383 u8 tx_ppp; 384 int rss_rings; 385 int inline_thold; 386 struct hwtstamp_config hwtstamp_config; 387 }; 388 389 struct mlx4_en_profile { 390 int udp_rss; 391 u8 rss_mask; 392 u32 active_ports; 393 u32 small_pkt_int; 394 u8 no_reset; 395 u8 num_tx_rings_p_up; 396 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1]; 397 }; 398 399 struct mlx4_en_dev { 400 struct mlx4_dev *dev; 401 struct pci_dev *pdev; 402 struct mutex state_lock; 403 struct net_device *pndev[MLX4_MAX_PORTS + 1]; 404 struct net_device *upper[MLX4_MAX_PORTS + 1]; 405 u32 port_cnt; 406 bool device_up; 407 struct mlx4_en_profile profile; 408 u32 LSO_support; 409 struct workqueue_struct *workqueue; 410 struct device *dma_device; 411 void __iomem *uar_map; 412 struct mlx4_uar priv_uar; 413 struct mlx4_mr mr; 414 u32 priv_pdn; 415 spinlock_t uar_lock; 416 u8 mac_removed[MLX4_MAX_PORTS + 1]; 417 rwlock_t clock_lock; 418 u32 nominal_c_mult; 419 struct cyclecounter cycles; 420 struct timecounter clock; 421 unsigned long last_overflow_check; 422 unsigned long overflow_period; 423 struct ptp_clock *ptp_clock; 424 struct ptp_clock_info ptp_clock_info; 425 struct notifier_block nb; 426 }; 427 428 429 struct mlx4_en_rss_map { 430 int base_qpn; 431 struct mlx4_qp qps[MAX_RX_RINGS]; 432 enum mlx4_qp_state state[MAX_RX_RINGS]; 433 struct mlx4_qp indir_qp; 434 enum mlx4_qp_state indir_state; 435 }; 436 437 enum mlx4_en_port_flag { 438 MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */ 439 MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */ 440 }; 441 442 struct mlx4_en_port_state { 443 int link_state; 444 int link_speed; 445 int transceiver; 446 u32 flags; 447 }; 448 449 enum mlx4_en_mclist_act { 450 MCLIST_NONE, 451 MCLIST_REM, 452 MCLIST_ADD, 453 }; 454 455 struct mlx4_en_mc_list { 456 struct list_head list; 457 enum mlx4_en_mclist_act action; 458 u8 addr[ETH_ALEN]; 459 u64 reg_id; 460 u64 tunnel_reg_id; 461 }; 462 463 struct mlx4_en_frag_info { 464 u16 frag_size; 465 u16 frag_prefix_size; 466 u32 frag_stride; 467 enum dma_data_direction dma_dir; 468 int order; 469 }; 470 471 #ifdef CONFIG_MLX4_EN_DCB 472 /* Minimal TC BW - setting to 0 will block traffic */ 473 #define MLX4_EN_BW_MIN 1 474 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */ 475 476 #define MLX4_EN_TC_ETS 7 477 478 enum dcb_pfc_type { 479 pfc_disabled = 0, 480 pfc_enabled_full, 481 pfc_enabled_tx, 482 pfc_enabled_rx 483 }; 484 485 struct tc_configuration { 486 enum dcb_pfc_type dcb_pfc; 487 }; 488 489 struct mlx4_en_cee_config { 490 bool pfc_state; 491 struct tc_configuration tc_config[MLX4_EN_NUM_UP]; 492 }; 493 494 struct mlx4_en_cee_params { 495 u8 dcbx_cap; 496 struct mlx4_en_cee_config dcb_cfg; 497 }; 498 499 #endif 500 501 struct ethtool_flow_id { 502 struct list_head list; 503 struct ethtool_rx_flow_spec flow_spec; 504 u64 id; 505 }; 506 507 enum { 508 MLX4_EN_FLAG_PROMISC = (1 << 0), 509 MLX4_EN_FLAG_MC_PROMISC = (1 << 1), 510 /* whether we need to enable hardware loopback by putting dmac 511 * in Tx WQE 512 */ 513 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2), 514 /* whether we need to drop packets that hardware loopback-ed */ 515 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3), 516 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4), 517 MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP = (1 << 5), 518 #ifdef CONFIG_MLX4_EN_DCB 519 MLX4_EN_FLAG_DCB_ENABLED = (1 << 6), 520 #endif 521 }; 522 523 #define PORT_BEACON_MAX_LIMIT (65535) 524 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE) 525 #define MLX4_EN_MAC_HASH_IDX 5 526 527 struct mlx4_en_stats_bitmap { 528 DECLARE_BITMAP(bitmap, NUM_ALL_STATS); 529 struct mutex mutex; /* for mutual access to stats bitmap */ 530 }; 531 532 struct mlx4_en_priv { 533 struct mlx4_en_dev *mdev; 534 struct mlx4_en_port_profile *prof; 535 struct net_device *dev; 536 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 537 struct mlx4_en_port_state port_state; 538 spinlock_t stats_lock; 539 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES]; 540 /* To allow rules removal while port is going down */ 541 struct list_head ethtool_list; 542 543 unsigned long last_moder_packets[MAX_RX_RINGS]; 544 unsigned long last_moder_tx_packets; 545 unsigned long last_moder_bytes[MAX_RX_RINGS]; 546 unsigned long last_moder_jiffies; 547 int last_moder_time[MAX_RX_RINGS]; 548 u16 rx_usecs; 549 u16 rx_frames; 550 u16 tx_usecs; 551 u16 tx_frames; 552 u32 pkt_rate_low; 553 u16 rx_usecs_low; 554 u32 pkt_rate_high; 555 u16 rx_usecs_high; 556 u16 sample_interval; 557 u16 adaptive_rx_coal; 558 u32 msg_enable; 559 u32 loopback_ok; 560 u32 validate_loopback; 561 562 struct mlx4_hwq_resources res; 563 int link_state; 564 int last_link_state; 565 bool port_up; 566 int port; 567 int registered; 568 int allocated; 569 int stride; 570 unsigned char current_mac[ETH_ALEN + 2]; 571 int mac_index; 572 unsigned max_mtu; 573 int base_qpn; 574 int cqe_factor; 575 int cqe_size; 576 577 struct mlx4_en_rss_map rss_map; 578 __be32 ctrl_flags; 579 u32 flags; 580 u8 num_tx_rings_p_up; 581 u32 tx_work_limit; 582 u32 tx_ring_num; 583 u32 rx_ring_num; 584 u32 rx_skb_size; 585 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS]; 586 u16 num_frags; 587 u16 log_rx_info; 588 int xdp_ring_num; 589 590 struct mlx4_en_tx_ring **tx_ring; 591 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS]; 592 struct mlx4_en_cq **tx_cq; 593 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS]; 594 struct mlx4_qp drop_qp; 595 struct work_struct rx_mode_task; 596 struct work_struct watchdog_task; 597 struct work_struct linkstate_task; 598 struct delayed_work stats_task; 599 struct delayed_work service_task; 600 struct work_struct vxlan_add_task; 601 struct work_struct vxlan_del_task; 602 struct mlx4_en_perf_stats pstats; 603 struct mlx4_en_pkt_stats pkstats; 604 struct mlx4_en_counter_stats pf_stats; 605 struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES]; 606 struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES]; 607 struct mlx4_en_flow_stats_rx rx_flowstats; 608 struct mlx4_en_flow_stats_tx tx_flowstats; 609 struct mlx4_en_port_stats port_stats; 610 struct mlx4_en_stats_bitmap stats_bitmap; 611 struct list_head mc_list; 612 struct list_head curr_list; 613 u64 broadcast_id; 614 struct mlx4_en_stat_out_mbox hw_stats; 615 int vids[128]; 616 bool wol; 617 struct device *ddev; 618 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE]; 619 struct hwtstamp_config hwtstamp_config; 620 u32 counter_index; 621 622 #ifdef CONFIG_MLX4_EN_DCB 623 #define MLX4_EN_DCB_ENABLED 0x3 624 struct ieee_ets ets; 625 u16 maxrate[IEEE_8021QAZ_MAX_TCS]; 626 enum dcbnl_cndd_states cndd_state[IEEE_8021QAZ_MAX_TCS]; 627 struct mlx4_en_cee_params cee_params; 628 #endif 629 #ifdef CONFIG_RFS_ACCEL 630 spinlock_t filters_lock; 631 int last_filter_id; 632 struct list_head filters; 633 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT]; 634 #endif 635 u64 tunnel_reg_id; 636 __be16 vxlan_port; 637 638 u32 pflags; 639 u8 rss_key[MLX4_EN_RSS_KEY_SIZE]; 640 u8 rss_hash_fn; 641 }; 642 643 enum mlx4_en_wol { 644 MLX4_EN_WOL_MAGIC = (1ULL << 61), 645 MLX4_EN_WOL_ENABLED = (1ULL << 62), 646 }; 647 648 struct mlx4_mac_entry { 649 struct hlist_node hlist; 650 unsigned char mac[ETH_ALEN + 2]; 651 u64 reg_id; 652 struct rcu_head rcu; 653 }; 654 655 static inline struct mlx4_cqe *mlx4_en_get_cqe(void *buf, int idx, int cqe_sz) 656 { 657 return buf + idx * cqe_sz; 658 } 659 660 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63) 661 662 void mlx4_en_init_ptys2ethtool_map(void); 663 void mlx4_en_update_loopback_state(struct net_device *dev, 664 netdev_features_t features); 665 666 void mlx4_en_destroy_netdev(struct net_device *dev); 667 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, 668 struct mlx4_en_port_profile *prof); 669 670 int mlx4_en_start_port(struct net_device *dev); 671 void mlx4_en_stop_port(struct net_device *dev, int detach); 672 673 void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev, 674 struct mlx4_en_stats_bitmap *stats_bitmap, 675 u8 rx_ppp, u8 rx_pause, 676 u8 tx_ppp, u8 tx_pause); 677 678 int mlx4_en_try_alloc_resources(struct mlx4_en_priv *priv, 679 struct mlx4_en_priv *tmp, 680 struct mlx4_en_port_profile *prof); 681 void mlx4_en_safe_replace_resources(struct mlx4_en_priv *priv, 682 struct mlx4_en_priv *tmp); 683 684 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq, 685 int entries, int ring, enum cq_type mode, int node); 686 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq); 687 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq, 688 int cq_idx); 689 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 690 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 691 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 692 693 void mlx4_en_tx_irq(struct mlx4_cq *mcq); 694 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, 695 void *accel_priv, select_queue_fallback_t fallback); 696 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev); 697 netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_alloc *frame, 698 struct net_device *dev, unsigned int length, 699 int tx_ind, int *doorbell_pending); 700 void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring); 701 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring, 702 struct mlx4_en_rx_alloc *frame); 703 704 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 705 struct mlx4_en_tx_ring **pring, 706 u32 size, u16 stride, 707 int node, int queue_index); 708 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 709 struct mlx4_en_tx_ring **pring); 710 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 711 struct mlx4_en_tx_ring *ring, 712 int cq, int user_prio); 713 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 714 struct mlx4_en_tx_ring *ring); 715 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev); 716 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv); 717 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 718 struct mlx4_en_rx_ring **pring, 719 u32 size, u16 stride, int node); 720 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 721 struct mlx4_en_rx_ring **pring, 722 u32 size, u16 stride); 723 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv); 724 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, 725 struct mlx4_en_rx_ring *ring); 726 int mlx4_en_process_rx_cq(struct net_device *dev, 727 struct mlx4_en_cq *cq, 728 int budget); 729 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget); 730 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget); 731 u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, 732 struct mlx4_en_tx_ring *ring, 733 int index, u8 owner, u64 timestamp, 734 int napi_mode); 735 u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv, 736 struct mlx4_en_tx_ring *ring, 737 int index, u8 owner, u64 timestamp, 738 int napi_mode); 739 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, 740 int is_tx, int rss, int qpn, int cqn, int user_prio, 741 struct mlx4_qp_context *context); 742 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event); 743 int mlx4_en_change_mcast_lb(struct mlx4_en_priv *priv, struct mlx4_qp *qp, 744 int loopback); 745 void mlx4_en_calc_rx_buf(struct net_device *dev); 746 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv); 747 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv); 748 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv); 749 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv); 750 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring); 751 void mlx4_en_rx_irq(struct mlx4_cq *mcq); 752 753 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 754 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv); 755 756 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset); 757 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port); 758 759 #ifdef CONFIG_MLX4_EN_DCB 760 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops; 761 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops; 762 #endif 763 764 int mlx4_en_setup_tc(struct net_device *dev, u8 up); 765 766 #ifdef CONFIG_RFS_ACCEL 767 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv); 768 #endif 769 770 #define MLX4_EN_NUM_SELF_TEST 5 771 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf); 772 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev); 773 774 #define DEV_FEATURE_CHANGED(dev, new_features, feature) \ 775 ((dev->features & feature) ^ (new_features & feature)) 776 777 int mlx4_en_reset_config(struct net_device *dev, 778 struct hwtstamp_config ts_config, 779 netdev_features_t new_features); 780 void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev, 781 struct mlx4_en_stats_bitmap *stats_bitmap, 782 u8 rx_ppp, u8 rx_pause, 783 u8 tx_ppp, u8 tx_pause); 784 int mlx4_en_netdev_event(struct notifier_block *this, 785 unsigned long event, void *ptr); 786 787 /* 788 * Functions for time stamping 789 */ 790 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe); 791 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev, 792 struct skb_shared_hwtstamps *hwts, 793 u64 timestamp); 794 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev); 795 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev); 796 797 /* Globals 798 */ 799 extern const struct ethtool_ops mlx4_en_ethtool_ops; 800 801 802 803 /* 804 * printk / logging functions 805 */ 806 807 __printf(3, 4) 808 void en_print(const char *level, const struct mlx4_en_priv *priv, 809 const char *format, ...); 810 811 #define en_dbg(mlevel, priv, format, ...) \ 812 do { \ 813 if (NETIF_MSG_##mlevel & (priv)->msg_enable) \ 814 en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__); \ 815 } while (0) 816 #define en_warn(priv, format, ...) \ 817 en_print(KERN_WARNING, priv, format, ##__VA_ARGS__) 818 #define en_err(priv, format, ...) \ 819 en_print(KERN_ERR, priv, format, ##__VA_ARGS__) 820 #define en_info(priv, format, ...) \ 821 en_print(KERN_INFO, priv, format, ##__VA_ARGS__) 822 823 #define mlx4_err(mdev, format, ...) \ 824 pr_err(DRV_NAME " %s: " format, \ 825 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 826 #define mlx4_info(mdev, format, ...) \ 827 pr_info(DRV_NAME " %s: " format, \ 828 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 829 #define mlx4_warn(mdev, format, ...) \ 830 pr_warn(DRV_NAME " %s: " format, \ 831 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 832 833 #endif 834