1 /*
2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  *
32  */
33 
34 #ifndef _MLX4_EN_H_
35 #define _MLX4_EN_H_
36 
37 #include <linux/bitops.h>
38 #include <linux/compiler.h>
39 #include <linux/ethtool.h>
40 #include <linux/list.h>
41 #include <linux/mutex.h>
42 #include <linux/netdevice.h>
43 #include <linux/if_vlan.h>
44 #include <linux/net_tstamp.h>
45 #ifdef CONFIG_MLX4_EN_DCB
46 #include <linux/dcbnl.h>
47 #endif
48 #include <linux/cpu_rmap.h>
49 #include <linux/ptp_clock_kernel.h>
50 #include <linux/irq.h>
51 #include <net/xdp.h>
52 #include <linux/notifier.h>
53 
54 #include <linux/mlx4/device.h>
55 #include <linux/mlx4/qp.h>
56 #include <linux/mlx4/cq.h>
57 #include <linux/mlx4/srq.h>
58 #include <linux/mlx4/doorbell.h>
59 #include <linux/mlx4/cmd.h>
60 
61 #include "en_port.h"
62 #include "mlx4_stats.h"
63 
64 #define DRV_NAME	"mlx4_en"
65 #define DRV_VERSION	"4.0-0"
66 
67 #define MLX4_EN_MSG_LEVEL	(NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
68 
69 /*
70  * Device constants
71  */
72 
73 
74 #define MLX4_EN_PAGE_SHIFT	12
75 #define MLX4_EN_PAGE_SIZE	(1 << MLX4_EN_PAGE_SHIFT)
76 #define DEF_RX_RINGS		16
77 #define MAX_RX_RINGS		128
78 #define MIN_RX_RINGS		1
79 #define LOG_TXBB_SIZE		6
80 #define TXBB_SIZE		BIT(LOG_TXBB_SIZE)
81 #define HEADROOM		(2048 / TXBB_SIZE + 1)
82 #define STAMP_STRIDE		64
83 #define STAMP_DWORDS		(STAMP_STRIDE / 4)
84 #define STAMP_SHIFT		31
85 #define STAMP_VAL		0x7fffffff
86 #define STATS_DELAY		(HZ / 4)
87 #define SERVICE_TASK_DELAY	(HZ / 4)
88 #define MAX_NUM_OF_FS_RULES	256
89 
90 #define MLX4_EN_FILTER_HASH_SHIFT 4
91 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60
92 
93 #define CTRL_SIZE	sizeof(struct mlx4_wqe_ctrl_seg)
94 #define DS_SIZE		sizeof(struct mlx4_wqe_data_seg)
95 
96 /* Maximal size of the bounce buffer:
97  * 256 bytes for LSO headers.
98  * CTRL_SIZE for control desc.
99  * DS_SIZE if skb->head contains some payload.
100  * MAX_SKB_FRAGS frags.
101  */
102 #define MLX4_TX_BOUNCE_BUFFER_SIZE \
103 	ALIGN(256 + CTRL_SIZE + DS_SIZE + MAX_SKB_FRAGS * DS_SIZE, TXBB_SIZE)
104 
105 #define MLX4_MAX_DESC_TXBBS	   (MLX4_TX_BOUNCE_BUFFER_SIZE / TXBB_SIZE)
106 
107 /*
108  * OS related constants and tunables
109  */
110 
111 #define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1
112 #define MLX4_EN_PRIV_FLAGS_PHV	     2
113 
114 #define MLX4_EN_WATCHDOG_TIMEOUT	(15 * HZ)
115 
116 /* Use the maximum between 16384 and a single page */
117 #define MLX4_EN_ALLOC_SIZE	PAGE_ALIGN(16384)
118 
119 #define MLX4_EN_MAX_RX_FRAGS	4
120 
121 /* Maximum ring sizes */
122 #define MLX4_EN_MAX_TX_SIZE	8192
123 #define MLX4_EN_MAX_RX_SIZE	8192
124 
125 /* Minimum ring size for our page-allocation scheme to work */
126 #define MLX4_EN_MIN_RX_SIZE	(MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
127 #define MLX4_EN_MIN_TX_SIZE	(4096 / TXBB_SIZE)
128 
129 #define MLX4_EN_SMALL_PKT_SIZE		64
130 #define MLX4_EN_MIN_TX_RING_P_UP	1
131 #define MLX4_EN_MAX_TX_RING_P_UP	32
132 #define MLX4_EN_NUM_UP_LOW		1
133 #define MLX4_EN_NUM_UP_HIGH		8
134 #define MLX4_EN_DEF_RX_RING_SIZE  	1024
135 #define MLX4_EN_DEF_TX_RING_SIZE	MLX4_EN_DEF_RX_RING_SIZE
136 #define MAX_TX_RINGS			(MLX4_EN_MAX_TX_RING_P_UP * \
137 					 MLX4_EN_NUM_UP_HIGH)
138 
139 #define MLX4_EN_DEFAULT_TX_WORK		256
140 
141 /* Target number of packets to coalesce with interrupt moderation */
142 #define MLX4_EN_RX_COAL_TARGET	44
143 #define MLX4_EN_RX_COAL_TIME	0x10
144 
145 #define MLX4_EN_TX_COAL_PKTS	16
146 #define MLX4_EN_TX_COAL_TIME	0x10
147 
148 #define MLX4_EN_MAX_COAL_PKTS	U16_MAX
149 #define MLX4_EN_MAX_COAL_TIME	U16_MAX
150 
151 #define MLX4_EN_RX_RATE_LOW		400000
152 #define MLX4_EN_RX_COAL_TIME_LOW	0
153 #define MLX4_EN_RX_RATE_HIGH		450000
154 #define MLX4_EN_RX_COAL_TIME_HIGH	128
155 #define MLX4_EN_RX_SIZE_THRESH		1024
156 #define MLX4_EN_RX_RATE_THRESH		(1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
157 #define MLX4_EN_SAMPLE_INTERVAL		0
158 #define MLX4_EN_AVG_PKT_SMALL		256
159 
160 #define MLX4_EN_AUTO_CONF	0xffff
161 
162 #define MLX4_EN_DEF_RX_PAUSE	1
163 #define MLX4_EN_DEF_TX_PAUSE	1
164 
165 /* Interval between successive polls in the Tx routine when polling is used
166    instead of interrupts (in per-core Tx rings) - should be power of 2 */
167 #define MLX4_EN_TX_POLL_MODER	16
168 #define MLX4_EN_TX_POLL_TIMEOUT	(HZ / 4)
169 
170 #define SMALL_PACKET_SIZE      (256 - NET_IP_ALIGN)
171 #define HEADER_COPY_SIZE       (128 - NET_IP_ALIGN)
172 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
173 #define PREAMBLE_LEN           8
174 #define MLX4_SELFTEST_LB_MIN_MTU (MLX4_LOOPBACK_TEST_PAYLOAD + NET_IP_ALIGN + \
175 				  ETH_HLEN + PREAMBLE_LEN)
176 
177 /* VLAN_HLEN is added twice,to support skb vlan tagged with multiple
178  * headers. (For example: ETH_P_8021Q and ETH_P_8021AD).
179  */
180 #define MLX4_EN_EFF_MTU(mtu)	((mtu) + ETH_HLEN + (2 * VLAN_HLEN))
181 #define ETH_BCAST		0xffffffffffffULL
182 
183 #define MLX4_EN_LOOPBACK_RETRIES	5
184 #define MLX4_EN_LOOPBACK_TIMEOUT	100
185 
186 /* Constants for TX flow */
187 enum {
188 	MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
189 	MAX_BF = 256,
190 	MIN_PKT_LEN = 17,
191 };
192 
193 /*
194  * Configurables
195  */
196 
197 enum cq_type {
198 	/* keep tx types first */
199 	TX,
200 	TX_XDP,
201 #define MLX4_EN_NUM_TX_TYPES (TX_XDP + 1)
202 	RX,
203 };
204 
205 
206 /*
207  * Useful macros
208  */
209 #define ROUNDUP_LOG2(x)		ilog2(roundup_pow_of_two(x))
210 #define XNOR(x, y)		(!(x) == !(y))
211 
212 
213 struct mlx4_en_tx_info {
214 	union {
215 		struct sk_buff *skb;
216 		struct page *page;
217 	};
218 	dma_addr_t	map0_dma;
219 	u32		map0_byte_count;
220 	u32		nr_txbb;
221 	u32		nr_bytes;
222 	u8		linear;
223 	u8		data_offset;
224 	u8		inl;
225 	u8		ts_requested;
226 	u8		nr_maps;
227 } ____cacheline_aligned_in_smp;
228 
229 
230 #define MLX4_EN_BIT_DESC_OWN	0x80000000
231 #define MLX4_EN_MEMTYPE_PAD	0x100
232 
233 
234 struct mlx4_en_tx_desc {
235 	struct mlx4_wqe_ctrl_seg ctrl;
236 	union {
237 		struct mlx4_wqe_data_seg data; /* at least one data segment */
238 		struct mlx4_wqe_lso_seg lso;
239 		struct mlx4_wqe_inline_seg inl;
240 	};
241 };
242 
243 #define MLX4_EN_USE_SRQ		0x01000000
244 
245 #define MLX4_EN_CX3_LOW_ID	0x1000
246 #define MLX4_EN_CX3_HIGH_ID	0x1005
247 
248 struct mlx4_en_rx_alloc {
249 	struct page	*page;
250 	dma_addr_t	dma;
251 	u32		page_offset;
252 };
253 
254 #define MLX4_EN_CACHE_SIZE (2 * NAPI_POLL_WEIGHT)
255 
256 struct mlx4_en_page_cache {
257 	u32 index;
258 	struct {
259 		struct page	*page;
260 		dma_addr_t	dma;
261 	} buf[MLX4_EN_CACHE_SIZE];
262 };
263 
264 enum {
265 	MLX4_EN_TX_RING_STATE_RECOVERING,
266 };
267 
268 struct mlx4_en_priv;
269 
270 struct mlx4_en_tx_ring {
271 	/* cache line used and dirtied in tx completion
272 	 * (mlx4_en_free_tx_buf())
273 	 */
274 	u32			last_nr_txbb;
275 	u32			cons;
276 	unsigned long		wake_queue;
277 	struct netdev_queue	*tx_queue;
278 	u32			(*free_tx_desc)(struct mlx4_en_priv *priv,
279 						struct mlx4_en_tx_ring *ring,
280 						int index,
281 						u64 timestamp, int napi_mode);
282 	struct mlx4_en_rx_ring	*recycle_ring;
283 
284 	/* cache line used and dirtied in mlx4_en_xmit() */
285 	u32			prod ____cacheline_aligned_in_smp;
286 	unsigned int		tx_dropped;
287 	unsigned long		bytes;
288 	unsigned long		packets;
289 	unsigned long		tx_csum;
290 	unsigned long		tso_packets;
291 	unsigned long		xmit_more;
292 	struct mlx4_bf		bf;
293 
294 	/* Following part should be mostly read */
295 	void __iomem		*doorbell_address;
296 	__be32			doorbell_qpn;
297 	__be32			mr_key;
298 	u32			size; /* number of TXBBs */
299 	u32			size_mask;
300 	u32			full_size;
301 	u32			buf_size;
302 	void			*buf;
303 	struct mlx4_en_tx_info	*tx_info;
304 	int			qpn;
305 	u8			queue_index;
306 	bool			bf_enabled;
307 	bool			bf_alloced;
308 	u8			hwtstamp_tx_type;
309 	u8			*bounce_buf;
310 
311 	/* Not used in fast path
312 	 * Only queue_stopped might be used if BQL is not properly working.
313 	 */
314 	unsigned long		queue_stopped;
315 	unsigned long		state;
316 	struct mlx4_hwq_resources sp_wqres;
317 	struct mlx4_qp		sp_qp;
318 	struct mlx4_qp_context	sp_context;
319 	cpumask_t		sp_affinity_mask;
320 	enum mlx4_qp_state	sp_qp_state;
321 	u16			sp_stride;
322 	u16			sp_cqn;	/* index of port CQ associated with this ring */
323 } ____cacheline_aligned_in_smp;
324 
325 struct mlx4_en_rx_desc {
326 	/* actual number of entries depends on rx ring stride */
327 	DECLARE_FLEX_ARRAY(struct mlx4_wqe_data_seg, data);
328 };
329 
330 struct mlx4_en_rx_ring {
331 	struct mlx4_hwq_resources wqres;
332 	u32 size ;	/* number of Rx descs*/
333 	u32 actual_size;
334 	u32 size_mask;
335 	u16 stride;
336 	u16 log_stride;
337 	u16 cqn;	/* index of port CQ associated with this ring */
338 	u32 prod;
339 	u32 cons;
340 	u32 buf_size;
341 	u8  fcs_del;
342 	void *buf;
343 	void *rx_info;
344 	struct bpf_prog __rcu *xdp_prog;
345 	struct mlx4_en_page_cache page_cache;
346 	unsigned long bytes;
347 	unsigned long packets;
348 	unsigned long csum_ok;
349 	unsigned long csum_none;
350 	unsigned long csum_complete;
351 	unsigned long rx_alloc_pages;
352 	unsigned long xdp_drop;
353 	unsigned long xdp_redirect;
354 	unsigned long xdp_redirect_fail;
355 	unsigned long xdp_tx;
356 	unsigned long xdp_tx_full;
357 	unsigned long dropped;
358 	int hwtstamp_rx_filter;
359 	cpumask_var_t affinity_mask;
360 	struct xdp_rxq_info xdp_rxq;
361 };
362 
363 struct mlx4_en_cq {
364 	struct mlx4_cq          mcq;
365 	struct mlx4_hwq_resources wqres;
366 	int                     ring;
367 	struct net_device      *dev;
368 	union {
369 		struct napi_struct napi;
370 		bool               xdp_busy;
371 	};
372 	int size;
373 	int buf_size;
374 	int vector;
375 	enum cq_type type;
376 	u16 moder_time;
377 	u16 moder_cnt;
378 	struct mlx4_cqe *buf;
379 #define MLX4_EN_OPCODE_ERROR	0x1e
380 
381 	const struct cpumask *aff_mask;
382 };
383 
384 struct mlx4_en_port_profile {
385 	u32 flags;
386 	u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES];
387 	u32 rx_ring_num;
388 	u32 tx_ring_size;
389 	u32 rx_ring_size;
390 	u8 num_tx_rings_p_up;
391 	u8 rx_pause;
392 	u8 rx_ppp;
393 	u8 tx_pause;
394 	u8 tx_ppp;
395 	u8 num_up;
396 	int rss_rings;
397 	int inline_thold;
398 	struct hwtstamp_config hwtstamp_config;
399 };
400 
401 struct mlx4_en_profile {
402 	int udp_rss;
403 	u8 rss_mask;
404 	u32 active_ports;
405 	u32 small_pkt_int;
406 	u8 no_reset;
407 	u8 max_num_tx_rings_p_up;
408 	struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
409 };
410 
411 struct mlx4_en_dev {
412 	struct mlx4_dev         *dev;
413 	struct pci_dev		*pdev;
414 	struct mutex		state_lock;
415 	struct net_device       *pndev[MLX4_MAX_PORTS + 1];
416 	struct net_device       *upper[MLX4_MAX_PORTS + 1];
417 	u32                     port_cnt;
418 	bool			device_up;
419 	struct mlx4_en_profile  profile;
420 	u32			LSO_support;
421 	struct workqueue_struct *workqueue;
422 	struct device           *dma_device;
423 	void __iomem            *uar_map;
424 	struct mlx4_uar         priv_uar;
425 	struct mlx4_mr		mr;
426 	u32                     priv_pdn;
427 	spinlock_t              uar_lock;
428 	u8			mac_removed[MLX4_MAX_PORTS + 1];
429 	u32			nominal_c_mult;
430 	struct cyclecounter	cycles;
431 	seqlock_t		clock_lock;
432 	struct timecounter	clock;
433 	unsigned long		last_overflow_check;
434 	struct ptp_clock	*ptp_clock;
435 	struct ptp_clock_info	ptp_clock_info;
436 	struct notifier_block	netdev_nb;
437 	struct notifier_block	mlx_nb;
438 };
439 
440 
441 struct mlx4_en_rss_map {
442 	int base_qpn;
443 	struct mlx4_qp qps[MAX_RX_RINGS];
444 	enum mlx4_qp_state state[MAX_RX_RINGS];
445 	struct mlx4_qp *indir_qp;
446 	enum mlx4_qp_state indir_state;
447 };
448 
449 enum mlx4_en_port_flag {
450 	MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */
451 	MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */
452 };
453 
454 struct mlx4_en_port_state {
455 	int link_state;
456 	int link_speed;
457 	int transceiver;
458 	u32 flags;
459 };
460 
461 enum mlx4_en_mclist_act {
462 	MCLIST_NONE,
463 	MCLIST_REM,
464 	MCLIST_ADD,
465 };
466 
467 struct mlx4_en_mc_list {
468 	struct list_head	list;
469 	enum mlx4_en_mclist_act	action;
470 	u8			addr[ETH_ALEN];
471 	u64			reg_id;
472 	u64			tunnel_reg_id;
473 };
474 
475 struct mlx4_en_frag_info {
476 	u16 frag_size;
477 	u32 frag_stride;
478 };
479 
480 #ifdef CONFIG_MLX4_EN_DCB
481 /* Minimal TC BW - setting to 0 will block traffic */
482 #define MLX4_EN_BW_MIN 1
483 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
484 
485 #define MLX4_EN_TC_VENDOR 0
486 #define MLX4_EN_TC_ETS 7
487 
488 enum dcb_pfc_type {
489 	pfc_disabled = 0,
490 	pfc_enabled_full,
491 	pfc_enabled_tx,
492 	pfc_enabled_rx
493 };
494 
495 struct mlx4_en_cee_config {
496 	bool	pfc_state;
497 	enum	dcb_pfc_type dcb_pfc[MLX4_EN_NUM_UP_HIGH];
498 };
499 #endif
500 
501 struct ethtool_flow_id {
502 	struct list_head list;
503 	struct ethtool_rx_flow_spec flow_spec;
504 	u64 id;
505 };
506 
507 enum {
508 	MLX4_EN_FLAG_PROMISC		= (1 << 0),
509 	MLX4_EN_FLAG_MC_PROMISC		= (1 << 1),
510 	/* whether we need to enable hardware loopback by putting dmac
511 	 * in Tx WQE
512 	 */
513 	MLX4_EN_FLAG_ENABLE_HW_LOOPBACK	= (1 << 2),
514 	/* whether we need to drop packets that hardware loopback-ed */
515 	MLX4_EN_FLAG_RX_FILTER_NEEDED	= (1 << 3),
516 	MLX4_EN_FLAG_FORCE_PROMISC	= (1 << 4),
517 	MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP	= (1 << 5),
518 #ifdef CONFIG_MLX4_EN_DCB
519 	MLX4_EN_FLAG_DCB_ENABLED        = (1 << 6),
520 #endif
521 };
522 
523 #define PORT_BEACON_MAX_LIMIT (65535)
524 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
525 #define MLX4_EN_MAC_HASH_IDX 5
526 
527 struct mlx4_en_stats_bitmap {
528 	DECLARE_BITMAP(bitmap, NUM_ALL_STATS);
529 	struct mutex mutex; /* for mutual access to stats bitmap */
530 };
531 
532 enum {
533 	MLX4_EN_STATE_FLAG_RESTARTING,
534 };
535 
536 struct mlx4_en_priv {
537 	struct mlx4_en_dev *mdev;
538 	struct mlx4_en_port_profile *prof;
539 	struct net_device *dev;
540 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
541 	struct mlx4_en_port_state port_state;
542 	spinlock_t stats_lock;
543 	struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
544 	/* To allow rules removal while port is going down */
545 	struct list_head ethtool_list;
546 
547 	unsigned long last_moder_packets[MAX_RX_RINGS];
548 	unsigned long last_moder_tx_packets;
549 	unsigned long last_moder_bytes[MAX_RX_RINGS];
550 	unsigned long last_moder_jiffies;
551 	int last_moder_time[MAX_RX_RINGS];
552 	u16 rx_usecs;
553 	u16 rx_frames;
554 	u16 tx_usecs;
555 	u16 tx_frames;
556 	u32 pkt_rate_low;
557 	u16 rx_usecs_low;
558 	u32 pkt_rate_high;
559 	u16 rx_usecs_high;
560 	u32 sample_interval;
561 	u32 adaptive_rx_coal;
562 	u32 msg_enable;
563 	u32 loopback_ok;
564 	u32 validate_loopback;
565 
566 	struct mlx4_hwq_resources res;
567 	int link_state;
568 	bool port_up;
569 	int port;
570 	int registered;
571 	int allocated;
572 	int stride;
573 	unsigned char current_mac[ETH_ALEN + 2];
574 	int mac_index;
575 	unsigned max_mtu;
576 	int base_qpn;
577 	int cqe_factor;
578 	int cqe_size;
579 
580 	struct mlx4_en_rss_map rss_map;
581 	__be32 ctrl_flags;
582 	u32 flags;
583 	u8 num_tx_rings_p_up;
584 	u32 tx_work_limit;
585 	u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES];
586 	u32 rx_ring_num;
587 	u32 rx_skb_size;
588 	struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
589 	u8 num_frags;
590 	u8 log_rx_info;
591 	u8 dma_dir;
592 	u16 rx_headroom;
593 
594 	struct mlx4_en_tx_ring **tx_ring[MLX4_EN_NUM_TX_TYPES];
595 	struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS];
596 	struct mlx4_en_cq **tx_cq[MLX4_EN_NUM_TX_TYPES];
597 	struct mlx4_en_cq *rx_cq[MAX_RX_RINGS];
598 	struct mlx4_qp drop_qp;
599 	struct work_struct rx_mode_task;
600 	struct work_struct restart_task;
601 	struct work_struct linkstate_task;
602 	struct delayed_work stats_task;
603 	struct delayed_work service_task;
604 	struct mlx4_en_pkt_stats pkstats;
605 	struct mlx4_en_counter_stats pf_stats;
606 	struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES];
607 	struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES];
608 	struct mlx4_en_flow_stats_rx rx_flowstats;
609 	struct mlx4_en_flow_stats_tx tx_flowstats;
610 	struct mlx4_en_port_stats port_stats;
611 	struct mlx4_en_xdp_stats xdp_stats;
612 	struct mlx4_en_phy_stats phy_stats;
613 	struct mlx4_en_stats_bitmap stats_bitmap;
614 	struct list_head mc_list;
615 	struct list_head curr_list;
616 	u64 broadcast_id;
617 	struct mlx4_en_stat_out_mbox hw_stats;
618 	int vids[128];
619 	bool wol;
620 	struct device *ddev;
621 	struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE];
622 	struct hwtstamp_config hwtstamp_config;
623 	u32 counter_index;
624 
625 #ifdef CONFIG_MLX4_EN_DCB
626 #define MLX4_EN_DCB_ENABLED	0x3
627 	struct ieee_ets ets;
628 	u16 maxrate[IEEE_8021QAZ_MAX_TCS];
629 	enum dcbnl_cndd_states cndd_state[IEEE_8021QAZ_MAX_TCS];
630 	struct mlx4_en_cee_config cee_config;
631 	u8 dcbx_cap;
632 #endif
633 #ifdef CONFIG_RFS_ACCEL
634 	spinlock_t filters_lock;
635 	int last_filter_id;
636 	struct list_head filters;
637 	struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
638 #endif
639 	u64 tunnel_reg_id;
640 	__be16 vxlan_port;
641 
642 	u32 pflags;
643 	u8 rss_key[MLX4_EN_RSS_KEY_SIZE];
644 	u8 rss_hash_fn;
645 	unsigned long state;
646 };
647 
648 enum mlx4_en_wol {
649 	MLX4_EN_WOL_MAGIC = (1ULL << 61),
650 	MLX4_EN_WOL_ENABLED = (1ULL << 62),
651 };
652 
653 struct mlx4_mac_entry {
654 	struct hlist_node hlist;
655 	unsigned char mac[ETH_ALEN + 2];
656 	u64 reg_id;
657 	struct rcu_head rcu;
658 };
659 
660 static inline struct mlx4_cqe *mlx4_en_get_cqe(void *buf, int idx, int cqe_sz)
661 {
662 	return buf + idx * cqe_sz;
663 }
664 
665 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
666 
667 void mlx4_en_init_ptys2ethtool_map(void);
668 void mlx4_en_update_loopback_state(struct net_device *dev,
669 				   netdev_features_t features);
670 
671 void mlx4_en_destroy_netdev(struct net_device *dev);
672 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
673 			struct mlx4_en_port_profile *prof);
674 
675 int mlx4_en_start_port(struct net_device *dev);
676 void mlx4_en_stop_port(struct net_device *dev, int detach);
677 
678 void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev,
679 			      struct mlx4_en_stats_bitmap *stats_bitmap,
680 			      u8 rx_ppp, u8 rx_pause,
681 			      u8 tx_ppp, u8 tx_pause);
682 
683 int mlx4_en_try_alloc_resources(struct mlx4_en_priv *priv,
684 				struct mlx4_en_priv *tmp,
685 				struct mlx4_en_port_profile *prof,
686 				bool carry_xdp_prog);
687 void mlx4_en_safe_replace_resources(struct mlx4_en_priv *priv,
688 				    struct mlx4_en_priv *tmp);
689 
690 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq,
691 		      int entries, int ring, enum cq_type mode, int node);
692 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq);
693 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
694 			int cq_idx);
695 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
696 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
697 void mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
698 
699 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
700 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
701 			 struct net_device *sb_dev);
702 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
703 netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring,
704 			       struct mlx4_en_rx_alloc *frame,
705 			       struct mlx4_en_priv *priv, unsigned int length,
706 			       int tx_ind, bool *doorbell_pending);
707 void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring);
708 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring,
709 			struct mlx4_en_rx_alloc *frame);
710 
711 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
712 			   struct mlx4_en_tx_ring **pring,
713 			   u32 size, u16 stride,
714 			   int node, int queue_index);
715 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
716 			     struct mlx4_en_tx_ring **pring);
717 void mlx4_en_init_tx_xdp_ring_descs(struct mlx4_en_priv *priv,
718 				    struct mlx4_en_tx_ring *ring);
719 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
720 			     struct mlx4_en_tx_ring *ring,
721 			     int cq, int user_prio);
722 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
723 				struct mlx4_en_tx_ring *ring);
724 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev);
725 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv);
726 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
727 			   struct mlx4_en_rx_ring **pring,
728 			   u32 size, u16 stride, int node, int queue_index);
729 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
730 			     struct mlx4_en_rx_ring **pring,
731 			     u32 size, u16 stride);
732 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
733 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
734 				struct mlx4_en_rx_ring *ring);
735 int mlx4_en_process_rx_cq(struct net_device *dev,
736 			  struct mlx4_en_cq *cq,
737 			  int budget);
738 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
739 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget);
740 int mlx4_en_process_tx_cq(struct net_device *dev,
741 			  struct mlx4_en_cq *cq, int napi_budget);
742 u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
743 			 struct mlx4_en_tx_ring *ring,
744 			 int index, u64 timestamp,
745 			 int napi_mode);
746 u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv,
747 			    struct mlx4_en_tx_ring *ring,
748 			    int index, u64 timestamp,
749 			    int napi_mode);
750 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
751 		int is_tx, int rss, int qpn, int cqn, int user_prio,
752 		struct mlx4_qp_context *context);
753 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
754 int mlx4_en_change_mcast_lb(struct mlx4_en_priv *priv, struct mlx4_qp *qp,
755 			    int loopback);
756 void mlx4_en_calc_rx_buf(struct net_device *dev);
757 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
758 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
759 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
760 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
761 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
762 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
763 
764 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
765 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
766 
767 void mlx4_en_fold_software_stats(struct net_device *dev);
768 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
769 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
770 
771 #ifdef CONFIG_MLX4_EN_DCB
772 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
773 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
774 #endif
775 
776 int mlx4_en_setup_tc(struct net_device *dev, u8 up);
777 int mlx4_en_alloc_tx_queue_per_tc(struct net_device *dev, u8 tc);
778 
779 #ifdef CONFIG_RFS_ACCEL
780 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv);
781 #endif
782 
783 #define MLX4_EN_NUM_SELF_TEST	5
784 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
785 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
786 
787 #define DEV_FEATURE_CHANGED(dev, new_features, feature) \
788 	((dev->features & feature) ^ (new_features & feature))
789 
790 int mlx4_en_moderation_update(struct mlx4_en_priv *priv);
791 int mlx4_en_reset_config(struct net_device *dev,
792 			 struct hwtstamp_config ts_config,
793 			 netdev_features_t new_features);
794 void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev,
795 				     struct mlx4_en_stats_bitmap *stats_bitmap,
796 				     u8 rx_ppp, u8 rx_pause,
797 				     u8 tx_ppp, u8 tx_pause);
798 int mlx4_en_netdev_event(struct notifier_block *this,
799 			 unsigned long event, void *ptr);
800 
801 struct xdp_md;
802 int mlx4_en_xdp_rx_timestamp(const struct xdp_md *ctx, u64 *timestamp);
803 int mlx4_en_xdp_rx_hash(const struct xdp_md *ctx, u32 *hash,
804 			enum xdp_rss_hash_type *rss_type);
805 
806 /*
807  * Functions for time stamping
808  */
809 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
810 u64 mlx4_en_get_hwtstamp(struct mlx4_en_dev *mdev, u64 timestamp);
811 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev,
812 			    struct skb_shared_hwtstamps *hwts,
813 			    u64 timestamp);
814 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev);
815 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev);
816 
817 /* Globals
818  */
819 extern const struct ethtool_ops mlx4_en_ethtool_ops;
820 
821 
822 
823 /*
824  * printk / logging functions
825  */
826 
827 __printf(3, 4)
828 void en_print(const char *level, const struct mlx4_en_priv *priv,
829 	      const char *format, ...);
830 
831 #define en_dbg(mlevel, priv, format, ...)				\
832 do {									\
833 	if (NETIF_MSG_##mlevel & (priv)->msg_enable)			\
834 		en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__);	\
835 } while (0)
836 #define en_warn(priv, format, ...)					\
837 	en_print(KERN_WARNING, priv, format, ##__VA_ARGS__)
838 #define en_err(priv, format, ...)					\
839 	en_print(KERN_ERR, priv, format, ##__VA_ARGS__)
840 #define en_info(priv, format, ...)					\
841 	en_print(KERN_INFO, priv, format, ##__VA_ARGS__)
842 
843 #define mlx4_err(mdev, format, ...)					\
844 	pr_err(DRV_NAME " %s: " format,					\
845 	       dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
846 #define mlx4_info(mdev, format, ...)					\
847 	pr_info(DRV_NAME " %s: " format,				\
848 		dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
849 #define mlx4_warn(mdev, format, ...)					\
850 	pr_warn(DRV_NAME " %s: " format,				\
851 		dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
852 
853 #endif
854