1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #ifndef _MLX4_EN_H_ 35 #define _MLX4_EN_H_ 36 37 #include <linux/bitops.h> 38 #include <linux/compiler.h> 39 #include <linux/list.h> 40 #include <linux/mutex.h> 41 #include <linux/netdevice.h> 42 #include <linux/if_vlan.h> 43 #include <linux/net_tstamp.h> 44 #ifdef CONFIG_MLX4_EN_DCB 45 #include <linux/dcbnl.h> 46 #endif 47 #include <linux/cpu_rmap.h> 48 #include <linux/ptp_clock_kernel.h> 49 50 #include <linux/mlx4/device.h> 51 #include <linux/mlx4/qp.h> 52 #include <linux/mlx4/cq.h> 53 #include <linux/mlx4/srq.h> 54 #include <linux/mlx4/doorbell.h> 55 #include <linux/mlx4/cmd.h> 56 57 #include "en_port.h" 58 #include "mlx4_stats.h" 59 60 #define DRV_NAME "mlx4_en" 61 #define DRV_VERSION "2.2-1" 62 #define DRV_RELDATE "Feb 2014" 63 64 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN) 65 66 /* 67 * Device constants 68 */ 69 70 71 #define MLX4_EN_PAGE_SHIFT 12 72 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT) 73 #define DEF_RX_RINGS 16 74 #define MAX_RX_RINGS 128 75 #define MIN_RX_RINGS 4 76 #define TXBB_SIZE 64 77 #define HEADROOM (2048 / TXBB_SIZE + 1) 78 #define STAMP_STRIDE 64 79 #define STAMP_DWORDS (STAMP_STRIDE / 4) 80 #define STAMP_SHIFT 31 81 #define STAMP_VAL 0x7fffffff 82 #define STATS_DELAY (HZ / 4) 83 #define SERVICE_TASK_DELAY (HZ / 4) 84 #define MAX_NUM_OF_FS_RULES 256 85 86 #define MLX4_EN_FILTER_HASH_SHIFT 4 87 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60 88 89 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */ 90 #define MAX_DESC_SIZE 512 91 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE) 92 93 /* 94 * OS related constants and tunables 95 */ 96 97 #define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1 98 #define MLX4_EN_PRIV_FLAGS_PHV 2 99 100 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ) 101 102 /* Use the maximum between 16384 and a single page */ 103 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384) 104 105 #define MLX4_EN_ALLOC_PREFER_ORDER min_t(int, get_order(32768), \ 106 PAGE_ALLOC_COSTLY_ORDER) 107 108 /* Receive fragment sizes; we use at most 3 fragments (for 9600 byte MTU 109 * and 4K allocations) */ 110 enum { 111 FRAG_SZ0 = 1536 - NET_IP_ALIGN, 112 FRAG_SZ1 = 4096, 113 FRAG_SZ2 = 4096, 114 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE 115 }; 116 #define MLX4_EN_MAX_RX_FRAGS 4 117 118 /* Maximum ring sizes */ 119 #define MLX4_EN_MAX_TX_SIZE 8192 120 #define MLX4_EN_MAX_RX_SIZE 8192 121 122 /* Minimum ring size for our page-allocation scheme to work */ 123 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES) 124 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE) 125 126 #define MLX4_EN_SMALL_PKT_SIZE 64 127 #define MLX4_EN_MIN_TX_RING_P_UP 1 128 #define MLX4_EN_MAX_TX_RING_P_UP 32 129 #define MLX4_EN_NUM_UP 8 130 #define MLX4_EN_DEF_TX_RING_SIZE 512 131 #define MLX4_EN_DEF_RX_RING_SIZE 1024 132 #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \ 133 MLX4_EN_NUM_UP) 134 135 #define MLX4_EN_DEFAULT_TX_WORK 256 136 #define MLX4_EN_DOORBELL_BUDGET 8 137 138 /* Target number of packets to coalesce with interrupt moderation */ 139 #define MLX4_EN_RX_COAL_TARGET 44 140 #define MLX4_EN_RX_COAL_TIME 0x10 141 142 #define MLX4_EN_TX_COAL_PKTS 16 143 #define MLX4_EN_TX_COAL_TIME 0x10 144 145 #define MLX4_EN_RX_RATE_LOW 400000 146 #define MLX4_EN_RX_COAL_TIME_LOW 0 147 #define MLX4_EN_RX_RATE_HIGH 450000 148 #define MLX4_EN_RX_COAL_TIME_HIGH 128 149 #define MLX4_EN_RX_SIZE_THRESH 1024 150 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH) 151 #define MLX4_EN_SAMPLE_INTERVAL 0 152 #define MLX4_EN_AVG_PKT_SMALL 256 153 154 #define MLX4_EN_AUTO_CONF 0xffff 155 156 #define MLX4_EN_DEF_RX_PAUSE 1 157 #define MLX4_EN_DEF_TX_PAUSE 1 158 159 /* Interval between successive polls in the Tx routine when polling is used 160 instead of interrupts (in per-core Tx rings) - should be power of 2 */ 161 #define MLX4_EN_TX_POLL_MODER 16 162 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4) 163 164 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN) 165 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN) 166 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN) 167 168 #define MLX4_EN_MIN_MTU 46 169 /* VLAN_HLEN is added twice,to support skb vlan tagged with multiple 170 * headers. (For example: ETH_P_8021Q and ETH_P_8021AD). 171 */ 172 #define MLX4_EN_EFF_MTU(mtu) ((mtu) + ETH_HLEN + (2 * VLAN_HLEN)) 173 #define ETH_BCAST 0xffffffffffffULL 174 175 #define MLX4_EN_LOOPBACK_RETRIES 5 176 #define MLX4_EN_LOOPBACK_TIMEOUT 100 177 178 #ifdef MLX4_EN_PERF_STAT 179 /* Number of samples to 'average' */ 180 #define AVG_SIZE 128 181 #define AVG_FACTOR 1024 182 183 #define INC_PERF_COUNTER(cnt) (++(cnt)) 184 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add)) 185 #define AVG_PERF_COUNTER(cnt, sample) \ 186 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE) 187 #define GET_PERF_COUNTER(cnt) (cnt) 188 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR) 189 190 #else 191 192 #define INC_PERF_COUNTER(cnt) do {} while (0) 193 #define ADD_PERF_COUNTER(cnt, add) do {} while (0) 194 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0) 195 #define GET_PERF_COUNTER(cnt) (0) 196 #define GET_AVG_PERF_COUNTER(cnt) (0) 197 #endif /* MLX4_EN_PERF_STAT */ 198 199 /* Constants for TX flow */ 200 enum { 201 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */ 202 MAX_BF = 256, 203 MIN_PKT_LEN = 17, 204 }; 205 206 /* 207 * Configurables 208 */ 209 210 enum cq_type { 211 /* keep tx types first */ 212 TX, 213 TX_XDP, 214 #define MLX4_EN_NUM_TX_TYPES (TX_XDP + 1) 215 RX, 216 }; 217 218 219 /* 220 * Useful macros 221 */ 222 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x)) 223 #define XNOR(x, y) (!(x) == !(y)) 224 225 226 struct mlx4_en_tx_info { 227 union { 228 struct sk_buff *skb; 229 struct page *page; 230 }; 231 dma_addr_t map0_dma; 232 u32 map0_byte_count; 233 u32 nr_txbb; 234 u32 nr_bytes; 235 u8 linear; 236 u8 data_offset; 237 u8 inl; 238 u8 ts_requested; 239 u8 nr_maps; 240 } ____cacheline_aligned_in_smp; 241 242 243 #define MLX4_EN_BIT_DESC_OWN 0x80000000 244 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg) 245 #define MLX4_EN_MEMTYPE_PAD 0x100 246 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg) 247 248 249 struct mlx4_en_tx_desc { 250 struct mlx4_wqe_ctrl_seg ctrl; 251 union { 252 struct mlx4_wqe_data_seg data; /* at least one data segment */ 253 struct mlx4_wqe_lso_seg lso; 254 struct mlx4_wqe_inline_seg inl; 255 }; 256 }; 257 258 #define MLX4_EN_USE_SRQ 0x01000000 259 260 #define MLX4_EN_CX3_LOW_ID 0x1000 261 #define MLX4_EN_CX3_HIGH_ID 0x1005 262 263 struct mlx4_en_rx_alloc { 264 struct page *page; 265 dma_addr_t dma; 266 u32 page_offset; 267 u32 page_size; 268 }; 269 270 #define MLX4_EN_CACHE_SIZE (2 * NAPI_POLL_WEIGHT) 271 struct mlx4_en_page_cache { 272 u32 index; 273 struct mlx4_en_rx_alloc buf[MLX4_EN_CACHE_SIZE]; 274 }; 275 276 struct mlx4_en_priv; 277 278 struct mlx4_en_tx_ring { 279 /* cache line used and dirtied in tx completion 280 * (mlx4_en_free_tx_buf()) 281 */ 282 u32 last_nr_txbb; 283 u32 cons; 284 unsigned long wake_queue; 285 struct netdev_queue *tx_queue; 286 u32 (*free_tx_desc)(struct mlx4_en_priv *priv, 287 struct mlx4_en_tx_ring *ring, 288 int index, u8 owner, 289 u64 timestamp, int napi_mode); 290 struct mlx4_en_rx_ring *recycle_ring; 291 292 /* cache line used and dirtied in mlx4_en_xmit() */ 293 u32 prod ____cacheline_aligned_in_smp; 294 unsigned int tx_dropped; 295 unsigned long bytes; 296 unsigned long packets; 297 unsigned long tx_csum; 298 unsigned long tso_packets; 299 unsigned long xmit_more; 300 struct mlx4_bf bf; 301 302 /* Following part should be mostly read */ 303 __be32 doorbell_qpn; 304 __be32 mr_key; 305 u32 size; /* number of TXBBs */ 306 u32 size_mask; 307 u32 full_size; 308 u32 buf_size; 309 void *buf; 310 struct mlx4_en_tx_info *tx_info; 311 int qpn; 312 u8 queue_index; 313 bool bf_enabled; 314 bool bf_alloced; 315 u8 hwtstamp_tx_type; 316 u8 *bounce_buf; 317 318 /* Not used in fast path 319 * Only queue_stopped might be used if BQL is not properly working. 320 */ 321 unsigned long queue_stopped; 322 struct mlx4_hwq_resources sp_wqres; 323 struct mlx4_qp sp_qp; 324 struct mlx4_qp_context sp_context; 325 cpumask_t sp_affinity_mask; 326 enum mlx4_qp_state sp_qp_state; 327 u16 sp_stride; 328 u16 sp_cqn; /* index of port CQ associated with this ring */ 329 } ____cacheline_aligned_in_smp; 330 331 struct mlx4_en_rx_desc { 332 /* actual number of entries depends on rx ring stride */ 333 struct mlx4_wqe_data_seg data[0]; 334 }; 335 336 struct mlx4_en_rx_ring { 337 struct mlx4_hwq_resources wqres; 338 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS]; 339 u32 size ; /* number of Rx descs*/ 340 u32 actual_size; 341 u32 size_mask; 342 u16 stride; 343 u16 log_stride; 344 u16 cqn; /* index of port CQ associated with this ring */ 345 u32 prod; 346 u32 cons; 347 u32 buf_size; 348 u8 fcs_del; 349 void *buf; 350 void *rx_info; 351 struct bpf_prog __rcu *xdp_prog; 352 struct mlx4_en_page_cache page_cache; 353 unsigned long bytes; 354 unsigned long packets; 355 unsigned long csum_ok; 356 unsigned long csum_none; 357 unsigned long csum_complete; 358 unsigned long xdp_drop; 359 unsigned long xdp_tx; 360 unsigned long xdp_tx_full; 361 unsigned long dropped; 362 int hwtstamp_rx_filter; 363 cpumask_var_t affinity_mask; 364 }; 365 366 struct mlx4_en_cq { 367 struct mlx4_cq mcq; 368 struct mlx4_hwq_resources wqres; 369 int ring; 370 struct net_device *dev; 371 struct napi_struct napi; 372 int size; 373 int buf_size; 374 int vector; 375 enum cq_type type; 376 u16 moder_time; 377 u16 moder_cnt; 378 struct mlx4_cqe *buf; 379 #define MLX4_EN_OPCODE_ERROR 0x1e 380 381 struct irq_desc *irq_desc; 382 }; 383 384 struct mlx4_en_port_profile { 385 u32 flags; 386 u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES]; 387 u32 rx_ring_num; 388 u32 tx_ring_size; 389 u32 rx_ring_size; 390 u8 num_tx_rings_p_up; 391 u8 rx_pause; 392 u8 rx_ppp; 393 u8 tx_pause; 394 u8 tx_ppp; 395 int rss_rings; 396 int inline_thold; 397 struct hwtstamp_config hwtstamp_config; 398 }; 399 400 struct mlx4_en_profile { 401 int udp_rss; 402 u8 rss_mask; 403 u32 active_ports; 404 u32 small_pkt_int; 405 u8 no_reset; 406 u8 num_tx_rings_p_up; 407 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1]; 408 }; 409 410 struct mlx4_en_dev { 411 struct mlx4_dev *dev; 412 struct pci_dev *pdev; 413 struct mutex state_lock; 414 struct net_device *pndev[MLX4_MAX_PORTS + 1]; 415 struct net_device *upper[MLX4_MAX_PORTS + 1]; 416 u32 port_cnt; 417 bool device_up; 418 struct mlx4_en_profile profile; 419 u32 LSO_support; 420 struct workqueue_struct *workqueue; 421 struct device *dma_device; 422 void __iomem *uar_map; 423 struct mlx4_uar priv_uar; 424 struct mlx4_mr mr; 425 u32 priv_pdn; 426 spinlock_t uar_lock; 427 u8 mac_removed[MLX4_MAX_PORTS + 1]; 428 u32 nominal_c_mult; 429 struct cyclecounter cycles; 430 seqlock_t clock_lock; 431 struct timecounter clock; 432 unsigned long last_overflow_check; 433 unsigned long overflow_period; 434 struct ptp_clock *ptp_clock; 435 struct ptp_clock_info ptp_clock_info; 436 struct notifier_block nb; 437 }; 438 439 440 struct mlx4_en_rss_map { 441 int base_qpn; 442 struct mlx4_qp qps[MAX_RX_RINGS]; 443 enum mlx4_qp_state state[MAX_RX_RINGS]; 444 struct mlx4_qp indir_qp; 445 enum mlx4_qp_state indir_state; 446 }; 447 448 enum mlx4_en_port_flag { 449 MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */ 450 MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */ 451 }; 452 453 struct mlx4_en_port_state { 454 int link_state; 455 int link_speed; 456 int transceiver; 457 u32 flags; 458 }; 459 460 enum mlx4_en_mclist_act { 461 MCLIST_NONE, 462 MCLIST_REM, 463 MCLIST_ADD, 464 }; 465 466 struct mlx4_en_mc_list { 467 struct list_head list; 468 enum mlx4_en_mclist_act action; 469 u8 addr[ETH_ALEN]; 470 u64 reg_id; 471 u64 tunnel_reg_id; 472 }; 473 474 struct mlx4_en_frag_info { 475 u16 frag_size; 476 u16 frag_prefix_size; 477 u32 frag_stride; 478 enum dma_data_direction dma_dir; 479 u16 order; 480 u16 rx_headroom; 481 }; 482 483 #ifdef CONFIG_MLX4_EN_DCB 484 /* Minimal TC BW - setting to 0 will block traffic */ 485 #define MLX4_EN_BW_MIN 1 486 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */ 487 488 #define MLX4_EN_TC_ETS 7 489 490 enum dcb_pfc_type { 491 pfc_disabled = 0, 492 pfc_enabled_full, 493 pfc_enabled_tx, 494 pfc_enabled_rx 495 }; 496 497 struct mlx4_en_cee_config { 498 bool pfc_state; 499 enum dcb_pfc_type dcb_pfc[MLX4_EN_NUM_UP]; 500 }; 501 #endif 502 503 struct ethtool_flow_id { 504 struct list_head list; 505 struct ethtool_rx_flow_spec flow_spec; 506 u64 id; 507 }; 508 509 enum { 510 MLX4_EN_FLAG_PROMISC = (1 << 0), 511 MLX4_EN_FLAG_MC_PROMISC = (1 << 1), 512 /* whether we need to enable hardware loopback by putting dmac 513 * in Tx WQE 514 */ 515 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2), 516 /* whether we need to drop packets that hardware loopback-ed */ 517 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3), 518 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4), 519 MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP = (1 << 5), 520 #ifdef CONFIG_MLX4_EN_DCB 521 MLX4_EN_FLAG_DCB_ENABLED = (1 << 6), 522 #endif 523 }; 524 525 #define PORT_BEACON_MAX_LIMIT (65535) 526 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE) 527 #define MLX4_EN_MAC_HASH_IDX 5 528 529 struct mlx4_en_stats_bitmap { 530 DECLARE_BITMAP(bitmap, NUM_ALL_STATS); 531 struct mutex mutex; /* for mutual access to stats bitmap */ 532 }; 533 534 struct mlx4_en_priv { 535 struct mlx4_en_dev *mdev; 536 struct mlx4_en_port_profile *prof; 537 struct net_device *dev; 538 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 539 struct mlx4_en_port_state port_state; 540 spinlock_t stats_lock; 541 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES]; 542 /* To allow rules removal while port is going down */ 543 struct list_head ethtool_list; 544 545 unsigned long last_moder_packets[MAX_RX_RINGS]; 546 unsigned long last_moder_tx_packets; 547 unsigned long last_moder_bytes[MAX_RX_RINGS]; 548 unsigned long last_moder_jiffies; 549 int last_moder_time[MAX_RX_RINGS]; 550 u16 rx_usecs; 551 u16 rx_frames; 552 u16 tx_usecs; 553 u16 tx_frames; 554 u32 pkt_rate_low; 555 u16 rx_usecs_low; 556 u32 pkt_rate_high; 557 u16 rx_usecs_high; 558 u16 sample_interval; 559 u16 adaptive_rx_coal; 560 u32 msg_enable; 561 u32 loopback_ok; 562 u32 validate_loopback; 563 564 struct mlx4_hwq_resources res; 565 int link_state; 566 int last_link_state; 567 bool port_up; 568 int port; 569 int registered; 570 int allocated; 571 int stride; 572 unsigned char current_mac[ETH_ALEN + 2]; 573 int mac_index; 574 unsigned max_mtu; 575 int base_qpn; 576 int cqe_factor; 577 int cqe_size; 578 579 struct mlx4_en_rss_map rss_map; 580 __be32 ctrl_flags; 581 u32 flags; 582 u8 num_tx_rings_p_up; 583 u32 tx_work_limit; 584 u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES]; 585 u32 rx_ring_num; 586 u32 rx_skb_size; 587 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS]; 588 u16 num_frags; 589 u16 log_rx_info; 590 591 struct mlx4_en_tx_ring **tx_ring[MLX4_EN_NUM_TX_TYPES]; 592 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS]; 593 struct mlx4_en_cq **tx_cq[MLX4_EN_NUM_TX_TYPES]; 594 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS]; 595 struct mlx4_qp drop_qp; 596 struct work_struct rx_mode_task; 597 struct work_struct watchdog_task; 598 struct work_struct linkstate_task; 599 struct delayed_work stats_task; 600 struct delayed_work service_task; 601 struct work_struct vxlan_add_task; 602 struct work_struct vxlan_del_task; 603 struct mlx4_en_perf_stats pstats; 604 struct mlx4_en_pkt_stats pkstats; 605 struct mlx4_en_counter_stats pf_stats; 606 struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES]; 607 struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES]; 608 struct mlx4_en_flow_stats_rx rx_flowstats; 609 struct mlx4_en_flow_stats_tx tx_flowstats; 610 struct mlx4_en_port_stats port_stats; 611 struct mlx4_en_xdp_stats xdp_stats; 612 struct mlx4_en_stats_bitmap stats_bitmap; 613 struct list_head mc_list; 614 struct list_head curr_list; 615 u64 broadcast_id; 616 struct mlx4_en_stat_out_mbox hw_stats; 617 int vids[128]; 618 bool wol; 619 struct device *ddev; 620 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE]; 621 struct hwtstamp_config hwtstamp_config; 622 u32 counter_index; 623 624 #ifdef CONFIG_MLX4_EN_DCB 625 #define MLX4_EN_DCB_ENABLED 0x3 626 struct ieee_ets ets; 627 u16 maxrate[IEEE_8021QAZ_MAX_TCS]; 628 enum dcbnl_cndd_states cndd_state[IEEE_8021QAZ_MAX_TCS]; 629 struct mlx4_en_cee_config cee_config; 630 u8 dcbx_cap; 631 #endif 632 #ifdef CONFIG_RFS_ACCEL 633 spinlock_t filters_lock; 634 int last_filter_id; 635 struct list_head filters; 636 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT]; 637 #endif 638 u64 tunnel_reg_id; 639 __be16 vxlan_port; 640 641 u32 pflags; 642 u8 rss_key[MLX4_EN_RSS_KEY_SIZE]; 643 u8 rss_hash_fn; 644 }; 645 646 enum mlx4_en_wol { 647 MLX4_EN_WOL_MAGIC = (1ULL << 61), 648 MLX4_EN_WOL_ENABLED = (1ULL << 62), 649 }; 650 651 struct mlx4_mac_entry { 652 struct hlist_node hlist; 653 unsigned char mac[ETH_ALEN + 2]; 654 u64 reg_id; 655 struct rcu_head rcu; 656 }; 657 658 static inline struct mlx4_cqe *mlx4_en_get_cqe(void *buf, int idx, int cqe_sz) 659 { 660 return buf + idx * cqe_sz; 661 } 662 663 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63) 664 665 void mlx4_en_init_ptys2ethtool_map(void); 666 void mlx4_en_update_loopback_state(struct net_device *dev, 667 netdev_features_t features); 668 669 void mlx4_en_destroy_netdev(struct net_device *dev); 670 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, 671 struct mlx4_en_port_profile *prof); 672 673 int mlx4_en_start_port(struct net_device *dev); 674 void mlx4_en_stop_port(struct net_device *dev, int detach); 675 676 void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev, 677 struct mlx4_en_stats_bitmap *stats_bitmap, 678 u8 rx_ppp, u8 rx_pause, 679 u8 tx_ppp, u8 tx_pause); 680 681 int mlx4_en_try_alloc_resources(struct mlx4_en_priv *priv, 682 struct mlx4_en_priv *tmp, 683 struct mlx4_en_port_profile *prof, 684 bool carry_xdp_prog); 685 void mlx4_en_safe_replace_resources(struct mlx4_en_priv *priv, 686 struct mlx4_en_priv *tmp); 687 688 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq, 689 int entries, int ring, enum cq_type mode, int node); 690 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq); 691 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq, 692 int cq_idx); 693 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 694 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 695 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 696 697 void mlx4_en_tx_irq(struct mlx4_cq *mcq); 698 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, 699 void *accel_priv, select_queue_fallback_t fallback); 700 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev); 701 netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring, 702 struct mlx4_en_rx_alloc *frame, 703 struct net_device *dev, unsigned int length, 704 int tx_ind, int *doorbell_pending); 705 void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring); 706 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring, 707 struct mlx4_en_rx_alloc *frame); 708 709 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 710 struct mlx4_en_tx_ring **pring, 711 u32 size, u16 stride, 712 int node, int queue_index); 713 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 714 struct mlx4_en_tx_ring **pring); 715 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 716 struct mlx4_en_tx_ring *ring, 717 int cq, int user_prio); 718 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 719 struct mlx4_en_tx_ring *ring); 720 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev); 721 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv); 722 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 723 struct mlx4_en_rx_ring **pring, 724 u32 size, u16 stride, int node); 725 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 726 struct mlx4_en_rx_ring **pring, 727 u32 size, u16 stride); 728 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv); 729 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, 730 struct mlx4_en_rx_ring *ring); 731 int mlx4_en_process_rx_cq(struct net_device *dev, 732 struct mlx4_en_cq *cq, 733 int budget); 734 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget); 735 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget); 736 u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, 737 struct mlx4_en_tx_ring *ring, 738 int index, u8 owner, u64 timestamp, 739 int napi_mode); 740 u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv, 741 struct mlx4_en_tx_ring *ring, 742 int index, u8 owner, u64 timestamp, 743 int napi_mode); 744 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, 745 int is_tx, int rss, int qpn, int cqn, int user_prio, 746 struct mlx4_qp_context *context); 747 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event); 748 int mlx4_en_change_mcast_lb(struct mlx4_en_priv *priv, struct mlx4_qp *qp, 749 int loopback); 750 void mlx4_en_calc_rx_buf(struct net_device *dev); 751 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv); 752 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv); 753 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv); 754 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv); 755 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring); 756 void mlx4_en_rx_irq(struct mlx4_cq *mcq); 757 758 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 759 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv); 760 761 void mlx4_en_fold_software_stats(struct net_device *dev); 762 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset); 763 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port); 764 765 #ifdef CONFIG_MLX4_EN_DCB 766 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops; 767 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops; 768 #endif 769 770 int mlx4_en_setup_tc(struct net_device *dev, u8 up); 771 772 #ifdef CONFIG_RFS_ACCEL 773 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv); 774 #endif 775 776 #define MLX4_EN_NUM_SELF_TEST 5 777 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf); 778 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev); 779 780 #define DEV_FEATURE_CHANGED(dev, new_features, feature) \ 781 ((dev->features & feature) ^ (new_features & feature)) 782 783 int mlx4_en_reset_config(struct net_device *dev, 784 struct hwtstamp_config ts_config, 785 netdev_features_t new_features); 786 void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev, 787 struct mlx4_en_stats_bitmap *stats_bitmap, 788 u8 rx_ppp, u8 rx_pause, 789 u8 tx_ppp, u8 tx_pause); 790 int mlx4_en_netdev_event(struct notifier_block *this, 791 unsigned long event, void *ptr); 792 793 /* 794 * Functions for time stamping 795 */ 796 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe); 797 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev, 798 struct skb_shared_hwtstamps *hwts, 799 u64 timestamp); 800 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev); 801 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev); 802 803 /* Globals 804 */ 805 extern const struct ethtool_ops mlx4_en_ethtool_ops; 806 807 808 809 /* 810 * printk / logging functions 811 */ 812 813 __printf(3, 4) 814 void en_print(const char *level, const struct mlx4_en_priv *priv, 815 const char *format, ...); 816 817 #define en_dbg(mlevel, priv, format, ...) \ 818 do { \ 819 if (NETIF_MSG_##mlevel & (priv)->msg_enable) \ 820 en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__); \ 821 } while (0) 822 #define en_warn(priv, format, ...) \ 823 en_print(KERN_WARNING, priv, format, ##__VA_ARGS__) 824 #define en_err(priv, format, ...) \ 825 en_print(KERN_ERR, priv, format, ##__VA_ARGS__) 826 #define en_info(priv, format, ...) \ 827 en_print(KERN_INFO, priv, format, ##__VA_ARGS__) 828 829 #define mlx4_err(mdev, format, ...) \ 830 pr_err(DRV_NAME " %s: " format, \ 831 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 832 #define mlx4_info(mdev, format, ...) \ 833 pr_info(DRV_NAME " %s: " format, \ 834 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 835 #define mlx4_warn(mdev, format, ...) \ 836 pr_warn(DRV_NAME " %s: " format, \ 837 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 838 839 #endif 840