1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #ifndef _MLX4_EN_H_ 35 #define _MLX4_EN_H_ 36 37 #include <linux/bitops.h> 38 #include <linux/compiler.h> 39 #include <linux/list.h> 40 #include <linux/mutex.h> 41 #include <linux/netdevice.h> 42 #include <linux/if_vlan.h> 43 #include <linux/net_tstamp.h> 44 #ifdef CONFIG_MLX4_EN_DCB 45 #include <linux/dcbnl.h> 46 #endif 47 #include <linux/cpu_rmap.h> 48 #include <linux/ptp_clock_kernel.h> 49 50 #include <linux/mlx4/device.h> 51 #include <linux/mlx4/qp.h> 52 #include <linux/mlx4/cq.h> 53 #include <linux/mlx4/srq.h> 54 #include <linux/mlx4/doorbell.h> 55 #include <linux/mlx4/cmd.h> 56 57 #include "en_port.h" 58 #include "mlx4_stats.h" 59 60 #define DRV_NAME "mlx4_en" 61 #define DRV_VERSION "2.2-1" 62 #define DRV_RELDATE "Feb 2014" 63 64 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN) 65 66 /* 67 * Device constants 68 */ 69 70 71 #define MLX4_EN_PAGE_SHIFT 12 72 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT) 73 #define DEF_RX_RINGS 16 74 #define MAX_RX_RINGS 128 75 #define MIN_RX_RINGS 4 76 #define TXBB_SIZE 64 77 #define HEADROOM (2048 / TXBB_SIZE + 1) 78 #define STAMP_STRIDE 64 79 #define STAMP_DWORDS (STAMP_STRIDE / 4) 80 #define STAMP_SHIFT 31 81 #define STAMP_VAL 0x7fffffff 82 #define STATS_DELAY (HZ / 4) 83 #define SERVICE_TASK_DELAY (HZ / 4) 84 #define MAX_NUM_OF_FS_RULES 256 85 86 #define MLX4_EN_FILTER_HASH_SHIFT 4 87 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60 88 89 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */ 90 #define MAX_DESC_SIZE 512 91 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE) 92 93 /* 94 * OS related constants and tunables 95 */ 96 97 #define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1 98 #define MLX4_EN_PRIV_FLAGS_PHV 2 99 100 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ) 101 102 /* Use the maximum between 16384 and a single page */ 103 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384) 104 105 #define MLX4_EN_ALLOC_PREFER_ORDER PAGE_ALLOC_COSTLY_ORDER 106 107 /* Receive fragment sizes; we use at most 3 fragments (for 9600 byte MTU 108 * and 4K allocations) */ 109 enum { 110 FRAG_SZ0 = 1536 - NET_IP_ALIGN, 111 FRAG_SZ1 = 4096, 112 FRAG_SZ2 = 4096, 113 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE 114 }; 115 #define MLX4_EN_MAX_RX_FRAGS 4 116 117 /* Maximum ring sizes */ 118 #define MLX4_EN_MAX_TX_SIZE 8192 119 #define MLX4_EN_MAX_RX_SIZE 8192 120 121 /* Minimum ring size for our page-allocation scheme to work */ 122 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES) 123 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE) 124 125 #define MLX4_EN_SMALL_PKT_SIZE 64 126 #define MLX4_EN_MIN_TX_RING_P_UP 1 127 #define MLX4_EN_MAX_TX_RING_P_UP 32 128 #define MLX4_EN_NUM_UP 8 129 #define MLX4_EN_DEF_TX_RING_SIZE 512 130 #define MLX4_EN_DEF_RX_RING_SIZE 1024 131 #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \ 132 MLX4_EN_NUM_UP) 133 134 #define MLX4_EN_DEFAULT_TX_WORK 256 135 136 /* Target number of packets to coalesce with interrupt moderation */ 137 #define MLX4_EN_RX_COAL_TARGET 44 138 #define MLX4_EN_RX_COAL_TIME 0x10 139 140 #define MLX4_EN_TX_COAL_PKTS 16 141 #define MLX4_EN_TX_COAL_TIME 0x10 142 143 #define MLX4_EN_RX_RATE_LOW 400000 144 #define MLX4_EN_RX_COAL_TIME_LOW 0 145 #define MLX4_EN_RX_RATE_HIGH 450000 146 #define MLX4_EN_RX_COAL_TIME_HIGH 128 147 #define MLX4_EN_RX_SIZE_THRESH 1024 148 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH) 149 #define MLX4_EN_SAMPLE_INTERVAL 0 150 #define MLX4_EN_AVG_PKT_SMALL 256 151 152 #define MLX4_EN_AUTO_CONF 0xffff 153 154 #define MLX4_EN_DEF_RX_PAUSE 1 155 #define MLX4_EN_DEF_TX_PAUSE 1 156 157 /* Interval between successive polls in the Tx routine when polling is used 158 instead of interrupts (in per-core Tx rings) - should be power of 2 */ 159 #define MLX4_EN_TX_POLL_MODER 16 160 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4) 161 162 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN) 163 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN) 164 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN) 165 166 #define MLX4_EN_MIN_MTU 46 167 #define ETH_BCAST 0xffffffffffffULL 168 169 #define MLX4_EN_LOOPBACK_RETRIES 5 170 #define MLX4_EN_LOOPBACK_TIMEOUT 100 171 172 #ifdef MLX4_EN_PERF_STAT 173 /* Number of samples to 'average' */ 174 #define AVG_SIZE 128 175 #define AVG_FACTOR 1024 176 177 #define INC_PERF_COUNTER(cnt) (++(cnt)) 178 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add)) 179 #define AVG_PERF_COUNTER(cnt, sample) \ 180 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE) 181 #define GET_PERF_COUNTER(cnt) (cnt) 182 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR) 183 184 #else 185 186 #define INC_PERF_COUNTER(cnt) do {} while (0) 187 #define ADD_PERF_COUNTER(cnt, add) do {} while (0) 188 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0) 189 #define GET_PERF_COUNTER(cnt) (0) 190 #define GET_AVG_PERF_COUNTER(cnt) (0) 191 #endif /* MLX4_EN_PERF_STAT */ 192 193 /* Constants for TX flow */ 194 enum { 195 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */ 196 MAX_BF = 256, 197 MIN_PKT_LEN = 17, 198 }; 199 200 /* 201 * Configurables 202 */ 203 204 enum cq_type { 205 RX = 0, 206 TX = 1, 207 }; 208 209 210 /* 211 * Useful macros 212 */ 213 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x)) 214 #define XNOR(x, y) (!(x) == !(y)) 215 216 217 struct mlx4_en_tx_info { 218 struct sk_buff *skb; 219 dma_addr_t map0_dma; 220 u32 map0_byte_count; 221 u32 nr_txbb; 222 u32 nr_bytes; 223 u8 linear; 224 u8 data_offset; 225 u8 inl; 226 u8 ts_requested; 227 u8 nr_maps; 228 } ____cacheline_aligned_in_smp; 229 230 231 #define MLX4_EN_BIT_DESC_OWN 0x80000000 232 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg) 233 #define MLX4_EN_MEMTYPE_PAD 0x100 234 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg) 235 236 237 struct mlx4_en_tx_desc { 238 struct mlx4_wqe_ctrl_seg ctrl; 239 union { 240 struct mlx4_wqe_data_seg data; /* at least one data segment */ 241 struct mlx4_wqe_lso_seg lso; 242 struct mlx4_wqe_inline_seg inl; 243 }; 244 }; 245 246 #define MLX4_EN_USE_SRQ 0x01000000 247 248 #define MLX4_EN_CX3_LOW_ID 0x1000 249 #define MLX4_EN_CX3_HIGH_ID 0x1005 250 251 struct mlx4_en_rx_alloc { 252 struct page *page; 253 dma_addr_t dma; 254 u32 page_offset; 255 u32 page_size; 256 }; 257 258 struct mlx4_en_tx_ring { 259 /* cache line used and dirtied in tx completion 260 * (mlx4_en_free_tx_buf()) 261 */ 262 u32 last_nr_txbb; 263 u32 cons; 264 unsigned long wake_queue; 265 266 /* cache line used and dirtied in mlx4_en_xmit() */ 267 u32 prod ____cacheline_aligned_in_smp; 268 unsigned long bytes; 269 unsigned long packets; 270 unsigned long tx_csum; 271 unsigned long tso_packets; 272 unsigned long xmit_more; 273 struct mlx4_bf bf; 274 unsigned long queue_stopped; 275 276 /* Following part should be mostly read */ 277 cpumask_t affinity_mask; 278 struct mlx4_qp qp; 279 struct mlx4_hwq_resources wqres; 280 u32 size; /* number of TXBBs */ 281 u32 size_mask; 282 u16 stride; 283 u32 full_size; 284 u16 cqn; /* index of port CQ associated with this ring */ 285 u32 buf_size; 286 __be32 doorbell_qpn; 287 __be32 mr_key; 288 void *buf; 289 struct mlx4_en_tx_info *tx_info; 290 u8 *bounce_buf; 291 struct mlx4_qp_context context; 292 int qpn; 293 enum mlx4_qp_state qp_state; 294 u8 queue_index; 295 bool bf_enabled; 296 bool bf_alloced; 297 struct netdev_queue *tx_queue; 298 int hwtstamp_tx_type; 299 } ____cacheline_aligned_in_smp; 300 301 struct mlx4_en_rx_desc { 302 /* actual number of entries depends on rx ring stride */ 303 struct mlx4_wqe_data_seg data[0]; 304 }; 305 306 struct mlx4_en_rx_ring { 307 struct mlx4_hwq_resources wqres; 308 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS]; 309 u32 size ; /* number of Rx descs*/ 310 u32 actual_size; 311 u32 size_mask; 312 u16 stride; 313 u16 log_stride; 314 u16 cqn; /* index of port CQ associated with this ring */ 315 u32 prod; 316 u32 cons; 317 u32 buf_size; 318 u8 fcs_del; 319 void *buf; 320 void *rx_info; 321 unsigned long bytes; 322 unsigned long packets; 323 unsigned long csum_ok; 324 unsigned long csum_none; 325 unsigned long csum_complete; 326 unsigned long dropped; 327 int hwtstamp_rx_filter; 328 cpumask_var_t affinity_mask; 329 }; 330 331 struct mlx4_en_cq { 332 struct mlx4_cq mcq; 333 struct mlx4_hwq_resources wqres; 334 int ring; 335 struct net_device *dev; 336 struct napi_struct napi; 337 int size; 338 int buf_size; 339 int vector; 340 enum cq_type is_tx; 341 u16 moder_time; 342 u16 moder_cnt; 343 struct mlx4_cqe *buf; 344 #define MLX4_EN_OPCODE_ERROR 0x1e 345 346 struct irq_desc *irq_desc; 347 }; 348 349 struct mlx4_en_port_profile { 350 u32 flags; 351 u32 tx_ring_num; 352 u32 rx_ring_num; 353 u32 tx_ring_size; 354 u32 rx_ring_size; 355 u8 rx_pause; 356 u8 rx_ppp; 357 u8 tx_pause; 358 u8 tx_ppp; 359 int rss_rings; 360 int inline_thold; 361 }; 362 363 struct mlx4_en_profile { 364 int udp_rss; 365 u8 rss_mask; 366 u32 active_ports; 367 u32 small_pkt_int; 368 u8 no_reset; 369 u8 num_tx_rings_p_up; 370 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1]; 371 }; 372 373 struct mlx4_en_dev { 374 struct mlx4_dev *dev; 375 struct pci_dev *pdev; 376 struct mutex state_lock; 377 struct net_device *pndev[MLX4_MAX_PORTS + 1]; 378 struct net_device *upper[MLX4_MAX_PORTS + 1]; 379 u32 port_cnt; 380 bool device_up; 381 struct mlx4_en_profile profile; 382 u32 LSO_support; 383 struct workqueue_struct *workqueue; 384 struct device *dma_device; 385 void __iomem *uar_map; 386 struct mlx4_uar priv_uar; 387 struct mlx4_mr mr; 388 u32 priv_pdn; 389 spinlock_t uar_lock; 390 u8 mac_removed[MLX4_MAX_PORTS + 1]; 391 rwlock_t clock_lock; 392 u32 nominal_c_mult; 393 struct cyclecounter cycles; 394 struct timecounter clock; 395 unsigned long last_overflow_check; 396 unsigned long overflow_period; 397 struct ptp_clock *ptp_clock; 398 struct ptp_clock_info ptp_clock_info; 399 struct notifier_block nb; 400 }; 401 402 403 struct mlx4_en_rss_map { 404 int base_qpn; 405 struct mlx4_qp qps[MAX_RX_RINGS]; 406 enum mlx4_qp_state state[MAX_RX_RINGS]; 407 struct mlx4_qp indir_qp; 408 enum mlx4_qp_state indir_state; 409 }; 410 411 enum mlx4_en_port_flag { 412 MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */ 413 MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */ 414 }; 415 416 struct mlx4_en_port_state { 417 int link_state; 418 int link_speed; 419 int transceiver; 420 u32 flags; 421 }; 422 423 enum mlx4_en_mclist_act { 424 MCLIST_NONE, 425 MCLIST_REM, 426 MCLIST_ADD, 427 }; 428 429 struct mlx4_en_mc_list { 430 struct list_head list; 431 enum mlx4_en_mclist_act action; 432 u8 addr[ETH_ALEN]; 433 u64 reg_id; 434 u64 tunnel_reg_id; 435 }; 436 437 struct mlx4_en_frag_info { 438 u16 frag_size; 439 u16 frag_prefix_size; 440 u16 frag_stride; 441 }; 442 443 #ifdef CONFIG_MLX4_EN_DCB 444 /* Minimal TC BW - setting to 0 will block traffic */ 445 #define MLX4_EN_BW_MIN 1 446 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */ 447 448 #define MLX4_EN_TC_ETS 7 449 450 #endif 451 452 struct ethtool_flow_id { 453 struct list_head list; 454 struct ethtool_rx_flow_spec flow_spec; 455 u64 id; 456 }; 457 458 enum { 459 MLX4_EN_FLAG_PROMISC = (1 << 0), 460 MLX4_EN_FLAG_MC_PROMISC = (1 << 1), 461 /* whether we need to enable hardware loopback by putting dmac 462 * in Tx WQE 463 */ 464 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2), 465 /* whether we need to drop packets that hardware loopback-ed */ 466 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3), 467 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4), 468 MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP = (1 << 5), 469 }; 470 471 #define PORT_BEACON_MAX_LIMIT (65535) 472 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE) 473 #define MLX4_EN_MAC_HASH_IDX 5 474 475 struct mlx4_en_stats_bitmap { 476 DECLARE_BITMAP(bitmap, NUM_ALL_STATS); 477 struct mutex mutex; /* for mutual access to stats bitmap */ 478 }; 479 480 struct mlx4_en_priv { 481 struct mlx4_en_dev *mdev; 482 struct mlx4_en_port_profile *prof; 483 struct net_device *dev; 484 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 485 struct net_device_stats stats; 486 struct net_device_stats ret_stats; 487 struct mlx4_en_port_state port_state; 488 spinlock_t stats_lock; 489 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES]; 490 /* To allow rules removal while port is going down */ 491 struct list_head ethtool_list; 492 493 unsigned long last_moder_packets[MAX_RX_RINGS]; 494 unsigned long last_moder_tx_packets; 495 unsigned long last_moder_bytes[MAX_RX_RINGS]; 496 unsigned long last_moder_jiffies; 497 int last_moder_time[MAX_RX_RINGS]; 498 u16 rx_usecs; 499 u16 rx_frames; 500 u16 tx_usecs; 501 u16 tx_frames; 502 u32 pkt_rate_low; 503 u16 rx_usecs_low; 504 u32 pkt_rate_high; 505 u16 rx_usecs_high; 506 u16 sample_interval; 507 u16 adaptive_rx_coal; 508 u32 msg_enable; 509 u32 loopback_ok; 510 u32 validate_loopback; 511 512 struct mlx4_hwq_resources res; 513 int link_state; 514 int last_link_state; 515 bool port_up; 516 int port; 517 int registered; 518 int allocated; 519 int stride; 520 unsigned char current_mac[ETH_ALEN + 2]; 521 int mac_index; 522 unsigned max_mtu; 523 int base_qpn; 524 int cqe_factor; 525 int cqe_size; 526 527 struct mlx4_en_rss_map rss_map; 528 __be32 ctrl_flags; 529 u32 flags; 530 u8 num_tx_rings_p_up; 531 u32 tx_work_limit; 532 u32 tx_ring_num; 533 u32 rx_ring_num; 534 u32 rx_skb_size; 535 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS]; 536 u16 num_frags; 537 u16 log_rx_info; 538 539 struct mlx4_en_tx_ring **tx_ring; 540 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS]; 541 struct mlx4_en_cq **tx_cq; 542 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS]; 543 struct mlx4_qp drop_qp; 544 struct work_struct rx_mode_task; 545 struct work_struct watchdog_task; 546 struct work_struct linkstate_task; 547 struct delayed_work stats_task; 548 struct delayed_work service_task; 549 #ifdef CONFIG_MLX4_EN_VXLAN 550 struct work_struct vxlan_add_task; 551 struct work_struct vxlan_del_task; 552 #endif 553 struct mlx4_en_perf_stats pstats; 554 struct mlx4_en_pkt_stats pkstats; 555 struct mlx4_en_counter_stats pf_stats; 556 struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES]; 557 struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES]; 558 struct mlx4_en_flow_stats_rx rx_flowstats; 559 struct mlx4_en_flow_stats_tx tx_flowstats; 560 struct mlx4_en_port_stats port_stats; 561 struct mlx4_en_stats_bitmap stats_bitmap; 562 struct list_head mc_list; 563 struct list_head curr_list; 564 u64 broadcast_id; 565 struct mlx4_en_stat_out_mbox hw_stats; 566 int vids[128]; 567 bool wol; 568 struct device *ddev; 569 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE]; 570 struct hwtstamp_config hwtstamp_config; 571 u32 counter_index; 572 573 #ifdef CONFIG_MLX4_EN_DCB 574 struct ieee_ets ets; 575 u16 maxrate[IEEE_8021QAZ_MAX_TCS]; 576 enum dcbnl_cndd_states cndd_state[IEEE_8021QAZ_MAX_TCS]; 577 #endif 578 #ifdef CONFIG_RFS_ACCEL 579 spinlock_t filters_lock; 580 int last_filter_id; 581 struct list_head filters; 582 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT]; 583 #endif 584 u64 tunnel_reg_id; 585 __be16 vxlan_port; 586 587 u32 pflags; 588 u8 rss_key[MLX4_EN_RSS_KEY_SIZE]; 589 u8 rss_hash_fn; 590 }; 591 592 enum mlx4_en_wol { 593 MLX4_EN_WOL_MAGIC = (1ULL << 61), 594 MLX4_EN_WOL_ENABLED = (1ULL << 62), 595 }; 596 597 struct mlx4_mac_entry { 598 struct hlist_node hlist; 599 unsigned char mac[ETH_ALEN + 2]; 600 u64 reg_id; 601 struct rcu_head rcu; 602 }; 603 604 static inline struct mlx4_cqe *mlx4_en_get_cqe(void *buf, int idx, int cqe_sz) 605 { 606 return buf + idx * cqe_sz; 607 } 608 609 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63) 610 611 void mlx4_en_init_ptys2ethtool_map(void); 612 void mlx4_en_update_loopback_state(struct net_device *dev, 613 netdev_features_t features); 614 615 void mlx4_en_destroy_netdev(struct net_device *dev); 616 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, 617 struct mlx4_en_port_profile *prof); 618 619 int mlx4_en_start_port(struct net_device *dev); 620 void mlx4_en_stop_port(struct net_device *dev, int detach); 621 622 void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev, 623 struct mlx4_en_stats_bitmap *stats_bitmap, 624 u8 rx_ppp, u8 rx_pause, 625 u8 tx_ppp, u8 tx_pause); 626 627 void mlx4_en_free_resources(struct mlx4_en_priv *priv); 628 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv); 629 630 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq, 631 int entries, int ring, enum cq_type mode, int node); 632 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq); 633 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq, 634 int cq_idx); 635 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 636 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 637 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 638 639 void mlx4_en_tx_irq(struct mlx4_cq *mcq); 640 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, 641 void *accel_priv, select_queue_fallback_t fallback); 642 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev); 643 644 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 645 struct mlx4_en_tx_ring **pring, 646 u32 size, u16 stride, 647 int node, int queue_index); 648 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 649 struct mlx4_en_tx_ring **pring); 650 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 651 struct mlx4_en_tx_ring *ring, 652 int cq, int user_prio); 653 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 654 struct mlx4_en_tx_ring *ring); 655 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev); 656 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv); 657 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 658 struct mlx4_en_rx_ring **pring, 659 u32 size, u16 stride, int node); 660 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 661 struct mlx4_en_rx_ring **pring, 662 u32 size, u16 stride); 663 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv); 664 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, 665 struct mlx4_en_rx_ring *ring); 666 int mlx4_en_process_rx_cq(struct net_device *dev, 667 struct mlx4_en_cq *cq, 668 int budget); 669 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget); 670 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget); 671 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, 672 int is_tx, int rss, int qpn, int cqn, int user_prio, 673 struct mlx4_qp_context *context); 674 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event); 675 int mlx4_en_change_mcast_lb(struct mlx4_en_priv *priv, struct mlx4_qp *qp, 676 int loopback); 677 void mlx4_en_calc_rx_buf(struct net_device *dev); 678 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv); 679 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv); 680 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv); 681 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv); 682 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring); 683 void mlx4_en_rx_irq(struct mlx4_cq *mcq); 684 685 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 686 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv); 687 688 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset); 689 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port); 690 691 #ifdef CONFIG_MLX4_EN_DCB 692 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops; 693 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops; 694 #endif 695 696 int mlx4_en_setup_tc(struct net_device *dev, u8 up); 697 698 #ifdef CONFIG_RFS_ACCEL 699 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv); 700 #endif 701 702 #define MLX4_EN_NUM_SELF_TEST 5 703 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf); 704 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev); 705 706 #define DEV_FEATURE_CHANGED(dev, new_features, feature) \ 707 ((dev->features & feature) ^ (new_features & feature)) 708 709 int mlx4_en_reset_config(struct net_device *dev, 710 struct hwtstamp_config ts_config, 711 netdev_features_t new_features); 712 void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev, 713 struct mlx4_en_stats_bitmap *stats_bitmap, 714 u8 rx_ppp, u8 rx_pause, 715 u8 tx_ppp, u8 tx_pause); 716 int mlx4_en_netdev_event(struct notifier_block *this, 717 unsigned long event, void *ptr); 718 719 /* 720 * Functions for time stamping 721 */ 722 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe); 723 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev, 724 struct skb_shared_hwtstamps *hwts, 725 u64 timestamp); 726 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev); 727 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev); 728 729 /* Globals 730 */ 731 extern const struct ethtool_ops mlx4_en_ethtool_ops; 732 733 734 735 /* 736 * printk / logging functions 737 */ 738 739 __printf(3, 4) 740 void en_print(const char *level, const struct mlx4_en_priv *priv, 741 const char *format, ...); 742 743 #define en_dbg(mlevel, priv, format, ...) \ 744 do { \ 745 if (NETIF_MSG_##mlevel & (priv)->msg_enable) \ 746 en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__); \ 747 } while (0) 748 #define en_warn(priv, format, ...) \ 749 en_print(KERN_WARNING, priv, format, ##__VA_ARGS__) 750 #define en_err(priv, format, ...) \ 751 en_print(KERN_ERR, priv, format, ##__VA_ARGS__) 752 #define en_info(priv, format, ...) \ 753 en_print(KERN_INFO, priv, format, ##__VA_ARGS__) 754 755 #define mlx4_err(mdev, format, ...) \ 756 pr_err(DRV_NAME " %s: " format, \ 757 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 758 #define mlx4_info(mdev, format, ...) \ 759 pr_info(DRV_NAME " %s: " format, \ 760 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 761 #define mlx4_warn(mdev, format, ...) \ 762 pr_warn(DRV_NAME " %s: " format, \ 763 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 764 765 #endif 766