1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #ifndef _MLX4_EN_H_ 35 #define _MLX4_EN_H_ 36 37 #include <linux/bitops.h> 38 #include <linux/compiler.h> 39 #include <linux/list.h> 40 #include <linux/mutex.h> 41 #include <linux/netdevice.h> 42 #include <linux/if_vlan.h> 43 44 #include <linux/mlx4/device.h> 45 #include <linux/mlx4/qp.h> 46 #include <linux/mlx4/cq.h> 47 #include <linux/mlx4/srq.h> 48 #include <linux/mlx4/doorbell.h> 49 #include <linux/mlx4/cmd.h> 50 51 #include "en_port.h" 52 53 #define DRV_NAME "mlx4_en" 54 #define DRV_VERSION "2.0" 55 #define DRV_RELDATE "Dec 2011" 56 57 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN) 58 59 /* 60 * Device constants 61 */ 62 63 64 #define MLX4_EN_PAGE_SHIFT 12 65 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT) 66 #define MAX_RX_RINGS 16 67 #define MIN_RX_RINGS 4 68 #define TXBB_SIZE 64 69 #define HEADROOM (2048 / TXBB_SIZE + 1) 70 #define STAMP_STRIDE 64 71 #define STAMP_DWORDS (STAMP_STRIDE / 4) 72 #define STAMP_SHIFT 31 73 #define STAMP_VAL 0x7fffffff 74 #define STATS_DELAY (HZ / 4) 75 76 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */ 77 #define MAX_DESC_SIZE 512 78 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE) 79 80 /* 81 * OS related constants and tunables 82 */ 83 84 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ) 85 86 /* Use the maximum between 16384 and a single page */ 87 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384) 88 #define MLX4_EN_ALLOC_ORDER get_order(MLX4_EN_ALLOC_SIZE) 89 90 #define MLX4_EN_MAX_LRO_DESCRIPTORS 32 91 92 /* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU 93 * and 4K allocations) */ 94 enum { 95 FRAG_SZ0 = 512 - NET_IP_ALIGN, 96 FRAG_SZ1 = 1024, 97 FRAG_SZ2 = 4096, 98 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE 99 }; 100 #define MLX4_EN_MAX_RX_FRAGS 4 101 102 /* Maximum ring sizes */ 103 #define MLX4_EN_MAX_TX_SIZE 8192 104 #define MLX4_EN_MAX_RX_SIZE 8192 105 106 /* Minimum ring size for our page-allocation sceme to work */ 107 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES) 108 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE) 109 110 #define MLX4_EN_SMALL_PKT_SIZE 64 111 #define MLX4_EN_NUM_TX_RINGS 8 112 #define MLX4_EN_NUM_PPP_RINGS 8 113 #define MAX_TX_RINGS (MLX4_EN_NUM_TX_RINGS + MLX4_EN_NUM_PPP_RINGS) 114 #define MLX4_EN_DEF_TX_RING_SIZE 512 115 #define MLX4_EN_DEF_RX_RING_SIZE 1024 116 117 /* Target number of packets to coalesce with interrupt moderation */ 118 #define MLX4_EN_RX_COAL_TARGET 44 119 #define MLX4_EN_RX_COAL_TIME 0x10 120 121 #define MLX4_EN_TX_COAL_PKTS 5 122 #define MLX4_EN_TX_COAL_TIME 0x80 123 124 #define MLX4_EN_RX_RATE_LOW 400000 125 #define MLX4_EN_RX_COAL_TIME_LOW 0 126 #define MLX4_EN_RX_RATE_HIGH 450000 127 #define MLX4_EN_RX_COAL_TIME_HIGH 128 128 #define MLX4_EN_RX_SIZE_THRESH 1024 129 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH) 130 #define MLX4_EN_SAMPLE_INTERVAL 0 131 #define MLX4_EN_AVG_PKT_SMALL 256 132 133 #define MLX4_EN_AUTO_CONF 0xffff 134 135 #define MLX4_EN_DEF_RX_PAUSE 1 136 #define MLX4_EN_DEF_TX_PAUSE 1 137 138 /* Interval between successive polls in the Tx routine when polling is used 139 instead of interrupts (in per-core Tx rings) - should be power of 2 */ 140 #define MLX4_EN_TX_POLL_MODER 16 141 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4) 142 143 #define ETH_LLC_SNAP_SIZE 8 144 145 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN) 146 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN) 147 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN) 148 149 #define MLX4_EN_MIN_MTU 46 150 #define ETH_BCAST 0xffffffffffffULL 151 152 #define MLX4_EN_LOOPBACK_RETRIES 5 153 #define MLX4_EN_LOOPBACK_TIMEOUT 100 154 155 #ifdef MLX4_EN_PERF_STAT 156 /* Number of samples to 'average' */ 157 #define AVG_SIZE 128 158 #define AVG_FACTOR 1024 159 #define NUM_PERF_STATS NUM_PERF_COUNTERS 160 161 #define INC_PERF_COUNTER(cnt) (++(cnt)) 162 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add)) 163 #define AVG_PERF_COUNTER(cnt, sample) \ 164 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE) 165 #define GET_PERF_COUNTER(cnt) (cnt) 166 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR) 167 168 #else 169 170 #define NUM_PERF_STATS 0 171 #define INC_PERF_COUNTER(cnt) do {} while (0) 172 #define ADD_PERF_COUNTER(cnt, add) do {} while (0) 173 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0) 174 #define GET_PERF_COUNTER(cnt) (0) 175 #define GET_AVG_PERF_COUNTER(cnt) (0) 176 #endif /* MLX4_EN_PERF_STAT */ 177 178 /* 179 * Configurables 180 */ 181 182 enum cq_type { 183 RX = 0, 184 TX = 1, 185 }; 186 187 188 /* 189 * Useful macros 190 */ 191 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x)) 192 #define XNOR(x, y) (!(x) == !(y)) 193 #define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL || addr == 0x0) 194 195 196 struct mlx4_en_tx_info { 197 struct sk_buff *skb; 198 u32 nr_txbb; 199 u8 linear; 200 u8 data_offset; 201 u8 inl; 202 }; 203 204 205 #define MLX4_EN_BIT_DESC_OWN 0x80000000 206 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg) 207 #define MLX4_EN_MEMTYPE_PAD 0x100 208 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg) 209 210 211 struct mlx4_en_tx_desc { 212 struct mlx4_wqe_ctrl_seg ctrl; 213 union { 214 struct mlx4_wqe_data_seg data; /* at least one data segment */ 215 struct mlx4_wqe_lso_seg lso; 216 struct mlx4_wqe_inline_seg inl; 217 }; 218 }; 219 220 #define MLX4_EN_USE_SRQ 0x01000000 221 222 #define MLX4_EN_CX3_LOW_ID 0x1000 223 #define MLX4_EN_CX3_HIGH_ID 0x1005 224 225 struct mlx4_en_rx_alloc { 226 struct page *page; 227 u16 offset; 228 }; 229 230 struct mlx4_en_tx_ring { 231 struct mlx4_hwq_resources wqres; 232 u32 size ; /* number of TXBBs */ 233 u32 size_mask; 234 u16 stride; 235 u16 cqn; /* index of port CQ associated with this ring */ 236 u32 prod; 237 u32 cons; 238 u32 buf_size; 239 u32 doorbell_qpn; 240 void *buf; 241 u16 poll_cnt; 242 int blocked; 243 struct mlx4_en_tx_info *tx_info; 244 u8 *bounce_buf; 245 u32 last_nr_txbb; 246 struct mlx4_qp qp; 247 struct mlx4_qp_context context; 248 int qpn; 249 enum mlx4_qp_state qp_state; 250 struct mlx4_srq dummy; 251 unsigned long bytes; 252 unsigned long packets; 253 unsigned long tx_csum; 254 spinlock_t comp_lock; 255 struct mlx4_bf bf; 256 bool bf_enabled; 257 }; 258 259 struct mlx4_en_rx_desc { 260 /* actual number of entries depends on rx ring stride */ 261 struct mlx4_wqe_data_seg data[0]; 262 }; 263 264 struct mlx4_en_rx_ring { 265 struct mlx4_hwq_resources wqres; 266 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS]; 267 u32 size ; /* number of Rx descs*/ 268 u32 actual_size; 269 u32 size_mask; 270 u16 stride; 271 u16 log_stride; 272 u16 cqn; /* index of port CQ associated with this ring */ 273 u32 prod; 274 u32 cons; 275 u32 buf_size; 276 u8 fcs_del; 277 void *buf; 278 void *rx_info; 279 unsigned long bytes; 280 unsigned long packets; 281 unsigned long csum_ok; 282 unsigned long csum_none; 283 }; 284 285 286 static inline int mlx4_en_can_lro(__be16 status) 287 { 288 return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 | 289 MLX4_CQE_STATUS_IPV4F | 290 MLX4_CQE_STATUS_IPV6 | 291 MLX4_CQE_STATUS_IPV4OPT | 292 MLX4_CQE_STATUS_TCP | 293 MLX4_CQE_STATUS_UDP | 294 MLX4_CQE_STATUS_IPOK)) == 295 cpu_to_be16(MLX4_CQE_STATUS_IPV4 | 296 MLX4_CQE_STATUS_IPOK | 297 MLX4_CQE_STATUS_TCP); 298 } 299 300 struct mlx4_en_cq { 301 struct mlx4_cq mcq; 302 struct mlx4_hwq_resources wqres; 303 int ring; 304 spinlock_t lock; 305 struct net_device *dev; 306 struct napi_struct napi; 307 /* Per-core Tx cq processing support */ 308 struct timer_list timer; 309 int size; 310 int buf_size; 311 unsigned vector; 312 enum cq_type is_tx; 313 u16 moder_time; 314 u16 moder_cnt; 315 struct mlx4_cqe *buf; 316 #define MLX4_EN_OPCODE_ERROR 0x1e 317 }; 318 319 struct mlx4_en_port_profile { 320 u32 flags; 321 u32 tx_ring_num; 322 u32 rx_ring_num; 323 u32 tx_ring_size; 324 u32 rx_ring_size; 325 u8 rx_pause; 326 u8 rx_ppp; 327 u8 tx_pause; 328 u8 tx_ppp; 329 int rss_rings; 330 }; 331 332 struct mlx4_en_profile { 333 int rss_xor; 334 int udp_rss; 335 u8 rss_mask; 336 u32 active_ports; 337 u32 small_pkt_int; 338 u8 no_reset; 339 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1]; 340 }; 341 342 struct mlx4_en_dev { 343 struct mlx4_dev *dev; 344 struct pci_dev *pdev; 345 struct mutex state_lock; 346 struct net_device *pndev[MLX4_MAX_PORTS + 1]; 347 u32 port_cnt; 348 bool device_up; 349 struct mlx4_en_profile profile; 350 u32 LSO_support; 351 struct workqueue_struct *workqueue; 352 struct device *dma_device; 353 void __iomem *uar_map; 354 struct mlx4_uar priv_uar; 355 struct mlx4_mr mr; 356 u32 priv_pdn; 357 spinlock_t uar_lock; 358 u8 mac_removed[MLX4_MAX_PORTS + 1]; 359 }; 360 361 362 struct mlx4_en_rss_map { 363 int base_qpn; 364 struct mlx4_qp qps[MAX_RX_RINGS]; 365 enum mlx4_qp_state state[MAX_RX_RINGS]; 366 struct mlx4_qp indir_qp; 367 enum mlx4_qp_state indir_state; 368 }; 369 370 struct mlx4_en_port_state { 371 int link_state; 372 int link_speed; 373 int transciver; 374 }; 375 376 struct mlx4_en_pkt_stats { 377 unsigned long broadcast; 378 unsigned long rx_prio[8]; 379 unsigned long tx_prio[8]; 380 #define NUM_PKT_STATS 17 381 }; 382 383 struct mlx4_en_port_stats { 384 unsigned long tso_packets; 385 unsigned long queue_stopped; 386 unsigned long wake_queue; 387 unsigned long tx_timeout; 388 unsigned long rx_alloc_failed; 389 unsigned long rx_chksum_good; 390 unsigned long rx_chksum_none; 391 unsigned long tx_chksum_offload; 392 #define NUM_PORT_STATS 8 393 }; 394 395 struct mlx4_en_perf_stats { 396 u32 tx_poll; 397 u64 tx_pktsz_avg; 398 u32 inflight_avg; 399 u16 tx_coal_avg; 400 u16 rx_coal_avg; 401 u32 napi_quota; 402 #define NUM_PERF_COUNTERS 6 403 }; 404 405 struct mlx4_en_frag_info { 406 u16 frag_size; 407 u16 frag_prefix_size; 408 u16 frag_stride; 409 u16 frag_align; 410 u16 last_offset; 411 412 }; 413 414 struct mlx4_en_priv { 415 struct mlx4_en_dev *mdev; 416 struct mlx4_en_port_profile *prof; 417 struct net_device *dev; 418 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 419 struct net_device_stats stats; 420 struct net_device_stats ret_stats; 421 struct mlx4_en_port_state port_state; 422 spinlock_t stats_lock; 423 424 unsigned long last_moder_packets[MAX_RX_RINGS]; 425 unsigned long last_moder_tx_packets; 426 unsigned long last_moder_bytes[MAX_RX_RINGS]; 427 unsigned long last_moder_jiffies; 428 int last_moder_time[MAX_RX_RINGS]; 429 u16 rx_usecs; 430 u16 rx_frames; 431 u16 tx_usecs; 432 u16 tx_frames; 433 u32 pkt_rate_low; 434 u16 rx_usecs_low; 435 u32 pkt_rate_high; 436 u16 rx_usecs_high; 437 u16 sample_interval; 438 u16 adaptive_rx_coal; 439 u32 msg_enable; 440 u32 loopback_ok; 441 u32 validate_loopback; 442 443 struct mlx4_hwq_resources res; 444 int link_state; 445 int last_link_state; 446 bool port_up; 447 int port; 448 int registered; 449 int allocated; 450 int stride; 451 u64 mac; 452 int mac_index; 453 unsigned max_mtu; 454 int base_qpn; 455 456 struct mlx4_en_rss_map rss_map; 457 __be32 ctrl_flags; 458 u32 flags; 459 #define MLX4_EN_FLAG_PROMISC 0x1 460 #define MLX4_EN_FLAG_MC_PROMISC 0x2 461 u32 tx_ring_num; 462 u32 rx_ring_num; 463 u32 rx_skb_size; 464 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS]; 465 u16 num_frags; 466 u16 log_rx_info; 467 468 struct mlx4_en_tx_ring tx_ring[MAX_TX_RINGS]; 469 struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS]; 470 struct mlx4_en_cq tx_cq[MAX_TX_RINGS]; 471 struct mlx4_en_cq rx_cq[MAX_RX_RINGS]; 472 struct work_struct mcast_task; 473 struct work_struct mac_task; 474 struct work_struct watchdog_task; 475 struct work_struct linkstate_task; 476 struct delayed_work stats_task; 477 struct mlx4_en_perf_stats pstats; 478 struct mlx4_en_pkt_stats pkstats; 479 struct mlx4_en_port_stats port_stats; 480 u64 stats_bitmap; 481 char *mc_addrs; 482 int mc_addrs_cnt; 483 struct mlx4_en_stat_out_mbox hw_stats; 484 int vids[128]; 485 bool wol; 486 struct device *ddev; 487 }; 488 489 enum mlx4_en_wol { 490 MLX4_EN_WOL_MAGIC = (1ULL << 61), 491 MLX4_EN_WOL_ENABLED = (1ULL << 62), 492 }; 493 494 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63) 495 496 void mlx4_en_destroy_netdev(struct net_device *dev); 497 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, 498 struct mlx4_en_port_profile *prof); 499 500 int mlx4_en_start_port(struct net_device *dev); 501 void mlx4_en_stop_port(struct net_device *dev); 502 503 void mlx4_en_free_resources(struct mlx4_en_priv *priv); 504 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv); 505 506 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq, 507 int entries, int ring, enum cq_type mode); 508 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 509 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq, 510 int cq_idx); 511 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 512 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 513 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 514 515 void mlx4_en_poll_tx_cq(unsigned long data); 516 void mlx4_en_tx_irq(struct mlx4_cq *mcq); 517 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb); 518 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev); 519 520 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring, 521 int qpn, u32 size, u16 stride); 522 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring); 523 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 524 struct mlx4_en_tx_ring *ring, 525 int cq); 526 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 527 struct mlx4_en_tx_ring *ring); 528 529 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 530 struct mlx4_en_rx_ring *ring, 531 u32 size, u16 stride); 532 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 533 struct mlx4_en_rx_ring *ring, 534 u32 size, u16 stride); 535 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv); 536 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, 537 struct mlx4_en_rx_ring *ring); 538 int mlx4_en_process_rx_cq(struct net_device *dev, 539 struct mlx4_en_cq *cq, 540 int budget); 541 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget); 542 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, 543 int is_tx, int rss, int qpn, int cqn, 544 struct mlx4_qp_context *context); 545 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event); 546 int mlx4_en_map_buffer(struct mlx4_buf *buf); 547 void mlx4_en_unmap_buffer(struct mlx4_buf *buf); 548 549 void mlx4_en_calc_rx_buf(struct net_device *dev); 550 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv); 551 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv); 552 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring); 553 void mlx4_en_rx_irq(struct mlx4_cq *mcq); 554 555 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 556 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv); 557 558 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset); 559 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port); 560 561 #define MLX4_EN_NUM_SELF_TEST 5 562 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf); 563 u64 mlx4_en_mac_to_u64(u8 *addr); 564 565 /* 566 * Globals 567 */ 568 extern const struct ethtool_ops mlx4_en_ethtool_ops; 569 570 571 572 /* 573 * printk / logging functions 574 */ 575 576 __printf(3, 4) 577 int en_print(const char *level, const struct mlx4_en_priv *priv, 578 const char *format, ...); 579 580 #define en_dbg(mlevel, priv, format, arg...) \ 581 do { \ 582 if (NETIF_MSG_##mlevel & priv->msg_enable) \ 583 en_print(KERN_DEBUG, priv, format, ##arg); \ 584 } while (0) 585 #define en_warn(priv, format, arg...) \ 586 en_print(KERN_WARNING, priv, format, ##arg) 587 #define en_err(priv, format, arg...) \ 588 en_print(KERN_ERR, priv, format, ##arg) 589 #define en_info(priv, format, arg...) \ 590 en_print(KERN_INFO, priv, format, ## arg) 591 592 #define mlx4_err(mdev, format, arg...) \ 593 pr_err("%s %s: " format, DRV_NAME, \ 594 dev_name(&mdev->pdev->dev), ##arg) 595 #define mlx4_info(mdev, format, arg...) \ 596 pr_info("%s %s: " format, DRV_NAME, \ 597 dev_name(&mdev->pdev->dev), ##arg) 598 #define mlx4_warn(mdev, format, arg...) \ 599 pr_warning("%s %s: " format, DRV_NAME, \ 600 dev_name(&mdev->pdev->dev), ##arg) 601 602 #endif 603