1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #ifndef _MLX4_EN_H_ 35 #define _MLX4_EN_H_ 36 37 #include <linux/bitops.h> 38 #include <linux/compiler.h> 39 #include <linux/list.h> 40 #include <linux/mutex.h> 41 #include <linux/netdevice.h> 42 #include <linux/if_vlan.h> 43 #include <linux/net_tstamp.h> 44 #ifdef CONFIG_MLX4_EN_DCB 45 #include <linux/dcbnl.h> 46 #endif 47 #include <linux/cpu_rmap.h> 48 #include <linux/ptp_clock_kernel.h> 49 50 #include <linux/mlx4/device.h> 51 #include <linux/mlx4/qp.h> 52 #include <linux/mlx4/cq.h> 53 #include <linux/mlx4/srq.h> 54 #include <linux/mlx4/doorbell.h> 55 #include <linux/mlx4/cmd.h> 56 57 #include "en_port.h" 58 59 #define DRV_NAME "mlx4_en" 60 #define DRV_VERSION "2.2-1" 61 #define DRV_RELDATE "Feb 2014" 62 63 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN) 64 65 /* 66 * Device constants 67 */ 68 69 70 #define MLX4_EN_PAGE_SHIFT 12 71 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT) 72 #define DEF_RX_RINGS 16 73 #define MAX_RX_RINGS 128 74 #define MIN_RX_RINGS 4 75 #define TXBB_SIZE 64 76 #define HEADROOM (2048 / TXBB_SIZE + 1) 77 #define STAMP_STRIDE 64 78 #define STAMP_DWORDS (STAMP_STRIDE / 4) 79 #define STAMP_SHIFT 31 80 #define STAMP_VAL 0x7fffffff 81 #define STATS_DELAY (HZ / 4) 82 #define SERVICE_TASK_DELAY (HZ / 4) 83 #define MAX_NUM_OF_FS_RULES 256 84 85 #define MLX4_EN_FILTER_HASH_SHIFT 4 86 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60 87 88 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */ 89 #define MAX_DESC_SIZE 512 90 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE) 91 92 /* 93 * OS related constants and tunables 94 */ 95 96 #define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1 97 98 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ) 99 100 /* Use the maximum between 16384 and a single page */ 101 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384) 102 103 #define MLX4_EN_ALLOC_PREFER_ORDER PAGE_ALLOC_COSTLY_ORDER 104 105 /* Receive fragment sizes; we use at most 3 fragments (for 9600 byte MTU 106 * and 4K allocations) */ 107 enum { 108 FRAG_SZ0 = 1536 - NET_IP_ALIGN, 109 FRAG_SZ1 = 4096, 110 FRAG_SZ2 = 4096, 111 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE 112 }; 113 #define MLX4_EN_MAX_RX_FRAGS 4 114 115 /* Maximum ring sizes */ 116 #define MLX4_EN_MAX_TX_SIZE 8192 117 #define MLX4_EN_MAX_RX_SIZE 8192 118 119 /* Minimum ring size for our page-allocation scheme to work */ 120 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES) 121 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE) 122 123 #define MLX4_EN_SMALL_PKT_SIZE 64 124 #define MLX4_EN_MIN_TX_RING_P_UP 1 125 #define MLX4_EN_MAX_TX_RING_P_UP 32 126 #define MLX4_EN_NUM_UP 8 127 #define MLX4_EN_DEF_TX_RING_SIZE 512 128 #define MLX4_EN_DEF_RX_RING_SIZE 1024 129 #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \ 130 MLX4_EN_NUM_UP) 131 132 #define MLX4_EN_DEFAULT_TX_WORK 256 133 134 /* Target number of packets to coalesce with interrupt moderation */ 135 #define MLX4_EN_RX_COAL_TARGET 44 136 #define MLX4_EN_RX_COAL_TIME 0x10 137 138 #define MLX4_EN_TX_COAL_PKTS 16 139 #define MLX4_EN_TX_COAL_TIME 0x10 140 141 #define MLX4_EN_RX_RATE_LOW 400000 142 #define MLX4_EN_RX_COAL_TIME_LOW 0 143 #define MLX4_EN_RX_RATE_HIGH 450000 144 #define MLX4_EN_RX_COAL_TIME_HIGH 128 145 #define MLX4_EN_RX_SIZE_THRESH 1024 146 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH) 147 #define MLX4_EN_SAMPLE_INTERVAL 0 148 #define MLX4_EN_AVG_PKT_SMALL 256 149 150 #define MLX4_EN_AUTO_CONF 0xffff 151 152 #define MLX4_EN_DEF_RX_PAUSE 1 153 #define MLX4_EN_DEF_TX_PAUSE 1 154 155 /* Interval between successive polls in the Tx routine when polling is used 156 instead of interrupts (in per-core Tx rings) - should be power of 2 */ 157 #define MLX4_EN_TX_POLL_MODER 16 158 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4) 159 160 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN) 161 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN) 162 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN) 163 164 #define MLX4_EN_MIN_MTU 46 165 #define ETH_BCAST 0xffffffffffffULL 166 167 #define MLX4_EN_LOOPBACK_RETRIES 5 168 #define MLX4_EN_LOOPBACK_TIMEOUT 100 169 170 #ifdef MLX4_EN_PERF_STAT 171 /* Number of samples to 'average' */ 172 #define AVG_SIZE 128 173 #define AVG_FACTOR 1024 174 #define NUM_PERF_STATS NUM_PERF_COUNTERS 175 176 #define INC_PERF_COUNTER(cnt) (++(cnt)) 177 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add)) 178 #define AVG_PERF_COUNTER(cnt, sample) \ 179 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE) 180 #define GET_PERF_COUNTER(cnt) (cnt) 181 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR) 182 183 #else 184 185 #define NUM_PERF_STATS 0 186 #define INC_PERF_COUNTER(cnt) do {} while (0) 187 #define ADD_PERF_COUNTER(cnt, add) do {} while (0) 188 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0) 189 #define GET_PERF_COUNTER(cnt) (0) 190 #define GET_AVG_PERF_COUNTER(cnt) (0) 191 #endif /* MLX4_EN_PERF_STAT */ 192 193 /* Constants for TX flow */ 194 enum { 195 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */ 196 MAX_BF = 256, 197 MIN_PKT_LEN = 17, 198 }; 199 200 /* 201 * Configurables 202 */ 203 204 enum cq_type { 205 RX = 0, 206 TX = 1, 207 }; 208 209 210 /* 211 * Useful macros 212 */ 213 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x)) 214 #define XNOR(x, y) (!(x) == !(y)) 215 216 217 struct mlx4_en_tx_info { 218 struct sk_buff *skb; 219 u32 nr_txbb; 220 u32 nr_bytes; 221 u8 linear; 222 u8 data_offset; 223 u8 inl; 224 u8 ts_requested; 225 }; 226 227 228 #define MLX4_EN_BIT_DESC_OWN 0x80000000 229 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg) 230 #define MLX4_EN_MEMTYPE_PAD 0x100 231 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg) 232 233 234 struct mlx4_en_tx_desc { 235 struct mlx4_wqe_ctrl_seg ctrl; 236 union { 237 struct mlx4_wqe_data_seg data; /* at least one data segment */ 238 struct mlx4_wqe_lso_seg lso; 239 struct mlx4_wqe_inline_seg inl; 240 }; 241 }; 242 243 #define MLX4_EN_USE_SRQ 0x01000000 244 245 #define MLX4_EN_CX3_LOW_ID 0x1000 246 #define MLX4_EN_CX3_HIGH_ID 0x1005 247 248 struct mlx4_en_rx_alloc { 249 struct page *page; 250 dma_addr_t dma; 251 u32 page_offset; 252 u32 page_size; 253 }; 254 255 struct mlx4_en_tx_ring { 256 struct mlx4_hwq_resources wqres; 257 u32 size ; /* number of TXBBs */ 258 u32 size_mask; 259 u16 stride; 260 u16 cqn; /* index of port CQ associated with this ring */ 261 u32 prod; 262 u32 cons; 263 u32 buf_size; 264 u32 doorbell_qpn; 265 void *buf; 266 u16 poll_cnt; 267 struct mlx4_en_tx_info *tx_info; 268 u8 *bounce_buf; 269 u8 queue_index; 270 cpumask_t affinity_mask; 271 u32 last_nr_txbb; 272 struct mlx4_qp qp; 273 struct mlx4_qp_context context; 274 int qpn; 275 enum mlx4_qp_state qp_state; 276 struct mlx4_srq dummy; 277 unsigned long bytes; 278 unsigned long packets; 279 unsigned long tx_csum; 280 unsigned long queue_stopped; 281 unsigned long wake_queue; 282 struct mlx4_bf bf; 283 bool bf_enabled; 284 bool bf_alloced; 285 struct netdev_queue *tx_queue; 286 int hwtstamp_tx_type; 287 int inline_thold; 288 }; 289 290 struct mlx4_en_rx_desc { 291 /* actual number of entries depends on rx ring stride */ 292 struct mlx4_wqe_data_seg data[0]; 293 }; 294 295 struct mlx4_en_rx_ring { 296 struct mlx4_hwq_resources wqres; 297 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS]; 298 u32 size ; /* number of Rx descs*/ 299 u32 actual_size; 300 u32 size_mask; 301 u16 stride; 302 u16 log_stride; 303 u16 cqn; /* index of port CQ associated with this ring */ 304 u32 prod; 305 u32 cons; 306 u32 buf_size; 307 u8 fcs_del; 308 void *buf; 309 void *rx_info; 310 unsigned long bytes; 311 unsigned long packets; 312 #ifdef CONFIG_NET_RX_BUSY_POLL 313 unsigned long yields; 314 unsigned long misses; 315 unsigned long cleaned; 316 #endif 317 unsigned long csum_ok; 318 unsigned long csum_none; 319 int hwtstamp_rx_filter; 320 cpumask_var_t affinity_mask; 321 }; 322 323 struct mlx4_en_cq { 324 struct mlx4_cq mcq; 325 struct mlx4_hwq_resources wqres; 326 int ring; 327 struct net_device *dev; 328 struct napi_struct napi; 329 int size; 330 int buf_size; 331 unsigned vector; 332 enum cq_type is_tx; 333 u16 moder_time; 334 u16 moder_cnt; 335 struct mlx4_cqe *buf; 336 #define MLX4_EN_OPCODE_ERROR 0x1e 337 338 #ifdef CONFIG_NET_RX_BUSY_POLL 339 unsigned int state; 340 #define MLX4_EN_CQ_STATE_IDLE 0 341 #define MLX4_EN_CQ_STATE_NAPI 1 /* NAPI owns this CQ */ 342 #define MLX4_EN_CQ_STATE_POLL 2 /* poll owns this CQ */ 343 #define MLX4_CQ_LOCKED (MLX4_EN_CQ_STATE_NAPI | MLX4_EN_CQ_STATE_POLL) 344 #define MLX4_EN_CQ_STATE_NAPI_YIELD 4 /* NAPI yielded this CQ */ 345 #define MLX4_EN_CQ_STATE_POLL_YIELD 8 /* poll yielded this CQ */ 346 #define CQ_YIELD (MLX4_EN_CQ_STATE_NAPI_YIELD | MLX4_EN_CQ_STATE_POLL_YIELD) 347 #define CQ_USER_PEND (MLX4_EN_CQ_STATE_POLL | MLX4_EN_CQ_STATE_POLL_YIELD) 348 spinlock_t poll_lock; /* protects from LLS/napi conflicts */ 349 #endif /* CONFIG_NET_RX_BUSY_POLL */ 350 struct irq_desc *irq_desc; 351 }; 352 353 struct mlx4_en_port_profile { 354 u32 flags; 355 u32 tx_ring_num; 356 u32 rx_ring_num; 357 u32 tx_ring_size; 358 u32 rx_ring_size; 359 u8 rx_pause; 360 u8 rx_ppp; 361 u8 tx_pause; 362 u8 tx_ppp; 363 int rss_rings; 364 int inline_thold; 365 }; 366 367 struct mlx4_en_profile { 368 int rss_xor; 369 int udp_rss; 370 u8 rss_mask; 371 u32 active_ports; 372 u32 small_pkt_int; 373 u8 no_reset; 374 u8 num_tx_rings_p_up; 375 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1]; 376 }; 377 378 struct mlx4_en_dev { 379 struct mlx4_dev *dev; 380 struct pci_dev *pdev; 381 struct mutex state_lock; 382 struct net_device *pndev[MLX4_MAX_PORTS + 1]; 383 u32 port_cnt; 384 bool device_up; 385 struct mlx4_en_profile profile; 386 u32 LSO_support; 387 struct workqueue_struct *workqueue; 388 struct device *dma_device; 389 void __iomem *uar_map; 390 struct mlx4_uar priv_uar; 391 struct mlx4_mr mr; 392 u32 priv_pdn; 393 spinlock_t uar_lock; 394 u8 mac_removed[MLX4_MAX_PORTS + 1]; 395 rwlock_t clock_lock; 396 u32 nominal_c_mult; 397 struct cyclecounter cycles; 398 struct timecounter clock; 399 unsigned long last_overflow_check; 400 unsigned long overflow_period; 401 struct ptp_clock *ptp_clock; 402 struct ptp_clock_info ptp_clock_info; 403 }; 404 405 406 struct mlx4_en_rss_map { 407 int base_qpn; 408 struct mlx4_qp qps[MAX_RX_RINGS]; 409 enum mlx4_qp_state state[MAX_RX_RINGS]; 410 struct mlx4_qp indir_qp; 411 enum mlx4_qp_state indir_state; 412 }; 413 414 struct mlx4_en_port_state { 415 int link_state; 416 int link_speed; 417 int transciver; 418 }; 419 420 struct mlx4_en_pkt_stats { 421 unsigned long broadcast; 422 unsigned long rx_prio[8]; 423 unsigned long tx_prio[8]; 424 #define NUM_PKT_STATS 17 425 }; 426 427 struct mlx4_en_port_stats { 428 unsigned long tso_packets; 429 unsigned long queue_stopped; 430 unsigned long wake_queue; 431 unsigned long tx_timeout; 432 unsigned long rx_alloc_failed; 433 unsigned long rx_chksum_good; 434 unsigned long rx_chksum_none; 435 unsigned long tx_chksum_offload; 436 #define NUM_PORT_STATS 8 437 }; 438 439 struct mlx4_en_perf_stats { 440 u32 tx_poll; 441 u64 tx_pktsz_avg; 442 u32 inflight_avg; 443 u16 tx_coal_avg; 444 u16 rx_coal_avg; 445 u32 napi_quota; 446 #define NUM_PERF_COUNTERS 6 447 }; 448 449 enum mlx4_en_mclist_act { 450 MCLIST_NONE, 451 MCLIST_REM, 452 MCLIST_ADD, 453 }; 454 455 struct mlx4_en_mc_list { 456 struct list_head list; 457 enum mlx4_en_mclist_act action; 458 u8 addr[ETH_ALEN]; 459 u64 reg_id; 460 u64 tunnel_reg_id; 461 }; 462 463 struct mlx4_en_frag_info { 464 u16 frag_size; 465 u16 frag_prefix_size; 466 u16 frag_stride; 467 u16 frag_align; 468 }; 469 470 #ifdef CONFIG_MLX4_EN_DCB 471 /* Minimal TC BW - setting to 0 will block traffic */ 472 #define MLX4_EN_BW_MIN 1 473 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */ 474 475 #define MLX4_EN_TC_ETS 7 476 477 #endif 478 479 struct ethtool_flow_id { 480 struct list_head list; 481 struct ethtool_rx_flow_spec flow_spec; 482 u64 id; 483 }; 484 485 enum { 486 MLX4_EN_FLAG_PROMISC = (1 << 0), 487 MLX4_EN_FLAG_MC_PROMISC = (1 << 1), 488 /* whether we need to enable hardware loopback by putting dmac 489 * in Tx WQE 490 */ 491 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2), 492 /* whether we need to drop packets that hardware loopback-ed */ 493 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3), 494 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4) 495 }; 496 497 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE) 498 #define MLX4_EN_MAC_HASH_IDX 5 499 500 struct mlx4_en_priv { 501 struct mlx4_en_dev *mdev; 502 struct mlx4_en_port_profile *prof; 503 struct net_device *dev; 504 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 505 struct net_device_stats stats; 506 struct net_device_stats ret_stats; 507 struct mlx4_en_port_state port_state; 508 spinlock_t stats_lock; 509 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES]; 510 /* To allow rules removal while port is going down */ 511 struct list_head ethtool_list; 512 513 unsigned long last_moder_packets[MAX_RX_RINGS]; 514 unsigned long last_moder_tx_packets; 515 unsigned long last_moder_bytes[MAX_RX_RINGS]; 516 unsigned long last_moder_jiffies; 517 int last_moder_time[MAX_RX_RINGS]; 518 u16 rx_usecs; 519 u16 rx_frames; 520 u16 tx_usecs; 521 u16 tx_frames; 522 u32 pkt_rate_low; 523 u16 rx_usecs_low; 524 u32 pkt_rate_high; 525 u16 rx_usecs_high; 526 u16 sample_interval; 527 u16 adaptive_rx_coal; 528 u32 msg_enable; 529 u32 loopback_ok; 530 u32 validate_loopback; 531 532 struct mlx4_hwq_resources res; 533 int link_state; 534 int last_link_state; 535 bool port_up; 536 int port; 537 int registered; 538 int allocated; 539 int stride; 540 unsigned char current_mac[ETH_ALEN + 2]; 541 int mac_index; 542 unsigned max_mtu; 543 int base_qpn; 544 int cqe_factor; 545 546 struct mlx4_en_rss_map rss_map; 547 __be32 ctrl_flags; 548 u32 flags; 549 u8 num_tx_rings_p_up; 550 u32 tx_work_limit; 551 u32 tx_ring_num; 552 u32 rx_ring_num; 553 u32 rx_skb_size; 554 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS]; 555 u16 num_frags; 556 u16 log_rx_info; 557 558 struct mlx4_en_tx_ring **tx_ring; 559 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS]; 560 struct mlx4_en_cq **tx_cq; 561 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS]; 562 struct mlx4_qp drop_qp; 563 struct work_struct rx_mode_task; 564 struct work_struct watchdog_task; 565 struct work_struct linkstate_task; 566 struct delayed_work stats_task; 567 struct delayed_work service_task; 568 #ifdef CONFIG_MLX4_EN_VXLAN 569 struct work_struct vxlan_add_task; 570 struct work_struct vxlan_del_task; 571 #endif 572 struct mlx4_en_perf_stats pstats; 573 struct mlx4_en_pkt_stats pkstats; 574 struct mlx4_en_port_stats port_stats; 575 u64 stats_bitmap; 576 struct list_head mc_list; 577 struct list_head curr_list; 578 u64 broadcast_id; 579 struct mlx4_en_stat_out_mbox hw_stats; 580 int vids[128]; 581 bool wol; 582 struct device *ddev; 583 int base_tx_qpn; 584 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE]; 585 struct hwtstamp_config hwtstamp_config; 586 587 #ifdef CONFIG_MLX4_EN_DCB 588 struct ieee_ets ets; 589 u16 maxrate[IEEE_8021QAZ_MAX_TCS]; 590 #endif 591 #ifdef CONFIG_RFS_ACCEL 592 spinlock_t filters_lock; 593 int last_filter_id; 594 struct list_head filters; 595 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT]; 596 #endif 597 u64 tunnel_reg_id; 598 __be16 vxlan_port; 599 600 u32 pflags; 601 }; 602 603 enum mlx4_en_wol { 604 MLX4_EN_WOL_MAGIC = (1ULL << 61), 605 MLX4_EN_WOL_ENABLED = (1ULL << 62), 606 }; 607 608 struct mlx4_mac_entry { 609 struct hlist_node hlist; 610 unsigned char mac[ETH_ALEN + 2]; 611 u64 reg_id; 612 struct rcu_head rcu; 613 }; 614 615 #ifdef CONFIG_NET_RX_BUSY_POLL 616 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq) 617 { 618 spin_lock_init(&cq->poll_lock); 619 cq->state = MLX4_EN_CQ_STATE_IDLE; 620 } 621 622 /* called from the device poll rutine to get ownership of a cq */ 623 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq) 624 { 625 int rc = true; 626 spin_lock(&cq->poll_lock); 627 if (cq->state & MLX4_CQ_LOCKED) { 628 WARN_ON(cq->state & MLX4_EN_CQ_STATE_NAPI); 629 cq->state |= MLX4_EN_CQ_STATE_NAPI_YIELD; 630 rc = false; 631 } else 632 /* we don't care if someone yielded */ 633 cq->state = MLX4_EN_CQ_STATE_NAPI; 634 spin_unlock(&cq->poll_lock); 635 return rc; 636 } 637 638 /* returns true is someone tried to get the cq while napi had it */ 639 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq) 640 { 641 int rc = false; 642 spin_lock(&cq->poll_lock); 643 WARN_ON(cq->state & (MLX4_EN_CQ_STATE_POLL | 644 MLX4_EN_CQ_STATE_NAPI_YIELD)); 645 646 if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD) 647 rc = true; 648 cq->state = MLX4_EN_CQ_STATE_IDLE; 649 spin_unlock(&cq->poll_lock); 650 return rc; 651 } 652 653 /* called from mlx4_en_low_latency_poll() */ 654 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq) 655 { 656 int rc = true; 657 spin_lock_bh(&cq->poll_lock); 658 if ((cq->state & MLX4_CQ_LOCKED)) { 659 struct net_device *dev = cq->dev; 660 struct mlx4_en_priv *priv = netdev_priv(dev); 661 struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring]; 662 663 cq->state |= MLX4_EN_CQ_STATE_POLL_YIELD; 664 rc = false; 665 rx_ring->yields++; 666 } else 667 /* preserve yield marks */ 668 cq->state |= MLX4_EN_CQ_STATE_POLL; 669 spin_unlock_bh(&cq->poll_lock); 670 return rc; 671 } 672 673 /* returns true if someone tried to get the cq while it was locked */ 674 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq) 675 { 676 int rc = false; 677 spin_lock_bh(&cq->poll_lock); 678 WARN_ON(cq->state & (MLX4_EN_CQ_STATE_NAPI)); 679 680 if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD) 681 rc = true; 682 cq->state = MLX4_EN_CQ_STATE_IDLE; 683 spin_unlock_bh(&cq->poll_lock); 684 return rc; 685 } 686 687 /* true if a socket is polling, even if it did not get the lock */ 688 static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq) 689 { 690 WARN_ON(!(cq->state & MLX4_CQ_LOCKED)); 691 return cq->state & CQ_USER_PEND; 692 } 693 #else 694 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq) 695 { 696 } 697 698 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq) 699 { 700 return true; 701 } 702 703 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq) 704 { 705 return false; 706 } 707 708 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq) 709 { 710 return false; 711 } 712 713 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq) 714 { 715 return false; 716 } 717 718 static inline bool mlx4_en_cq_busy_polling(struct mlx4_en_cq *cq) 719 { 720 return false; 721 } 722 #endif /* CONFIG_NET_RX_BUSY_POLL */ 723 724 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63) 725 726 void mlx4_en_update_loopback_state(struct net_device *dev, 727 netdev_features_t features); 728 729 void mlx4_en_destroy_netdev(struct net_device *dev); 730 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, 731 struct mlx4_en_port_profile *prof); 732 733 int mlx4_en_start_port(struct net_device *dev); 734 void mlx4_en_stop_port(struct net_device *dev, int detach); 735 736 void mlx4_en_free_resources(struct mlx4_en_priv *priv); 737 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv); 738 739 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq, 740 int entries, int ring, enum cq_type mode, int node); 741 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq); 742 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq, 743 int cq_idx); 744 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 745 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 746 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 747 748 void mlx4_en_tx_irq(struct mlx4_cq *mcq); 749 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, 750 void *accel_priv, select_queue_fallback_t fallback); 751 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev); 752 753 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 754 struct mlx4_en_tx_ring **pring, 755 int qpn, u32 size, u16 stride, 756 int node, int queue_index); 757 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 758 struct mlx4_en_tx_ring **pring); 759 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 760 struct mlx4_en_tx_ring *ring, 761 int cq, int user_prio); 762 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 763 struct mlx4_en_tx_ring *ring); 764 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev); 765 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 766 struct mlx4_en_rx_ring **pring, 767 u32 size, u16 stride, int node); 768 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 769 struct mlx4_en_rx_ring **pring, 770 u32 size, u16 stride); 771 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv); 772 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, 773 struct mlx4_en_rx_ring *ring); 774 int mlx4_en_process_rx_cq(struct net_device *dev, 775 struct mlx4_en_cq *cq, 776 int budget); 777 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget); 778 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget); 779 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, 780 int is_tx, int rss, int qpn, int cqn, int user_prio, 781 struct mlx4_qp_context *context); 782 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event); 783 int mlx4_en_map_buffer(struct mlx4_buf *buf); 784 void mlx4_en_unmap_buffer(struct mlx4_buf *buf); 785 786 void mlx4_en_calc_rx_buf(struct net_device *dev); 787 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv); 788 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv); 789 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv); 790 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv); 791 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring); 792 void mlx4_en_rx_irq(struct mlx4_cq *mcq); 793 794 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 795 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv); 796 797 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset); 798 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port); 799 800 #ifdef CONFIG_MLX4_EN_DCB 801 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops; 802 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops; 803 #endif 804 805 int mlx4_en_setup_tc(struct net_device *dev, u8 up); 806 807 #ifdef CONFIG_RFS_ACCEL 808 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv); 809 #endif 810 811 #define MLX4_EN_NUM_SELF_TEST 5 812 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf); 813 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev); 814 815 /* 816 * Functions for time stamping 817 */ 818 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe); 819 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev, 820 struct skb_shared_hwtstamps *hwts, 821 u64 timestamp); 822 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev); 823 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev); 824 int mlx4_en_timestamp_config(struct net_device *dev, 825 int tx_type, 826 int rx_filter); 827 828 /* Globals 829 */ 830 extern const struct ethtool_ops mlx4_en_ethtool_ops; 831 832 833 834 /* 835 * printk / logging functions 836 */ 837 838 __printf(3, 4) 839 int en_print(const char *level, const struct mlx4_en_priv *priv, 840 const char *format, ...); 841 842 #define en_dbg(mlevel, priv, format, ...) \ 843 do { \ 844 if (NETIF_MSG_##mlevel & (priv)->msg_enable) \ 845 en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__); \ 846 } while (0) 847 #define en_warn(priv, format, ...) \ 848 en_print(KERN_WARNING, priv, format, ##__VA_ARGS__) 849 #define en_err(priv, format, ...) \ 850 en_print(KERN_ERR, priv, format, ##__VA_ARGS__) 851 #define en_info(priv, format, ...) \ 852 en_print(KERN_INFO, priv, format, ##__VA_ARGS__) 853 854 #define mlx4_err(mdev, format, ...) \ 855 pr_err(DRV_NAME " %s: " format, \ 856 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 857 #define mlx4_info(mdev, format, ...) \ 858 pr_info(DRV_NAME " %s: " format, \ 859 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 860 #define mlx4_warn(mdev, format, ...) \ 861 pr_warn(DRV_NAME " %s: " format, \ 862 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__) 863 864 #endif 865