1 /*
2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  *
32  */
33 
34 #ifndef _MLX4_EN_H_
35 #define _MLX4_EN_H_
36 
37 #include <linux/bitops.h>
38 #include <linux/compiler.h>
39 #include <linux/list.h>
40 #include <linux/mutex.h>
41 #include <linux/netdevice.h>
42 #include <linux/if_vlan.h>
43 #include <linux/net_tstamp.h>
44 #ifdef CONFIG_MLX4_EN_DCB
45 #include <linux/dcbnl.h>
46 #endif
47 #include <linux/cpu_rmap.h>
48 #include <linux/ptp_clock_kernel.h>
49 #include <net/xdp.h>
50 
51 #include <linux/mlx4/device.h>
52 #include <linux/mlx4/qp.h>
53 #include <linux/mlx4/cq.h>
54 #include <linux/mlx4/srq.h>
55 #include <linux/mlx4/doorbell.h>
56 #include <linux/mlx4/cmd.h>
57 
58 #include "en_port.h"
59 #include "mlx4_stats.h"
60 
61 #define DRV_NAME	"mlx4_en"
62 #define DRV_VERSION	"4.0-0"
63 
64 #define MLX4_EN_MSG_LEVEL	(NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
65 
66 /*
67  * Device constants
68  */
69 
70 
71 #define MLX4_EN_PAGE_SHIFT	12
72 #define MLX4_EN_PAGE_SIZE	(1 << MLX4_EN_PAGE_SHIFT)
73 #define DEF_RX_RINGS		16
74 #define MAX_RX_RINGS		128
75 #define MIN_RX_RINGS		1
76 #define LOG_TXBB_SIZE		6
77 #define TXBB_SIZE		BIT(LOG_TXBB_SIZE)
78 #define HEADROOM		(2048 / TXBB_SIZE + 1)
79 #define STAMP_STRIDE		64
80 #define STAMP_DWORDS		(STAMP_STRIDE / 4)
81 #define STAMP_SHIFT		31
82 #define STAMP_VAL		0x7fffffff
83 #define STATS_DELAY		(HZ / 4)
84 #define SERVICE_TASK_DELAY	(HZ / 4)
85 #define MAX_NUM_OF_FS_RULES	256
86 
87 #define MLX4_EN_FILTER_HASH_SHIFT 4
88 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60
89 
90 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
91 #define MAX_DESC_SIZE		512
92 #define MAX_DESC_TXBBS		(MAX_DESC_SIZE / TXBB_SIZE)
93 
94 /*
95  * OS related constants and tunables
96  */
97 
98 #define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1
99 #define MLX4_EN_PRIV_FLAGS_PHV	     2
100 
101 #define MLX4_EN_WATCHDOG_TIMEOUT	(15 * HZ)
102 
103 /* Use the maximum between 16384 and a single page */
104 #define MLX4_EN_ALLOC_SIZE	PAGE_ALIGN(16384)
105 
106 #define MLX4_EN_MAX_RX_FRAGS	4
107 
108 /* Maximum ring sizes */
109 #define MLX4_EN_MAX_TX_SIZE	8192
110 #define MLX4_EN_MAX_RX_SIZE	8192
111 
112 /* Minimum ring size for our page-allocation scheme to work */
113 #define MLX4_EN_MIN_RX_SIZE	(MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
114 #define MLX4_EN_MIN_TX_SIZE	(4096 / TXBB_SIZE)
115 
116 #define MLX4_EN_SMALL_PKT_SIZE		64
117 #define MLX4_EN_MIN_TX_RING_P_UP	1
118 #define MLX4_EN_MAX_TX_RING_P_UP	32
119 #define MLX4_EN_NUM_UP_LOW		1
120 #define MLX4_EN_NUM_UP_HIGH		8
121 #define MLX4_EN_DEF_RX_RING_SIZE  	1024
122 #define MLX4_EN_DEF_TX_RING_SIZE	MLX4_EN_DEF_RX_RING_SIZE
123 #define MAX_TX_RINGS			(MLX4_EN_MAX_TX_RING_P_UP * \
124 					 MLX4_EN_NUM_UP_HIGH)
125 
126 #define MLX4_EN_DEFAULT_TX_WORK		256
127 
128 /* Target number of packets to coalesce with interrupt moderation */
129 #define MLX4_EN_RX_COAL_TARGET	44
130 #define MLX4_EN_RX_COAL_TIME	0x10
131 
132 #define MLX4_EN_TX_COAL_PKTS	16
133 #define MLX4_EN_TX_COAL_TIME	0x10
134 
135 #define MLX4_EN_MAX_COAL_PKTS	U16_MAX
136 #define MLX4_EN_MAX_COAL_TIME	U16_MAX
137 
138 #define MLX4_EN_RX_RATE_LOW		400000
139 #define MLX4_EN_RX_COAL_TIME_LOW	0
140 #define MLX4_EN_RX_RATE_HIGH		450000
141 #define MLX4_EN_RX_COAL_TIME_HIGH	128
142 #define MLX4_EN_RX_SIZE_THRESH		1024
143 #define MLX4_EN_RX_RATE_THRESH		(1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
144 #define MLX4_EN_SAMPLE_INTERVAL		0
145 #define MLX4_EN_AVG_PKT_SMALL		256
146 
147 #define MLX4_EN_AUTO_CONF	0xffff
148 
149 #define MLX4_EN_DEF_RX_PAUSE	1
150 #define MLX4_EN_DEF_TX_PAUSE	1
151 
152 /* Interval between successive polls in the Tx routine when polling is used
153    instead of interrupts (in per-core Tx rings) - should be power of 2 */
154 #define MLX4_EN_TX_POLL_MODER	16
155 #define MLX4_EN_TX_POLL_TIMEOUT	(HZ / 4)
156 
157 #define SMALL_PACKET_SIZE      (256 - NET_IP_ALIGN)
158 #define HEADER_COPY_SIZE       (128 - NET_IP_ALIGN)
159 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
160 #define PREAMBLE_LEN           8
161 #define MLX4_SELFTEST_LB_MIN_MTU (MLX4_LOOPBACK_TEST_PAYLOAD + NET_IP_ALIGN + \
162 				  ETH_HLEN + PREAMBLE_LEN)
163 
164 /* VLAN_HLEN is added twice,to support skb vlan tagged with multiple
165  * headers. (For example: ETH_P_8021Q and ETH_P_8021AD).
166  */
167 #define MLX4_EN_EFF_MTU(mtu)	((mtu) + ETH_HLEN + (2 * VLAN_HLEN))
168 #define ETH_BCAST		0xffffffffffffULL
169 
170 #define MLX4_EN_LOOPBACK_RETRIES	5
171 #define MLX4_EN_LOOPBACK_TIMEOUT	100
172 
173 #ifdef MLX4_EN_PERF_STAT
174 /* Number of samples to 'average' */
175 #define AVG_SIZE			128
176 #define AVG_FACTOR			1024
177 
178 #define INC_PERF_COUNTER(cnt)		(++(cnt))
179 #define ADD_PERF_COUNTER(cnt, add)	((cnt) += (add))
180 #define AVG_PERF_COUNTER(cnt, sample) \
181 	((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
182 #define GET_PERF_COUNTER(cnt)		(cnt)
183 #define GET_AVG_PERF_COUNTER(cnt)	((cnt) / AVG_FACTOR)
184 
185 #else
186 
187 #define INC_PERF_COUNTER(cnt)		do {} while (0)
188 #define ADD_PERF_COUNTER(cnt, add)	do {} while (0)
189 #define AVG_PERF_COUNTER(cnt, sample)	do {} while (0)
190 #define GET_PERF_COUNTER(cnt)		(0)
191 #define GET_AVG_PERF_COUNTER(cnt)	(0)
192 #endif /* MLX4_EN_PERF_STAT */
193 
194 /* Constants for TX flow */
195 enum {
196 	MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
197 	MAX_BF = 256,
198 	MIN_PKT_LEN = 17,
199 };
200 
201 /*
202  * Configurables
203  */
204 
205 enum cq_type {
206 	/* keep tx types first */
207 	TX,
208 	TX_XDP,
209 #define MLX4_EN_NUM_TX_TYPES (TX_XDP + 1)
210 	RX,
211 };
212 
213 
214 /*
215  * Useful macros
216  */
217 #define ROUNDUP_LOG2(x)		ilog2(roundup_pow_of_two(x))
218 #define XNOR(x, y)		(!(x) == !(y))
219 
220 
221 struct mlx4_en_tx_info {
222 	union {
223 		struct sk_buff *skb;
224 		struct page *page;
225 	};
226 	dma_addr_t	map0_dma;
227 	u32		map0_byte_count;
228 	u32		nr_txbb;
229 	u32		nr_bytes;
230 	u8		linear;
231 	u8		data_offset;
232 	u8		inl;
233 	u8		ts_requested;
234 	u8		nr_maps;
235 } ____cacheline_aligned_in_smp;
236 
237 
238 #define MLX4_EN_BIT_DESC_OWN	0x80000000
239 #define CTRL_SIZE	sizeof(struct mlx4_wqe_ctrl_seg)
240 #define MLX4_EN_MEMTYPE_PAD	0x100
241 #define DS_SIZE		sizeof(struct mlx4_wqe_data_seg)
242 
243 
244 struct mlx4_en_tx_desc {
245 	struct mlx4_wqe_ctrl_seg ctrl;
246 	union {
247 		struct mlx4_wqe_data_seg data; /* at least one data segment */
248 		struct mlx4_wqe_lso_seg lso;
249 		struct mlx4_wqe_inline_seg inl;
250 	};
251 };
252 
253 #define MLX4_EN_USE_SRQ		0x01000000
254 
255 #define MLX4_EN_CX3_LOW_ID	0x1000
256 #define MLX4_EN_CX3_HIGH_ID	0x1005
257 
258 struct mlx4_en_rx_alloc {
259 	struct page	*page;
260 	dma_addr_t	dma;
261 	u32		page_offset;
262 };
263 
264 #define MLX4_EN_CACHE_SIZE (2 * NAPI_POLL_WEIGHT)
265 
266 struct mlx4_en_page_cache {
267 	u32 index;
268 	struct {
269 		struct page	*page;
270 		dma_addr_t	dma;
271 	} buf[MLX4_EN_CACHE_SIZE];
272 };
273 
274 struct mlx4_en_priv;
275 
276 struct mlx4_en_tx_ring {
277 	/* cache line used and dirtied in tx completion
278 	 * (mlx4_en_free_tx_buf())
279 	 */
280 	u32			last_nr_txbb;
281 	u32			cons;
282 	unsigned long		wake_queue;
283 	struct netdev_queue	*tx_queue;
284 	u32			(*free_tx_desc)(struct mlx4_en_priv *priv,
285 						struct mlx4_en_tx_ring *ring,
286 						int index,
287 						u64 timestamp, int napi_mode);
288 	struct mlx4_en_rx_ring	*recycle_ring;
289 
290 	/* cache line used and dirtied in mlx4_en_xmit() */
291 	u32			prod ____cacheline_aligned_in_smp;
292 	unsigned int		tx_dropped;
293 	unsigned long		bytes;
294 	unsigned long		packets;
295 	unsigned long		tx_csum;
296 	unsigned long		tso_packets;
297 	unsigned long		xmit_more;
298 	struct mlx4_bf		bf;
299 
300 	/* Following part should be mostly read */
301 	__be32			doorbell_qpn;
302 	__be32			mr_key;
303 	u32			size; /* number of TXBBs */
304 	u32			size_mask;
305 	u32			full_size;
306 	u32			buf_size;
307 	void			*buf;
308 	struct mlx4_en_tx_info	*tx_info;
309 	int			qpn;
310 	u8			queue_index;
311 	bool			bf_enabled;
312 	bool			bf_alloced;
313 	u8			hwtstamp_tx_type;
314 	u8			*bounce_buf;
315 
316 	/* Not used in fast path
317 	 * Only queue_stopped might be used if BQL is not properly working.
318 	 */
319 	unsigned long		queue_stopped;
320 	struct mlx4_hwq_resources sp_wqres;
321 	struct mlx4_qp		sp_qp;
322 	struct mlx4_qp_context	sp_context;
323 	cpumask_t		sp_affinity_mask;
324 	enum mlx4_qp_state	sp_qp_state;
325 	u16			sp_stride;
326 	u16			sp_cqn;	/* index of port CQ associated with this ring */
327 } ____cacheline_aligned_in_smp;
328 
329 struct mlx4_en_rx_desc {
330 	/* actual number of entries depends on rx ring stride */
331 	struct mlx4_wqe_data_seg data[0];
332 };
333 
334 struct mlx4_en_rx_ring {
335 	struct mlx4_hwq_resources wqres;
336 	u32 size ;	/* number of Rx descs*/
337 	u32 actual_size;
338 	u32 size_mask;
339 	u16 stride;
340 	u16 log_stride;
341 	u16 cqn;	/* index of port CQ associated with this ring */
342 	u32 prod;
343 	u32 cons;
344 	u32 buf_size;
345 	u8  fcs_del;
346 	void *buf;
347 	void *rx_info;
348 	struct bpf_prog __rcu *xdp_prog;
349 	struct mlx4_en_page_cache page_cache;
350 	unsigned long bytes;
351 	unsigned long packets;
352 	unsigned long csum_ok;
353 	unsigned long csum_none;
354 	unsigned long csum_complete;
355 	unsigned long rx_alloc_pages;
356 	unsigned long xdp_drop;
357 	unsigned long xdp_tx;
358 	unsigned long xdp_tx_full;
359 	unsigned long dropped;
360 	int hwtstamp_rx_filter;
361 	cpumask_var_t affinity_mask;
362 	struct xdp_rxq_info xdp_rxq;
363 };
364 
365 struct mlx4_en_cq {
366 	struct mlx4_cq          mcq;
367 	struct mlx4_hwq_resources wqres;
368 	int                     ring;
369 	struct net_device      *dev;
370 	union {
371 		struct napi_struct napi;
372 		bool               xdp_busy;
373 	};
374 	int size;
375 	int buf_size;
376 	int vector;
377 	enum cq_type type;
378 	u16 moder_time;
379 	u16 moder_cnt;
380 	struct mlx4_cqe *buf;
381 #define MLX4_EN_OPCODE_ERROR	0x1e
382 
383 	struct irq_desc *irq_desc;
384 };
385 
386 struct mlx4_en_port_profile {
387 	u32 flags;
388 	u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES];
389 	u32 rx_ring_num;
390 	u32 tx_ring_size;
391 	u32 rx_ring_size;
392 	u8 num_tx_rings_p_up;
393 	u8 rx_pause;
394 	u8 rx_ppp;
395 	u8 tx_pause;
396 	u8 tx_ppp;
397 	u8 num_up;
398 	int rss_rings;
399 	int inline_thold;
400 	struct hwtstamp_config hwtstamp_config;
401 };
402 
403 struct mlx4_en_profile {
404 	int udp_rss;
405 	u8 rss_mask;
406 	u32 active_ports;
407 	u32 small_pkt_int;
408 	u8 no_reset;
409 	u8 max_num_tx_rings_p_up;
410 	struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
411 };
412 
413 struct mlx4_en_dev {
414 	struct mlx4_dev         *dev;
415 	struct pci_dev		*pdev;
416 	struct mutex		state_lock;
417 	struct net_device       *pndev[MLX4_MAX_PORTS + 1];
418 	struct net_device       *upper[MLX4_MAX_PORTS + 1];
419 	u32                     port_cnt;
420 	bool			device_up;
421 	struct mlx4_en_profile  profile;
422 	u32			LSO_support;
423 	struct workqueue_struct *workqueue;
424 	struct device           *dma_device;
425 	void __iomem            *uar_map;
426 	struct mlx4_uar         priv_uar;
427 	struct mlx4_mr		mr;
428 	u32                     priv_pdn;
429 	spinlock_t              uar_lock;
430 	u8			mac_removed[MLX4_MAX_PORTS + 1];
431 	u32			nominal_c_mult;
432 	struct cyclecounter	cycles;
433 	seqlock_t		clock_lock;
434 	struct timecounter	clock;
435 	unsigned long		last_overflow_check;
436 	struct ptp_clock	*ptp_clock;
437 	struct ptp_clock_info	ptp_clock_info;
438 	struct notifier_block	nb;
439 };
440 
441 
442 struct mlx4_en_rss_map {
443 	int base_qpn;
444 	struct mlx4_qp qps[MAX_RX_RINGS];
445 	enum mlx4_qp_state state[MAX_RX_RINGS];
446 	struct mlx4_qp *indir_qp;
447 	enum mlx4_qp_state indir_state;
448 };
449 
450 enum mlx4_en_port_flag {
451 	MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */
452 	MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */
453 };
454 
455 struct mlx4_en_port_state {
456 	int link_state;
457 	int link_speed;
458 	int transceiver;
459 	u32 flags;
460 };
461 
462 enum mlx4_en_mclist_act {
463 	MCLIST_NONE,
464 	MCLIST_REM,
465 	MCLIST_ADD,
466 };
467 
468 struct mlx4_en_mc_list {
469 	struct list_head	list;
470 	enum mlx4_en_mclist_act	action;
471 	u8			addr[ETH_ALEN];
472 	u64			reg_id;
473 	u64			tunnel_reg_id;
474 };
475 
476 struct mlx4_en_frag_info {
477 	u16 frag_size;
478 	u32 frag_stride;
479 };
480 
481 #ifdef CONFIG_MLX4_EN_DCB
482 /* Minimal TC BW - setting to 0 will block traffic */
483 #define MLX4_EN_BW_MIN 1
484 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
485 
486 #define MLX4_EN_TC_VENDOR 0
487 #define MLX4_EN_TC_ETS 7
488 
489 enum dcb_pfc_type {
490 	pfc_disabled = 0,
491 	pfc_enabled_full,
492 	pfc_enabled_tx,
493 	pfc_enabled_rx
494 };
495 
496 struct mlx4_en_cee_config {
497 	bool	pfc_state;
498 	enum	dcb_pfc_type dcb_pfc[MLX4_EN_NUM_UP_HIGH];
499 };
500 #endif
501 
502 struct ethtool_flow_id {
503 	struct list_head list;
504 	struct ethtool_rx_flow_spec flow_spec;
505 	u64 id;
506 };
507 
508 enum {
509 	MLX4_EN_FLAG_PROMISC		= (1 << 0),
510 	MLX4_EN_FLAG_MC_PROMISC		= (1 << 1),
511 	/* whether we need to enable hardware loopback by putting dmac
512 	 * in Tx WQE
513 	 */
514 	MLX4_EN_FLAG_ENABLE_HW_LOOPBACK	= (1 << 2),
515 	/* whether we need to drop packets that hardware loopback-ed */
516 	MLX4_EN_FLAG_RX_FILTER_NEEDED	= (1 << 3),
517 	MLX4_EN_FLAG_FORCE_PROMISC	= (1 << 4),
518 	MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP	= (1 << 5),
519 #ifdef CONFIG_MLX4_EN_DCB
520 	MLX4_EN_FLAG_DCB_ENABLED        = (1 << 6),
521 #endif
522 };
523 
524 #define PORT_BEACON_MAX_LIMIT (65535)
525 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
526 #define MLX4_EN_MAC_HASH_IDX 5
527 
528 struct mlx4_en_stats_bitmap {
529 	DECLARE_BITMAP(bitmap, NUM_ALL_STATS);
530 	struct mutex mutex; /* for mutual access to stats bitmap */
531 };
532 
533 struct mlx4_en_priv {
534 	struct mlx4_en_dev *mdev;
535 	struct mlx4_en_port_profile *prof;
536 	struct net_device *dev;
537 	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
538 	struct mlx4_en_port_state port_state;
539 	spinlock_t stats_lock;
540 	struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
541 	/* To allow rules removal while port is going down */
542 	struct list_head ethtool_list;
543 
544 	unsigned long last_moder_packets[MAX_RX_RINGS];
545 	unsigned long last_moder_tx_packets;
546 	unsigned long last_moder_bytes[MAX_RX_RINGS];
547 	unsigned long last_moder_jiffies;
548 	int last_moder_time[MAX_RX_RINGS];
549 	u16 rx_usecs;
550 	u16 rx_frames;
551 	u16 tx_usecs;
552 	u16 tx_frames;
553 	u32 pkt_rate_low;
554 	u16 rx_usecs_low;
555 	u32 pkt_rate_high;
556 	u16 rx_usecs_high;
557 	u32 sample_interval;
558 	u32 adaptive_rx_coal;
559 	u32 msg_enable;
560 	u32 loopback_ok;
561 	u32 validate_loopback;
562 
563 	struct mlx4_hwq_resources res;
564 	int link_state;
565 	int last_link_state;
566 	bool port_up;
567 	int port;
568 	int registered;
569 	int allocated;
570 	int stride;
571 	unsigned char current_mac[ETH_ALEN + 2];
572 	int mac_index;
573 	unsigned max_mtu;
574 	int base_qpn;
575 	int cqe_factor;
576 	int cqe_size;
577 
578 	struct mlx4_en_rss_map rss_map;
579 	__be32 ctrl_flags;
580 	u32 flags;
581 	u8 num_tx_rings_p_up;
582 	u32 tx_work_limit;
583 	u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES];
584 	u32 rx_ring_num;
585 	u32 rx_skb_size;
586 	struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
587 	u8 num_frags;
588 	u8 log_rx_info;
589 	u8 dma_dir;
590 	u16 rx_headroom;
591 
592 	struct mlx4_en_tx_ring **tx_ring[MLX4_EN_NUM_TX_TYPES];
593 	struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS];
594 	struct mlx4_en_cq **tx_cq[MLX4_EN_NUM_TX_TYPES];
595 	struct mlx4_en_cq *rx_cq[MAX_RX_RINGS];
596 	struct mlx4_qp drop_qp;
597 	struct work_struct rx_mode_task;
598 	struct work_struct watchdog_task;
599 	struct work_struct linkstate_task;
600 	struct delayed_work stats_task;
601 	struct delayed_work service_task;
602 	struct work_struct vxlan_add_task;
603 	struct work_struct vxlan_del_task;
604 	struct mlx4_en_perf_stats pstats;
605 	struct mlx4_en_pkt_stats pkstats;
606 	struct mlx4_en_counter_stats pf_stats;
607 	struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES];
608 	struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES];
609 	struct mlx4_en_flow_stats_rx rx_flowstats;
610 	struct mlx4_en_flow_stats_tx tx_flowstats;
611 	struct mlx4_en_port_stats port_stats;
612 	struct mlx4_en_xdp_stats xdp_stats;
613 	struct mlx4_en_phy_stats phy_stats;
614 	struct mlx4_en_stats_bitmap stats_bitmap;
615 	struct list_head mc_list;
616 	struct list_head curr_list;
617 	u64 broadcast_id;
618 	struct mlx4_en_stat_out_mbox hw_stats;
619 	int vids[128];
620 	bool wol;
621 	struct device *ddev;
622 	struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE];
623 	struct hwtstamp_config hwtstamp_config;
624 	u32 counter_index;
625 
626 #ifdef CONFIG_MLX4_EN_DCB
627 #define MLX4_EN_DCB_ENABLED	0x3
628 	struct ieee_ets ets;
629 	u16 maxrate[IEEE_8021QAZ_MAX_TCS];
630 	enum dcbnl_cndd_states cndd_state[IEEE_8021QAZ_MAX_TCS];
631 	struct mlx4_en_cee_config cee_config;
632 	u8 dcbx_cap;
633 #endif
634 #ifdef CONFIG_RFS_ACCEL
635 	spinlock_t filters_lock;
636 	int last_filter_id;
637 	struct list_head filters;
638 	struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
639 #endif
640 	u64 tunnel_reg_id;
641 	__be16 vxlan_port;
642 
643 	u32 pflags;
644 	u8 rss_key[MLX4_EN_RSS_KEY_SIZE];
645 	u8 rss_hash_fn;
646 };
647 
648 enum mlx4_en_wol {
649 	MLX4_EN_WOL_MAGIC = (1ULL << 61),
650 	MLX4_EN_WOL_ENABLED = (1ULL << 62),
651 };
652 
653 struct mlx4_mac_entry {
654 	struct hlist_node hlist;
655 	unsigned char mac[ETH_ALEN + 2];
656 	u64 reg_id;
657 	struct rcu_head rcu;
658 };
659 
660 static inline struct mlx4_cqe *mlx4_en_get_cqe(void *buf, int idx, int cqe_sz)
661 {
662 	return buf + idx * cqe_sz;
663 }
664 
665 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
666 
667 void mlx4_en_init_ptys2ethtool_map(void);
668 void mlx4_en_update_loopback_state(struct net_device *dev,
669 				   netdev_features_t features);
670 
671 void mlx4_en_destroy_netdev(struct net_device *dev);
672 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
673 			struct mlx4_en_port_profile *prof);
674 
675 int mlx4_en_start_port(struct net_device *dev);
676 void mlx4_en_stop_port(struct net_device *dev, int detach);
677 
678 void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev,
679 			      struct mlx4_en_stats_bitmap *stats_bitmap,
680 			      u8 rx_ppp, u8 rx_pause,
681 			      u8 tx_ppp, u8 tx_pause);
682 
683 int mlx4_en_try_alloc_resources(struct mlx4_en_priv *priv,
684 				struct mlx4_en_priv *tmp,
685 				struct mlx4_en_port_profile *prof,
686 				bool carry_xdp_prog);
687 void mlx4_en_safe_replace_resources(struct mlx4_en_priv *priv,
688 				    struct mlx4_en_priv *tmp);
689 
690 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq,
691 		      int entries, int ring, enum cq_type mode, int node);
692 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq);
693 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
694 			int cq_idx);
695 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
696 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
697 void mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
698 
699 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
700 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
701 			 struct net_device *sb_dev,
702 			 select_queue_fallback_t fallback);
703 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
704 netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring,
705 			       struct mlx4_en_rx_alloc *frame,
706 			       struct mlx4_en_priv *priv, unsigned int length,
707 			       int tx_ind, bool *doorbell_pending);
708 void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring);
709 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring,
710 			struct mlx4_en_rx_alloc *frame);
711 
712 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
713 			   struct mlx4_en_tx_ring **pring,
714 			   u32 size, u16 stride,
715 			   int node, int queue_index);
716 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
717 			     struct mlx4_en_tx_ring **pring);
718 void mlx4_en_init_tx_xdp_ring_descs(struct mlx4_en_priv *priv,
719 				    struct mlx4_en_tx_ring *ring);
720 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
721 			     struct mlx4_en_tx_ring *ring,
722 			     int cq, int user_prio);
723 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
724 				struct mlx4_en_tx_ring *ring);
725 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev);
726 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv);
727 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
728 			   struct mlx4_en_rx_ring **pring,
729 			   u32 size, u16 stride, int node, int queue_index);
730 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
731 			     struct mlx4_en_rx_ring **pring,
732 			     u32 size, u16 stride);
733 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
734 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
735 				struct mlx4_en_rx_ring *ring);
736 int mlx4_en_process_rx_cq(struct net_device *dev,
737 			  struct mlx4_en_cq *cq,
738 			  int budget);
739 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
740 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget);
741 bool mlx4_en_process_tx_cq(struct net_device *dev,
742 			   struct mlx4_en_cq *cq, int napi_budget);
743 u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
744 			 struct mlx4_en_tx_ring *ring,
745 			 int index, u64 timestamp,
746 			 int napi_mode);
747 u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv,
748 			    struct mlx4_en_tx_ring *ring,
749 			    int index, u64 timestamp,
750 			    int napi_mode);
751 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
752 		int is_tx, int rss, int qpn, int cqn, int user_prio,
753 		struct mlx4_qp_context *context);
754 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
755 int mlx4_en_change_mcast_lb(struct mlx4_en_priv *priv, struct mlx4_qp *qp,
756 			    int loopback);
757 void mlx4_en_calc_rx_buf(struct net_device *dev);
758 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
759 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
760 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
761 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
762 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
763 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
764 
765 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
766 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
767 
768 void mlx4_en_fold_software_stats(struct net_device *dev);
769 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
770 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
771 
772 #ifdef CONFIG_MLX4_EN_DCB
773 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
774 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
775 #endif
776 
777 int mlx4_en_setup_tc(struct net_device *dev, u8 up);
778 int mlx4_en_alloc_tx_queue_per_tc(struct net_device *dev, u8 tc);
779 
780 #ifdef CONFIG_RFS_ACCEL
781 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv);
782 #endif
783 
784 #define MLX4_EN_NUM_SELF_TEST	5
785 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
786 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
787 
788 #define DEV_FEATURE_CHANGED(dev, new_features, feature) \
789 	((dev->features & feature) ^ (new_features & feature))
790 
791 int mlx4_en_reset_config(struct net_device *dev,
792 			 struct hwtstamp_config ts_config,
793 			 netdev_features_t new_features);
794 void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev,
795 				     struct mlx4_en_stats_bitmap *stats_bitmap,
796 				     u8 rx_ppp, u8 rx_pause,
797 				     u8 tx_ppp, u8 tx_pause);
798 int mlx4_en_netdev_event(struct notifier_block *this,
799 			 unsigned long event, void *ptr);
800 
801 /*
802  * Functions for time stamping
803  */
804 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
805 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev,
806 			    struct skb_shared_hwtstamps *hwts,
807 			    u64 timestamp);
808 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev);
809 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev);
810 
811 /* Globals
812  */
813 extern const struct ethtool_ops mlx4_en_ethtool_ops;
814 
815 
816 
817 /*
818  * printk / logging functions
819  */
820 
821 __printf(3, 4)
822 void en_print(const char *level, const struct mlx4_en_priv *priv,
823 	      const char *format, ...);
824 
825 #define en_dbg(mlevel, priv, format, ...)				\
826 do {									\
827 	if (NETIF_MSG_##mlevel & (priv)->msg_enable)			\
828 		en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__);	\
829 } while (0)
830 #define en_warn(priv, format, ...)					\
831 	en_print(KERN_WARNING, priv, format, ##__VA_ARGS__)
832 #define en_err(priv, format, ...)					\
833 	en_print(KERN_ERR, priv, format, ##__VA_ARGS__)
834 #define en_info(priv, format, ...)					\
835 	en_print(KERN_INFO, priv, format, ##__VA_ARGS__)
836 
837 #define mlx4_err(mdev, format, ...)					\
838 	pr_err(DRV_NAME " %s: " format,					\
839 	       dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
840 #define mlx4_info(mdev, format, ...)					\
841 	pr_info(DRV_NAME " %s: " format,				\
842 		dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
843 #define mlx4_warn(mdev, format, ...)					\
844 	pr_warn(DRV_NAME " %s: " format,				\
845 		dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
846 
847 #endif
848