1 /* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 #ifndef _MLX4_EN_H_ 35 #define _MLX4_EN_H_ 36 37 #include <linux/bitops.h> 38 #include <linux/compiler.h> 39 #include <linux/list.h> 40 #include <linux/mutex.h> 41 #include <linux/netdevice.h> 42 #include <linux/if_vlan.h> 43 #include <linux/net_tstamp.h> 44 #ifdef CONFIG_MLX4_EN_DCB 45 #include <linux/dcbnl.h> 46 #endif 47 #include <linux/cpu_rmap.h> 48 49 #include <linux/mlx4/device.h> 50 #include <linux/mlx4/qp.h> 51 #include <linux/mlx4/cq.h> 52 #include <linux/mlx4/srq.h> 53 #include <linux/mlx4/doorbell.h> 54 #include <linux/mlx4/cmd.h> 55 56 #include "en_port.h" 57 58 #define DRV_NAME "mlx4_en" 59 #define DRV_VERSION "2.0" 60 #define DRV_RELDATE "Dec 2011" 61 62 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN) 63 64 /* 65 * Device constants 66 */ 67 68 69 #define MLX4_EN_PAGE_SHIFT 12 70 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT) 71 #define DEF_RX_RINGS 16 72 #define MAX_RX_RINGS 128 73 #define MIN_RX_RINGS 4 74 #define TXBB_SIZE 64 75 #define HEADROOM (2048 / TXBB_SIZE + 1) 76 #define STAMP_STRIDE 64 77 #define STAMP_DWORDS (STAMP_STRIDE / 4) 78 #define STAMP_SHIFT 31 79 #define STAMP_VAL 0x7fffffff 80 #define STATS_DELAY (HZ / 4) 81 #define SERVICE_TASK_DELAY (HZ / 4) 82 #define MAX_NUM_OF_FS_RULES 256 83 84 #define MLX4_EN_FILTER_HASH_SHIFT 4 85 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60 86 87 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */ 88 #define MAX_DESC_SIZE 512 89 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE) 90 91 /* 92 * OS related constants and tunables 93 */ 94 95 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ) 96 97 /* Use the maximum between 16384 and a single page */ 98 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384) 99 100 #define MLX4_EN_ALLOC_PREFER_ORDER PAGE_ALLOC_COSTLY_ORDER 101 102 /* Receive fragment sizes; we use at most 3 fragments (for 9600 byte MTU 103 * and 4K allocations) */ 104 enum { 105 FRAG_SZ0 = 1536 - NET_IP_ALIGN, 106 FRAG_SZ1 = 4096, 107 FRAG_SZ2 = 4096, 108 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE 109 }; 110 #define MLX4_EN_MAX_RX_FRAGS 4 111 112 /* Maximum ring sizes */ 113 #define MLX4_EN_MAX_TX_SIZE 8192 114 #define MLX4_EN_MAX_RX_SIZE 8192 115 116 /* Minimum ring size for our page-allocation scheme to work */ 117 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES) 118 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE) 119 120 #define MLX4_EN_SMALL_PKT_SIZE 64 121 #define MLX4_EN_MAX_TX_RING_P_UP 32 122 #define MLX4_EN_NUM_UP 8 123 #define MLX4_EN_DEF_TX_RING_SIZE 512 124 #define MLX4_EN_DEF_RX_RING_SIZE 1024 125 #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \ 126 MLX4_EN_NUM_UP) 127 128 /* Target number of packets to coalesce with interrupt moderation */ 129 #define MLX4_EN_RX_COAL_TARGET 44 130 #define MLX4_EN_RX_COAL_TIME 0x10 131 132 #define MLX4_EN_TX_COAL_PKTS 16 133 #define MLX4_EN_TX_COAL_TIME 0x10 134 135 #define MLX4_EN_RX_RATE_LOW 400000 136 #define MLX4_EN_RX_COAL_TIME_LOW 0 137 #define MLX4_EN_RX_RATE_HIGH 450000 138 #define MLX4_EN_RX_COAL_TIME_HIGH 128 139 #define MLX4_EN_RX_SIZE_THRESH 1024 140 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH) 141 #define MLX4_EN_SAMPLE_INTERVAL 0 142 #define MLX4_EN_AVG_PKT_SMALL 256 143 144 #define MLX4_EN_AUTO_CONF 0xffff 145 146 #define MLX4_EN_DEF_RX_PAUSE 1 147 #define MLX4_EN_DEF_TX_PAUSE 1 148 149 /* Interval between successive polls in the Tx routine when polling is used 150 instead of interrupts (in per-core Tx rings) - should be power of 2 */ 151 #define MLX4_EN_TX_POLL_MODER 16 152 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4) 153 154 #define ETH_LLC_SNAP_SIZE 8 155 156 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN) 157 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN) 158 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN) 159 160 #define MLX4_EN_MIN_MTU 46 161 #define ETH_BCAST 0xffffffffffffULL 162 163 #define MLX4_EN_LOOPBACK_RETRIES 5 164 #define MLX4_EN_LOOPBACK_TIMEOUT 100 165 166 #ifdef MLX4_EN_PERF_STAT 167 /* Number of samples to 'average' */ 168 #define AVG_SIZE 128 169 #define AVG_FACTOR 1024 170 #define NUM_PERF_STATS NUM_PERF_COUNTERS 171 172 #define INC_PERF_COUNTER(cnt) (++(cnt)) 173 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add)) 174 #define AVG_PERF_COUNTER(cnt, sample) \ 175 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE) 176 #define GET_PERF_COUNTER(cnt) (cnt) 177 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR) 178 179 #else 180 181 #define NUM_PERF_STATS 0 182 #define INC_PERF_COUNTER(cnt) do {} while (0) 183 #define ADD_PERF_COUNTER(cnt, add) do {} while (0) 184 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0) 185 #define GET_PERF_COUNTER(cnt) (0) 186 #define GET_AVG_PERF_COUNTER(cnt) (0) 187 #endif /* MLX4_EN_PERF_STAT */ 188 189 /* 190 * Configurables 191 */ 192 193 enum cq_type { 194 RX = 0, 195 TX = 1, 196 }; 197 198 199 /* 200 * Useful macros 201 */ 202 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x)) 203 #define XNOR(x, y) (!(x) == !(y)) 204 205 206 struct mlx4_en_tx_info { 207 struct sk_buff *skb; 208 u32 nr_txbb; 209 u32 nr_bytes; 210 u8 linear; 211 u8 data_offset; 212 u8 inl; 213 u8 ts_requested; 214 }; 215 216 217 #define MLX4_EN_BIT_DESC_OWN 0x80000000 218 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg) 219 #define MLX4_EN_MEMTYPE_PAD 0x100 220 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg) 221 222 223 struct mlx4_en_tx_desc { 224 struct mlx4_wqe_ctrl_seg ctrl; 225 union { 226 struct mlx4_wqe_data_seg data; /* at least one data segment */ 227 struct mlx4_wqe_lso_seg lso; 228 struct mlx4_wqe_inline_seg inl; 229 }; 230 }; 231 232 #define MLX4_EN_USE_SRQ 0x01000000 233 234 #define MLX4_EN_CX3_LOW_ID 0x1000 235 #define MLX4_EN_CX3_HIGH_ID 0x1005 236 237 struct mlx4_en_rx_alloc { 238 struct page *page; 239 dma_addr_t dma; 240 u32 page_offset; 241 u32 page_size; 242 }; 243 244 struct mlx4_en_tx_ring { 245 struct mlx4_hwq_resources wqres; 246 u32 size ; /* number of TXBBs */ 247 u32 size_mask; 248 u16 stride; 249 u16 cqn; /* index of port CQ associated with this ring */ 250 u32 prod; 251 u32 cons; 252 u32 buf_size; 253 u32 doorbell_qpn; 254 void *buf; 255 u16 poll_cnt; 256 struct mlx4_en_tx_info *tx_info; 257 u8 *bounce_buf; 258 u32 last_nr_txbb; 259 struct mlx4_qp qp; 260 struct mlx4_qp_context context; 261 int qpn; 262 enum mlx4_qp_state qp_state; 263 struct mlx4_srq dummy; 264 unsigned long bytes; 265 unsigned long packets; 266 unsigned long tx_csum; 267 struct mlx4_bf bf; 268 bool bf_enabled; 269 struct netdev_queue *tx_queue; 270 int hwtstamp_tx_type; 271 }; 272 273 struct mlx4_en_rx_desc { 274 /* actual number of entries depends on rx ring stride */ 275 struct mlx4_wqe_data_seg data[0]; 276 }; 277 278 struct mlx4_en_rx_ring { 279 struct mlx4_hwq_resources wqres; 280 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS]; 281 u32 size ; /* number of Rx descs*/ 282 u32 actual_size; 283 u32 size_mask; 284 u16 stride; 285 u16 log_stride; 286 u16 cqn; /* index of port CQ associated with this ring */ 287 u32 prod; 288 u32 cons; 289 u32 buf_size; 290 u8 fcs_del; 291 void *buf; 292 void *rx_info; 293 unsigned long bytes; 294 unsigned long packets; 295 #ifdef CONFIG_NET_RX_BUSY_POLL 296 unsigned long yields; 297 unsigned long misses; 298 unsigned long cleaned; 299 #endif 300 unsigned long csum_ok; 301 unsigned long csum_none; 302 int hwtstamp_rx_filter; 303 }; 304 305 struct mlx4_en_cq { 306 struct mlx4_cq mcq; 307 struct mlx4_hwq_resources wqres; 308 int ring; 309 spinlock_t lock; 310 struct net_device *dev; 311 struct napi_struct napi; 312 int size; 313 int buf_size; 314 unsigned vector; 315 enum cq_type is_tx; 316 u16 moder_time; 317 u16 moder_cnt; 318 struct mlx4_cqe *buf; 319 #define MLX4_EN_OPCODE_ERROR 0x1e 320 321 #ifdef CONFIG_NET_RX_BUSY_POLL 322 unsigned int state; 323 #define MLX4_EN_CQ_STATE_IDLE 0 324 #define MLX4_EN_CQ_STATE_NAPI 1 /* NAPI owns this CQ */ 325 #define MLX4_EN_CQ_STATE_POLL 2 /* poll owns this CQ */ 326 #define MLX4_CQ_LOCKED (MLX4_EN_CQ_STATE_NAPI | MLX4_EN_CQ_STATE_POLL) 327 #define MLX4_EN_CQ_STATE_NAPI_YIELD 4 /* NAPI yielded this CQ */ 328 #define MLX4_EN_CQ_STATE_POLL_YIELD 8 /* poll yielded this CQ */ 329 #define CQ_YIELD (MLX4_EN_CQ_STATE_NAPI_YIELD | MLX4_EN_CQ_STATE_POLL_YIELD) 330 #define CQ_USER_PEND (MLX4_EN_CQ_STATE_POLL | MLX4_EN_CQ_STATE_POLL_YIELD) 331 spinlock_t poll_lock; /* protects from LLS/napi conflicts */ 332 #endif /* CONFIG_NET_RX_BUSY_POLL */ 333 }; 334 335 struct mlx4_en_port_profile { 336 u32 flags; 337 u32 tx_ring_num; 338 u32 rx_ring_num; 339 u32 tx_ring_size; 340 u32 rx_ring_size; 341 u8 rx_pause; 342 u8 rx_ppp; 343 u8 tx_pause; 344 u8 tx_ppp; 345 int rss_rings; 346 }; 347 348 struct mlx4_en_profile { 349 int rss_xor; 350 int udp_rss; 351 u8 rss_mask; 352 u32 active_ports; 353 u32 small_pkt_int; 354 u8 no_reset; 355 u8 num_tx_rings_p_up; 356 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1]; 357 }; 358 359 struct mlx4_en_dev { 360 struct mlx4_dev *dev; 361 struct pci_dev *pdev; 362 struct mutex state_lock; 363 struct net_device *pndev[MLX4_MAX_PORTS + 1]; 364 u32 port_cnt; 365 bool device_up; 366 struct mlx4_en_profile profile; 367 u32 LSO_support; 368 struct workqueue_struct *workqueue; 369 struct device *dma_device; 370 void __iomem *uar_map; 371 struct mlx4_uar priv_uar; 372 struct mlx4_mr mr; 373 u32 priv_pdn; 374 spinlock_t uar_lock; 375 u8 mac_removed[MLX4_MAX_PORTS + 1]; 376 struct cyclecounter cycles; 377 struct timecounter clock; 378 unsigned long last_overflow_check; 379 unsigned long overflow_period; 380 }; 381 382 383 struct mlx4_en_rss_map { 384 int base_qpn; 385 struct mlx4_qp qps[MAX_RX_RINGS]; 386 enum mlx4_qp_state state[MAX_RX_RINGS]; 387 struct mlx4_qp indir_qp; 388 enum mlx4_qp_state indir_state; 389 }; 390 391 struct mlx4_en_port_state { 392 int link_state; 393 int link_speed; 394 int transciver; 395 }; 396 397 struct mlx4_en_pkt_stats { 398 unsigned long broadcast; 399 unsigned long rx_prio[8]; 400 unsigned long tx_prio[8]; 401 #define NUM_PKT_STATS 17 402 }; 403 404 struct mlx4_en_port_stats { 405 unsigned long tso_packets; 406 unsigned long queue_stopped; 407 unsigned long wake_queue; 408 unsigned long tx_timeout; 409 unsigned long rx_alloc_failed; 410 unsigned long rx_chksum_good; 411 unsigned long rx_chksum_none; 412 unsigned long tx_chksum_offload; 413 #define NUM_PORT_STATS 8 414 }; 415 416 struct mlx4_en_perf_stats { 417 u32 tx_poll; 418 u64 tx_pktsz_avg; 419 u32 inflight_avg; 420 u16 tx_coal_avg; 421 u16 rx_coal_avg; 422 u32 napi_quota; 423 #define NUM_PERF_COUNTERS 6 424 }; 425 426 enum mlx4_en_mclist_act { 427 MCLIST_NONE, 428 MCLIST_REM, 429 MCLIST_ADD, 430 }; 431 432 struct mlx4_en_mc_list { 433 struct list_head list; 434 enum mlx4_en_mclist_act action; 435 u8 addr[ETH_ALEN]; 436 u64 reg_id; 437 }; 438 439 struct mlx4_en_frag_info { 440 u16 frag_size; 441 u16 frag_prefix_size; 442 u16 frag_stride; 443 u16 frag_align; 444 }; 445 446 #ifdef CONFIG_MLX4_EN_DCB 447 /* Minimal TC BW - setting to 0 will block traffic */ 448 #define MLX4_EN_BW_MIN 1 449 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */ 450 451 #define MLX4_EN_TC_ETS 7 452 453 #endif 454 455 struct ethtool_flow_id { 456 struct list_head list; 457 struct ethtool_rx_flow_spec flow_spec; 458 u64 id; 459 }; 460 461 enum { 462 MLX4_EN_FLAG_PROMISC = (1 << 0), 463 MLX4_EN_FLAG_MC_PROMISC = (1 << 1), 464 /* whether we need to enable hardware loopback by putting dmac 465 * in Tx WQE 466 */ 467 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2), 468 /* whether we need to drop packets that hardware loopback-ed */ 469 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3), 470 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4) 471 }; 472 473 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE) 474 #define MLX4_EN_MAC_HASH_IDX 5 475 476 struct mlx4_en_priv { 477 struct mlx4_en_dev *mdev; 478 struct mlx4_en_port_profile *prof; 479 struct net_device *dev; 480 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 481 struct net_device_stats stats; 482 struct net_device_stats ret_stats; 483 struct mlx4_en_port_state port_state; 484 spinlock_t stats_lock; 485 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES]; 486 /* To allow rules removal while port is going down */ 487 struct list_head ethtool_list; 488 489 unsigned long last_moder_packets[MAX_RX_RINGS]; 490 unsigned long last_moder_tx_packets; 491 unsigned long last_moder_bytes[MAX_RX_RINGS]; 492 unsigned long last_moder_jiffies; 493 int last_moder_time[MAX_RX_RINGS]; 494 u16 rx_usecs; 495 u16 rx_frames; 496 u16 tx_usecs; 497 u16 tx_frames; 498 u32 pkt_rate_low; 499 u16 rx_usecs_low; 500 u32 pkt_rate_high; 501 u16 rx_usecs_high; 502 u16 sample_interval; 503 u16 adaptive_rx_coal; 504 u32 msg_enable; 505 u32 loopback_ok; 506 u32 validate_loopback; 507 508 struct mlx4_hwq_resources res; 509 int link_state; 510 int last_link_state; 511 bool port_up; 512 int port; 513 int registered; 514 int allocated; 515 int stride; 516 unsigned char prev_mac[ETH_ALEN + 2]; 517 int mac_index; 518 unsigned max_mtu; 519 int base_qpn; 520 int cqe_factor; 521 522 struct mlx4_en_rss_map rss_map; 523 __be32 ctrl_flags; 524 u32 flags; 525 u8 num_tx_rings_p_up; 526 u32 tx_ring_num; 527 u32 rx_ring_num; 528 u32 rx_skb_size; 529 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS]; 530 u16 num_frags; 531 u16 log_rx_info; 532 533 struct mlx4_en_tx_ring **tx_ring; 534 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS]; 535 struct mlx4_en_cq **tx_cq; 536 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS]; 537 struct mlx4_qp drop_qp; 538 struct work_struct rx_mode_task; 539 struct work_struct watchdog_task; 540 struct work_struct linkstate_task; 541 struct delayed_work stats_task; 542 struct delayed_work service_task; 543 struct mlx4_en_perf_stats pstats; 544 struct mlx4_en_pkt_stats pkstats; 545 struct mlx4_en_port_stats port_stats; 546 u64 stats_bitmap; 547 struct list_head mc_list; 548 struct list_head curr_list; 549 u64 broadcast_id; 550 struct mlx4_en_stat_out_mbox hw_stats; 551 int vids[128]; 552 bool wol; 553 struct device *ddev; 554 int base_tx_qpn; 555 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE]; 556 struct hwtstamp_config hwtstamp_config; 557 558 #ifdef CONFIG_MLX4_EN_DCB 559 struct ieee_ets ets; 560 u16 maxrate[IEEE_8021QAZ_MAX_TCS]; 561 #endif 562 #ifdef CONFIG_RFS_ACCEL 563 spinlock_t filters_lock; 564 int last_filter_id; 565 struct list_head filters; 566 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT]; 567 #endif 568 569 }; 570 571 enum mlx4_en_wol { 572 MLX4_EN_WOL_MAGIC = (1ULL << 61), 573 MLX4_EN_WOL_ENABLED = (1ULL << 62), 574 }; 575 576 struct mlx4_mac_entry { 577 struct hlist_node hlist; 578 unsigned char mac[ETH_ALEN + 2]; 579 u64 reg_id; 580 struct rcu_head rcu; 581 }; 582 583 #ifdef CONFIG_NET_RX_BUSY_POLL 584 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq) 585 { 586 spin_lock_init(&cq->poll_lock); 587 cq->state = MLX4_EN_CQ_STATE_IDLE; 588 } 589 590 /* called from the device poll rutine to get ownership of a cq */ 591 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq) 592 { 593 int rc = true; 594 spin_lock(&cq->poll_lock); 595 if (cq->state & MLX4_CQ_LOCKED) { 596 WARN_ON(cq->state & MLX4_EN_CQ_STATE_NAPI); 597 cq->state |= MLX4_EN_CQ_STATE_NAPI_YIELD; 598 rc = false; 599 } else 600 /* we don't care if someone yielded */ 601 cq->state = MLX4_EN_CQ_STATE_NAPI; 602 spin_unlock(&cq->poll_lock); 603 return rc; 604 } 605 606 /* returns true is someone tried to get the cq while napi had it */ 607 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq) 608 { 609 int rc = false; 610 spin_lock(&cq->poll_lock); 611 WARN_ON(cq->state & (MLX4_EN_CQ_STATE_POLL | 612 MLX4_EN_CQ_STATE_NAPI_YIELD)); 613 614 if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD) 615 rc = true; 616 cq->state = MLX4_EN_CQ_STATE_IDLE; 617 spin_unlock(&cq->poll_lock); 618 return rc; 619 } 620 621 /* called from mlx4_en_low_latency_poll() */ 622 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq) 623 { 624 int rc = true; 625 spin_lock_bh(&cq->poll_lock); 626 if ((cq->state & MLX4_CQ_LOCKED)) { 627 struct net_device *dev = cq->dev; 628 struct mlx4_en_priv *priv = netdev_priv(dev); 629 struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring]; 630 631 cq->state |= MLX4_EN_CQ_STATE_POLL_YIELD; 632 rc = false; 633 rx_ring->yields++; 634 } else 635 /* preserve yield marks */ 636 cq->state |= MLX4_EN_CQ_STATE_POLL; 637 spin_unlock_bh(&cq->poll_lock); 638 return rc; 639 } 640 641 /* returns true if someone tried to get the cq while it was locked */ 642 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq) 643 { 644 int rc = false; 645 spin_lock_bh(&cq->poll_lock); 646 WARN_ON(cq->state & (MLX4_EN_CQ_STATE_NAPI)); 647 648 if (cq->state & MLX4_EN_CQ_STATE_POLL_YIELD) 649 rc = true; 650 cq->state = MLX4_EN_CQ_STATE_IDLE; 651 spin_unlock_bh(&cq->poll_lock); 652 return rc; 653 } 654 655 /* true if a socket is polling, even if it did not get the lock */ 656 static inline bool mlx4_en_cq_ll_polling(struct mlx4_en_cq *cq) 657 { 658 WARN_ON(!(cq->state & MLX4_CQ_LOCKED)); 659 return cq->state & CQ_USER_PEND; 660 } 661 #else 662 static inline void mlx4_en_cq_init_lock(struct mlx4_en_cq *cq) 663 { 664 } 665 666 static inline bool mlx4_en_cq_lock_napi(struct mlx4_en_cq *cq) 667 { 668 return true; 669 } 670 671 static inline bool mlx4_en_cq_unlock_napi(struct mlx4_en_cq *cq) 672 { 673 return false; 674 } 675 676 static inline bool mlx4_en_cq_lock_poll(struct mlx4_en_cq *cq) 677 { 678 return false; 679 } 680 681 static inline bool mlx4_en_cq_unlock_poll(struct mlx4_en_cq *cq) 682 { 683 return false; 684 } 685 686 static inline bool mlx4_en_cq_ll_polling(struct mlx4_en_cq *cq) 687 { 688 return false; 689 } 690 #endif /* CONFIG_NET_RX_BUSY_POLL */ 691 692 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63) 693 694 void mlx4_en_update_loopback_state(struct net_device *dev, 695 netdev_features_t features); 696 697 void mlx4_en_destroy_netdev(struct net_device *dev); 698 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, 699 struct mlx4_en_port_profile *prof); 700 701 int mlx4_en_start_port(struct net_device *dev); 702 void mlx4_en_stop_port(struct net_device *dev, int detach); 703 704 void mlx4_en_free_resources(struct mlx4_en_priv *priv); 705 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv); 706 707 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq, 708 int entries, int ring, enum cq_type mode, int node); 709 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq); 710 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq, 711 int cq_idx); 712 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 713 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 714 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 715 716 void mlx4_en_tx_irq(struct mlx4_cq *mcq); 717 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, 718 void *accel_priv); 719 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev); 720 721 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, 722 struct mlx4_en_tx_ring **pring, 723 int qpn, u32 size, u16 stride, int node); 724 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, 725 struct mlx4_en_tx_ring **pring); 726 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 727 struct mlx4_en_tx_ring *ring, 728 int cq, int user_prio); 729 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 730 struct mlx4_en_tx_ring *ring); 731 732 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 733 struct mlx4_en_rx_ring **pring, 734 u32 size, u16 stride, int node); 735 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 736 struct mlx4_en_rx_ring **pring, 737 u32 size, u16 stride); 738 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv); 739 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, 740 struct mlx4_en_rx_ring *ring); 741 int mlx4_en_process_rx_cq(struct net_device *dev, 742 struct mlx4_en_cq *cq, 743 int budget); 744 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget); 745 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, 746 int is_tx, int rss, int qpn, int cqn, int user_prio, 747 struct mlx4_qp_context *context); 748 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event); 749 int mlx4_en_map_buffer(struct mlx4_buf *buf); 750 void mlx4_en_unmap_buffer(struct mlx4_buf *buf); 751 752 void mlx4_en_calc_rx_buf(struct net_device *dev); 753 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv); 754 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv); 755 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv); 756 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv); 757 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring); 758 void mlx4_en_rx_irq(struct mlx4_cq *mcq); 759 760 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 761 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv); 762 763 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset); 764 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port); 765 766 #ifdef CONFIG_MLX4_EN_DCB 767 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops; 768 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops; 769 #endif 770 771 int mlx4_en_setup_tc(struct net_device *dev, u8 up); 772 773 #ifdef CONFIG_RFS_ACCEL 774 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv); 775 #endif 776 777 #define MLX4_EN_NUM_SELF_TEST 5 778 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf); 779 u64 mlx4_en_mac_to_u64(u8 *addr); 780 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev); 781 782 /* 783 * Functions for time stamping 784 */ 785 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe); 786 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev, 787 struct skb_shared_hwtstamps *hwts, 788 u64 timestamp); 789 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev); 790 int mlx4_en_timestamp_config(struct net_device *dev, 791 int tx_type, 792 int rx_filter); 793 794 /* Globals 795 */ 796 extern const struct ethtool_ops mlx4_en_ethtool_ops; 797 798 799 800 /* 801 * printk / logging functions 802 */ 803 804 __printf(3, 4) 805 int en_print(const char *level, const struct mlx4_en_priv *priv, 806 const char *format, ...); 807 808 #define en_dbg(mlevel, priv, format, arg...) \ 809 do { \ 810 if (NETIF_MSG_##mlevel & priv->msg_enable) \ 811 en_print(KERN_DEBUG, priv, format, ##arg); \ 812 } while (0) 813 #define en_warn(priv, format, arg...) \ 814 en_print(KERN_WARNING, priv, format, ##arg) 815 #define en_err(priv, format, arg...) \ 816 en_print(KERN_ERR, priv, format, ##arg) 817 #define en_info(priv, format, arg...) \ 818 en_print(KERN_INFO, priv, format, ## arg) 819 820 #define mlx4_err(mdev, format, arg...) \ 821 pr_err("%s %s: " format, DRV_NAME, \ 822 dev_name(&mdev->pdev->dev), ##arg) 823 #define mlx4_info(mdev, format, arg...) \ 824 pr_info("%s %s: " format, DRV_NAME, \ 825 dev_name(&mdev->pdev->dev), ##arg) 826 #define mlx4_warn(mdev, format, arg...) \ 827 pr_warning("%s %s: " format, DRV_NAME, \ 828 dev_name(&mdev->pdev->dev), ##arg) 829 830 #endif 831