1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved. 5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved. 7 * 8 * This software is available to you under a choice of one of two 9 * licenses. You may choose to be licensed under the terms of the GNU 10 * General Public License (GPL) Version 2, available from the file 11 * COPYING in the main directory of this source tree, or the 12 * OpenIB.org BSD license below: 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * - Redistributions of source code must retain the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer. 21 * 22 * - Redistributions in binary form must reproduce the above 23 * copyright notice, this list of conditions and the following 24 * disclaimer in the documentation and/or other materials 25 * provided with the distribution. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 * SOFTWARE. 35 */ 36 37 #ifndef MLX4_H 38 #define MLX4_H 39 40 #include <linux/mutex.h> 41 #include <linux/radix-tree.h> 42 #include <linux/rbtree.h> 43 #include <linux/timer.h> 44 #include <linux/semaphore.h> 45 #include <linux/workqueue.h> 46 #include <linux/interrupt.h> 47 #include <linux/spinlock.h> 48 49 #include <linux/mlx4/device.h> 50 #include <linux/mlx4/driver.h> 51 #include <linux/mlx4/doorbell.h> 52 #include <linux/mlx4/cmd.h> 53 #include "fw_qos.h" 54 55 #define DRV_NAME "mlx4_core" 56 #define PFX DRV_NAME ": " 57 #define DRV_VERSION "2.2-1" 58 #define DRV_RELDATE "Feb, 2014" 59 60 #define MLX4_FS_UDP_UC_EN (1 << 1) 61 #define MLX4_FS_TCP_UC_EN (1 << 2) 62 #define MLX4_FS_NUM_OF_L2_ADDR 8 63 #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7 64 #define MLX4_FS_NUM_MCG (1 << 17) 65 66 #define INIT_HCA_TPT_MW_ENABLE (1 << 7) 67 68 #define MLX4_QUERY_IF_STAT_RESET BIT(31) 69 70 enum { 71 MLX4_HCR_BASE = 0x80680, 72 MLX4_HCR_SIZE = 0x0001c, 73 MLX4_CLR_INT_SIZE = 0x00008, 74 MLX4_SLAVE_COMM_BASE = 0x0, 75 MLX4_COMM_PAGESIZE = 0x1000, 76 MLX4_CLOCK_SIZE = 0x00008, 77 MLX4_COMM_CHAN_CAPS = 0x8, 78 MLX4_COMM_CHAN_FLAGS = 0xc 79 }; 80 81 enum { 82 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10, 83 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7, 84 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12, 85 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2), 86 MLX4_MTT_ENTRY_PER_SEG = 8, 87 }; 88 89 enum { 90 MLX4_NUM_PDS = 1 << 15 91 }; 92 93 enum { 94 MLX4_CMPT_TYPE_QP = 0, 95 MLX4_CMPT_TYPE_SRQ = 1, 96 MLX4_CMPT_TYPE_CQ = 2, 97 MLX4_CMPT_TYPE_EQ = 3, 98 MLX4_CMPT_NUM_TYPE 99 }; 100 101 enum { 102 MLX4_CMPT_SHIFT = 24, 103 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT 104 }; 105 106 enum mlx4_mpt_state { 107 MLX4_MPT_DISABLED = 0, 108 MLX4_MPT_EN_HW, 109 MLX4_MPT_EN_SW 110 }; 111 112 #define MLX4_COMM_TIME 10000 113 #define MLX4_COMM_OFFLINE_TIME_OUT 30000 114 #define MLX4_COMM_CMD_NA_OP 0x0 115 116 117 enum { 118 MLX4_COMM_CMD_RESET, 119 MLX4_COMM_CMD_VHCR0, 120 MLX4_COMM_CMD_VHCR1, 121 MLX4_COMM_CMD_VHCR2, 122 MLX4_COMM_CMD_VHCR_EN, 123 MLX4_COMM_CMD_VHCR_POST, 124 MLX4_COMM_CMD_FLR = 254 125 }; 126 127 enum { 128 MLX4_VF_SMI_DISABLED, 129 MLX4_VF_SMI_ENABLED 130 }; 131 132 /*The flag indicates that the slave should delay the RESET cmd*/ 133 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb 134 /*indicates how many retries will be done if we are in the middle of FLR*/ 135 #define NUM_OF_RESET_RETRIES 10 136 #define SLEEP_TIME_IN_RESET (2 * 1000) 137 enum mlx4_resource { 138 RES_QP, 139 RES_CQ, 140 RES_SRQ, 141 RES_XRCD, 142 RES_MPT, 143 RES_MTT, 144 RES_MAC, 145 RES_VLAN, 146 RES_EQ, 147 RES_COUNTER, 148 RES_FS_RULE, 149 MLX4_NUM_OF_RESOURCE_TYPE 150 }; 151 152 enum mlx4_alloc_mode { 153 RES_OP_RESERVE, 154 RES_OP_RESERVE_AND_MAP, 155 RES_OP_MAP_ICM, 156 }; 157 158 enum mlx4_res_tracker_free_type { 159 RES_TR_FREE_ALL, 160 RES_TR_FREE_SLAVES_ONLY, 161 RES_TR_FREE_STRUCTS_ONLY, 162 }; 163 164 /* 165 *Virtual HCR structures. 166 * mlx4_vhcr is the sw representation, in machine endianness 167 * 168 * mlx4_vhcr_cmd is the formalized structure, the one that is passed 169 * to FW to go through communication channel. 170 * It is big endian, and has the same structure as the physical HCR 171 * used by command interface 172 */ 173 struct mlx4_vhcr { 174 u64 in_param; 175 u64 out_param; 176 u32 in_modifier; 177 u32 errno; 178 u16 op; 179 u16 token; 180 u8 op_modifier; 181 u8 e_bit; 182 }; 183 184 struct mlx4_vhcr_cmd { 185 __be64 in_param; 186 __be32 in_modifier; 187 u32 reserved1; 188 __be64 out_param; 189 __be16 token; 190 u16 reserved; 191 u8 status; 192 u8 flags; 193 __be16 opcode; 194 }; 195 196 struct mlx4_cmd_info { 197 u16 opcode; 198 bool has_inbox; 199 bool has_outbox; 200 bool out_is_imm; 201 bool encode_slave_id; 202 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 203 struct mlx4_cmd_mailbox *inbox); 204 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 205 struct mlx4_cmd_mailbox *inbox, 206 struct mlx4_cmd_mailbox *outbox, 207 struct mlx4_cmd_info *cmd); 208 }; 209 210 #ifdef CONFIG_MLX4_DEBUG 211 extern int mlx4_debug_level; 212 #else /* CONFIG_MLX4_DEBUG */ 213 #define mlx4_debug_level (0) 214 #endif /* CONFIG_MLX4_DEBUG */ 215 216 #define mlx4_dbg(mdev, format, ...) \ 217 do { \ 218 if (mlx4_debug_level) \ 219 dev_printk(KERN_DEBUG, \ 220 &(mdev)->persist->pdev->dev, format, \ 221 ##__VA_ARGS__); \ 222 } while (0) 223 224 #define mlx4_err(mdev, format, ...) \ 225 dev_err(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__) 226 #define mlx4_info(mdev, format, ...) \ 227 dev_info(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__) 228 #define mlx4_warn(mdev, format, ...) \ 229 dev_warn(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__) 230 231 extern int mlx4_log_num_mgm_entry_size; 232 extern int log_mtts_per_seg; 233 extern int mlx4_internal_err_reset; 234 235 #define MLX4_MAX_NUM_SLAVES (min(MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF, \ 236 MLX4_MFUNC_MAX)) 237 #define ALL_SLAVES 0xff 238 239 struct mlx4_bitmap { 240 u32 last; 241 u32 top; 242 u32 max; 243 u32 reserved_top; 244 u32 mask; 245 u32 avail; 246 u32 effective_len; 247 spinlock_t lock; 248 unsigned long *table; 249 }; 250 251 struct mlx4_buddy { 252 unsigned long **bits; 253 unsigned int *num_free; 254 u32 max_order; 255 spinlock_t lock; 256 }; 257 258 struct mlx4_icm; 259 260 struct mlx4_icm_table { 261 u64 virt; 262 int num_icm; 263 u32 num_obj; 264 int obj_size; 265 int lowmem; 266 int coherent; 267 struct mutex mutex; 268 struct mlx4_icm **icm; 269 }; 270 271 #define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28) 272 #define MLX4_MPT_FLAG_FREE (0x3UL << 28) 273 #define MLX4_MPT_FLAG_MIO (1 << 17) 274 #define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15) 275 #define MLX4_MPT_FLAG_PHYSICAL (1 << 9) 276 #define MLX4_MPT_FLAG_REGION (1 << 8) 277 278 #define MLX4_MPT_PD_MASK (0x1FFFFUL) 279 #define MLX4_MPT_PD_VF_MASK (0xFE0000UL) 280 #define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27) 281 #define MLX4_MPT_PD_FLAG_RAE (1 << 28) 282 #define MLX4_MPT_PD_FLAG_EN_INV (3 << 24) 283 284 #define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7) 285 286 #define MLX4_MPT_STATUS_SW 0xF0 287 #define MLX4_MPT_STATUS_HW 0x00 288 289 #define MLX4_CQE_SIZE_MASK_STRIDE 0x3 290 #define MLX4_EQE_SIZE_MASK_STRIDE 0x30 291 292 #define MLX4_EQ_ASYNC 0 293 #define MLX4_EQ_TO_CQ_VECTOR(vector) ((vector) - \ 294 !!((int)(vector) >= MLX4_EQ_ASYNC)) 295 #define MLX4_CQ_TO_EQ_VECTOR(vector) ((vector) + \ 296 !!((int)(vector) >= MLX4_EQ_ASYNC)) 297 298 /* 299 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits. 300 */ 301 struct mlx4_mpt_entry { 302 __be32 flags; 303 __be32 qpn; 304 __be32 key; 305 __be32 pd_flags; 306 __be64 start; 307 __be64 length; 308 __be32 lkey; 309 __be32 win_cnt; 310 u8 reserved1[3]; 311 u8 mtt_rep; 312 __be64 mtt_addr; 313 __be32 mtt_sz; 314 __be32 entity_size; 315 __be32 first_byte_offset; 316 } __packed; 317 318 /* 319 * Must be packed because start is 64 bits but only aligned to 32 bits. 320 */ 321 struct mlx4_eq_context { 322 __be32 flags; 323 u16 reserved1[3]; 324 __be16 page_offset; 325 u8 log_eq_size; 326 u8 reserved2[4]; 327 u8 eq_period; 328 u8 reserved3; 329 u8 eq_max_count; 330 u8 reserved4[3]; 331 u8 intr; 332 u8 log_page_size; 333 u8 reserved5[2]; 334 u8 mtt_base_addr_h; 335 __be32 mtt_base_addr_l; 336 u32 reserved6[2]; 337 __be32 consumer_index; 338 __be32 producer_index; 339 u32 reserved7[4]; 340 }; 341 342 struct mlx4_cq_context { 343 __be32 flags; 344 u16 reserved1[3]; 345 __be16 page_offset; 346 __be32 logsize_usrpage; 347 __be16 cq_period; 348 __be16 cq_max_count; 349 u8 reserved2[3]; 350 u8 comp_eqn; 351 u8 log_page_size; 352 u8 reserved3[2]; 353 u8 mtt_base_addr_h; 354 __be32 mtt_base_addr_l; 355 __be32 last_notified_index; 356 __be32 solicit_producer_index; 357 __be32 consumer_index; 358 __be32 producer_index; 359 u32 reserved4[2]; 360 __be64 db_rec_addr; 361 }; 362 363 struct mlx4_srq_context { 364 __be32 state_logsize_srqn; 365 u8 logstride; 366 u8 reserved1; 367 __be16 xrcd; 368 __be32 pg_offset_cqn; 369 u32 reserved2; 370 u8 log_page_size; 371 u8 reserved3[2]; 372 u8 mtt_base_addr_h; 373 __be32 mtt_base_addr_l; 374 __be32 pd; 375 __be16 limit_watermark; 376 __be16 wqe_cnt; 377 u16 reserved4; 378 __be16 wqe_counter; 379 u32 reserved5; 380 __be64 db_rec_addr; 381 }; 382 383 struct mlx4_eq_tasklet { 384 struct list_head list; 385 struct list_head process_list; 386 struct tasklet_struct task; 387 /* lock on completion tasklet list */ 388 spinlock_t lock; 389 }; 390 391 struct mlx4_eq { 392 struct mlx4_dev *dev; 393 void __iomem *doorbell; 394 int eqn; 395 u32 cons_index; 396 u16 irq; 397 u16 have_irq; 398 int nent; 399 struct mlx4_buf_list *page_list; 400 struct mlx4_mtt mtt; 401 struct mlx4_eq_tasklet tasklet_ctx; 402 struct mlx4_active_ports actv_ports; 403 u32 ref_count; 404 cpumask_var_t affinity_mask; 405 }; 406 407 struct mlx4_slave_eqe { 408 u8 type; 409 u8 port; 410 u32 param; 411 }; 412 413 struct mlx4_slave_event_eq_info { 414 int eqn; 415 u16 token; 416 }; 417 418 struct mlx4_profile { 419 int num_qp; 420 int rdmarc_per_qp; 421 int num_srq; 422 int num_cq; 423 int num_mcg; 424 int num_mpt; 425 unsigned num_mtt; 426 }; 427 428 struct mlx4_fw { 429 u64 clr_int_base; 430 u64 catas_offset; 431 u64 comm_base; 432 u64 clock_offset; 433 struct mlx4_icm *fw_icm; 434 struct mlx4_icm *aux_icm; 435 u32 catas_size; 436 u16 fw_pages; 437 u8 clr_int_bar; 438 u8 catas_bar; 439 u8 comm_bar; 440 u8 clock_bar; 441 }; 442 443 struct mlx4_comm { 444 u32 slave_write; 445 u32 slave_read; 446 }; 447 448 enum { 449 MLX4_MCAST_CONFIG = 0, 450 MLX4_MCAST_DISABLE = 1, 451 MLX4_MCAST_ENABLE = 2, 452 }; 453 454 #define VLAN_FLTR_SIZE 128 455 456 struct mlx4_vlan_fltr { 457 __be32 entry[VLAN_FLTR_SIZE]; 458 }; 459 460 struct mlx4_mcast_entry { 461 struct list_head list; 462 u64 addr; 463 }; 464 465 struct mlx4_promisc_qp { 466 struct list_head list; 467 u32 qpn; 468 }; 469 470 struct mlx4_steer_index { 471 struct list_head list; 472 unsigned int index; 473 struct list_head duplicates; 474 }; 475 476 #define MLX4_EVENT_TYPES_NUM 64 477 478 struct mlx4_slave_state { 479 u8 comm_toggle; 480 u8 last_cmd; 481 u8 init_port_mask; 482 bool active; 483 bool old_vlan_api; 484 u8 function; 485 dma_addr_t vhcr_dma; 486 u16 mtu[MLX4_MAX_PORTS + 1]; 487 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1]; 488 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES]; 489 struct list_head mcast_filters[MLX4_MAX_PORTS + 1]; 490 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1]; 491 /* event type to eq number lookup */ 492 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM]; 493 u16 eq_pi; 494 u16 eq_ci; 495 spinlock_t lock; 496 /*initialized via the kzalloc*/ 497 u8 is_slave_going_down; 498 u32 cookie; 499 enum slave_port_state port_state[MLX4_MAX_PORTS + 1]; 500 }; 501 502 #define MLX4_VGT 4095 503 #define NO_INDX (-1) 504 505 struct mlx4_vport_state { 506 u64 mac; 507 u16 default_vlan; 508 u8 default_qos; 509 u32 tx_rate; 510 bool spoofchk; 511 u32 link_state; 512 u8 qos_vport; 513 __be64 guid; 514 }; 515 516 struct mlx4_vf_admin_state { 517 struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1]; 518 u8 enable_smi[MLX4_MAX_PORTS + 1]; 519 }; 520 521 struct mlx4_vport_oper_state { 522 struct mlx4_vport_state state; 523 int mac_idx; 524 int vlan_idx; 525 }; 526 527 struct mlx4_vf_oper_state { 528 struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1]; 529 u8 smi_enabled[MLX4_MAX_PORTS + 1]; 530 }; 531 532 struct slave_list { 533 struct mutex mutex; 534 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE]; 535 }; 536 537 struct resource_allocator { 538 spinlock_t alloc_lock; /* protect quotas */ 539 union { 540 int res_reserved; 541 int res_port_rsvd[MLX4_MAX_PORTS]; 542 }; 543 union { 544 int res_free; 545 int res_port_free[MLX4_MAX_PORTS]; 546 }; 547 int *quota; 548 int *allocated; 549 int *guaranteed; 550 }; 551 552 struct mlx4_resource_tracker { 553 spinlock_t lock; 554 /* tree for each resources */ 555 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE]; 556 /* num_of_slave's lists, one per slave */ 557 struct slave_list *slave_list; 558 struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE]; 559 }; 560 561 #define SLAVE_EVENT_EQ_SIZE 128 562 struct mlx4_slave_event_eq { 563 u32 eqn; 564 u32 cons; 565 u32 prod; 566 spinlock_t event_lock; 567 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE]; 568 }; 569 570 struct mlx4_qos_manager { 571 int num_of_qos_vfs; 572 DECLARE_BITMAP(priority_bm, MLX4_NUM_UP); 573 }; 574 575 struct mlx4_master_qp0_state { 576 int proxy_qp0_active; 577 int qp0_active; 578 int port_active; 579 }; 580 581 struct mlx4_mfunc_master_ctx { 582 struct mlx4_slave_state *slave_state; 583 struct mlx4_vf_admin_state *vf_admin; 584 struct mlx4_vf_oper_state *vf_oper; 585 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1]; 586 int init_port_ref[MLX4_MAX_PORTS + 1]; 587 u16 max_mtu[MLX4_MAX_PORTS + 1]; 588 int disable_mcast_ref[MLX4_MAX_PORTS + 1]; 589 struct mlx4_resource_tracker res_tracker; 590 struct workqueue_struct *comm_wq; 591 struct work_struct comm_work; 592 struct work_struct slave_event_work; 593 struct work_struct slave_flr_event_work; 594 spinlock_t slave_state_lock; 595 __be32 comm_arm_bit_vector[4]; 596 struct mlx4_eqe cmd_eqe; 597 struct mlx4_slave_event_eq slave_eq; 598 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX]; 599 struct mlx4_qos_manager qos_ctl[MLX4_MAX_PORTS + 1]; 600 }; 601 602 struct mlx4_mfunc { 603 struct mlx4_comm __iomem *comm; 604 struct mlx4_vhcr_cmd *vhcr; 605 dma_addr_t vhcr_dma; 606 607 struct mlx4_mfunc_master_ctx master; 608 }; 609 610 #define MGM_QPN_MASK 0x00FFFFFF 611 #define MGM_BLCK_LB_BIT 30 612 613 struct mlx4_mgm { 614 __be32 next_gid_index; 615 __be32 members_count; 616 u32 reserved[2]; 617 u8 gid[16]; 618 __be32 qp[MLX4_MAX_QP_PER_MGM]; 619 }; 620 621 struct mlx4_cmd { 622 struct pci_pool *pool; 623 void __iomem *hcr; 624 struct mutex slave_cmd_mutex; 625 struct semaphore poll_sem; 626 struct semaphore event_sem; 627 int max_cmds; 628 spinlock_t context_lock; 629 int free_head; 630 struct mlx4_cmd_context *context; 631 u16 token_mask; 632 u8 use_events; 633 u8 toggle; 634 u8 comm_toggle; 635 u8 initialized; 636 }; 637 638 enum { 639 MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0, 640 MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1, 641 MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE = 1 << 2, 642 }; 643 struct mlx4_vf_immed_vlan_work { 644 struct work_struct work; 645 struct mlx4_priv *priv; 646 int flags; 647 int slave; 648 int vlan_ix; 649 int orig_vlan_ix; 650 u8 port; 651 u8 qos; 652 u8 qos_vport; 653 u16 vlan_id; 654 u16 orig_vlan_id; 655 }; 656 657 658 struct mlx4_uar_table { 659 struct mlx4_bitmap bitmap; 660 }; 661 662 struct mlx4_mr_table { 663 struct mlx4_bitmap mpt_bitmap; 664 struct mlx4_buddy mtt_buddy; 665 u64 mtt_base; 666 u64 mpt_base; 667 struct mlx4_icm_table mtt_table; 668 struct mlx4_icm_table dmpt_table; 669 }; 670 671 struct mlx4_cq_table { 672 struct mlx4_bitmap bitmap; 673 spinlock_t lock; 674 struct radix_tree_root tree; 675 struct mlx4_icm_table table; 676 struct mlx4_icm_table cmpt_table; 677 }; 678 679 struct mlx4_eq_table { 680 struct mlx4_bitmap bitmap; 681 char *irq_names; 682 void __iomem *clr_int; 683 void __iomem **uar_map; 684 u32 clr_mask; 685 struct mlx4_eq *eq; 686 struct mlx4_icm_table table; 687 struct mlx4_icm_table cmpt_table; 688 int have_irq; 689 u8 inta_pin; 690 }; 691 692 struct mlx4_srq_table { 693 struct mlx4_bitmap bitmap; 694 spinlock_t lock; 695 struct radix_tree_root tree; 696 struct mlx4_icm_table table; 697 struct mlx4_icm_table cmpt_table; 698 }; 699 700 enum mlx4_qp_table_zones { 701 MLX4_QP_TABLE_ZONE_GENERAL, 702 MLX4_QP_TABLE_ZONE_RSS, 703 MLX4_QP_TABLE_ZONE_RAW_ETH, 704 MLX4_QP_TABLE_ZONE_NUM 705 }; 706 707 struct mlx4_qp_table { 708 struct mlx4_bitmap *bitmap_gen; 709 struct mlx4_zone_allocator *zones; 710 u32 zones_uids[MLX4_QP_TABLE_ZONE_NUM]; 711 u32 rdmarc_base; 712 int rdmarc_shift; 713 spinlock_t lock; 714 struct mlx4_icm_table qp_table; 715 struct mlx4_icm_table auxc_table; 716 struct mlx4_icm_table altc_table; 717 struct mlx4_icm_table rdmarc_table; 718 struct mlx4_icm_table cmpt_table; 719 }; 720 721 struct mlx4_mcg_table { 722 struct mutex mutex; 723 struct mlx4_bitmap bitmap; 724 struct mlx4_icm_table table; 725 }; 726 727 struct mlx4_catas_err { 728 u32 __iomem *map; 729 struct timer_list timer; 730 struct list_head list; 731 }; 732 733 #define MLX4_MAX_MAC_NUM 128 734 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3) 735 736 struct mlx4_mac_table { 737 __be64 entries[MLX4_MAX_MAC_NUM]; 738 int refs[MLX4_MAX_MAC_NUM]; 739 struct mutex mutex; 740 int total; 741 int max; 742 }; 743 744 #define MLX4_ROCE_GID_ENTRY_SIZE 16 745 746 struct mlx4_roce_gid_entry { 747 u8 raw[MLX4_ROCE_GID_ENTRY_SIZE]; 748 }; 749 750 struct mlx4_roce_gid_table { 751 struct mlx4_roce_gid_entry roce_gids[MLX4_ROCE_MAX_GIDS]; 752 struct mutex mutex; 753 }; 754 755 #define MLX4_MAX_VLAN_NUM 128 756 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2) 757 758 struct mlx4_vlan_table { 759 __be32 entries[MLX4_MAX_VLAN_NUM]; 760 int refs[MLX4_MAX_VLAN_NUM]; 761 struct mutex mutex; 762 int total; 763 int max; 764 }; 765 766 #define SET_PORT_GEN_ALL_VALID 0x7 767 #define SET_PORT_PROMISC_SHIFT 31 768 #define SET_PORT_MC_PROMISC_SHIFT 30 769 770 enum { 771 MCAST_DIRECT_ONLY = 0, 772 MCAST_DIRECT = 1, 773 MCAST_DEFAULT = 2 774 }; 775 776 777 struct mlx4_set_port_general_context { 778 u16 reserved1; 779 u8 v_ignore_fcs; 780 u8 flags; 781 u8 ignore_fcs; 782 u8 reserved2; 783 __be16 mtu; 784 u8 pptx; 785 u8 pfctx; 786 u16 reserved3; 787 u8 pprx; 788 u8 pfcrx; 789 u16 reserved4; 790 }; 791 792 struct mlx4_set_port_rqp_calc_context { 793 __be32 base_qpn; 794 u8 rererved; 795 u8 n_mac; 796 u8 n_vlan; 797 u8 n_prio; 798 u8 reserved2[3]; 799 u8 mac_miss; 800 u8 intra_no_vlan; 801 u8 no_vlan; 802 u8 intra_vlan_miss; 803 u8 vlan_miss; 804 u8 reserved3[3]; 805 u8 no_vlan_prio; 806 __be32 promisc; 807 __be32 mcast; 808 }; 809 810 struct mlx4_port_info { 811 struct mlx4_dev *dev; 812 int port; 813 char dev_name[16]; 814 struct device_attribute port_attr; 815 enum mlx4_port_type tmp_type; 816 char dev_mtu_name[16]; 817 struct device_attribute port_mtu_attr; 818 struct mlx4_mac_table mac_table; 819 struct mlx4_vlan_table vlan_table; 820 struct mlx4_roce_gid_table gid_table; 821 int base_qpn; 822 struct cpu_rmap *rmap; 823 }; 824 825 struct mlx4_sense { 826 struct mlx4_dev *dev; 827 u8 do_sense_port[MLX4_MAX_PORTS + 1]; 828 u8 sense_allowed[MLX4_MAX_PORTS + 1]; 829 struct delayed_work sense_poll; 830 }; 831 832 struct mlx4_msix_ctl { 833 DECLARE_BITMAP(pool_bm, MAX_MSIX); 834 struct mutex pool_lock; 835 }; 836 837 struct mlx4_steer { 838 struct list_head promisc_qps[MLX4_NUM_STEERS]; 839 struct list_head steer_entries[MLX4_NUM_STEERS]; 840 }; 841 842 enum { 843 MLX4_PCI_DEV_IS_VF = 1 << 0, 844 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1, 845 }; 846 847 enum { 848 MLX4_NO_RR = 0, 849 MLX4_USE_RR = 1, 850 }; 851 852 struct mlx4_priv { 853 struct mlx4_dev dev; 854 855 struct list_head dev_list; 856 struct list_head ctx_list; 857 spinlock_t ctx_lock; 858 859 int pci_dev_data; 860 int removed; 861 862 struct list_head pgdir_list; 863 struct mutex pgdir_mutex; 864 865 struct mlx4_fw fw; 866 struct mlx4_cmd cmd; 867 struct mlx4_mfunc mfunc; 868 869 struct mlx4_bitmap pd_bitmap; 870 struct mlx4_bitmap xrcd_bitmap; 871 struct mlx4_uar_table uar_table; 872 struct mlx4_mr_table mr_table; 873 struct mlx4_cq_table cq_table; 874 struct mlx4_eq_table eq_table; 875 struct mlx4_srq_table srq_table; 876 struct mlx4_qp_table qp_table; 877 struct mlx4_mcg_table mcg_table; 878 struct mlx4_bitmap counters_bitmap; 879 int def_counter[MLX4_MAX_PORTS]; 880 881 struct mlx4_catas_err catas_err; 882 883 void __iomem *clr_base; 884 885 struct mlx4_uar driver_uar; 886 void __iomem *kar; 887 struct mlx4_port_info port[MLX4_MAX_PORTS + 1]; 888 struct mlx4_sense sense; 889 struct mutex port_mutex; 890 struct mlx4_msix_ctl msix_ctl; 891 struct mlx4_steer *steer; 892 struct list_head bf_list; 893 struct mutex bf_mutex; 894 struct io_mapping *bf_mapping; 895 void __iomem *clock_mapping; 896 int reserved_mtts; 897 int fs_hash_mode; 898 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS]; 899 struct mlx4_port_map v2p; /* cached port mapping configuration */ 900 struct mutex bond_mutex; /* for bond mode */ 901 __be64 slave_node_guids[MLX4_MFUNC_MAX]; 902 903 atomic_t opreq_count; 904 struct work_struct opreq_task; 905 }; 906 907 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev) 908 { 909 return container_of(dev, struct mlx4_priv, dev); 910 } 911 912 #define MLX4_SENSE_RANGE (HZ * 3) 913 914 extern struct workqueue_struct *mlx4_wq; 915 916 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap); 917 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj, int use_rr); 918 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, 919 int align, u32 skip_mask); 920 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt, 921 int use_rr); 922 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap); 923 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, 924 u32 reserved_bot, u32 resetrved_top); 925 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap); 926 927 int mlx4_reset(struct mlx4_dev *dev); 928 929 int mlx4_alloc_eq_table(struct mlx4_dev *dev); 930 void mlx4_free_eq_table(struct mlx4_dev *dev); 931 932 int mlx4_init_pd_table(struct mlx4_dev *dev); 933 int mlx4_init_xrcd_table(struct mlx4_dev *dev); 934 int mlx4_init_uar_table(struct mlx4_dev *dev); 935 int mlx4_init_mr_table(struct mlx4_dev *dev); 936 int mlx4_init_eq_table(struct mlx4_dev *dev); 937 int mlx4_init_cq_table(struct mlx4_dev *dev); 938 int mlx4_init_qp_table(struct mlx4_dev *dev); 939 int mlx4_init_srq_table(struct mlx4_dev *dev); 940 int mlx4_init_mcg_table(struct mlx4_dev *dev); 941 942 void mlx4_cleanup_pd_table(struct mlx4_dev *dev); 943 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev); 944 void mlx4_cleanup_uar_table(struct mlx4_dev *dev); 945 void mlx4_cleanup_mr_table(struct mlx4_dev *dev); 946 void mlx4_cleanup_eq_table(struct mlx4_dev *dev); 947 void mlx4_cleanup_cq_table(struct mlx4_dev *dev); 948 void mlx4_cleanup_qp_table(struct mlx4_dev *dev); 949 void mlx4_cleanup_srq_table(struct mlx4_dev *dev); 950 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev); 951 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn, gfp_t gfp); 952 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn); 953 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn); 954 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn); 955 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn); 956 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn); 957 int __mlx4_mpt_reserve(struct mlx4_dev *dev); 958 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index); 959 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp); 960 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index); 961 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order); 962 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order); 963 964 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave, 965 struct mlx4_vhcr *vhcr, 966 struct mlx4_cmd_mailbox *inbox, 967 struct mlx4_cmd_mailbox *outbox, 968 struct mlx4_cmd_info *cmd); 969 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave, 970 struct mlx4_vhcr *vhcr, 971 struct mlx4_cmd_mailbox *inbox, 972 struct mlx4_cmd_mailbox *outbox, 973 struct mlx4_cmd_info *cmd); 974 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave, 975 struct mlx4_vhcr *vhcr, 976 struct mlx4_cmd_mailbox *inbox, 977 struct mlx4_cmd_mailbox *outbox, 978 struct mlx4_cmd_info *cmd); 979 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave, 980 struct mlx4_vhcr *vhcr, 981 struct mlx4_cmd_mailbox *inbox, 982 struct mlx4_cmd_mailbox *outbox, 983 struct mlx4_cmd_info *cmd); 984 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave, 985 struct mlx4_vhcr *vhcr, 986 struct mlx4_cmd_mailbox *inbox, 987 struct mlx4_cmd_mailbox *outbox, 988 struct mlx4_cmd_info *cmd); 989 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave, 990 struct mlx4_vhcr *vhcr, 991 struct mlx4_cmd_mailbox *inbox, 992 struct mlx4_cmd_mailbox *outbox, 993 struct mlx4_cmd_info *cmd); 994 int mlx4_CONFIG_DEV_wrapper(struct mlx4_dev *dev, int slave, 995 struct mlx4_vhcr *vhcr, 996 struct mlx4_cmd_mailbox *inbox, 997 struct mlx4_cmd_mailbox *outbox, 998 struct mlx4_cmd_info *cmd); 999 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave, 1000 struct mlx4_vhcr *vhcr, 1001 struct mlx4_cmd_mailbox *inbox, 1002 struct mlx4_cmd_mailbox *outbox, 1003 struct mlx4_cmd_info *cmd); 1004 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 1005 int *base, u8 flags); 1006 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 1007 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1008 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 1009 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 1010 int start_index, int npages, u64 *page_list); 1011 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); 1012 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx); 1013 int mlx4_calc_vf_counters(struct mlx4_dev *dev, int slave, int port, 1014 struct mlx4_counter *data); 1015 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 1016 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 1017 1018 void mlx4_start_catas_poll(struct mlx4_dev *dev); 1019 void mlx4_stop_catas_poll(struct mlx4_dev *dev); 1020 int mlx4_catas_init(struct mlx4_dev *dev); 1021 void mlx4_catas_end(struct mlx4_dev *dev); 1022 int mlx4_restart_one(struct pci_dev *pdev); 1023 int mlx4_register_device(struct mlx4_dev *dev); 1024 void mlx4_unregister_device(struct mlx4_dev *dev); 1025 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, 1026 unsigned long param); 1027 1028 struct mlx4_dev_cap; 1029 struct mlx4_init_hca_param; 1030 1031 u64 mlx4_make_profile(struct mlx4_dev *dev, 1032 struct mlx4_profile *request, 1033 struct mlx4_dev_cap *dev_cap, 1034 struct mlx4_init_hca_param *init_hca); 1035 void mlx4_master_comm_channel(struct work_struct *work); 1036 void mlx4_gen_slave_eqe(struct work_struct *work); 1037 void mlx4_master_handle_slave_flr(struct work_struct *work); 1038 1039 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave, 1040 struct mlx4_vhcr *vhcr, 1041 struct mlx4_cmd_mailbox *inbox, 1042 struct mlx4_cmd_mailbox *outbox, 1043 struct mlx4_cmd_info *cmd); 1044 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave, 1045 struct mlx4_vhcr *vhcr, 1046 struct mlx4_cmd_mailbox *inbox, 1047 struct mlx4_cmd_mailbox *outbox, 1048 struct mlx4_cmd_info *cmd); 1049 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave, 1050 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox, 1051 struct mlx4_cmd_mailbox *outbox, 1052 struct mlx4_cmd_info *cmd); 1053 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave, 1054 struct mlx4_vhcr *vhcr, 1055 struct mlx4_cmd_mailbox *inbox, 1056 struct mlx4_cmd_mailbox *outbox, 1057 struct mlx4_cmd_info *cmd); 1058 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave, 1059 struct mlx4_vhcr *vhcr, 1060 struct mlx4_cmd_mailbox *inbox, 1061 struct mlx4_cmd_mailbox *outbox, 1062 struct mlx4_cmd_info *cmd); 1063 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave, 1064 struct mlx4_vhcr *vhcr, 1065 struct mlx4_cmd_mailbox *inbox, 1066 struct mlx4_cmd_mailbox *outbox, 1067 struct mlx4_cmd_info *cmd); 1068 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave, 1069 struct mlx4_vhcr *vhcr, 1070 struct mlx4_cmd_mailbox *inbox, 1071 struct mlx4_cmd_mailbox *outbox, 1072 struct mlx4_cmd_info *cmd); 1073 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave, 1074 struct mlx4_vhcr *vhcr, 1075 struct mlx4_cmd_mailbox *inbox, 1076 struct mlx4_cmd_mailbox *outbox, 1077 struct mlx4_cmd_info *cmd); 1078 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave, 1079 struct mlx4_vhcr *vhcr, 1080 struct mlx4_cmd_mailbox *inbox, 1081 struct mlx4_cmd_mailbox *outbox, 1082 struct mlx4_cmd_info *cmd); 1083 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave, 1084 struct mlx4_vhcr *vhcr, 1085 struct mlx4_cmd_mailbox *inbox, 1086 struct mlx4_cmd_mailbox *outbox, 1087 struct mlx4_cmd_info *cmd); 1088 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1089 struct mlx4_vhcr *vhcr, 1090 struct mlx4_cmd_mailbox *inbox, 1091 struct mlx4_cmd_mailbox *outbox, 1092 struct mlx4_cmd_info *cmd); 1093 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1094 struct mlx4_vhcr *vhcr, 1095 struct mlx4_cmd_mailbox *inbox, 1096 struct mlx4_cmd_mailbox *outbox, 1097 struct mlx4_cmd_info *cmd); 1098 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1099 struct mlx4_vhcr *vhcr, 1100 struct mlx4_cmd_mailbox *inbox, 1101 struct mlx4_cmd_mailbox *outbox, 1102 struct mlx4_cmd_info *cmd); 1103 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1104 struct mlx4_vhcr *vhcr, 1105 struct mlx4_cmd_mailbox *inbox, 1106 struct mlx4_cmd_mailbox *outbox, 1107 struct mlx4_cmd_info *cmd); 1108 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave, 1109 struct mlx4_vhcr *vhcr, 1110 struct mlx4_cmd_mailbox *inbox, 1111 struct mlx4_cmd_mailbox *outbox, 1112 struct mlx4_cmd_info *cmd); 1113 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, 1114 struct mlx4_vhcr *vhcr, 1115 struct mlx4_cmd_mailbox *inbox, 1116 struct mlx4_cmd_mailbox *outbox, 1117 struct mlx4_cmd_info *cmd); 1118 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, 1119 struct mlx4_vhcr *vhcr, 1120 struct mlx4_cmd_mailbox *inbox, 1121 struct mlx4_cmd_mailbox *outbox, 1122 struct mlx4_cmd_info *cmd); 1123 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave, 1124 struct mlx4_vhcr *vhcr, 1125 struct mlx4_cmd_mailbox *inbox, 1126 struct mlx4_cmd_mailbox *outbox, 1127 struct mlx4_cmd_info *cmd); 1128 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1129 struct mlx4_vhcr *vhcr, 1130 struct mlx4_cmd_mailbox *inbox, 1131 struct mlx4_cmd_mailbox *outbox, 1132 struct mlx4_cmd_info *cmd); 1133 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1134 struct mlx4_vhcr *vhcr, 1135 struct mlx4_cmd_mailbox *inbox, 1136 struct mlx4_cmd_mailbox *outbox, 1137 struct mlx4_cmd_info *cmd); 1138 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1139 struct mlx4_vhcr *vhcr, 1140 struct mlx4_cmd_mailbox *inbox, 1141 struct mlx4_cmd_mailbox *outbox, 1142 struct mlx4_cmd_info *cmd); 1143 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave, 1144 struct mlx4_vhcr *vhcr, 1145 struct mlx4_cmd_mailbox *inbox, 1146 struct mlx4_cmd_mailbox *outbox, 1147 struct mlx4_cmd_info *cmd); 1148 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave, 1149 struct mlx4_vhcr *vhcr, 1150 struct mlx4_cmd_mailbox *inbox, 1151 struct mlx4_cmd_mailbox *outbox, 1152 struct mlx4_cmd_info *cmd); 1153 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave, 1154 struct mlx4_vhcr *vhcr, 1155 struct mlx4_cmd_mailbox *inbox, 1156 struct mlx4_cmd_mailbox *outbox, 1157 struct mlx4_cmd_info *cmd); 1158 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1159 struct mlx4_vhcr *vhcr, 1160 struct mlx4_cmd_mailbox *inbox, 1161 struct mlx4_cmd_mailbox *outbox, 1162 struct mlx4_cmd_info *cmd); 1163 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave, 1164 struct mlx4_vhcr *vhcr, 1165 struct mlx4_cmd_mailbox *inbox, 1166 struct mlx4_cmd_mailbox *outbox, 1167 struct mlx4_cmd_info *cmd); 1168 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave, 1169 struct mlx4_vhcr *vhcr, 1170 struct mlx4_cmd_mailbox *inbox, 1171 struct mlx4_cmd_mailbox *outbox, 1172 struct mlx4_cmd_info *cmd); 1173 1174 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe); 1175 1176 enum { 1177 MLX4_CMD_CLEANUP_STRUCT = 1UL << 0, 1178 MLX4_CMD_CLEANUP_POOL = 1UL << 1, 1179 MLX4_CMD_CLEANUP_HCR = 1UL << 2, 1180 MLX4_CMD_CLEANUP_VHCR = 1UL << 3, 1181 MLX4_CMD_CLEANUP_ALL = (MLX4_CMD_CLEANUP_VHCR << 1) - 1 1182 }; 1183 1184 int mlx4_cmd_init(struct mlx4_dev *dev); 1185 void mlx4_cmd_cleanup(struct mlx4_dev *dev, int cleanup_mask); 1186 int mlx4_multi_func_init(struct mlx4_dev *dev); 1187 int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev); 1188 void mlx4_multi_func_cleanup(struct mlx4_dev *dev); 1189 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param); 1190 int mlx4_cmd_use_events(struct mlx4_dev *dev); 1191 void mlx4_cmd_use_polling(struct mlx4_dev *dev); 1192 1193 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param, 1194 u16 op, unsigned long timeout); 1195 1196 void mlx4_cq_tasklet_cb(unsigned long data); 1197 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn); 1198 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type); 1199 1200 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type); 1201 1202 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type); 1203 1204 void mlx4_enter_error_state(struct mlx4_dev_persistent *persist); 1205 1206 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port, 1207 enum mlx4_port_type *type); 1208 void mlx4_do_sense_ports(struct mlx4_dev *dev, 1209 enum mlx4_port_type *stype, 1210 enum mlx4_port_type *defaults); 1211 void mlx4_start_sense(struct mlx4_dev *dev); 1212 void mlx4_stop_sense(struct mlx4_dev *dev); 1213 void mlx4_sense_init(struct mlx4_dev *dev); 1214 int mlx4_check_port_params(struct mlx4_dev *dev, 1215 enum mlx4_port_type *port_type); 1216 int mlx4_change_port_types(struct mlx4_dev *dev, 1217 enum mlx4_port_type *port_types); 1218 1219 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table); 1220 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table); 1221 void mlx4_init_roce_gid_table(struct mlx4_dev *dev, 1222 struct mlx4_roce_gid_table *table); 1223 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); 1224 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 1225 1226 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz); 1227 /* resource tracker functions*/ 1228 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev, 1229 enum mlx4_resource resource_type, 1230 u64 resource_id, int *slave); 1231 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id); 1232 void mlx4_reset_roce_gids(struct mlx4_dev *dev, int slave); 1233 int mlx4_init_resource_tracker(struct mlx4_dev *dev); 1234 1235 void mlx4_free_resource_tracker(struct mlx4_dev *dev, 1236 enum mlx4_res_tracker_free_type type); 1237 1238 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, 1239 struct mlx4_vhcr *vhcr, 1240 struct mlx4_cmd_mailbox *inbox, 1241 struct mlx4_cmd_mailbox *outbox, 1242 struct mlx4_cmd_info *cmd); 1243 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave, 1244 struct mlx4_vhcr *vhcr, 1245 struct mlx4_cmd_mailbox *inbox, 1246 struct mlx4_cmd_mailbox *outbox, 1247 struct mlx4_cmd_info *cmd); 1248 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, 1249 struct mlx4_vhcr *vhcr, 1250 struct mlx4_cmd_mailbox *inbox, 1251 struct mlx4_cmd_mailbox *outbox, 1252 struct mlx4_cmd_info *cmd); 1253 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, 1254 struct mlx4_vhcr *vhcr, 1255 struct mlx4_cmd_mailbox *inbox, 1256 struct mlx4_cmd_mailbox *outbox, 1257 struct mlx4_cmd_info *cmd); 1258 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, 1259 struct mlx4_vhcr *vhcr, 1260 struct mlx4_cmd_mailbox *inbox, 1261 struct mlx4_cmd_mailbox *outbox, 1262 struct mlx4_cmd_info *cmd); 1263 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, 1264 struct mlx4_vhcr *vhcr, 1265 struct mlx4_cmd_mailbox *inbox, 1266 struct mlx4_cmd_mailbox *outbox, 1267 struct mlx4_cmd_info *cmd); 1268 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps); 1269 1270 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, 1271 int *gid_tbl_len, int *pkey_tbl_len); 1272 1273 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave, 1274 struct mlx4_vhcr *vhcr, 1275 struct mlx4_cmd_mailbox *inbox, 1276 struct mlx4_cmd_mailbox *outbox, 1277 struct mlx4_cmd_info *cmd); 1278 1279 int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave, 1280 struct mlx4_vhcr *vhcr, 1281 struct mlx4_cmd_mailbox *inbox, 1282 struct mlx4_cmd_mailbox *outbox, 1283 struct mlx4_cmd_info *cmd); 1284 1285 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave, 1286 struct mlx4_vhcr *vhcr, 1287 struct mlx4_cmd_mailbox *inbox, 1288 struct mlx4_cmd_mailbox *outbox, 1289 struct mlx4_cmd_info *cmd); 1290 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1291 enum mlx4_protocol prot, enum mlx4_steer_type steer); 1292 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1293 int block_mcast_loopback, enum mlx4_protocol prot, 1294 enum mlx4_steer_type steer); 1295 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, 1296 u8 gid[16], u8 port, 1297 int block_mcast_loopback, 1298 enum mlx4_protocol prot, u64 *reg_id); 1299 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave, 1300 struct mlx4_vhcr *vhcr, 1301 struct mlx4_cmd_mailbox *inbox, 1302 struct mlx4_cmd_mailbox *outbox, 1303 struct mlx4_cmd_info *cmd); 1304 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave, 1305 struct mlx4_vhcr *vhcr, 1306 struct mlx4_cmd_mailbox *inbox, 1307 struct mlx4_cmd_mailbox *outbox, 1308 struct mlx4_cmd_info *cmd); 1309 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function, 1310 int port, void *buf); 1311 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod, 1312 struct mlx4_cmd_mailbox *outbox); 1313 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave, 1314 struct mlx4_vhcr *vhcr, 1315 struct mlx4_cmd_mailbox *inbox, 1316 struct mlx4_cmd_mailbox *outbox, 1317 struct mlx4_cmd_info *cmd); 1318 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave, 1319 struct mlx4_vhcr *vhcr, 1320 struct mlx4_cmd_mailbox *inbox, 1321 struct mlx4_cmd_mailbox *outbox, 1322 struct mlx4_cmd_info *cmd); 1323 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave, 1324 struct mlx4_vhcr *vhcr, 1325 struct mlx4_cmd_mailbox *inbox, 1326 struct mlx4_cmd_mailbox *outbox, 1327 struct mlx4_cmd_info *cmd); 1328 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave, 1329 struct mlx4_vhcr *vhcr, 1330 struct mlx4_cmd_mailbox *inbox, 1331 struct mlx4_cmd_mailbox *outbox, 1332 struct mlx4_cmd_info *cmd); 1333 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave, 1334 struct mlx4_vhcr *vhcr, 1335 struct mlx4_cmd_mailbox *inbox, 1336 struct mlx4_cmd_mailbox *outbox, 1337 struct mlx4_cmd_info *cmd); 1338 int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave, 1339 struct mlx4_vhcr *vhcr, 1340 struct mlx4_cmd_mailbox *inbox, 1341 struct mlx4_cmd_mailbox *outbox, 1342 struct mlx4_cmd_info *cmd); 1343 1344 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev); 1345 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev); 1346 1347 static inline void set_param_l(u64 *arg, u32 val) 1348 { 1349 *arg = (*arg & 0xffffffff00000000ULL) | (u64) val; 1350 } 1351 1352 static inline void set_param_h(u64 *arg, u32 val) 1353 { 1354 *arg = (*arg & 0xffffffff) | ((u64) val << 32); 1355 } 1356 1357 static inline u32 get_param_l(u64 *arg) 1358 { 1359 return (u32) (*arg & 0xffffffff); 1360 } 1361 1362 static inline u32 get_param_h(u64 *arg) 1363 { 1364 return (u32)(*arg >> 32); 1365 } 1366 1367 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev) 1368 { 1369 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock; 1370 } 1371 1372 #define NOT_MASKED_PD_BITS 17 1373 1374 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work); 1375 1376 void mlx4_init_quotas(struct mlx4_dev *dev); 1377 1378 int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port); 1379 /* Returns the VF index of slave */ 1380 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave); 1381 int mlx4_config_mad_demux(struct mlx4_dev *dev); 1382 int mlx4_do_bond(struct mlx4_dev *dev, bool enable); 1383 1384 enum mlx4_zone_flags { 1385 MLX4_ZONE_ALLOW_ALLOC_FROM_LOWER_PRIO = 1UL << 0, 1386 MLX4_ZONE_ALLOW_ALLOC_FROM_EQ_PRIO = 1UL << 1, 1387 MLX4_ZONE_FALLBACK_TO_HIGHER_PRIO = 1UL << 2, 1388 MLX4_ZONE_USE_RR = 1UL << 3, 1389 }; 1390 1391 enum mlx4_zone_alloc_flags { 1392 /* No two objects could overlap between zones. UID 1393 * could be left unused. If this flag is given and 1394 * two overlapped zones are used, an object will be free'd 1395 * from the smallest possible matching zone. 1396 */ 1397 MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP = 1UL << 0, 1398 }; 1399 1400 struct mlx4_zone_allocator; 1401 1402 /* Create a new zone allocator */ 1403 struct mlx4_zone_allocator *mlx4_zone_allocator_create(enum mlx4_zone_alloc_flags flags); 1404 1405 /* Attach a mlx4_bitmap <bitmap> of priority <priority> to the zone allocator 1406 * <zone_alloc>. Allocating an object from this zone adds an offset <offset>. 1407 * Similarly, when searching for an object to free, this offset it taken into 1408 * account. The use_rr mlx4_ib parameter for allocating objects from this <bitmap> 1409 * is given through the MLX4_ZONE_USE_RR flag in <flags>. 1410 * When an allocation fails, <zone_alloc> tries to allocate from other zones 1411 * according to the policy set by <flags>. <puid> is the unique identifier 1412 * received to this zone. 1413 */ 1414 int mlx4_zone_add_one(struct mlx4_zone_allocator *zone_alloc, 1415 struct mlx4_bitmap *bitmap, 1416 u32 flags, 1417 int priority, 1418 int offset, 1419 u32 *puid); 1420 1421 /* Remove bitmap indicated by <uid> from <zone_alloc> */ 1422 int mlx4_zone_remove_one(struct mlx4_zone_allocator *zone_alloc, u32 uid); 1423 1424 /* Delete the zone allocator <zone_alloc. This function doesn't destroy 1425 * the attached bitmaps. 1426 */ 1427 void mlx4_zone_allocator_destroy(struct mlx4_zone_allocator *zone_alloc); 1428 1429 /* Allocate <count> objects with align <align> and skip_mask <skip_mask> 1430 * from the mlx4_bitmap whose uid is <uid>. The bitmap which we actually 1431 * allocated from is returned in <puid>. If the allocation fails, a negative 1432 * number is returned. Otherwise, the offset of the first object is returned. 1433 */ 1434 u32 mlx4_zone_alloc_entries(struct mlx4_zone_allocator *zones, u32 uid, int count, 1435 int align, u32 skip_mask, u32 *puid); 1436 1437 /* Free <count> objects, start from <obj> of the uid <uid> from zone_allocator 1438 * <zones>. 1439 */ 1440 u32 mlx4_zone_free_entries(struct mlx4_zone_allocator *zones, 1441 u32 uid, u32 obj, u32 count); 1442 1443 /* If <zones> was allocated with MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP, instead of 1444 * specifying the uid when freeing an object, zone allocator could figure it by 1445 * itself. Other parameters are similar to mlx4_zone_free. 1446 */ 1447 u32 mlx4_zone_free_entries_unique(struct mlx4_zone_allocator *zones, u32 obj, u32 count); 1448 1449 /* Returns a pointer to mlx4_bitmap that was attached to <zones> with <uid> */ 1450 struct mlx4_bitmap *mlx4_zone_get_bitmap(struct mlx4_zone_allocator *zones, u32 uid); 1451 1452 #endif /* MLX4_H */ 1453