1 /*
2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4  * Copyright (c) 2005, 2006, 2007 Cisco Systems.  All rights reserved.
5  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
6  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7  *
8  * This software is available to you under a choice of one of two
9  * licenses.  You may choose to be licensed under the terms of the GNU
10  * General Public License (GPL) Version 2, available from the file
11  * COPYING in the main directory of this source tree, or the
12  * OpenIB.org BSD license below:
13  *
14  *     Redistribution and use in source and binary forms, with or
15  *     without modification, are permitted provided that the following
16  *     conditions are met:
17  *
18  *      - Redistributions of source code must retain the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer.
21  *
22  *      - Redistributions in binary form must reproduce the above
23  *        copyright notice, this list of conditions and the following
24  *        disclaimer in the documentation and/or other materials
25  *        provided with the distribution.
26  *
27  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34  * SOFTWARE.
35  */
36 
37 #ifndef MLX4_H
38 #define MLX4_H
39 
40 #include <linux/mutex.h>
41 #include <linux/radix-tree.h>
42 #include <linux/rbtree.h>
43 #include <linux/timer.h>
44 #include <linux/semaphore.h>
45 #include <linux/workqueue.h>
46 
47 #include <linux/mlx4/device.h>
48 #include <linux/mlx4/driver.h>
49 #include <linux/mlx4/doorbell.h>
50 #include <linux/mlx4/cmd.h>
51 
52 #define DRV_NAME	"mlx4_core"
53 #define PFX		DRV_NAME ": "
54 #define DRV_VERSION	"2.2-1"
55 #define DRV_RELDATE	"Feb, 2014"
56 
57 #define MLX4_FS_UDP_UC_EN		(1 << 1)
58 #define MLX4_FS_TCP_UC_EN		(1 << 2)
59 #define MLX4_FS_NUM_OF_L2_ADDR		8
60 #define MLX4_FS_MGM_LOG_ENTRY_SIZE	7
61 #define MLX4_FS_NUM_MCG			(1 << 17)
62 
63 #define INIT_HCA_TPT_MW_ENABLE          (1 << 7)
64 
65 #define MLX4_NUM_UP		8
66 #define MLX4_NUM_TC		8
67 #define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */
68 #define MLX4_RATELIMIT_DEFAULT 0xffff
69 
70 struct mlx4_set_port_prio2tc_context {
71 	u8 prio2tc[4];
72 };
73 
74 struct mlx4_port_scheduler_tc_cfg_be {
75 	__be16 pg;
76 	__be16 bw_precentage;
77 	__be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
78 	__be16 max_bw_value;
79 };
80 
81 struct mlx4_set_port_scheduler_context {
82 	struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
83 };
84 
85 enum {
86 	MLX4_HCR_BASE		= 0x80680,
87 	MLX4_HCR_SIZE		= 0x0001c,
88 	MLX4_CLR_INT_SIZE	= 0x00008,
89 	MLX4_SLAVE_COMM_BASE	= 0x0,
90 	MLX4_COMM_PAGESIZE	= 0x1000,
91 	MLX4_CLOCK_SIZE		= 0x00008
92 };
93 
94 enum {
95 	MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10,
96 	MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7,
97 	MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12,
98 	MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2),
99 	MLX4_MTT_ENTRY_PER_SEG	= 8,
100 };
101 
102 enum {
103 	MLX4_NUM_PDS		= 1 << 15
104 };
105 
106 enum {
107 	MLX4_CMPT_TYPE_QP	= 0,
108 	MLX4_CMPT_TYPE_SRQ	= 1,
109 	MLX4_CMPT_TYPE_CQ	= 2,
110 	MLX4_CMPT_TYPE_EQ	= 3,
111 	MLX4_CMPT_NUM_TYPE
112 };
113 
114 enum {
115 	MLX4_CMPT_SHIFT		= 24,
116 	MLX4_NUM_CMPTS		= MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
117 };
118 
119 enum mlx4_mpt_state {
120 	MLX4_MPT_DISABLED = 0,
121 	MLX4_MPT_EN_HW,
122 	MLX4_MPT_EN_SW
123 };
124 
125 #define MLX4_COMM_TIME		10000
126 enum {
127 	MLX4_COMM_CMD_RESET,
128 	MLX4_COMM_CMD_VHCR0,
129 	MLX4_COMM_CMD_VHCR1,
130 	MLX4_COMM_CMD_VHCR2,
131 	MLX4_COMM_CMD_VHCR_EN,
132 	MLX4_COMM_CMD_VHCR_POST,
133 	MLX4_COMM_CMD_FLR = 254
134 };
135 
136 /*The flag indicates that the slave should delay the RESET cmd*/
137 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
138 /*indicates how many retries will be done if we are in the middle of FLR*/
139 #define NUM_OF_RESET_RETRIES	10
140 #define SLEEP_TIME_IN_RESET	(2 * 1000)
141 enum mlx4_resource {
142 	RES_QP,
143 	RES_CQ,
144 	RES_SRQ,
145 	RES_XRCD,
146 	RES_MPT,
147 	RES_MTT,
148 	RES_MAC,
149 	RES_VLAN,
150 	RES_EQ,
151 	RES_COUNTER,
152 	RES_FS_RULE,
153 	MLX4_NUM_OF_RESOURCE_TYPE
154 };
155 
156 enum mlx4_alloc_mode {
157 	RES_OP_RESERVE,
158 	RES_OP_RESERVE_AND_MAP,
159 	RES_OP_MAP_ICM,
160 };
161 
162 enum mlx4_res_tracker_free_type {
163 	RES_TR_FREE_ALL,
164 	RES_TR_FREE_SLAVES_ONLY,
165 	RES_TR_FREE_STRUCTS_ONLY,
166 };
167 
168 /*
169  *Virtual HCR structures.
170  * mlx4_vhcr is the sw representation, in machine endianess
171  *
172  * mlx4_vhcr_cmd is the formalized structure, the one that is passed
173  * to FW to go through communication channel.
174  * It is big endian, and has the same structure as the physical HCR
175  * used by command interface
176  */
177 struct mlx4_vhcr {
178 	u64	in_param;
179 	u64	out_param;
180 	u32	in_modifier;
181 	u32	errno;
182 	u16	op;
183 	u16	token;
184 	u8	op_modifier;
185 	u8	e_bit;
186 };
187 
188 struct mlx4_vhcr_cmd {
189 	__be64 in_param;
190 	__be32 in_modifier;
191 	__be64 out_param;
192 	__be16 token;
193 	u16 reserved;
194 	u8 status;
195 	u8 flags;
196 	__be16 opcode;
197 };
198 
199 struct mlx4_cmd_info {
200 	u16 opcode;
201 	bool has_inbox;
202 	bool has_outbox;
203 	bool out_is_imm;
204 	bool encode_slave_id;
205 	int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
206 		      struct mlx4_cmd_mailbox *inbox);
207 	int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
208 		       struct mlx4_cmd_mailbox *inbox,
209 		       struct mlx4_cmd_mailbox *outbox,
210 		       struct mlx4_cmd_info *cmd);
211 };
212 
213 #ifdef CONFIG_MLX4_DEBUG
214 extern int mlx4_debug_level;
215 #else /* CONFIG_MLX4_DEBUG */
216 #define mlx4_debug_level	(0)
217 #endif /* CONFIG_MLX4_DEBUG */
218 
219 #define mlx4_dbg(mdev, format, arg...)					\
220 do {									\
221 	if (mlx4_debug_level)						\
222 		dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
223 } while (0)
224 
225 #define mlx4_err(mdev, format, arg...) \
226 	dev_err(&mdev->pdev->dev, format, ##arg)
227 #define mlx4_info(mdev, format, arg...) \
228 	dev_info(&mdev->pdev->dev, format, ##arg)
229 #define mlx4_warn(mdev, format, arg...) \
230 	dev_warn(&mdev->pdev->dev, format, ##arg)
231 
232 extern int mlx4_log_num_mgm_entry_size;
233 extern int log_mtts_per_seg;
234 
235 #define MLX4_MAX_NUM_SLAVES	(MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
236 #define ALL_SLAVES 0xff
237 
238 struct mlx4_bitmap {
239 	u32			last;
240 	u32			top;
241 	u32			max;
242 	u32                     reserved_top;
243 	u32			mask;
244 	u32			avail;
245 	spinlock_t		lock;
246 	unsigned long	       *table;
247 };
248 
249 struct mlx4_buddy {
250 	unsigned long	      **bits;
251 	unsigned int	       *num_free;
252 	u32			max_order;
253 	spinlock_t		lock;
254 };
255 
256 struct mlx4_icm;
257 
258 struct mlx4_icm_table {
259 	u64			virt;
260 	int			num_icm;
261 	u32			num_obj;
262 	int			obj_size;
263 	int			lowmem;
264 	int			coherent;
265 	struct mutex		mutex;
266 	struct mlx4_icm	      **icm;
267 };
268 
269 #define MLX4_MPT_FLAG_SW_OWNS	    (0xfUL << 28)
270 #define MLX4_MPT_FLAG_FREE	    (0x3UL << 28)
271 #define MLX4_MPT_FLAG_MIO	    (1 << 17)
272 #define MLX4_MPT_FLAG_BIND_ENABLE   (1 << 15)
273 #define MLX4_MPT_FLAG_PHYSICAL	    (1 <<  9)
274 #define MLX4_MPT_FLAG_REGION	    (1 <<  8)
275 
276 #define MLX4_MPT_PD_FLAG_FAST_REG   (1 << 27)
277 #define MLX4_MPT_PD_FLAG_RAE	    (1 << 28)
278 #define MLX4_MPT_PD_FLAG_EN_INV	    (3 << 24)
279 
280 #define MLX4_MPT_QP_FLAG_BOUND_QP   (1 << 7)
281 
282 #define MLX4_MPT_STATUS_SW		0xF0
283 #define MLX4_MPT_STATUS_HW		0x00
284 
285 /*
286  * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
287  */
288 struct mlx4_mpt_entry {
289 	__be32 flags;
290 	__be32 qpn;
291 	__be32 key;
292 	__be32 pd_flags;
293 	__be64 start;
294 	__be64 length;
295 	__be32 lkey;
296 	__be32 win_cnt;
297 	u8	reserved1[3];
298 	u8	mtt_rep;
299 	__be64 mtt_addr;
300 	__be32 mtt_sz;
301 	__be32 entity_size;
302 	__be32 first_byte_offset;
303 } __packed;
304 
305 /*
306  * Must be packed because start is 64 bits but only aligned to 32 bits.
307  */
308 struct mlx4_eq_context {
309 	__be32			flags;
310 	u16			reserved1[3];
311 	__be16			page_offset;
312 	u8			log_eq_size;
313 	u8			reserved2[4];
314 	u8			eq_period;
315 	u8			reserved3;
316 	u8			eq_max_count;
317 	u8			reserved4[3];
318 	u8			intr;
319 	u8			log_page_size;
320 	u8			reserved5[2];
321 	u8			mtt_base_addr_h;
322 	__be32			mtt_base_addr_l;
323 	u32			reserved6[2];
324 	__be32			consumer_index;
325 	__be32			producer_index;
326 	u32			reserved7[4];
327 };
328 
329 struct mlx4_cq_context {
330 	__be32			flags;
331 	u16			reserved1[3];
332 	__be16			page_offset;
333 	__be32			logsize_usrpage;
334 	__be16			cq_period;
335 	__be16			cq_max_count;
336 	u8			reserved2[3];
337 	u8			comp_eqn;
338 	u8			log_page_size;
339 	u8			reserved3[2];
340 	u8			mtt_base_addr_h;
341 	__be32			mtt_base_addr_l;
342 	__be32			last_notified_index;
343 	__be32			solicit_producer_index;
344 	__be32			consumer_index;
345 	__be32			producer_index;
346 	u32			reserved4[2];
347 	__be64			db_rec_addr;
348 };
349 
350 struct mlx4_srq_context {
351 	__be32			state_logsize_srqn;
352 	u8			logstride;
353 	u8			reserved1;
354 	__be16			xrcd;
355 	__be32			pg_offset_cqn;
356 	u32			reserved2;
357 	u8			log_page_size;
358 	u8			reserved3[2];
359 	u8			mtt_base_addr_h;
360 	__be32			mtt_base_addr_l;
361 	__be32			pd;
362 	__be16			limit_watermark;
363 	__be16			wqe_cnt;
364 	u16			reserved4;
365 	__be16			wqe_counter;
366 	u32			reserved5;
367 	__be64			db_rec_addr;
368 };
369 
370 struct mlx4_eq {
371 	struct mlx4_dev	       *dev;
372 	void __iomem	       *doorbell;
373 	int			eqn;
374 	u32			cons_index;
375 	u16			irq;
376 	u16			have_irq;
377 	int			nent;
378 	struct mlx4_buf_list   *page_list;
379 	struct mlx4_mtt		mtt;
380 };
381 
382 struct mlx4_slave_eqe {
383 	u8 type;
384 	u8 port;
385 	u32 param;
386 };
387 
388 struct mlx4_slave_event_eq_info {
389 	int eqn;
390 	u16 token;
391 };
392 
393 struct mlx4_profile {
394 	int			num_qp;
395 	int			rdmarc_per_qp;
396 	int			num_srq;
397 	int			num_cq;
398 	int			num_mcg;
399 	int			num_mpt;
400 	unsigned		num_mtt;
401 };
402 
403 struct mlx4_fw {
404 	u64			clr_int_base;
405 	u64			catas_offset;
406 	u64			comm_base;
407 	u64			clock_offset;
408 	struct mlx4_icm	       *fw_icm;
409 	struct mlx4_icm	       *aux_icm;
410 	u32			catas_size;
411 	u16			fw_pages;
412 	u8			clr_int_bar;
413 	u8			catas_bar;
414 	u8			comm_bar;
415 	u8			clock_bar;
416 };
417 
418 struct mlx4_comm {
419 	u32			slave_write;
420 	u32			slave_read;
421 };
422 
423 enum {
424 	MLX4_MCAST_CONFIG       = 0,
425 	MLX4_MCAST_DISABLE      = 1,
426 	MLX4_MCAST_ENABLE       = 2,
427 };
428 
429 #define VLAN_FLTR_SIZE	128
430 
431 struct mlx4_vlan_fltr {
432 	__be32 entry[VLAN_FLTR_SIZE];
433 };
434 
435 struct mlx4_mcast_entry {
436 	struct list_head list;
437 	u64 addr;
438 };
439 
440 struct mlx4_promisc_qp {
441 	struct list_head list;
442 	u32 qpn;
443 };
444 
445 struct mlx4_steer_index {
446 	struct list_head list;
447 	unsigned int index;
448 	struct list_head duplicates;
449 };
450 
451 #define MLX4_EVENT_TYPES_NUM 64
452 
453 struct mlx4_slave_state {
454 	u8 comm_toggle;
455 	u8 last_cmd;
456 	u8 init_port_mask;
457 	bool active;
458 	bool old_vlan_api;
459 	u8 function;
460 	dma_addr_t vhcr_dma;
461 	u16 mtu[MLX4_MAX_PORTS + 1];
462 	__be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
463 	struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
464 	struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
465 	struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
466 	/* event type to eq number lookup */
467 	struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
468 	u16 eq_pi;
469 	u16 eq_ci;
470 	spinlock_t lock;
471 	/*initialized via the kzalloc*/
472 	u8 is_slave_going_down;
473 	u32 cookie;
474 	enum slave_port_state port_state[MLX4_MAX_PORTS + 1];
475 };
476 
477 #define MLX4_VGT 4095
478 #define NO_INDX  (-1)
479 
480 struct mlx4_vport_state {
481 	u64 mac;
482 	u16 default_vlan;
483 	u8  default_qos;
484 	u32 tx_rate;
485 	bool spoofchk;
486 	u32 link_state;
487 };
488 
489 struct mlx4_vf_admin_state {
490 	struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1];
491 };
492 
493 struct mlx4_vport_oper_state {
494 	struct mlx4_vport_state state;
495 	int mac_idx;
496 	int vlan_idx;
497 };
498 struct mlx4_vf_oper_state {
499 	struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1];
500 };
501 
502 struct slave_list {
503 	struct mutex mutex;
504 	struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
505 };
506 
507 struct resource_allocator {
508 	spinlock_t alloc_lock; /* protect quotas */
509 	union {
510 		int res_reserved;
511 		int res_port_rsvd[MLX4_MAX_PORTS];
512 	};
513 	union {
514 		int res_free;
515 		int res_port_free[MLX4_MAX_PORTS];
516 	};
517 	int *quota;
518 	int *allocated;
519 	int *guaranteed;
520 };
521 
522 struct mlx4_resource_tracker {
523 	spinlock_t lock;
524 	/* tree for each resources */
525 	struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
526 	/* num_of_slave's lists, one per slave */
527 	struct slave_list *slave_list;
528 	struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE];
529 };
530 
531 #define SLAVE_EVENT_EQ_SIZE	128
532 struct mlx4_slave_event_eq {
533 	u32 eqn;
534 	u32 cons;
535 	u32 prod;
536 	spinlock_t event_lock;
537 	struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
538 };
539 
540 struct mlx4_master_qp0_state {
541 	int proxy_qp0_active;
542 	int qp0_active;
543 	int port_active;
544 };
545 
546 struct mlx4_mfunc_master_ctx {
547 	struct mlx4_slave_state *slave_state;
548 	struct mlx4_vf_admin_state *vf_admin;
549 	struct mlx4_vf_oper_state *vf_oper;
550 	struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
551 	int			init_port_ref[MLX4_MAX_PORTS + 1];
552 	u16			max_mtu[MLX4_MAX_PORTS + 1];
553 	int			disable_mcast_ref[MLX4_MAX_PORTS + 1];
554 	struct mlx4_resource_tracker res_tracker;
555 	struct workqueue_struct *comm_wq;
556 	struct work_struct	comm_work;
557 	struct work_struct	slave_event_work;
558 	struct work_struct	slave_flr_event_work;
559 	spinlock_t		slave_state_lock;
560 	__be32			comm_arm_bit_vector[4];
561 	struct mlx4_eqe		cmd_eqe;
562 	struct mlx4_slave_event_eq slave_eq;
563 	struct mutex		gen_eqe_mutex[MLX4_MFUNC_MAX];
564 };
565 
566 struct mlx4_mfunc {
567 	struct mlx4_comm __iomem       *comm;
568 	struct mlx4_vhcr_cmd	       *vhcr;
569 	dma_addr_t			vhcr_dma;
570 
571 	struct mlx4_mfunc_master_ctx	master;
572 };
573 
574 #define MGM_QPN_MASK       0x00FFFFFF
575 #define MGM_BLCK_LB_BIT    30
576 
577 struct mlx4_mgm {
578 	__be32			next_gid_index;
579 	__be32			members_count;
580 	u32			reserved[2];
581 	u8			gid[16];
582 	__be32			qp[MLX4_MAX_QP_PER_MGM];
583 };
584 
585 struct mlx4_cmd {
586 	struct pci_pool	       *pool;
587 	void __iomem	       *hcr;
588 	struct mutex		hcr_mutex;
589 	struct mutex		slave_cmd_mutex;
590 	struct semaphore	poll_sem;
591 	struct semaphore	event_sem;
592 	int			max_cmds;
593 	spinlock_t		context_lock;
594 	int			free_head;
595 	struct mlx4_cmd_context *context;
596 	u16			token_mask;
597 	u8			use_events;
598 	u8			toggle;
599 	u8			comm_toggle;
600 };
601 
602 enum {
603 	MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0,
604 	MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1,
605 	MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE = 1 << 2,
606 };
607 struct mlx4_vf_immed_vlan_work {
608 	struct work_struct	work;
609 	struct mlx4_priv	*priv;
610 	int			flags;
611 	int			slave;
612 	int			vlan_ix;
613 	int			orig_vlan_ix;
614 	u8			port;
615 	u8			qos;
616 	u16			vlan_id;
617 	u16			orig_vlan_id;
618 };
619 
620 
621 struct mlx4_uar_table {
622 	struct mlx4_bitmap	bitmap;
623 };
624 
625 struct mlx4_mr_table {
626 	struct mlx4_bitmap	mpt_bitmap;
627 	struct mlx4_buddy	mtt_buddy;
628 	u64			mtt_base;
629 	u64			mpt_base;
630 	struct mlx4_icm_table	mtt_table;
631 	struct mlx4_icm_table	dmpt_table;
632 };
633 
634 struct mlx4_cq_table {
635 	struct mlx4_bitmap	bitmap;
636 	spinlock_t		lock;
637 	struct radix_tree_root	tree;
638 	struct mlx4_icm_table	table;
639 	struct mlx4_icm_table	cmpt_table;
640 };
641 
642 struct mlx4_eq_table {
643 	struct mlx4_bitmap	bitmap;
644 	char		       *irq_names;
645 	void __iomem	       *clr_int;
646 	void __iomem	      **uar_map;
647 	u32			clr_mask;
648 	struct mlx4_eq	       *eq;
649 	struct mlx4_icm_table	table;
650 	struct mlx4_icm_table	cmpt_table;
651 	int			have_irq;
652 	u8			inta_pin;
653 };
654 
655 struct mlx4_srq_table {
656 	struct mlx4_bitmap	bitmap;
657 	spinlock_t		lock;
658 	struct radix_tree_root	tree;
659 	struct mlx4_icm_table	table;
660 	struct mlx4_icm_table	cmpt_table;
661 };
662 
663 struct mlx4_qp_table {
664 	struct mlx4_bitmap	bitmap;
665 	u32			rdmarc_base;
666 	int			rdmarc_shift;
667 	spinlock_t		lock;
668 	struct mlx4_icm_table	qp_table;
669 	struct mlx4_icm_table	auxc_table;
670 	struct mlx4_icm_table	altc_table;
671 	struct mlx4_icm_table	rdmarc_table;
672 	struct mlx4_icm_table	cmpt_table;
673 };
674 
675 struct mlx4_mcg_table {
676 	struct mutex		mutex;
677 	struct mlx4_bitmap	bitmap;
678 	struct mlx4_icm_table	table;
679 };
680 
681 struct mlx4_catas_err {
682 	u32 __iomem	       *map;
683 	struct timer_list	timer;
684 	struct list_head	list;
685 };
686 
687 #define MLX4_MAX_MAC_NUM	128
688 #define MLX4_MAC_TABLE_SIZE	(MLX4_MAX_MAC_NUM << 3)
689 
690 struct mlx4_mac_table {
691 	__be64			entries[MLX4_MAX_MAC_NUM];
692 	int			refs[MLX4_MAX_MAC_NUM];
693 	struct mutex		mutex;
694 	int			total;
695 	int			max;
696 };
697 
698 #define MLX4_MAX_VLAN_NUM	128
699 #define MLX4_VLAN_TABLE_SIZE	(MLX4_MAX_VLAN_NUM << 2)
700 
701 struct mlx4_vlan_table {
702 	__be32			entries[MLX4_MAX_VLAN_NUM];
703 	int			refs[MLX4_MAX_VLAN_NUM];
704 	struct mutex		mutex;
705 	int			total;
706 	int			max;
707 };
708 
709 #define SET_PORT_GEN_ALL_VALID		0x7
710 #define SET_PORT_PROMISC_SHIFT		31
711 #define SET_PORT_MC_PROMISC_SHIFT	30
712 
713 enum {
714 	MCAST_DIRECT_ONLY	= 0,
715 	MCAST_DIRECT		= 1,
716 	MCAST_DEFAULT		= 2
717 };
718 
719 
720 struct mlx4_set_port_general_context {
721 	u8 reserved[3];
722 	u8 flags;
723 	u16 reserved2;
724 	__be16 mtu;
725 	u8 pptx;
726 	u8 pfctx;
727 	u16 reserved3;
728 	u8 pprx;
729 	u8 pfcrx;
730 	u16 reserved4;
731 };
732 
733 struct mlx4_set_port_rqp_calc_context {
734 	__be32 base_qpn;
735 	u8 rererved;
736 	u8 n_mac;
737 	u8 n_vlan;
738 	u8 n_prio;
739 	u8 reserved2[3];
740 	u8 mac_miss;
741 	u8 intra_no_vlan;
742 	u8 no_vlan;
743 	u8 intra_vlan_miss;
744 	u8 vlan_miss;
745 	u8 reserved3[3];
746 	u8 no_vlan_prio;
747 	__be32 promisc;
748 	__be32 mcast;
749 };
750 
751 struct mlx4_port_info {
752 	struct mlx4_dev	       *dev;
753 	int			port;
754 	char			dev_name[16];
755 	struct device_attribute port_attr;
756 	enum mlx4_port_type	tmp_type;
757 	char			dev_mtu_name[16];
758 	struct device_attribute port_mtu_attr;
759 	struct mlx4_mac_table	mac_table;
760 	struct mlx4_vlan_table	vlan_table;
761 	int			base_qpn;
762 };
763 
764 struct mlx4_sense {
765 	struct mlx4_dev		*dev;
766 	u8			do_sense_port[MLX4_MAX_PORTS + 1];
767 	u8			sense_allowed[MLX4_MAX_PORTS + 1];
768 	struct delayed_work	sense_poll;
769 };
770 
771 struct mlx4_msix_ctl {
772 	u64		pool_bm;
773 	struct mutex	pool_lock;
774 };
775 
776 struct mlx4_steer {
777 	struct list_head promisc_qps[MLX4_NUM_STEERS];
778 	struct list_head steer_entries[MLX4_NUM_STEERS];
779 };
780 
781 enum {
782 	MLX4_PCI_DEV_IS_VF		= 1 << 0,
783 	MLX4_PCI_DEV_FORCE_SENSE_PORT	= 1 << 1,
784 };
785 
786 enum {
787 	MLX4_NO_RR	= 0,
788 	MLX4_USE_RR	= 1,
789 };
790 
791 struct mlx4_roce_gid_entry {
792 	u8 raw[16];
793 };
794 
795 struct mlx4_priv {
796 	struct mlx4_dev		dev;
797 
798 	struct list_head	dev_list;
799 	struct list_head	ctx_list;
800 	spinlock_t		ctx_lock;
801 
802 	int			pci_dev_data;
803 
804 	struct list_head        pgdir_list;
805 	struct mutex            pgdir_mutex;
806 
807 	struct mlx4_fw		fw;
808 	struct mlx4_cmd		cmd;
809 	struct mlx4_mfunc	mfunc;
810 
811 	struct mlx4_bitmap	pd_bitmap;
812 	struct mlx4_bitmap	xrcd_bitmap;
813 	struct mlx4_uar_table	uar_table;
814 	struct mlx4_mr_table	mr_table;
815 	struct mlx4_cq_table	cq_table;
816 	struct mlx4_eq_table	eq_table;
817 	struct mlx4_srq_table	srq_table;
818 	struct mlx4_qp_table	qp_table;
819 	struct mlx4_mcg_table	mcg_table;
820 	struct mlx4_bitmap	counters_bitmap;
821 
822 	struct mlx4_catas_err	catas_err;
823 
824 	void __iomem	       *clr_base;
825 
826 	struct mlx4_uar		driver_uar;
827 	void __iomem	       *kar;
828 	struct mlx4_port_info	port[MLX4_MAX_PORTS + 1];
829 	struct mlx4_sense       sense;
830 	struct mutex		port_mutex;
831 	struct mlx4_msix_ctl	msix_ctl;
832 	struct mlx4_steer	*steer;
833 	struct list_head	bf_list;
834 	struct mutex		bf_mutex;
835 	struct io_mapping	*bf_mapping;
836 	void __iomem            *clock_mapping;
837 	int			reserved_mtts;
838 	int			fs_hash_mode;
839 	u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
840 	__be64			slave_node_guids[MLX4_MFUNC_MAX];
841 	struct mlx4_roce_gid_entry roce_gids[MLX4_MAX_PORTS][MLX4_ROCE_MAX_GIDS];
842 
843 	atomic_t		opreq_count;
844 	struct work_struct	opreq_task;
845 };
846 
847 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
848 {
849 	return container_of(dev, struct mlx4_priv, dev);
850 }
851 
852 #define MLX4_SENSE_RANGE	(HZ * 3)
853 
854 extern struct workqueue_struct *mlx4_wq;
855 
856 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
857 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj, int use_rr);
858 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
859 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt,
860 			    int use_rr);
861 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
862 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
863 		     u32 reserved_bot, u32 resetrved_top);
864 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
865 
866 int mlx4_reset(struct mlx4_dev *dev);
867 
868 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
869 void mlx4_free_eq_table(struct mlx4_dev *dev);
870 
871 int mlx4_init_pd_table(struct mlx4_dev *dev);
872 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
873 int mlx4_init_uar_table(struct mlx4_dev *dev);
874 int mlx4_init_mr_table(struct mlx4_dev *dev);
875 int mlx4_init_eq_table(struct mlx4_dev *dev);
876 int mlx4_init_cq_table(struct mlx4_dev *dev);
877 int mlx4_init_qp_table(struct mlx4_dev *dev);
878 int mlx4_init_srq_table(struct mlx4_dev *dev);
879 int mlx4_init_mcg_table(struct mlx4_dev *dev);
880 
881 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
882 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
883 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
884 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
885 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
886 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
887 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
888 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
889 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
890 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
891 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
892 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
893 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
894 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
895 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
896 int __mlx4_mpt_reserve(struct mlx4_dev *dev);
897 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index);
898 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index);
899 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index);
900 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
901 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
902 
903 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
904 			   struct mlx4_vhcr *vhcr,
905 			   struct mlx4_cmd_mailbox *inbox,
906 			   struct mlx4_cmd_mailbox *outbox,
907 			   struct mlx4_cmd_info *cmd);
908 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
909 			   struct mlx4_vhcr *vhcr,
910 			   struct mlx4_cmd_mailbox *inbox,
911 			   struct mlx4_cmd_mailbox *outbox,
912 			   struct mlx4_cmd_info *cmd);
913 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
914 			   struct mlx4_vhcr *vhcr,
915 			   struct mlx4_cmd_mailbox *inbox,
916 			   struct mlx4_cmd_mailbox *outbox,
917 			   struct mlx4_cmd_info *cmd);
918 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
919 			   struct mlx4_vhcr *vhcr,
920 			   struct mlx4_cmd_mailbox *inbox,
921 			   struct mlx4_cmd_mailbox *outbox,
922 			   struct mlx4_cmd_info *cmd);
923 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
924 			   struct mlx4_vhcr *vhcr,
925 			   struct mlx4_cmd_mailbox *inbox,
926 			   struct mlx4_cmd_mailbox *outbox,
927 			   struct mlx4_cmd_info *cmd);
928 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
929 			  struct mlx4_vhcr *vhcr,
930 			  struct mlx4_cmd_mailbox *inbox,
931 			  struct mlx4_cmd_mailbox *outbox,
932 			  struct mlx4_cmd_info *cmd);
933 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
934 		     struct mlx4_vhcr *vhcr,
935 		     struct mlx4_cmd_mailbox *inbox,
936 		     struct mlx4_cmd_mailbox *outbox,
937 		     struct mlx4_cmd_info *cmd);
938 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
939 			    int *base);
940 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
941 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
942 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
943 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
944 		     int start_index, int npages, u64 *page_list);
945 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
946 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
947 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
948 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
949 
950 void mlx4_start_catas_poll(struct mlx4_dev *dev);
951 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
952 void mlx4_catas_init(void);
953 int mlx4_restart_one(struct pci_dev *pdev);
954 int mlx4_register_device(struct mlx4_dev *dev);
955 void mlx4_unregister_device(struct mlx4_dev *dev);
956 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
957 			 unsigned long param);
958 
959 struct mlx4_dev_cap;
960 struct mlx4_init_hca_param;
961 
962 u64 mlx4_make_profile(struct mlx4_dev *dev,
963 		      struct mlx4_profile *request,
964 		      struct mlx4_dev_cap *dev_cap,
965 		      struct mlx4_init_hca_param *init_hca);
966 void mlx4_master_comm_channel(struct work_struct *work);
967 void mlx4_gen_slave_eqe(struct work_struct *work);
968 void mlx4_master_handle_slave_flr(struct work_struct *work);
969 
970 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
971 			   struct mlx4_vhcr *vhcr,
972 			   struct mlx4_cmd_mailbox *inbox,
973 			   struct mlx4_cmd_mailbox *outbox,
974 			   struct mlx4_cmd_info *cmd);
975 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
976 			  struct mlx4_vhcr *vhcr,
977 			  struct mlx4_cmd_mailbox *inbox,
978 			  struct mlx4_cmd_mailbox *outbox,
979 			  struct mlx4_cmd_info *cmd);
980 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
981 			struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
982 			struct mlx4_cmd_mailbox *outbox,
983 			struct mlx4_cmd_info *cmd);
984 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
985 			  struct mlx4_vhcr *vhcr,
986 			  struct mlx4_cmd_mailbox *inbox,
987 			  struct mlx4_cmd_mailbox *outbox,
988 			  struct mlx4_cmd_info *cmd);
989 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
990 			    struct mlx4_vhcr *vhcr,
991 			    struct mlx4_cmd_mailbox *inbox,
992 			    struct mlx4_cmd_mailbox *outbox,
993 			  struct mlx4_cmd_info *cmd);
994 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
995 			  struct mlx4_vhcr *vhcr,
996 			  struct mlx4_cmd_mailbox *inbox,
997 			  struct mlx4_cmd_mailbox *outbox,
998 			  struct mlx4_cmd_info *cmd);
999 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1000 			  struct mlx4_vhcr *vhcr,
1001 			  struct mlx4_cmd_mailbox *inbox,
1002 			  struct mlx4_cmd_mailbox *outbox,
1003 			  struct mlx4_cmd_info *cmd);
1004 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1005 			  struct mlx4_vhcr *vhcr,
1006 			  struct mlx4_cmd_mailbox *inbox,
1007 			  struct mlx4_cmd_mailbox *outbox,
1008 			  struct mlx4_cmd_info *cmd);
1009 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1010 			  struct mlx4_vhcr *vhcr,
1011 			  struct mlx4_cmd_mailbox *inbox,
1012 			  struct mlx4_cmd_mailbox *outbox,
1013 			  struct mlx4_cmd_info *cmd);
1014 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1015 			  struct mlx4_vhcr *vhcr,
1016 			  struct mlx4_cmd_mailbox *inbox,
1017 			  struct mlx4_cmd_mailbox *outbox,
1018 			   struct mlx4_cmd_info *cmd);
1019 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1020 			   struct mlx4_vhcr *vhcr,
1021 			   struct mlx4_cmd_mailbox *inbox,
1022 			   struct mlx4_cmd_mailbox *outbox,
1023 			   struct mlx4_cmd_info *cmd);
1024 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1025 			   struct mlx4_vhcr *vhcr,
1026 			   struct mlx4_cmd_mailbox *inbox,
1027 			   struct mlx4_cmd_mailbox *outbox,
1028 			   struct mlx4_cmd_info *cmd);
1029 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1030 			   struct mlx4_vhcr *vhcr,
1031 			   struct mlx4_cmd_mailbox *inbox,
1032 			   struct mlx4_cmd_mailbox *outbox,
1033 			   struct mlx4_cmd_info *cmd);
1034 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1035 			 struct mlx4_vhcr *vhcr,
1036 			 struct mlx4_cmd_mailbox *inbox,
1037 			 struct mlx4_cmd_mailbox *outbox,
1038 			 struct mlx4_cmd_info *cmd);
1039 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
1040 			struct mlx4_vhcr *vhcr,
1041 			struct mlx4_cmd_mailbox *inbox,
1042 			struct mlx4_cmd_mailbox *outbox,
1043 			struct mlx4_cmd_info *cmd);
1044 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1045 			     struct mlx4_vhcr *vhcr,
1046 			     struct mlx4_cmd_mailbox *inbox,
1047 			     struct mlx4_cmd_mailbox *outbox,
1048 			     struct mlx4_cmd_info *cmd);
1049 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1050 			      struct mlx4_vhcr *vhcr,
1051 			      struct mlx4_cmd_mailbox *inbox,
1052 			      struct mlx4_cmd_mailbox *outbox,
1053 			      struct mlx4_cmd_info *cmd);
1054 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
1055 			     struct mlx4_vhcr *vhcr,
1056 			     struct mlx4_cmd_mailbox *inbox,
1057 			     struct mlx4_cmd_mailbox *outbox,
1058 			     struct mlx4_cmd_info *cmd);
1059 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1060 			    struct mlx4_vhcr *vhcr,
1061 			    struct mlx4_cmd_mailbox *inbox,
1062 			    struct mlx4_cmd_mailbox *outbox,
1063 			    struct mlx4_cmd_info *cmd);
1064 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1065 			    struct mlx4_vhcr *vhcr,
1066 			    struct mlx4_cmd_mailbox *inbox,
1067 			    struct mlx4_cmd_mailbox *outbox,
1068 			    struct mlx4_cmd_info *cmd);
1069 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1070 			      struct mlx4_vhcr *vhcr,
1071 			      struct mlx4_cmd_mailbox *inbox,
1072 			      struct mlx4_cmd_mailbox *outbox,
1073 			      struct mlx4_cmd_info *cmd);
1074 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave,
1075 			 struct mlx4_vhcr *vhcr,
1076 			 struct mlx4_cmd_mailbox *inbox,
1077 			 struct mlx4_cmd_mailbox *outbox,
1078 			 struct mlx4_cmd_info *cmd);
1079 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1080 			    struct mlx4_vhcr *vhcr,
1081 			    struct mlx4_cmd_mailbox *inbox,
1082 			    struct mlx4_cmd_mailbox *outbox,
1083 			    struct mlx4_cmd_info *cmd);
1084 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1085 			    struct mlx4_vhcr *vhcr,
1086 			    struct mlx4_cmd_mailbox *inbox,
1087 			    struct mlx4_cmd_mailbox *outbox,
1088 			    struct mlx4_cmd_info *cmd);
1089 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1090 			    struct mlx4_vhcr *vhcr,
1091 			    struct mlx4_cmd_mailbox *inbox,
1092 			    struct mlx4_cmd_mailbox *outbox,
1093 			    struct mlx4_cmd_info *cmd);
1094 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1095 			 struct mlx4_vhcr *vhcr,
1096 			 struct mlx4_cmd_mailbox *inbox,
1097 			 struct mlx4_cmd_mailbox *outbox,
1098 			 struct mlx4_cmd_info *cmd);
1099 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave,
1100 			  struct mlx4_vhcr *vhcr,
1101 			  struct mlx4_cmd_mailbox *inbox,
1102 			  struct mlx4_cmd_mailbox *outbox,
1103 			  struct mlx4_cmd_info *cmd);
1104 
1105 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
1106 
1107 int mlx4_cmd_init(struct mlx4_dev *dev);
1108 void mlx4_cmd_cleanup(struct mlx4_dev *dev);
1109 int mlx4_multi_func_init(struct mlx4_dev *dev);
1110 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
1111 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1112 int mlx4_cmd_use_events(struct mlx4_dev *dev);
1113 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1114 
1115 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1116 		  unsigned long timeout);
1117 
1118 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1119 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1120 
1121 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1122 
1123 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1124 
1125 void mlx4_handle_catas_err(struct mlx4_dev *dev);
1126 
1127 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1128 		    enum mlx4_port_type *type);
1129 void mlx4_do_sense_ports(struct mlx4_dev *dev,
1130 			 enum mlx4_port_type *stype,
1131 			 enum mlx4_port_type *defaults);
1132 void mlx4_start_sense(struct mlx4_dev *dev);
1133 void mlx4_stop_sense(struct mlx4_dev *dev);
1134 void mlx4_sense_init(struct mlx4_dev *dev);
1135 int mlx4_check_port_params(struct mlx4_dev *dev,
1136 			   enum mlx4_port_type *port_type);
1137 int mlx4_change_port_types(struct mlx4_dev *dev,
1138 			   enum mlx4_port_type *port_types);
1139 
1140 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1141 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1142 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1143 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1144 
1145 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
1146 /* resource tracker functions*/
1147 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1148 				    enum mlx4_resource resource_type,
1149 				    u64 resource_id, int *slave);
1150 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1151 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1152 
1153 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1154 				enum mlx4_res_tracker_free_type type);
1155 
1156 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1157 			  struct mlx4_vhcr *vhcr,
1158 			  struct mlx4_cmd_mailbox *inbox,
1159 			  struct mlx4_cmd_mailbox *outbox,
1160 			  struct mlx4_cmd_info *cmd);
1161 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1162 			  struct mlx4_vhcr *vhcr,
1163 			  struct mlx4_cmd_mailbox *inbox,
1164 			  struct mlx4_cmd_mailbox *outbox,
1165 			  struct mlx4_cmd_info *cmd);
1166 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1167 			   struct mlx4_vhcr *vhcr,
1168 			   struct mlx4_cmd_mailbox *inbox,
1169 			   struct mlx4_cmd_mailbox *outbox,
1170 			   struct mlx4_cmd_info *cmd);
1171 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1172 			    struct mlx4_vhcr *vhcr,
1173 			    struct mlx4_cmd_mailbox *inbox,
1174 			    struct mlx4_cmd_mailbox *outbox,
1175 			    struct mlx4_cmd_info *cmd);
1176 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1177 			       struct mlx4_vhcr *vhcr,
1178 			       struct mlx4_cmd_mailbox *inbox,
1179 			       struct mlx4_cmd_mailbox *outbox,
1180 			       struct mlx4_cmd_info *cmd);
1181 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1182 			    struct mlx4_vhcr *vhcr,
1183 			    struct mlx4_cmd_mailbox *inbox,
1184 			    struct mlx4_cmd_mailbox *outbox,
1185 			    struct mlx4_cmd_info *cmd);
1186 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1187 
1188 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1189 				    int *gid_tbl_len, int *pkey_tbl_len);
1190 
1191 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1192 			   struct mlx4_vhcr *vhcr,
1193 			   struct mlx4_cmd_mailbox *inbox,
1194 			   struct mlx4_cmd_mailbox *outbox,
1195 			   struct mlx4_cmd_info *cmd);
1196 
1197 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1198 			 struct mlx4_vhcr *vhcr,
1199 			 struct mlx4_cmd_mailbox *inbox,
1200 			 struct mlx4_cmd_mailbox *outbox,
1201 			 struct mlx4_cmd_info *cmd);
1202 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1203 			  enum mlx4_protocol prot, enum mlx4_steer_type steer);
1204 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1205 			  int block_mcast_loopback, enum mlx4_protocol prot,
1206 			  enum mlx4_steer_type steer);
1207 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1208 			      u8 gid[16], u8 port,
1209 			      int block_mcast_loopback,
1210 			      enum mlx4_protocol prot, u64 *reg_id);
1211 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1212 				struct mlx4_vhcr *vhcr,
1213 				struct mlx4_cmd_mailbox *inbox,
1214 				struct mlx4_cmd_mailbox *outbox,
1215 				struct mlx4_cmd_info *cmd);
1216 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1217 			       struct mlx4_vhcr *vhcr,
1218 			       struct mlx4_cmd_mailbox *inbox,
1219 			       struct mlx4_cmd_mailbox *outbox,
1220 			       struct mlx4_cmd_info *cmd);
1221 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1222 				     int port, void *buf);
1223 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1224 				struct mlx4_cmd_mailbox *outbox);
1225 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1226 				   struct mlx4_vhcr *vhcr,
1227 				   struct mlx4_cmd_mailbox *inbox,
1228 				   struct mlx4_cmd_mailbox *outbox,
1229 				struct mlx4_cmd_info *cmd);
1230 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1231 			    struct mlx4_vhcr *vhcr,
1232 			    struct mlx4_cmd_mailbox *inbox,
1233 			    struct mlx4_cmd_mailbox *outbox,
1234 			    struct mlx4_cmd_info *cmd);
1235 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1236 			       struct mlx4_vhcr *vhcr,
1237 			       struct mlx4_cmd_mailbox *inbox,
1238 			       struct mlx4_cmd_mailbox *outbox,
1239 			       struct mlx4_cmd_info *cmd);
1240 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1241 					 struct mlx4_vhcr *vhcr,
1242 					 struct mlx4_cmd_mailbox *inbox,
1243 					 struct mlx4_cmd_mailbox *outbox,
1244 					 struct mlx4_cmd_info *cmd);
1245 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1246 					 struct mlx4_vhcr *vhcr,
1247 					 struct mlx4_cmd_mailbox *inbox,
1248 					 struct mlx4_cmd_mailbox *outbox,
1249 					 struct mlx4_cmd_info *cmd);
1250 
1251 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1252 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1253 
1254 static inline void set_param_l(u64 *arg, u32 val)
1255 {
1256 	*arg = (*arg & 0xffffffff00000000ULL) | (u64) val;
1257 }
1258 
1259 static inline void set_param_h(u64 *arg, u32 val)
1260 {
1261 	*arg = (*arg & 0xffffffff) | ((u64) val << 32);
1262 }
1263 
1264 static inline u32 get_param_l(u64 *arg)
1265 {
1266 	return (u32) (*arg & 0xffffffff);
1267 }
1268 
1269 static inline u32 get_param_h(u64 *arg)
1270 {
1271 	return (u32)(*arg >> 32);
1272 }
1273 
1274 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1275 {
1276 	return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1277 }
1278 
1279 #define NOT_MASKED_PD_BITS 17
1280 
1281 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work);
1282 
1283 void mlx4_init_quotas(struct mlx4_dev *dev);
1284 
1285 int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port);
1286 /* Returns the VF index of slave */
1287 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave);
1288 
1289 #endif /* MLX4_H */
1290