1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved. 5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved. 7 * 8 * This software is available to you under a choice of one of two 9 * licenses. You may choose to be licensed under the terms of the GNU 10 * General Public License (GPL) Version 2, available from the file 11 * COPYING in the main directory of this source tree, or the 12 * OpenIB.org BSD license below: 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * - Redistributions of source code must retain the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer. 21 * 22 * - Redistributions in binary form must reproduce the above 23 * copyright notice, this list of conditions and the following 24 * disclaimer in the documentation and/or other materials 25 * provided with the distribution. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 * SOFTWARE. 35 */ 36 37 #ifndef MLX4_H 38 #define MLX4_H 39 40 #include <linux/mutex.h> 41 #include <linux/radix-tree.h> 42 #include <linux/rbtree.h> 43 #include <linux/timer.h> 44 #include <linux/semaphore.h> 45 #include <linux/workqueue.h> 46 #include <linux/interrupt.h> 47 #include <linux/spinlock.h> 48 49 #include <linux/mlx4/device.h> 50 #include <linux/mlx4/driver.h> 51 #include <linux/mlx4/doorbell.h> 52 #include <linux/mlx4/cmd.h> 53 54 #define DRV_NAME "mlx4_core" 55 #define PFX DRV_NAME ": " 56 #define DRV_VERSION "2.2-1" 57 #define DRV_RELDATE "Feb, 2014" 58 59 #define MLX4_FS_UDP_UC_EN (1 << 1) 60 #define MLX4_FS_TCP_UC_EN (1 << 2) 61 #define MLX4_FS_NUM_OF_L2_ADDR 8 62 #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7 63 #define MLX4_FS_NUM_MCG (1 << 17) 64 65 #define INIT_HCA_TPT_MW_ENABLE (1 << 7) 66 67 struct mlx4_set_port_prio2tc_context { 68 u8 prio2tc[4]; 69 }; 70 71 struct mlx4_port_scheduler_tc_cfg_be { 72 __be16 pg; 73 __be16 bw_precentage; 74 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */ 75 __be16 max_bw_value; 76 }; 77 78 struct mlx4_set_port_scheduler_context { 79 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC]; 80 }; 81 82 enum { 83 MLX4_HCR_BASE = 0x80680, 84 MLX4_HCR_SIZE = 0x0001c, 85 MLX4_CLR_INT_SIZE = 0x00008, 86 MLX4_SLAVE_COMM_BASE = 0x0, 87 MLX4_COMM_PAGESIZE = 0x1000, 88 MLX4_CLOCK_SIZE = 0x00008, 89 MLX4_COMM_CHAN_CAPS = 0x8, 90 MLX4_COMM_CHAN_FLAGS = 0xc 91 }; 92 93 enum { 94 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10, 95 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7, 96 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12, 97 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2), 98 MLX4_MTT_ENTRY_PER_SEG = 8, 99 }; 100 101 enum { 102 MLX4_NUM_PDS = 1 << 15 103 }; 104 105 enum { 106 MLX4_CMPT_TYPE_QP = 0, 107 MLX4_CMPT_TYPE_SRQ = 1, 108 MLX4_CMPT_TYPE_CQ = 2, 109 MLX4_CMPT_TYPE_EQ = 3, 110 MLX4_CMPT_NUM_TYPE 111 }; 112 113 enum { 114 MLX4_CMPT_SHIFT = 24, 115 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT 116 }; 117 118 enum mlx4_mpt_state { 119 MLX4_MPT_DISABLED = 0, 120 MLX4_MPT_EN_HW, 121 MLX4_MPT_EN_SW 122 }; 123 124 #define MLX4_COMM_TIME 10000 125 #define MLX4_COMM_OFFLINE_TIME_OUT 30000 126 #define MLX4_COMM_CMD_NA_OP 0x0 127 128 129 enum { 130 MLX4_COMM_CMD_RESET, 131 MLX4_COMM_CMD_VHCR0, 132 MLX4_COMM_CMD_VHCR1, 133 MLX4_COMM_CMD_VHCR2, 134 MLX4_COMM_CMD_VHCR_EN, 135 MLX4_COMM_CMD_VHCR_POST, 136 MLX4_COMM_CMD_FLR = 254 137 }; 138 139 enum { 140 MLX4_VF_SMI_DISABLED, 141 MLX4_VF_SMI_ENABLED 142 }; 143 144 /*The flag indicates that the slave should delay the RESET cmd*/ 145 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb 146 /*indicates how many retries will be done if we are in the middle of FLR*/ 147 #define NUM_OF_RESET_RETRIES 10 148 #define SLEEP_TIME_IN_RESET (2 * 1000) 149 enum mlx4_resource { 150 RES_QP, 151 RES_CQ, 152 RES_SRQ, 153 RES_XRCD, 154 RES_MPT, 155 RES_MTT, 156 RES_MAC, 157 RES_VLAN, 158 RES_EQ, 159 RES_COUNTER, 160 RES_FS_RULE, 161 MLX4_NUM_OF_RESOURCE_TYPE 162 }; 163 164 enum mlx4_alloc_mode { 165 RES_OP_RESERVE, 166 RES_OP_RESERVE_AND_MAP, 167 RES_OP_MAP_ICM, 168 }; 169 170 enum mlx4_res_tracker_free_type { 171 RES_TR_FREE_ALL, 172 RES_TR_FREE_SLAVES_ONLY, 173 RES_TR_FREE_STRUCTS_ONLY, 174 }; 175 176 /* 177 *Virtual HCR structures. 178 * mlx4_vhcr is the sw representation, in machine endianness 179 * 180 * mlx4_vhcr_cmd is the formalized structure, the one that is passed 181 * to FW to go through communication channel. 182 * It is big endian, and has the same structure as the physical HCR 183 * used by command interface 184 */ 185 struct mlx4_vhcr { 186 u64 in_param; 187 u64 out_param; 188 u32 in_modifier; 189 u32 errno; 190 u16 op; 191 u16 token; 192 u8 op_modifier; 193 u8 e_bit; 194 }; 195 196 struct mlx4_vhcr_cmd { 197 __be64 in_param; 198 __be32 in_modifier; 199 u32 reserved1; 200 __be64 out_param; 201 __be16 token; 202 u16 reserved; 203 u8 status; 204 u8 flags; 205 __be16 opcode; 206 }; 207 208 struct mlx4_cmd_info { 209 u16 opcode; 210 bool has_inbox; 211 bool has_outbox; 212 bool out_is_imm; 213 bool encode_slave_id; 214 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 215 struct mlx4_cmd_mailbox *inbox); 216 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 217 struct mlx4_cmd_mailbox *inbox, 218 struct mlx4_cmd_mailbox *outbox, 219 struct mlx4_cmd_info *cmd); 220 }; 221 222 #ifdef CONFIG_MLX4_DEBUG 223 extern int mlx4_debug_level; 224 #else /* CONFIG_MLX4_DEBUG */ 225 #define mlx4_debug_level (0) 226 #endif /* CONFIG_MLX4_DEBUG */ 227 228 #define mlx4_dbg(mdev, format, ...) \ 229 do { \ 230 if (mlx4_debug_level) \ 231 dev_printk(KERN_DEBUG, \ 232 &(mdev)->persist->pdev->dev, format, \ 233 ##__VA_ARGS__); \ 234 } while (0) 235 236 #define mlx4_err(mdev, format, ...) \ 237 dev_err(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__) 238 #define mlx4_info(mdev, format, ...) \ 239 dev_info(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__) 240 #define mlx4_warn(mdev, format, ...) \ 241 dev_warn(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__) 242 243 extern int mlx4_log_num_mgm_entry_size; 244 extern int log_mtts_per_seg; 245 extern int mlx4_internal_err_reset; 246 247 #define MLX4_MAX_NUM_SLAVES (min(MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF, \ 248 MLX4_MFUNC_MAX)) 249 #define ALL_SLAVES 0xff 250 251 struct mlx4_bitmap { 252 u32 last; 253 u32 top; 254 u32 max; 255 u32 reserved_top; 256 u32 mask; 257 u32 avail; 258 u32 effective_len; 259 spinlock_t lock; 260 unsigned long *table; 261 }; 262 263 struct mlx4_buddy { 264 unsigned long **bits; 265 unsigned int *num_free; 266 u32 max_order; 267 spinlock_t lock; 268 }; 269 270 struct mlx4_icm; 271 272 struct mlx4_icm_table { 273 u64 virt; 274 int num_icm; 275 u32 num_obj; 276 int obj_size; 277 int lowmem; 278 int coherent; 279 struct mutex mutex; 280 struct mlx4_icm **icm; 281 }; 282 283 #define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28) 284 #define MLX4_MPT_FLAG_FREE (0x3UL << 28) 285 #define MLX4_MPT_FLAG_MIO (1 << 17) 286 #define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15) 287 #define MLX4_MPT_FLAG_PHYSICAL (1 << 9) 288 #define MLX4_MPT_FLAG_REGION (1 << 8) 289 290 #define MLX4_MPT_PD_MASK (0x1FFFFUL) 291 #define MLX4_MPT_PD_VF_MASK (0xFE0000UL) 292 #define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27) 293 #define MLX4_MPT_PD_FLAG_RAE (1 << 28) 294 #define MLX4_MPT_PD_FLAG_EN_INV (3 << 24) 295 296 #define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7) 297 298 #define MLX4_MPT_STATUS_SW 0xF0 299 #define MLX4_MPT_STATUS_HW 0x00 300 301 #define MLX4_CQE_SIZE_MASK_STRIDE 0x3 302 #define MLX4_EQE_SIZE_MASK_STRIDE 0x30 303 304 /* 305 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits. 306 */ 307 struct mlx4_mpt_entry { 308 __be32 flags; 309 __be32 qpn; 310 __be32 key; 311 __be32 pd_flags; 312 __be64 start; 313 __be64 length; 314 __be32 lkey; 315 __be32 win_cnt; 316 u8 reserved1[3]; 317 u8 mtt_rep; 318 __be64 mtt_addr; 319 __be32 mtt_sz; 320 __be32 entity_size; 321 __be32 first_byte_offset; 322 } __packed; 323 324 /* 325 * Must be packed because start is 64 bits but only aligned to 32 bits. 326 */ 327 struct mlx4_eq_context { 328 __be32 flags; 329 u16 reserved1[3]; 330 __be16 page_offset; 331 u8 log_eq_size; 332 u8 reserved2[4]; 333 u8 eq_period; 334 u8 reserved3; 335 u8 eq_max_count; 336 u8 reserved4[3]; 337 u8 intr; 338 u8 log_page_size; 339 u8 reserved5[2]; 340 u8 mtt_base_addr_h; 341 __be32 mtt_base_addr_l; 342 u32 reserved6[2]; 343 __be32 consumer_index; 344 __be32 producer_index; 345 u32 reserved7[4]; 346 }; 347 348 struct mlx4_cq_context { 349 __be32 flags; 350 u16 reserved1[3]; 351 __be16 page_offset; 352 __be32 logsize_usrpage; 353 __be16 cq_period; 354 __be16 cq_max_count; 355 u8 reserved2[3]; 356 u8 comp_eqn; 357 u8 log_page_size; 358 u8 reserved3[2]; 359 u8 mtt_base_addr_h; 360 __be32 mtt_base_addr_l; 361 __be32 last_notified_index; 362 __be32 solicit_producer_index; 363 __be32 consumer_index; 364 __be32 producer_index; 365 u32 reserved4[2]; 366 __be64 db_rec_addr; 367 }; 368 369 struct mlx4_srq_context { 370 __be32 state_logsize_srqn; 371 u8 logstride; 372 u8 reserved1; 373 __be16 xrcd; 374 __be32 pg_offset_cqn; 375 u32 reserved2; 376 u8 log_page_size; 377 u8 reserved3[2]; 378 u8 mtt_base_addr_h; 379 __be32 mtt_base_addr_l; 380 __be32 pd; 381 __be16 limit_watermark; 382 __be16 wqe_cnt; 383 u16 reserved4; 384 __be16 wqe_counter; 385 u32 reserved5; 386 __be64 db_rec_addr; 387 }; 388 389 struct mlx4_eq_tasklet { 390 struct list_head list; 391 struct list_head process_list; 392 struct tasklet_struct task; 393 /* lock on completion tasklet list */ 394 spinlock_t lock; 395 }; 396 397 struct mlx4_eq { 398 struct mlx4_dev *dev; 399 void __iomem *doorbell; 400 int eqn; 401 u32 cons_index; 402 u16 irq; 403 u16 have_irq; 404 int nent; 405 struct mlx4_buf_list *page_list; 406 struct mlx4_mtt mtt; 407 struct mlx4_eq_tasklet tasklet_ctx; 408 }; 409 410 struct mlx4_slave_eqe { 411 u8 type; 412 u8 port; 413 u32 param; 414 }; 415 416 struct mlx4_slave_event_eq_info { 417 int eqn; 418 u16 token; 419 }; 420 421 struct mlx4_profile { 422 int num_qp; 423 int rdmarc_per_qp; 424 int num_srq; 425 int num_cq; 426 int num_mcg; 427 int num_mpt; 428 unsigned num_mtt; 429 }; 430 431 struct mlx4_fw { 432 u64 clr_int_base; 433 u64 catas_offset; 434 u64 comm_base; 435 u64 clock_offset; 436 struct mlx4_icm *fw_icm; 437 struct mlx4_icm *aux_icm; 438 u32 catas_size; 439 u16 fw_pages; 440 u8 clr_int_bar; 441 u8 catas_bar; 442 u8 comm_bar; 443 u8 clock_bar; 444 }; 445 446 struct mlx4_comm { 447 u32 slave_write; 448 u32 slave_read; 449 }; 450 451 enum { 452 MLX4_MCAST_CONFIG = 0, 453 MLX4_MCAST_DISABLE = 1, 454 MLX4_MCAST_ENABLE = 2, 455 }; 456 457 #define VLAN_FLTR_SIZE 128 458 459 struct mlx4_vlan_fltr { 460 __be32 entry[VLAN_FLTR_SIZE]; 461 }; 462 463 struct mlx4_mcast_entry { 464 struct list_head list; 465 u64 addr; 466 }; 467 468 struct mlx4_promisc_qp { 469 struct list_head list; 470 u32 qpn; 471 }; 472 473 struct mlx4_steer_index { 474 struct list_head list; 475 unsigned int index; 476 struct list_head duplicates; 477 }; 478 479 #define MLX4_EVENT_TYPES_NUM 64 480 481 struct mlx4_slave_state { 482 u8 comm_toggle; 483 u8 last_cmd; 484 u8 init_port_mask; 485 bool active; 486 bool old_vlan_api; 487 u8 function; 488 dma_addr_t vhcr_dma; 489 u16 mtu[MLX4_MAX_PORTS + 1]; 490 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1]; 491 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES]; 492 struct list_head mcast_filters[MLX4_MAX_PORTS + 1]; 493 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1]; 494 /* event type to eq number lookup */ 495 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM]; 496 u16 eq_pi; 497 u16 eq_ci; 498 spinlock_t lock; 499 /*initialized via the kzalloc*/ 500 u8 is_slave_going_down; 501 u32 cookie; 502 enum slave_port_state port_state[MLX4_MAX_PORTS + 1]; 503 }; 504 505 #define MLX4_VGT 4095 506 #define NO_INDX (-1) 507 508 struct mlx4_vport_state { 509 u64 mac; 510 u16 default_vlan; 511 u8 default_qos; 512 u32 tx_rate; 513 bool spoofchk; 514 u32 link_state; 515 }; 516 517 struct mlx4_vf_admin_state { 518 struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1]; 519 u8 enable_smi[MLX4_MAX_PORTS + 1]; 520 }; 521 522 struct mlx4_vport_oper_state { 523 struct mlx4_vport_state state; 524 int mac_idx; 525 int vlan_idx; 526 }; 527 528 struct mlx4_vf_oper_state { 529 struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1]; 530 u8 smi_enabled[MLX4_MAX_PORTS + 1]; 531 }; 532 533 struct slave_list { 534 struct mutex mutex; 535 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE]; 536 }; 537 538 struct resource_allocator { 539 spinlock_t alloc_lock; /* protect quotas */ 540 union { 541 int res_reserved; 542 int res_port_rsvd[MLX4_MAX_PORTS]; 543 }; 544 union { 545 int res_free; 546 int res_port_free[MLX4_MAX_PORTS]; 547 }; 548 int *quota; 549 int *allocated; 550 int *guaranteed; 551 }; 552 553 struct mlx4_resource_tracker { 554 spinlock_t lock; 555 /* tree for each resources */ 556 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE]; 557 /* num_of_slave's lists, one per slave */ 558 struct slave_list *slave_list; 559 struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE]; 560 }; 561 562 #define SLAVE_EVENT_EQ_SIZE 128 563 struct mlx4_slave_event_eq { 564 u32 eqn; 565 u32 cons; 566 u32 prod; 567 spinlock_t event_lock; 568 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE]; 569 }; 570 571 struct mlx4_master_qp0_state { 572 int proxy_qp0_active; 573 int qp0_active; 574 int port_active; 575 }; 576 577 struct mlx4_mfunc_master_ctx { 578 struct mlx4_slave_state *slave_state; 579 struct mlx4_vf_admin_state *vf_admin; 580 struct mlx4_vf_oper_state *vf_oper; 581 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1]; 582 int init_port_ref[MLX4_MAX_PORTS + 1]; 583 u16 max_mtu[MLX4_MAX_PORTS + 1]; 584 int disable_mcast_ref[MLX4_MAX_PORTS + 1]; 585 struct mlx4_resource_tracker res_tracker; 586 struct workqueue_struct *comm_wq; 587 struct work_struct comm_work; 588 struct work_struct slave_event_work; 589 struct work_struct slave_flr_event_work; 590 spinlock_t slave_state_lock; 591 __be32 comm_arm_bit_vector[4]; 592 struct mlx4_eqe cmd_eqe; 593 struct mlx4_slave_event_eq slave_eq; 594 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX]; 595 }; 596 597 struct mlx4_mfunc { 598 struct mlx4_comm __iomem *comm; 599 struct mlx4_vhcr_cmd *vhcr; 600 dma_addr_t vhcr_dma; 601 602 struct mlx4_mfunc_master_ctx master; 603 }; 604 605 #define MGM_QPN_MASK 0x00FFFFFF 606 #define MGM_BLCK_LB_BIT 30 607 608 struct mlx4_mgm { 609 __be32 next_gid_index; 610 __be32 members_count; 611 u32 reserved[2]; 612 u8 gid[16]; 613 __be32 qp[MLX4_MAX_QP_PER_MGM]; 614 }; 615 616 struct mlx4_cmd { 617 struct pci_pool *pool; 618 void __iomem *hcr; 619 struct mutex slave_cmd_mutex; 620 struct semaphore poll_sem; 621 struct semaphore event_sem; 622 int max_cmds; 623 spinlock_t context_lock; 624 int free_head; 625 struct mlx4_cmd_context *context; 626 u16 token_mask; 627 u8 use_events; 628 u8 toggle; 629 u8 comm_toggle; 630 u8 initialized; 631 }; 632 633 enum { 634 MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0, 635 MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1, 636 MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE = 1 << 2, 637 }; 638 struct mlx4_vf_immed_vlan_work { 639 struct work_struct work; 640 struct mlx4_priv *priv; 641 int flags; 642 int slave; 643 int vlan_ix; 644 int orig_vlan_ix; 645 u8 port; 646 u8 qos; 647 u16 vlan_id; 648 u16 orig_vlan_id; 649 }; 650 651 652 struct mlx4_uar_table { 653 struct mlx4_bitmap bitmap; 654 }; 655 656 struct mlx4_mr_table { 657 struct mlx4_bitmap mpt_bitmap; 658 struct mlx4_buddy mtt_buddy; 659 u64 mtt_base; 660 u64 mpt_base; 661 struct mlx4_icm_table mtt_table; 662 struct mlx4_icm_table dmpt_table; 663 }; 664 665 struct mlx4_cq_table { 666 struct mlx4_bitmap bitmap; 667 spinlock_t lock; 668 struct radix_tree_root tree; 669 struct mlx4_icm_table table; 670 struct mlx4_icm_table cmpt_table; 671 }; 672 673 struct mlx4_eq_table { 674 struct mlx4_bitmap bitmap; 675 char *irq_names; 676 void __iomem *clr_int; 677 void __iomem **uar_map; 678 u32 clr_mask; 679 struct mlx4_eq *eq; 680 struct mlx4_icm_table table; 681 struct mlx4_icm_table cmpt_table; 682 int have_irq; 683 u8 inta_pin; 684 }; 685 686 struct mlx4_srq_table { 687 struct mlx4_bitmap bitmap; 688 spinlock_t lock; 689 struct radix_tree_root tree; 690 struct mlx4_icm_table table; 691 struct mlx4_icm_table cmpt_table; 692 }; 693 694 enum mlx4_qp_table_zones { 695 MLX4_QP_TABLE_ZONE_GENERAL, 696 MLX4_QP_TABLE_ZONE_RSS, 697 MLX4_QP_TABLE_ZONE_RAW_ETH, 698 MLX4_QP_TABLE_ZONE_NUM 699 }; 700 701 struct mlx4_qp_table { 702 struct mlx4_bitmap *bitmap_gen; 703 struct mlx4_zone_allocator *zones; 704 u32 zones_uids[MLX4_QP_TABLE_ZONE_NUM]; 705 u32 rdmarc_base; 706 int rdmarc_shift; 707 spinlock_t lock; 708 struct mlx4_icm_table qp_table; 709 struct mlx4_icm_table auxc_table; 710 struct mlx4_icm_table altc_table; 711 struct mlx4_icm_table rdmarc_table; 712 struct mlx4_icm_table cmpt_table; 713 }; 714 715 struct mlx4_mcg_table { 716 struct mutex mutex; 717 struct mlx4_bitmap bitmap; 718 struct mlx4_icm_table table; 719 }; 720 721 struct mlx4_catas_err { 722 u32 __iomem *map; 723 struct timer_list timer; 724 struct list_head list; 725 }; 726 727 #define MLX4_MAX_MAC_NUM 128 728 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3) 729 730 struct mlx4_mac_table { 731 __be64 entries[MLX4_MAX_MAC_NUM]; 732 int refs[MLX4_MAX_MAC_NUM]; 733 struct mutex mutex; 734 int total; 735 int max; 736 }; 737 738 #define MLX4_ROCE_GID_ENTRY_SIZE 16 739 740 struct mlx4_roce_gid_entry { 741 u8 raw[MLX4_ROCE_GID_ENTRY_SIZE]; 742 }; 743 744 struct mlx4_roce_gid_table { 745 struct mlx4_roce_gid_entry roce_gids[MLX4_ROCE_MAX_GIDS]; 746 struct mutex mutex; 747 }; 748 749 #define MLX4_MAX_VLAN_NUM 128 750 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2) 751 752 struct mlx4_vlan_table { 753 __be32 entries[MLX4_MAX_VLAN_NUM]; 754 int refs[MLX4_MAX_VLAN_NUM]; 755 struct mutex mutex; 756 int total; 757 int max; 758 }; 759 760 #define SET_PORT_GEN_ALL_VALID 0x7 761 #define SET_PORT_PROMISC_SHIFT 31 762 #define SET_PORT_MC_PROMISC_SHIFT 30 763 764 enum { 765 MCAST_DIRECT_ONLY = 0, 766 MCAST_DIRECT = 1, 767 MCAST_DEFAULT = 2 768 }; 769 770 771 struct mlx4_set_port_general_context { 772 u8 reserved[3]; 773 u8 flags; 774 u16 reserved2; 775 __be16 mtu; 776 u8 pptx; 777 u8 pfctx; 778 u16 reserved3; 779 u8 pprx; 780 u8 pfcrx; 781 u16 reserved4; 782 }; 783 784 struct mlx4_set_port_rqp_calc_context { 785 __be32 base_qpn; 786 u8 rererved; 787 u8 n_mac; 788 u8 n_vlan; 789 u8 n_prio; 790 u8 reserved2[3]; 791 u8 mac_miss; 792 u8 intra_no_vlan; 793 u8 no_vlan; 794 u8 intra_vlan_miss; 795 u8 vlan_miss; 796 u8 reserved3[3]; 797 u8 no_vlan_prio; 798 __be32 promisc; 799 __be32 mcast; 800 }; 801 802 struct mlx4_port_info { 803 struct mlx4_dev *dev; 804 int port; 805 char dev_name[16]; 806 struct device_attribute port_attr; 807 enum mlx4_port_type tmp_type; 808 char dev_mtu_name[16]; 809 struct device_attribute port_mtu_attr; 810 struct mlx4_mac_table mac_table; 811 struct mlx4_vlan_table vlan_table; 812 struct mlx4_roce_gid_table gid_table; 813 int base_qpn; 814 }; 815 816 struct mlx4_sense { 817 struct mlx4_dev *dev; 818 u8 do_sense_port[MLX4_MAX_PORTS + 1]; 819 u8 sense_allowed[MLX4_MAX_PORTS + 1]; 820 struct delayed_work sense_poll; 821 }; 822 823 struct mlx4_msix_ctl { 824 u64 pool_bm; 825 struct mutex pool_lock; 826 }; 827 828 struct mlx4_steer { 829 struct list_head promisc_qps[MLX4_NUM_STEERS]; 830 struct list_head steer_entries[MLX4_NUM_STEERS]; 831 }; 832 833 enum { 834 MLX4_PCI_DEV_IS_VF = 1 << 0, 835 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1, 836 }; 837 838 enum { 839 MLX4_NO_RR = 0, 840 MLX4_USE_RR = 1, 841 }; 842 843 struct mlx4_priv { 844 struct mlx4_dev dev; 845 846 struct list_head dev_list; 847 struct list_head ctx_list; 848 spinlock_t ctx_lock; 849 850 int pci_dev_data; 851 int removed; 852 853 struct list_head pgdir_list; 854 struct mutex pgdir_mutex; 855 856 struct mlx4_fw fw; 857 struct mlx4_cmd cmd; 858 struct mlx4_mfunc mfunc; 859 860 struct mlx4_bitmap pd_bitmap; 861 struct mlx4_bitmap xrcd_bitmap; 862 struct mlx4_uar_table uar_table; 863 struct mlx4_mr_table mr_table; 864 struct mlx4_cq_table cq_table; 865 struct mlx4_eq_table eq_table; 866 struct mlx4_srq_table srq_table; 867 struct mlx4_qp_table qp_table; 868 struct mlx4_mcg_table mcg_table; 869 struct mlx4_bitmap counters_bitmap; 870 871 struct mlx4_catas_err catas_err; 872 873 void __iomem *clr_base; 874 875 struct mlx4_uar driver_uar; 876 void __iomem *kar; 877 struct mlx4_port_info port[MLX4_MAX_PORTS + 1]; 878 struct mlx4_sense sense; 879 struct mutex port_mutex; 880 struct mlx4_msix_ctl msix_ctl; 881 struct mlx4_steer *steer; 882 struct list_head bf_list; 883 struct mutex bf_mutex; 884 struct io_mapping *bf_mapping; 885 void __iomem *clock_mapping; 886 int reserved_mtts; 887 int fs_hash_mode; 888 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS]; 889 struct mlx4_port_map v2p; /* cached port mapping configuration */ 890 struct mutex bond_mutex; /* for bond mode */ 891 __be64 slave_node_guids[MLX4_MFUNC_MAX]; 892 893 atomic_t opreq_count; 894 struct work_struct opreq_task; 895 }; 896 897 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev) 898 { 899 return container_of(dev, struct mlx4_priv, dev); 900 } 901 902 #define MLX4_SENSE_RANGE (HZ * 3) 903 904 extern struct workqueue_struct *mlx4_wq; 905 906 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap); 907 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj, int use_rr); 908 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, 909 int align, u32 skip_mask); 910 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt, 911 int use_rr); 912 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap); 913 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, 914 u32 reserved_bot, u32 resetrved_top); 915 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap); 916 917 int mlx4_reset(struct mlx4_dev *dev); 918 919 int mlx4_alloc_eq_table(struct mlx4_dev *dev); 920 void mlx4_free_eq_table(struct mlx4_dev *dev); 921 922 int mlx4_init_pd_table(struct mlx4_dev *dev); 923 int mlx4_init_xrcd_table(struct mlx4_dev *dev); 924 int mlx4_init_uar_table(struct mlx4_dev *dev); 925 int mlx4_init_mr_table(struct mlx4_dev *dev); 926 int mlx4_init_eq_table(struct mlx4_dev *dev); 927 int mlx4_init_cq_table(struct mlx4_dev *dev); 928 int mlx4_init_qp_table(struct mlx4_dev *dev); 929 int mlx4_init_srq_table(struct mlx4_dev *dev); 930 int mlx4_init_mcg_table(struct mlx4_dev *dev); 931 932 void mlx4_cleanup_pd_table(struct mlx4_dev *dev); 933 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev); 934 void mlx4_cleanup_uar_table(struct mlx4_dev *dev); 935 void mlx4_cleanup_mr_table(struct mlx4_dev *dev); 936 void mlx4_cleanup_eq_table(struct mlx4_dev *dev); 937 void mlx4_cleanup_cq_table(struct mlx4_dev *dev); 938 void mlx4_cleanup_qp_table(struct mlx4_dev *dev); 939 void mlx4_cleanup_srq_table(struct mlx4_dev *dev); 940 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev); 941 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn, gfp_t gfp); 942 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn); 943 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn); 944 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn); 945 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn); 946 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn); 947 int __mlx4_mpt_reserve(struct mlx4_dev *dev); 948 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index); 949 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp); 950 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index); 951 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order); 952 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order); 953 954 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave, 955 struct mlx4_vhcr *vhcr, 956 struct mlx4_cmd_mailbox *inbox, 957 struct mlx4_cmd_mailbox *outbox, 958 struct mlx4_cmd_info *cmd); 959 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave, 960 struct mlx4_vhcr *vhcr, 961 struct mlx4_cmd_mailbox *inbox, 962 struct mlx4_cmd_mailbox *outbox, 963 struct mlx4_cmd_info *cmd); 964 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave, 965 struct mlx4_vhcr *vhcr, 966 struct mlx4_cmd_mailbox *inbox, 967 struct mlx4_cmd_mailbox *outbox, 968 struct mlx4_cmd_info *cmd); 969 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave, 970 struct mlx4_vhcr *vhcr, 971 struct mlx4_cmd_mailbox *inbox, 972 struct mlx4_cmd_mailbox *outbox, 973 struct mlx4_cmd_info *cmd); 974 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave, 975 struct mlx4_vhcr *vhcr, 976 struct mlx4_cmd_mailbox *inbox, 977 struct mlx4_cmd_mailbox *outbox, 978 struct mlx4_cmd_info *cmd); 979 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave, 980 struct mlx4_vhcr *vhcr, 981 struct mlx4_cmd_mailbox *inbox, 982 struct mlx4_cmd_mailbox *outbox, 983 struct mlx4_cmd_info *cmd); 984 int mlx4_CONFIG_DEV_wrapper(struct mlx4_dev *dev, int slave, 985 struct mlx4_vhcr *vhcr, 986 struct mlx4_cmd_mailbox *inbox, 987 struct mlx4_cmd_mailbox *outbox, 988 struct mlx4_cmd_info *cmd); 989 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave, 990 struct mlx4_vhcr *vhcr, 991 struct mlx4_cmd_mailbox *inbox, 992 struct mlx4_cmd_mailbox *outbox, 993 struct mlx4_cmd_info *cmd); 994 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 995 int *base, u8 flags); 996 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 997 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 998 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 999 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 1000 int start_index, int npages, u64 *page_list); 1001 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); 1002 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx); 1003 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 1004 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 1005 1006 void mlx4_start_catas_poll(struct mlx4_dev *dev); 1007 void mlx4_stop_catas_poll(struct mlx4_dev *dev); 1008 int mlx4_catas_init(struct mlx4_dev *dev); 1009 void mlx4_catas_end(struct mlx4_dev *dev); 1010 int mlx4_restart_one(struct pci_dev *pdev); 1011 int mlx4_register_device(struct mlx4_dev *dev); 1012 void mlx4_unregister_device(struct mlx4_dev *dev); 1013 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, 1014 unsigned long param); 1015 1016 struct mlx4_dev_cap; 1017 struct mlx4_init_hca_param; 1018 1019 u64 mlx4_make_profile(struct mlx4_dev *dev, 1020 struct mlx4_profile *request, 1021 struct mlx4_dev_cap *dev_cap, 1022 struct mlx4_init_hca_param *init_hca); 1023 void mlx4_master_comm_channel(struct work_struct *work); 1024 void mlx4_gen_slave_eqe(struct work_struct *work); 1025 void mlx4_master_handle_slave_flr(struct work_struct *work); 1026 1027 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave, 1028 struct mlx4_vhcr *vhcr, 1029 struct mlx4_cmd_mailbox *inbox, 1030 struct mlx4_cmd_mailbox *outbox, 1031 struct mlx4_cmd_info *cmd); 1032 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave, 1033 struct mlx4_vhcr *vhcr, 1034 struct mlx4_cmd_mailbox *inbox, 1035 struct mlx4_cmd_mailbox *outbox, 1036 struct mlx4_cmd_info *cmd); 1037 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave, 1038 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox, 1039 struct mlx4_cmd_mailbox *outbox, 1040 struct mlx4_cmd_info *cmd); 1041 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave, 1042 struct mlx4_vhcr *vhcr, 1043 struct mlx4_cmd_mailbox *inbox, 1044 struct mlx4_cmd_mailbox *outbox, 1045 struct mlx4_cmd_info *cmd); 1046 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave, 1047 struct mlx4_vhcr *vhcr, 1048 struct mlx4_cmd_mailbox *inbox, 1049 struct mlx4_cmd_mailbox *outbox, 1050 struct mlx4_cmd_info *cmd); 1051 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave, 1052 struct mlx4_vhcr *vhcr, 1053 struct mlx4_cmd_mailbox *inbox, 1054 struct mlx4_cmd_mailbox *outbox, 1055 struct mlx4_cmd_info *cmd); 1056 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave, 1057 struct mlx4_vhcr *vhcr, 1058 struct mlx4_cmd_mailbox *inbox, 1059 struct mlx4_cmd_mailbox *outbox, 1060 struct mlx4_cmd_info *cmd); 1061 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave, 1062 struct mlx4_vhcr *vhcr, 1063 struct mlx4_cmd_mailbox *inbox, 1064 struct mlx4_cmd_mailbox *outbox, 1065 struct mlx4_cmd_info *cmd); 1066 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave, 1067 struct mlx4_vhcr *vhcr, 1068 struct mlx4_cmd_mailbox *inbox, 1069 struct mlx4_cmd_mailbox *outbox, 1070 struct mlx4_cmd_info *cmd); 1071 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave, 1072 struct mlx4_vhcr *vhcr, 1073 struct mlx4_cmd_mailbox *inbox, 1074 struct mlx4_cmd_mailbox *outbox, 1075 struct mlx4_cmd_info *cmd); 1076 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1077 struct mlx4_vhcr *vhcr, 1078 struct mlx4_cmd_mailbox *inbox, 1079 struct mlx4_cmd_mailbox *outbox, 1080 struct mlx4_cmd_info *cmd); 1081 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1082 struct mlx4_vhcr *vhcr, 1083 struct mlx4_cmd_mailbox *inbox, 1084 struct mlx4_cmd_mailbox *outbox, 1085 struct mlx4_cmd_info *cmd); 1086 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1087 struct mlx4_vhcr *vhcr, 1088 struct mlx4_cmd_mailbox *inbox, 1089 struct mlx4_cmd_mailbox *outbox, 1090 struct mlx4_cmd_info *cmd); 1091 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1092 struct mlx4_vhcr *vhcr, 1093 struct mlx4_cmd_mailbox *inbox, 1094 struct mlx4_cmd_mailbox *outbox, 1095 struct mlx4_cmd_info *cmd); 1096 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave, 1097 struct mlx4_vhcr *vhcr, 1098 struct mlx4_cmd_mailbox *inbox, 1099 struct mlx4_cmd_mailbox *outbox, 1100 struct mlx4_cmd_info *cmd); 1101 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, 1102 struct mlx4_vhcr *vhcr, 1103 struct mlx4_cmd_mailbox *inbox, 1104 struct mlx4_cmd_mailbox *outbox, 1105 struct mlx4_cmd_info *cmd); 1106 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, 1107 struct mlx4_vhcr *vhcr, 1108 struct mlx4_cmd_mailbox *inbox, 1109 struct mlx4_cmd_mailbox *outbox, 1110 struct mlx4_cmd_info *cmd); 1111 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave, 1112 struct mlx4_vhcr *vhcr, 1113 struct mlx4_cmd_mailbox *inbox, 1114 struct mlx4_cmd_mailbox *outbox, 1115 struct mlx4_cmd_info *cmd); 1116 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1117 struct mlx4_vhcr *vhcr, 1118 struct mlx4_cmd_mailbox *inbox, 1119 struct mlx4_cmd_mailbox *outbox, 1120 struct mlx4_cmd_info *cmd); 1121 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1122 struct mlx4_vhcr *vhcr, 1123 struct mlx4_cmd_mailbox *inbox, 1124 struct mlx4_cmd_mailbox *outbox, 1125 struct mlx4_cmd_info *cmd); 1126 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1127 struct mlx4_vhcr *vhcr, 1128 struct mlx4_cmd_mailbox *inbox, 1129 struct mlx4_cmd_mailbox *outbox, 1130 struct mlx4_cmd_info *cmd); 1131 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave, 1132 struct mlx4_vhcr *vhcr, 1133 struct mlx4_cmd_mailbox *inbox, 1134 struct mlx4_cmd_mailbox *outbox, 1135 struct mlx4_cmd_info *cmd); 1136 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave, 1137 struct mlx4_vhcr *vhcr, 1138 struct mlx4_cmd_mailbox *inbox, 1139 struct mlx4_cmd_mailbox *outbox, 1140 struct mlx4_cmd_info *cmd); 1141 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave, 1142 struct mlx4_vhcr *vhcr, 1143 struct mlx4_cmd_mailbox *inbox, 1144 struct mlx4_cmd_mailbox *outbox, 1145 struct mlx4_cmd_info *cmd); 1146 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1147 struct mlx4_vhcr *vhcr, 1148 struct mlx4_cmd_mailbox *inbox, 1149 struct mlx4_cmd_mailbox *outbox, 1150 struct mlx4_cmd_info *cmd); 1151 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave, 1152 struct mlx4_vhcr *vhcr, 1153 struct mlx4_cmd_mailbox *inbox, 1154 struct mlx4_cmd_mailbox *outbox, 1155 struct mlx4_cmd_info *cmd); 1156 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave, 1157 struct mlx4_vhcr *vhcr, 1158 struct mlx4_cmd_mailbox *inbox, 1159 struct mlx4_cmd_mailbox *outbox, 1160 struct mlx4_cmd_info *cmd); 1161 1162 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe); 1163 1164 enum { 1165 MLX4_CMD_CLEANUP_STRUCT = 1UL << 0, 1166 MLX4_CMD_CLEANUP_POOL = 1UL << 1, 1167 MLX4_CMD_CLEANUP_HCR = 1UL << 2, 1168 MLX4_CMD_CLEANUP_VHCR = 1UL << 3, 1169 MLX4_CMD_CLEANUP_ALL = (MLX4_CMD_CLEANUP_VHCR << 1) - 1 1170 }; 1171 1172 int mlx4_cmd_init(struct mlx4_dev *dev); 1173 void mlx4_cmd_cleanup(struct mlx4_dev *dev, int cleanup_mask); 1174 int mlx4_multi_func_init(struct mlx4_dev *dev); 1175 int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev); 1176 void mlx4_multi_func_cleanup(struct mlx4_dev *dev); 1177 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param); 1178 int mlx4_cmd_use_events(struct mlx4_dev *dev); 1179 void mlx4_cmd_use_polling(struct mlx4_dev *dev); 1180 1181 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param, 1182 u16 op, unsigned long timeout); 1183 1184 void mlx4_cq_tasklet_cb(unsigned long data); 1185 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn); 1186 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type); 1187 1188 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type); 1189 1190 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type); 1191 1192 void mlx4_enter_error_state(struct mlx4_dev_persistent *persist); 1193 1194 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port, 1195 enum mlx4_port_type *type); 1196 void mlx4_do_sense_ports(struct mlx4_dev *dev, 1197 enum mlx4_port_type *stype, 1198 enum mlx4_port_type *defaults); 1199 void mlx4_start_sense(struct mlx4_dev *dev); 1200 void mlx4_stop_sense(struct mlx4_dev *dev); 1201 void mlx4_sense_init(struct mlx4_dev *dev); 1202 int mlx4_check_port_params(struct mlx4_dev *dev, 1203 enum mlx4_port_type *port_type); 1204 int mlx4_change_port_types(struct mlx4_dev *dev, 1205 enum mlx4_port_type *port_types); 1206 1207 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table); 1208 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table); 1209 void mlx4_init_roce_gid_table(struct mlx4_dev *dev, 1210 struct mlx4_roce_gid_table *table); 1211 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); 1212 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 1213 1214 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz); 1215 /* resource tracker functions*/ 1216 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev, 1217 enum mlx4_resource resource_type, 1218 u64 resource_id, int *slave); 1219 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id); 1220 void mlx4_reset_roce_gids(struct mlx4_dev *dev, int slave); 1221 int mlx4_init_resource_tracker(struct mlx4_dev *dev); 1222 1223 void mlx4_free_resource_tracker(struct mlx4_dev *dev, 1224 enum mlx4_res_tracker_free_type type); 1225 1226 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, 1227 struct mlx4_vhcr *vhcr, 1228 struct mlx4_cmd_mailbox *inbox, 1229 struct mlx4_cmd_mailbox *outbox, 1230 struct mlx4_cmd_info *cmd); 1231 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave, 1232 struct mlx4_vhcr *vhcr, 1233 struct mlx4_cmd_mailbox *inbox, 1234 struct mlx4_cmd_mailbox *outbox, 1235 struct mlx4_cmd_info *cmd); 1236 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, 1237 struct mlx4_vhcr *vhcr, 1238 struct mlx4_cmd_mailbox *inbox, 1239 struct mlx4_cmd_mailbox *outbox, 1240 struct mlx4_cmd_info *cmd); 1241 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, 1242 struct mlx4_vhcr *vhcr, 1243 struct mlx4_cmd_mailbox *inbox, 1244 struct mlx4_cmd_mailbox *outbox, 1245 struct mlx4_cmd_info *cmd); 1246 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, 1247 struct mlx4_vhcr *vhcr, 1248 struct mlx4_cmd_mailbox *inbox, 1249 struct mlx4_cmd_mailbox *outbox, 1250 struct mlx4_cmd_info *cmd); 1251 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, 1252 struct mlx4_vhcr *vhcr, 1253 struct mlx4_cmd_mailbox *inbox, 1254 struct mlx4_cmd_mailbox *outbox, 1255 struct mlx4_cmd_info *cmd); 1256 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps); 1257 1258 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, 1259 int *gid_tbl_len, int *pkey_tbl_len); 1260 1261 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave, 1262 struct mlx4_vhcr *vhcr, 1263 struct mlx4_cmd_mailbox *inbox, 1264 struct mlx4_cmd_mailbox *outbox, 1265 struct mlx4_cmd_info *cmd); 1266 1267 int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave, 1268 struct mlx4_vhcr *vhcr, 1269 struct mlx4_cmd_mailbox *inbox, 1270 struct mlx4_cmd_mailbox *outbox, 1271 struct mlx4_cmd_info *cmd); 1272 1273 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave, 1274 struct mlx4_vhcr *vhcr, 1275 struct mlx4_cmd_mailbox *inbox, 1276 struct mlx4_cmd_mailbox *outbox, 1277 struct mlx4_cmd_info *cmd); 1278 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1279 enum mlx4_protocol prot, enum mlx4_steer_type steer); 1280 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1281 int block_mcast_loopback, enum mlx4_protocol prot, 1282 enum mlx4_steer_type steer); 1283 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, 1284 u8 gid[16], u8 port, 1285 int block_mcast_loopback, 1286 enum mlx4_protocol prot, u64 *reg_id); 1287 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave, 1288 struct mlx4_vhcr *vhcr, 1289 struct mlx4_cmd_mailbox *inbox, 1290 struct mlx4_cmd_mailbox *outbox, 1291 struct mlx4_cmd_info *cmd); 1292 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave, 1293 struct mlx4_vhcr *vhcr, 1294 struct mlx4_cmd_mailbox *inbox, 1295 struct mlx4_cmd_mailbox *outbox, 1296 struct mlx4_cmd_info *cmd); 1297 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function, 1298 int port, void *buf); 1299 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod, 1300 struct mlx4_cmd_mailbox *outbox); 1301 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave, 1302 struct mlx4_vhcr *vhcr, 1303 struct mlx4_cmd_mailbox *inbox, 1304 struct mlx4_cmd_mailbox *outbox, 1305 struct mlx4_cmd_info *cmd); 1306 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave, 1307 struct mlx4_vhcr *vhcr, 1308 struct mlx4_cmd_mailbox *inbox, 1309 struct mlx4_cmd_mailbox *outbox, 1310 struct mlx4_cmd_info *cmd); 1311 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave, 1312 struct mlx4_vhcr *vhcr, 1313 struct mlx4_cmd_mailbox *inbox, 1314 struct mlx4_cmd_mailbox *outbox, 1315 struct mlx4_cmd_info *cmd); 1316 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave, 1317 struct mlx4_vhcr *vhcr, 1318 struct mlx4_cmd_mailbox *inbox, 1319 struct mlx4_cmd_mailbox *outbox, 1320 struct mlx4_cmd_info *cmd); 1321 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave, 1322 struct mlx4_vhcr *vhcr, 1323 struct mlx4_cmd_mailbox *inbox, 1324 struct mlx4_cmd_mailbox *outbox, 1325 struct mlx4_cmd_info *cmd); 1326 int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave, 1327 struct mlx4_vhcr *vhcr, 1328 struct mlx4_cmd_mailbox *inbox, 1329 struct mlx4_cmd_mailbox *outbox, 1330 struct mlx4_cmd_info *cmd); 1331 1332 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev); 1333 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev); 1334 1335 static inline void set_param_l(u64 *arg, u32 val) 1336 { 1337 *arg = (*arg & 0xffffffff00000000ULL) | (u64) val; 1338 } 1339 1340 static inline void set_param_h(u64 *arg, u32 val) 1341 { 1342 *arg = (*arg & 0xffffffff) | ((u64) val << 32); 1343 } 1344 1345 static inline u32 get_param_l(u64 *arg) 1346 { 1347 return (u32) (*arg & 0xffffffff); 1348 } 1349 1350 static inline u32 get_param_h(u64 *arg) 1351 { 1352 return (u32)(*arg >> 32); 1353 } 1354 1355 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev) 1356 { 1357 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock; 1358 } 1359 1360 #define NOT_MASKED_PD_BITS 17 1361 1362 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work); 1363 1364 void mlx4_init_quotas(struct mlx4_dev *dev); 1365 1366 int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port); 1367 /* Returns the VF index of slave */ 1368 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave); 1369 int mlx4_config_mad_demux(struct mlx4_dev *dev); 1370 int mlx4_do_bond(struct mlx4_dev *dev, bool enable); 1371 1372 enum mlx4_zone_flags { 1373 MLX4_ZONE_ALLOW_ALLOC_FROM_LOWER_PRIO = 1UL << 0, 1374 MLX4_ZONE_ALLOW_ALLOC_FROM_EQ_PRIO = 1UL << 1, 1375 MLX4_ZONE_FALLBACK_TO_HIGHER_PRIO = 1UL << 2, 1376 MLX4_ZONE_USE_RR = 1UL << 3, 1377 }; 1378 1379 enum mlx4_zone_alloc_flags { 1380 /* No two objects could overlap between zones. UID 1381 * could be left unused. If this flag is given and 1382 * two overlapped zones are used, an object will be free'd 1383 * from the smallest possible matching zone. 1384 */ 1385 MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP = 1UL << 0, 1386 }; 1387 1388 struct mlx4_zone_allocator; 1389 1390 /* Create a new zone allocator */ 1391 struct mlx4_zone_allocator *mlx4_zone_allocator_create(enum mlx4_zone_alloc_flags flags); 1392 1393 /* Attach a mlx4_bitmap <bitmap> of priority <priority> to the zone allocator 1394 * <zone_alloc>. Allocating an object from this zone adds an offset <offset>. 1395 * Similarly, when searching for an object to free, this offset it taken into 1396 * account. The use_rr mlx4_ib parameter for allocating objects from this <bitmap> 1397 * is given through the MLX4_ZONE_USE_RR flag in <flags>. 1398 * When an allocation fails, <zone_alloc> tries to allocate from other zones 1399 * according to the policy set by <flags>. <puid> is the unique identifier 1400 * received to this zone. 1401 */ 1402 int mlx4_zone_add_one(struct mlx4_zone_allocator *zone_alloc, 1403 struct mlx4_bitmap *bitmap, 1404 u32 flags, 1405 int priority, 1406 int offset, 1407 u32 *puid); 1408 1409 /* Remove bitmap indicated by <uid> from <zone_alloc> */ 1410 int mlx4_zone_remove_one(struct mlx4_zone_allocator *zone_alloc, u32 uid); 1411 1412 /* Delete the zone allocator <zone_alloc. This function doesn't destroy 1413 * the attached bitmaps. 1414 */ 1415 void mlx4_zone_allocator_destroy(struct mlx4_zone_allocator *zone_alloc); 1416 1417 /* Allocate <count> objects with align <align> and skip_mask <skip_mask> 1418 * from the mlx4_bitmap whose uid is <uid>. The bitmap which we actually 1419 * allocated from is returned in <puid>. If the allocation fails, a negative 1420 * number is returned. Otherwise, the offset of the first object is returned. 1421 */ 1422 u32 mlx4_zone_alloc_entries(struct mlx4_zone_allocator *zones, u32 uid, int count, 1423 int align, u32 skip_mask, u32 *puid); 1424 1425 /* Free <count> objects, start from <obj> of the uid <uid> from zone_allocator 1426 * <zones>. 1427 */ 1428 u32 mlx4_zone_free_entries(struct mlx4_zone_allocator *zones, 1429 u32 uid, u32 obj, u32 count); 1430 1431 /* If <zones> was allocated with MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP, instead of 1432 * specifying the uid when freeing an object, zone allocator could figure it by 1433 * itself. Other parameters are similar to mlx4_zone_free. 1434 */ 1435 u32 mlx4_zone_free_entries_unique(struct mlx4_zone_allocator *zones, u32 obj, u32 count); 1436 1437 /* Returns a pointer to mlx4_bitmap that was attached to <zones> with <uid> */ 1438 struct mlx4_bitmap *mlx4_zone_get_bitmap(struct mlx4_zone_allocator *zones, u32 uid); 1439 1440 #endif /* MLX4_H */ 1441