1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved. 5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved. 7 * 8 * This software is available to you under a choice of one of two 9 * licenses. You may choose to be licensed under the terms of the GNU 10 * General Public License (GPL) Version 2, available from the file 11 * COPYING in the main directory of this source tree, or the 12 * OpenIB.org BSD license below: 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * - Redistributions of source code must retain the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer. 21 * 22 * - Redistributions in binary form must reproduce the above 23 * copyright notice, this list of conditions and the following 24 * disclaimer in the documentation and/or other materials 25 * provided with the distribution. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 * SOFTWARE. 35 */ 36 37 #ifndef MLX4_H 38 #define MLX4_H 39 40 #include <linux/mutex.h> 41 #include <linux/radix-tree.h> 42 #include <linux/timer.h> 43 #include <linux/semaphore.h> 44 #include <linux/workqueue.h> 45 46 #include <linux/mlx4/device.h> 47 #include <linux/mlx4/driver.h> 48 #include <linux/mlx4/doorbell.h> 49 #include <linux/mlx4/cmd.h> 50 51 #define DRV_NAME "mlx4_core" 52 #define PFX DRV_NAME ": " 53 #define DRV_VERSION "1.1" 54 #define DRV_RELDATE "Dec, 2011" 55 56 enum { 57 MLX4_HCR_BASE = 0x80680, 58 MLX4_HCR_SIZE = 0x0001c, 59 MLX4_CLR_INT_SIZE = 0x00008, 60 MLX4_SLAVE_COMM_BASE = 0x0, 61 MLX4_COMM_PAGESIZE = 0x1000 62 }; 63 64 enum { 65 MLX4_MAX_MGM_ENTRY_SIZE = 0x1000, 66 MLX4_MAX_QP_PER_MGM = 4 * (MLX4_MAX_MGM_ENTRY_SIZE / 16 - 2), 67 MLX4_MTT_ENTRY_PER_SEG = 8, 68 }; 69 70 enum { 71 MLX4_NUM_PDS = 1 << 15 72 }; 73 74 enum { 75 MLX4_CMPT_TYPE_QP = 0, 76 MLX4_CMPT_TYPE_SRQ = 1, 77 MLX4_CMPT_TYPE_CQ = 2, 78 MLX4_CMPT_TYPE_EQ = 3, 79 MLX4_CMPT_NUM_TYPE 80 }; 81 82 enum { 83 MLX4_CMPT_SHIFT = 24, 84 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT 85 }; 86 87 enum mlx4_mr_state { 88 MLX4_MR_DISABLED = 0, 89 MLX4_MR_EN_HW, 90 MLX4_MR_EN_SW 91 }; 92 93 #define MLX4_COMM_TIME 10000 94 enum { 95 MLX4_COMM_CMD_RESET, 96 MLX4_COMM_CMD_VHCR0, 97 MLX4_COMM_CMD_VHCR1, 98 MLX4_COMM_CMD_VHCR2, 99 MLX4_COMM_CMD_VHCR_EN, 100 MLX4_COMM_CMD_VHCR_POST, 101 MLX4_COMM_CMD_FLR = 254 102 }; 103 104 /*The flag indicates that the slave should delay the RESET cmd*/ 105 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb 106 /*indicates how many retries will be done if we are in the middle of FLR*/ 107 #define NUM_OF_RESET_RETRIES 10 108 #define SLEEP_TIME_IN_RESET (2 * 1000) 109 enum mlx4_resource { 110 RES_QP, 111 RES_CQ, 112 RES_SRQ, 113 RES_XRCD, 114 RES_MPT, 115 RES_MTT, 116 RES_MAC, 117 RES_VLAN, 118 RES_EQ, 119 RES_COUNTER, 120 MLX4_NUM_OF_RESOURCE_TYPE 121 }; 122 123 enum mlx4_alloc_mode { 124 RES_OP_RESERVE, 125 RES_OP_RESERVE_AND_MAP, 126 RES_OP_MAP_ICM, 127 }; 128 129 130 /* 131 *Virtual HCR structures. 132 * mlx4_vhcr is the sw representation, in machine endianess 133 * 134 * mlx4_vhcr_cmd is the formalized structure, the one that is passed 135 * to FW to go through communication channel. 136 * It is big endian, and has the same structure as the physical HCR 137 * used by command interface 138 */ 139 struct mlx4_vhcr { 140 u64 in_param; 141 u64 out_param; 142 u32 in_modifier; 143 u32 errno; 144 u16 op; 145 u16 token; 146 u8 op_modifier; 147 u8 e_bit; 148 }; 149 150 struct mlx4_vhcr_cmd { 151 __be64 in_param; 152 __be32 in_modifier; 153 __be64 out_param; 154 __be16 token; 155 u16 reserved; 156 u8 status; 157 u8 flags; 158 __be16 opcode; 159 }; 160 161 struct mlx4_cmd_info { 162 u16 opcode; 163 bool has_inbox; 164 bool has_outbox; 165 bool out_is_imm; 166 bool encode_slave_id; 167 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 168 struct mlx4_cmd_mailbox *inbox); 169 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 170 struct mlx4_cmd_mailbox *inbox, 171 struct mlx4_cmd_mailbox *outbox, 172 struct mlx4_cmd_info *cmd); 173 }; 174 175 #ifdef CONFIG_MLX4_DEBUG 176 extern int mlx4_debug_level; 177 #else /* CONFIG_MLX4_DEBUG */ 178 #define mlx4_debug_level (0) 179 #endif /* CONFIG_MLX4_DEBUG */ 180 181 #define mlx4_dbg(mdev, format, arg...) \ 182 do { \ 183 if (mlx4_debug_level) \ 184 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \ 185 } while (0) 186 187 #define mlx4_err(mdev, format, arg...) \ 188 dev_err(&mdev->pdev->dev, format, ##arg) 189 #define mlx4_info(mdev, format, arg...) \ 190 dev_info(&mdev->pdev->dev, format, ##arg) 191 #define mlx4_warn(mdev, format, arg...) \ 192 dev_warn(&mdev->pdev->dev, format, ##arg) 193 194 extern int mlx4_log_num_mgm_entry_size; 195 extern int log_mtts_per_seg; 196 197 #define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF) 198 #define ALL_SLAVES 0xff 199 200 struct mlx4_bitmap { 201 u32 last; 202 u32 top; 203 u32 max; 204 u32 reserved_top; 205 u32 mask; 206 u32 avail; 207 spinlock_t lock; 208 unsigned long *table; 209 }; 210 211 struct mlx4_buddy { 212 unsigned long **bits; 213 unsigned int *num_free; 214 int max_order; 215 spinlock_t lock; 216 }; 217 218 struct mlx4_icm; 219 220 struct mlx4_icm_table { 221 u64 virt; 222 int num_icm; 223 int num_obj; 224 int obj_size; 225 int lowmem; 226 int coherent; 227 struct mutex mutex; 228 struct mlx4_icm **icm; 229 }; 230 231 /* 232 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits. 233 */ 234 struct mlx4_mpt_entry { 235 __be32 flags; 236 __be32 qpn; 237 __be32 key; 238 __be32 pd_flags; 239 __be64 start; 240 __be64 length; 241 __be32 lkey; 242 __be32 win_cnt; 243 u8 reserved1[3]; 244 u8 mtt_rep; 245 __be64 mtt_addr; 246 __be32 mtt_sz; 247 __be32 entity_size; 248 __be32 first_byte_offset; 249 } __packed; 250 251 /* 252 * Must be packed because start is 64 bits but only aligned to 32 bits. 253 */ 254 struct mlx4_eq_context { 255 __be32 flags; 256 u16 reserved1[3]; 257 __be16 page_offset; 258 u8 log_eq_size; 259 u8 reserved2[4]; 260 u8 eq_period; 261 u8 reserved3; 262 u8 eq_max_count; 263 u8 reserved4[3]; 264 u8 intr; 265 u8 log_page_size; 266 u8 reserved5[2]; 267 u8 mtt_base_addr_h; 268 __be32 mtt_base_addr_l; 269 u32 reserved6[2]; 270 __be32 consumer_index; 271 __be32 producer_index; 272 u32 reserved7[4]; 273 }; 274 275 struct mlx4_cq_context { 276 __be32 flags; 277 u16 reserved1[3]; 278 __be16 page_offset; 279 __be32 logsize_usrpage; 280 __be16 cq_period; 281 __be16 cq_max_count; 282 u8 reserved2[3]; 283 u8 comp_eqn; 284 u8 log_page_size; 285 u8 reserved3[2]; 286 u8 mtt_base_addr_h; 287 __be32 mtt_base_addr_l; 288 __be32 last_notified_index; 289 __be32 solicit_producer_index; 290 __be32 consumer_index; 291 __be32 producer_index; 292 u32 reserved4[2]; 293 __be64 db_rec_addr; 294 }; 295 296 struct mlx4_srq_context { 297 __be32 state_logsize_srqn; 298 u8 logstride; 299 u8 reserved1; 300 __be16 xrcd; 301 __be32 pg_offset_cqn; 302 u32 reserved2; 303 u8 log_page_size; 304 u8 reserved3[2]; 305 u8 mtt_base_addr_h; 306 __be32 mtt_base_addr_l; 307 __be32 pd; 308 __be16 limit_watermark; 309 __be16 wqe_cnt; 310 u16 reserved4; 311 __be16 wqe_counter; 312 u32 reserved5; 313 __be64 db_rec_addr; 314 }; 315 316 struct mlx4_eqe { 317 u8 reserved1; 318 u8 type; 319 u8 reserved2; 320 u8 subtype; 321 union { 322 u32 raw[6]; 323 struct { 324 __be32 cqn; 325 } __packed comp; 326 struct { 327 u16 reserved1; 328 __be16 token; 329 u32 reserved2; 330 u8 reserved3[3]; 331 u8 status; 332 __be64 out_param; 333 } __packed cmd; 334 struct { 335 __be32 qpn; 336 } __packed qp; 337 struct { 338 __be32 srqn; 339 } __packed srq; 340 struct { 341 __be32 cqn; 342 u32 reserved1; 343 u8 reserved2[3]; 344 u8 syndrome; 345 } __packed cq_err; 346 struct { 347 u32 reserved1[2]; 348 __be32 port; 349 } __packed port_change; 350 struct { 351 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 352 u32 reserved; 353 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; 354 } __packed comm_channel_arm; 355 struct { 356 u8 port; 357 u8 reserved[3]; 358 __be64 mac; 359 } __packed mac_update; 360 struct { 361 u8 port; 362 } __packed sw_event; 363 struct { 364 __be32 slave_id; 365 } __packed flr_event; 366 struct { 367 __be16 current_temperature; 368 __be16 warning_threshold; 369 } __packed warming; 370 } event; 371 u8 slave_id; 372 u8 reserved3[2]; 373 u8 owner; 374 } __packed; 375 376 struct mlx4_eq { 377 struct mlx4_dev *dev; 378 void __iomem *doorbell; 379 int eqn; 380 u32 cons_index; 381 u16 irq; 382 u16 have_irq; 383 int nent; 384 struct mlx4_buf_list *page_list; 385 struct mlx4_mtt mtt; 386 }; 387 388 struct mlx4_slave_eqe { 389 u8 type; 390 u8 port; 391 u32 param; 392 }; 393 394 struct mlx4_slave_event_eq_info { 395 int eqn; 396 u16 token; 397 }; 398 399 struct mlx4_profile { 400 int num_qp; 401 int rdmarc_per_qp; 402 int num_srq; 403 int num_cq; 404 int num_mcg; 405 int num_mpt; 406 unsigned num_mtt; 407 }; 408 409 struct mlx4_fw { 410 u64 clr_int_base; 411 u64 catas_offset; 412 u64 comm_base; 413 struct mlx4_icm *fw_icm; 414 struct mlx4_icm *aux_icm; 415 u32 catas_size; 416 u16 fw_pages; 417 u8 clr_int_bar; 418 u8 catas_bar; 419 u8 comm_bar; 420 }; 421 422 struct mlx4_comm { 423 u32 slave_write; 424 u32 slave_read; 425 }; 426 427 enum { 428 MLX4_MCAST_CONFIG = 0, 429 MLX4_MCAST_DISABLE = 1, 430 MLX4_MCAST_ENABLE = 2, 431 }; 432 433 #define VLAN_FLTR_SIZE 128 434 435 struct mlx4_vlan_fltr { 436 __be32 entry[VLAN_FLTR_SIZE]; 437 }; 438 439 struct mlx4_mcast_entry { 440 struct list_head list; 441 u64 addr; 442 }; 443 444 struct mlx4_promisc_qp { 445 struct list_head list; 446 u32 qpn; 447 }; 448 449 struct mlx4_steer_index { 450 struct list_head list; 451 unsigned int index; 452 struct list_head duplicates; 453 }; 454 455 #define MLX4_EVENT_TYPES_NUM 64 456 457 struct mlx4_slave_state { 458 u8 comm_toggle; 459 u8 last_cmd; 460 u8 init_port_mask; 461 bool active; 462 u8 function; 463 dma_addr_t vhcr_dma; 464 u16 mtu[MLX4_MAX_PORTS + 1]; 465 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1]; 466 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES]; 467 struct list_head mcast_filters[MLX4_MAX_PORTS + 1]; 468 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1]; 469 /* event type to eq number lookup */ 470 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM]; 471 u16 eq_pi; 472 u16 eq_ci; 473 spinlock_t lock; 474 /*initialized via the kzalloc*/ 475 u8 is_slave_going_down; 476 u32 cookie; 477 }; 478 479 struct slave_list { 480 struct mutex mutex; 481 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE]; 482 }; 483 484 struct mlx4_resource_tracker { 485 spinlock_t lock; 486 /* tree for each resources */ 487 struct radix_tree_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE]; 488 /* num_of_slave's lists, one per slave */ 489 struct slave_list *slave_list; 490 }; 491 492 #define SLAVE_EVENT_EQ_SIZE 128 493 struct mlx4_slave_event_eq { 494 u32 eqn; 495 u32 cons; 496 u32 prod; 497 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE]; 498 }; 499 500 struct mlx4_master_qp0_state { 501 int proxy_qp0_active; 502 int qp0_active; 503 int port_active; 504 }; 505 506 struct mlx4_mfunc_master_ctx { 507 struct mlx4_slave_state *slave_state; 508 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1]; 509 int init_port_ref[MLX4_MAX_PORTS + 1]; 510 u16 max_mtu[MLX4_MAX_PORTS + 1]; 511 int disable_mcast_ref[MLX4_MAX_PORTS + 1]; 512 struct mlx4_resource_tracker res_tracker; 513 struct workqueue_struct *comm_wq; 514 struct work_struct comm_work; 515 struct work_struct slave_event_work; 516 struct work_struct slave_flr_event_work; 517 spinlock_t slave_state_lock; 518 __be32 comm_arm_bit_vector[4]; 519 struct mlx4_eqe cmd_eqe; 520 struct mlx4_slave_event_eq slave_eq; 521 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX]; 522 }; 523 524 struct mlx4_mfunc { 525 struct mlx4_comm __iomem *comm; 526 struct mlx4_vhcr_cmd *vhcr; 527 dma_addr_t vhcr_dma; 528 529 struct mlx4_mfunc_master_ctx master; 530 }; 531 532 struct mlx4_cmd { 533 struct pci_pool *pool; 534 void __iomem *hcr; 535 struct mutex hcr_mutex; 536 struct semaphore poll_sem; 537 struct semaphore event_sem; 538 struct semaphore slave_sem; 539 int max_cmds; 540 spinlock_t context_lock; 541 int free_head; 542 struct mlx4_cmd_context *context; 543 u16 token_mask; 544 u8 use_events; 545 u8 toggle; 546 u8 comm_toggle; 547 }; 548 549 struct mlx4_uar_table { 550 struct mlx4_bitmap bitmap; 551 }; 552 553 struct mlx4_mr_table { 554 struct mlx4_bitmap mpt_bitmap; 555 struct mlx4_buddy mtt_buddy; 556 u64 mtt_base; 557 u64 mpt_base; 558 struct mlx4_icm_table mtt_table; 559 struct mlx4_icm_table dmpt_table; 560 }; 561 562 struct mlx4_cq_table { 563 struct mlx4_bitmap bitmap; 564 spinlock_t lock; 565 struct radix_tree_root tree; 566 struct mlx4_icm_table table; 567 struct mlx4_icm_table cmpt_table; 568 }; 569 570 struct mlx4_eq_table { 571 struct mlx4_bitmap bitmap; 572 char *irq_names; 573 void __iomem *clr_int; 574 void __iomem **uar_map; 575 u32 clr_mask; 576 struct mlx4_eq *eq; 577 struct mlx4_icm_table table; 578 struct mlx4_icm_table cmpt_table; 579 int have_irq; 580 u8 inta_pin; 581 }; 582 583 struct mlx4_srq_table { 584 struct mlx4_bitmap bitmap; 585 spinlock_t lock; 586 struct radix_tree_root tree; 587 struct mlx4_icm_table table; 588 struct mlx4_icm_table cmpt_table; 589 }; 590 591 struct mlx4_qp_table { 592 struct mlx4_bitmap bitmap; 593 u32 rdmarc_base; 594 int rdmarc_shift; 595 spinlock_t lock; 596 struct mlx4_icm_table qp_table; 597 struct mlx4_icm_table auxc_table; 598 struct mlx4_icm_table altc_table; 599 struct mlx4_icm_table rdmarc_table; 600 struct mlx4_icm_table cmpt_table; 601 }; 602 603 struct mlx4_mcg_table { 604 struct mutex mutex; 605 struct mlx4_bitmap bitmap; 606 struct mlx4_icm_table table; 607 }; 608 609 struct mlx4_catas_err { 610 u32 __iomem *map; 611 struct timer_list timer; 612 struct list_head list; 613 }; 614 615 #define MLX4_MAX_MAC_NUM 128 616 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3) 617 618 struct mlx4_mac_table { 619 __be64 entries[MLX4_MAX_MAC_NUM]; 620 int refs[MLX4_MAX_MAC_NUM]; 621 struct mutex mutex; 622 int total; 623 int max; 624 }; 625 626 #define MLX4_MAX_VLAN_NUM 128 627 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2) 628 629 struct mlx4_vlan_table { 630 __be32 entries[MLX4_MAX_VLAN_NUM]; 631 int refs[MLX4_MAX_VLAN_NUM]; 632 struct mutex mutex; 633 int total; 634 int max; 635 }; 636 637 #define SET_PORT_GEN_ALL_VALID 0x7 638 #define SET_PORT_PROMISC_SHIFT 31 639 #define SET_PORT_MC_PROMISC_SHIFT 30 640 641 enum { 642 MCAST_DIRECT_ONLY = 0, 643 MCAST_DIRECT = 1, 644 MCAST_DEFAULT = 2 645 }; 646 647 648 struct mlx4_set_port_general_context { 649 u8 reserved[3]; 650 u8 flags; 651 u16 reserved2; 652 __be16 mtu; 653 u8 pptx; 654 u8 pfctx; 655 u16 reserved3; 656 u8 pprx; 657 u8 pfcrx; 658 u16 reserved4; 659 }; 660 661 struct mlx4_set_port_rqp_calc_context { 662 __be32 base_qpn; 663 u8 rererved; 664 u8 n_mac; 665 u8 n_vlan; 666 u8 n_prio; 667 u8 reserved2[3]; 668 u8 mac_miss; 669 u8 intra_no_vlan; 670 u8 no_vlan; 671 u8 intra_vlan_miss; 672 u8 vlan_miss; 673 u8 reserved3[3]; 674 u8 no_vlan_prio; 675 __be32 promisc; 676 __be32 mcast; 677 }; 678 679 struct mlx4_mac_entry { 680 u64 mac; 681 }; 682 683 struct mlx4_port_info { 684 struct mlx4_dev *dev; 685 int port; 686 char dev_name[16]; 687 struct device_attribute port_attr; 688 enum mlx4_port_type tmp_type; 689 char dev_mtu_name[16]; 690 struct device_attribute port_mtu_attr; 691 struct mlx4_mac_table mac_table; 692 struct radix_tree_root mac_tree; 693 struct mlx4_vlan_table vlan_table; 694 int base_qpn; 695 }; 696 697 struct mlx4_sense { 698 struct mlx4_dev *dev; 699 u8 do_sense_port[MLX4_MAX_PORTS + 1]; 700 u8 sense_allowed[MLX4_MAX_PORTS + 1]; 701 struct delayed_work sense_poll; 702 }; 703 704 struct mlx4_msix_ctl { 705 u64 pool_bm; 706 struct mutex pool_lock; 707 }; 708 709 struct mlx4_steer { 710 struct list_head promisc_qps[MLX4_NUM_STEERS]; 711 struct list_head steer_entries[MLX4_NUM_STEERS]; 712 }; 713 714 struct mlx4_priv { 715 struct mlx4_dev dev; 716 717 struct list_head dev_list; 718 struct list_head ctx_list; 719 spinlock_t ctx_lock; 720 721 struct list_head pgdir_list; 722 struct mutex pgdir_mutex; 723 724 struct mlx4_fw fw; 725 struct mlx4_cmd cmd; 726 struct mlx4_mfunc mfunc; 727 728 struct mlx4_bitmap pd_bitmap; 729 struct mlx4_bitmap xrcd_bitmap; 730 struct mlx4_uar_table uar_table; 731 struct mlx4_mr_table mr_table; 732 struct mlx4_cq_table cq_table; 733 struct mlx4_eq_table eq_table; 734 struct mlx4_srq_table srq_table; 735 struct mlx4_qp_table qp_table; 736 struct mlx4_mcg_table mcg_table; 737 struct mlx4_bitmap counters_bitmap; 738 739 struct mlx4_catas_err catas_err; 740 741 void __iomem *clr_base; 742 743 struct mlx4_uar driver_uar; 744 void __iomem *kar; 745 struct mlx4_port_info port[MLX4_MAX_PORTS + 1]; 746 struct mlx4_sense sense; 747 struct mutex port_mutex; 748 struct mlx4_msix_ctl msix_ctl; 749 struct mlx4_steer *steer; 750 struct list_head bf_list; 751 struct mutex bf_mutex; 752 struct io_mapping *bf_mapping; 753 int reserved_mtts; 754 }; 755 756 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev) 757 { 758 return container_of(dev, struct mlx4_priv, dev); 759 } 760 761 #define MLX4_SENSE_RANGE (HZ * 3) 762 763 extern struct workqueue_struct *mlx4_wq; 764 765 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap); 766 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj); 767 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align); 768 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt); 769 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap); 770 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, 771 u32 reserved_bot, u32 resetrved_top); 772 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap); 773 774 int mlx4_reset(struct mlx4_dev *dev); 775 776 int mlx4_alloc_eq_table(struct mlx4_dev *dev); 777 void mlx4_free_eq_table(struct mlx4_dev *dev); 778 779 int mlx4_init_pd_table(struct mlx4_dev *dev); 780 int mlx4_init_xrcd_table(struct mlx4_dev *dev); 781 int mlx4_init_uar_table(struct mlx4_dev *dev); 782 int mlx4_init_mr_table(struct mlx4_dev *dev); 783 int mlx4_init_eq_table(struct mlx4_dev *dev); 784 int mlx4_init_cq_table(struct mlx4_dev *dev); 785 int mlx4_init_qp_table(struct mlx4_dev *dev); 786 int mlx4_init_srq_table(struct mlx4_dev *dev); 787 int mlx4_init_mcg_table(struct mlx4_dev *dev); 788 789 void mlx4_cleanup_pd_table(struct mlx4_dev *dev); 790 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev); 791 void mlx4_cleanup_uar_table(struct mlx4_dev *dev); 792 void mlx4_cleanup_mr_table(struct mlx4_dev *dev); 793 void mlx4_cleanup_eq_table(struct mlx4_dev *dev); 794 void mlx4_cleanup_cq_table(struct mlx4_dev *dev); 795 void mlx4_cleanup_qp_table(struct mlx4_dev *dev); 796 void mlx4_cleanup_srq_table(struct mlx4_dev *dev); 797 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev); 798 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn); 799 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn); 800 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn); 801 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn); 802 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn); 803 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn); 804 int __mlx4_mr_reserve(struct mlx4_dev *dev); 805 void __mlx4_mr_release(struct mlx4_dev *dev, u32 index); 806 int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index); 807 void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index); 808 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order); 809 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order); 810 811 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave, 812 struct mlx4_vhcr *vhcr, 813 struct mlx4_cmd_mailbox *inbox, 814 struct mlx4_cmd_mailbox *outbox, 815 struct mlx4_cmd_info *cmd); 816 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave, 817 struct mlx4_vhcr *vhcr, 818 struct mlx4_cmd_mailbox *inbox, 819 struct mlx4_cmd_mailbox *outbox, 820 struct mlx4_cmd_info *cmd); 821 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave, 822 struct mlx4_vhcr *vhcr, 823 struct mlx4_cmd_mailbox *inbox, 824 struct mlx4_cmd_mailbox *outbox, 825 struct mlx4_cmd_info *cmd); 826 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave, 827 struct mlx4_vhcr *vhcr, 828 struct mlx4_cmd_mailbox *inbox, 829 struct mlx4_cmd_mailbox *outbox, 830 struct mlx4_cmd_info *cmd); 831 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave, 832 struct mlx4_vhcr *vhcr, 833 struct mlx4_cmd_mailbox *inbox, 834 struct mlx4_cmd_mailbox *outbox, 835 struct mlx4_cmd_info *cmd); 836 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave, 837 struct mlx4_vhcr *vhcr, 838 struct mlx4_cmd_mailbox *inbox, 839 struct mlx4_cmd_mailbox *outbox, 840 struct mlx4_cmd_info *cmd); 841 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave, 842 struct mlx4_vhcr *vhcr, 843 struct mlx4_cmd_mailbox *inbox, 844 struct mlx4_cmd_mailbox *outbox, 845 struct mlx4_cmd_info *cmd); 846 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 847 int *base); 848 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 849 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 850 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 851 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); 852 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 853 int start_index, int npages, u64 *page_list); 854 855 void mlx4_start_catas_poll(struct mlx4_dev *dev); 856 void mlx4_stop_catas_poll(struct mlx4_dev *dev); 857 void mlx4_catas_init(void); 858 int mlx4_restart_one(struct pci_dev *pdev); 859 int mlx4_register_device(struct mlx4_dev *dev); 860 void mlx4_unregister_device(struct mlx4_dev *dev); 861 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, int port); 862 863 struct mlx4_dev_cap; 864 struct mlx4_init_hca_param; 865 866 u64 mlx4_make_profile(struct mlx4_dev *dev, 867 struct mlx4_profile *request, 868 struct mlx4_dev_cap *dev_cap, 869 struct mlx4_init_hca_param *init_hca); 870 void mlx4_master_comm_channel(struct work_struct *work); 871 void mlx4_gen_slave_eqe(struct work_struct *work); 872 void mlx4_master_handle_slave_flr(struct work_struct *work); 873 874 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave, 875 struct mlx4_vhcr *vhcr, 876 struct mlx4_cmd_mailbox *inbox, 877 struct mlx4_cmd_mailbox *outbox, 878 struct mlx4_cmd_info *cmd); 879 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave, 880 struct mlx4_vhcr *vhcr, 881 struct mlx4_cmd_mailbox *inbox, 882 struct mlx4_cmd_mailbox *outbox, 883 struct mlx4_cmd_info *cmd); 884 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave, 885 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox, 886 struct mlx4_cmd_mailbox *outbox, 887 struct mlx4_cmd_info *cmd); 888 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave, 889 struct mlx4_vhcr *vhcr, 890 struct mlx4_cmd_mailbox *inbox, 891 struct mlx4_cmd_mailbox *outbox, 892 struct mlx4_cmd_info *cmd); 893 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave, 894 struct mlx4_vhcr *vhcr, 895 struct mlx4_cmd_mailbox *inbox, 896 struct mlx4_cmd_mailbox *outbox, 897 struct mlx4_cmd_info *cmd); 898 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave, 899 struct mlx4_vhcr *vhcr, 900 struct mlx4_cmd_mailbox *inbox, 901 struct mlx4_cmd_mailbox *outbox, 902 struct mlx4_cmd_info *cmd); 903 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave, 904 struct mlx4_vhcr *vhcr, 905 struct mlx4_cmd_mailbox *inbox, 906 struct mlx4_cmd_mailbox *outbox, 907 struct mlx4_cmd_info *cmd); 908 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave, 909 struct mlx4_vhcr *vhcr, 910 struct mlx4_cmd_mailbox *inbox, 911 struct mlx4_cmd_mailbox *outbox, 912 struct mlx4_cmd_info *cmd); 913 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave, 914 struct mlx4_vhcr *vhcr, 915 struct mlx4_cmd_mailbox *inbox, 916 struct mlx4_cmd_mailbox *outbox, 917 struct mlx4_cmd_info *cmd); 918 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave, 919 struct mlx4_vhcr *vhcr, 920 struct mlx4_cmd_mailbox *inbox, 921 struct mlx4_cmd_mailbox *outbox, 922 struct mlx4_cmd_info *cmd); 923 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 924 struct mlx4_vhcr *vhcr, 925 struct mlx4_cmd_mailbox *inbox, 926 struct mlx4_cmd_mailbox *outbox, 927 struct mlx4_cmd_info *cmd); 928 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 929 struct mlx4_vhcr *vhcr, 930 struct mlx4_cmd_mailbox *inbox, 931 struct mlx4_cmd_mailbox *outbox, 932 struct mlx4_cmd_info *cmd); 933 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave, 934 struct mlx4_vhcr *vhcr, 935 struct mlx4_cmd_mailbox *inbox, 936 struct mlx4_cmd_mailbox *outbox, 937 struct mlx4_cmd_info *cmd); 938 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave, 939 struct mlx4_vhcr *vhcr, 940 struct mlx4_cmd_mailbox *inbox, 941 struct mlx4_cmd_mailbox *outbox, 942 struct mlx4_cmd_info *cmd); 943 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave, 944 struct mlx4_vhcr *vhcr, 945 struct mlx4_cmd_mailbox *inbox, 946 struct mlx4_cmd_mailbox *outbox, 947 struct mlx4_cmd_info *cmd); 948 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, 949 struct mlx4_vhcr *vhcr, 950 struct mlx4_cmd_mailbox *inbox, 951 struct mlx4_cmd_mailbox *outbox, 952 struct mlx4_cmd_info *cmd); 953 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave, 954 struct mlx4_vhcr *vhcr, 955 struct mlx4_cmd_mailbox *inbox, 956 struct mlx4_cmd_mailbox *outbox, 957 struct mlx4_cmd_info *cmd); 958 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave, 959 struct mlx4_vhcr *vhcr, 960 struct mlx4_cmd_mailbox *inbox, 961 struct mlx4_cmd_mailbox *outbox, 962 struct mlx4_cmd_info *cmd); 963 964 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe); 965 966 int mlx4_cmd_init(struct mlx4_dev *dev); 967 void mlx4_cmd_cleanup(struct mlx4_dev *dev); 968 int mlx4_multi_func_init(struct mlx4_dev *dev); 969 void mlx4_multi_func_cleanup(struct mlx4_dev *dev); 970 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param); 971 int mlx4_cmd_use_events(struct mlx4_dev *dev); 972 void mlx4_cmd_use_polling(struct mlx4_dev *dev); 973 974 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param, 975 unsigned long timeout); 976 977 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn); 978 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type); 979 980 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type); 981 982 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type); 983 984 void mlx4_handle_catas_err(struct mlx4_dev *dev); 985 986 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port, 987 enum mlx4_port_type *type); 988 void mlx4_do_sense_ports(struct mlx4_dev *dev, 989 enum mlx4_port_type *stype, 990 enum mlx4_port_type *defaults); 991 void mlx4_start_sense(struct mlx4_dev *dev); 992 void mlx4_stop_sense(struct mlx4_dev *dev); 993 void mlx4_sense_init(struct mlx4_dev *dev); 994 int mlx4_check_port_params(struct mlx4_dev *dev, 995 enum mlx4_port_type *port_type); 996 int mlx4_change_port_types(struct mlx4_dev *dev, 997 enum mlx4_port_type *port_types); 998 999 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table); 1000 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table); 1001 1002 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port); 1003 /* resource tracker functions*/ 1004 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev, 1005 enum mlx4_resource resource_type, 1006 int resource_id, int *slave); 1007 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id); 1008 int mlx4_init_resource_tracker(struct mlx4_dev *dev); 1009 1010 void mlx4_free_resource_tracker(struct mlx4_dev *dev); 1011 1012 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave, 1013 struct mlx4_vhcr *vhcr, 1014 struct mlx4_cmd_mailbox *inbox, 1015 struct mlx4_cmd_mailbox *outbox, 1016 struct mlx4_cmd_info *cmd); 1017 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, 1018 struct mlx4_vhcr *vhcr, 1019 struct mlx4_cmd_mailbox *inbox, 1020 struct mlx4_cmd_mailbox *outbox, 1021 struct mlx4_cmd_info *cmd); 1022 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, 1023 struct mlx4_vhcr *vhcr, 1024 struct mlx4_cmd_mailbox *inbox, 1025 struct mlx4_cmd_mailbox *outbox, 1026 struct mlx4_cmd_info *cmd); 1027 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, 1028 struct mlx4_vhcr *vhcr, 1029 struct mlx4_cmd_mailbox *inbox, 1030 struct mlx4_cmd_mailbox *outbox, 1031 struct mlx4_cmd_info *cmd); 1032 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps); 1033 1034 1035 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave, 1036 struct mlx4_vhcr *vhcr, 1037 struct mlx4_cmd_mailbox *inbox, 1038 struct mlx4_cmd_mailbox *outbox, 1039 struct mlx4_cmd_info *cmd); 1040 1041 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave, 1042 struct mlx4_vhcr *vhcr, 1043 struct mlx4_cmd_mailbox *inbox, 1044 struct mlx4_cmd_mailbox *outbox, 1045 struct mlx4_cmd_info *cmd); 1046 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1047 enum mlx4_protocol prot, enum mlx4_steer_type steer); 1048 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1049 int block_mcast_loopback, enum mlx4_protocol prot, 1050 enum mlx4_steer_type steer); 1051 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave, 1052 struct mlx4_vhcr *vhcr, 1053 struct mlx4_cmd_mailbox *inbox, 1054 struct mlx4_cmd_mailbox *outbox, 1055 struct mlx4_cmd_info *cmd); 1056 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave, 1057 struct mlx4_vhcr *vhcr, 1058 struct mlx4_cmd_mailbox *inbox, 1059 struct mlx4_cmd_mailbox *outbox, 1060 struct mlx4_cmd_info *cmd); 1061 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function, 1062 int port, void *buf); 1063 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod, 1064 struct mlx4_cmd_mailbox *outbox); 1065 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave, 1066 struct mlx4_vhcr *vhcr, 1067 struct mlx4_cmd_mailbox *inbox, 1068 struct mlx4_cmd_mailbox *outbox, 1069 struct mlx4_cmd_info *cmd); 1070 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave, 1071 struct mlx4_vhcr *vhcr, 1072 struct mlx4_cmd_mailbox *inbox, 1073 struct mlx4_cmd_mailbox *outbox, 1074 struct mlx4_cmd_info *cmd); 1075 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave, 1076 struct mlx4_vhcr *vhcr, 1077 struct mlx4_cmd_mailbox *inbox, 1078 struct mlx4_cmd_mailbox *outbox, 1079 struct mlx4_cmd_info *cmd); 1080 1081 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev); 1082 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev); 1083 1084 static inline void set_param_l(u64 *arg, u32 val) 1085 { 1086 *((u32 *)arg) = val; 1087 } 1088 1089 static inline void set_param_h(u64 *arg, u32 val) 1090 { 1091 *arg = (*arg & 0xffffffff) | ((u64) val << 32); 1092 } 1093 1094 static inline u32 get_param_l(u64 *arg) 1095 { 1096 return (u32) (*arg & 0xffffffff); 1097 } 1098 1099 static inline u32 get_param_h(u64 *arg) 1100 { 1101 return (u32)(*arg >> 32); 1102 } 1103 1104 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev) 1105 { 1106 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock; 1107 } 1108 1109 #define NOT_MASKED_PD_BITS 17 1110 1111 #endif /* MLX4_H */ 1112